Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions

[Richard Henderson <richard.henderson@linaro.org>]

On 8/4/21 4:53 PM, LIU Zhiwei wrote:
> +static TCGv gpr_src_u(DisasContext *ctx, int reg_num)
> +{
> +    if (reg_num == 0) {
> +        return ctx->zero;
> +    }
> +    if (ctx->uxl32) {
> +        tcg_gen_ext32u_tl(cpu_gpr[reg_num], cpu_gpr[reg_num]);
> +    }
> +    return cpu_gpr[reg_num];
> +}
> +
> +static TCGv gpr_src_s(DisasContext *ctx, int reg_num)
> +{
> +    if (reg_num == 0) {
> +        return ctx->zero;
> +    }
> +    if (ctx->uxl32) {
> +        tcg_gen_ext32s_tl(cpu_gpr[reg_num], cpu_gpr[reg_num]);
> +    }
> +    return cpu_gpr[reg_num];
> +}

This is bad: you cannot modify the source registers like this.

These incorrect modifications will be visible to the kernel on transition back to S-mode.

> 
> +static bool gen_branch_u(DisasContext *ctx, arg_b *a, TCGCond cond)
> +{
> +    TCGv src1 = gpr_src_u(ctx, a->rs1);
> +    TCGv src2 = gpr_src_u(ctx, a->rs2);
> +
> +    return gen_branch_internal(ctx, a, cond, src1, src2);
> +}

This is unnecessary.  Unsigned comparisons work just fine with sign-extended values.  It 
will be simpler to keep all values sign-extended.


r~