From: "Luis R. Rodriguez" <lrodriguez@atheros.com>
To: linville@tuxdriver.com
Cc: linux-wireless@vger.kernel.org, Felix Fietkau <nbd@openwrt.org>
Subject: [PATCH 025/102] ath9k_hw: Add AR9003 PHY register definitions
Date: Thu, 8 Apr 2010 15:26:21 -0400 [thread overview]
Message-ID: <1270754858-26266-26-git-send-email-lrodriguez@atheros.com> (raw)
In-Reply-To: <1270754858-26266-1-git-send-email-lrodriguez@atheros.com>
From: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
drivers/net/wireless/ath/ath9k/ar9003_phy.c | 1 +
drivers/net/wireless/ath/ath9k/ar9003_phy.h | 804 +++++++++++++++++++++++++++
2 files changed, 805 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/wireless/ath/ath9k/ar9003_phy.h
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index e3c97da..7698223 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -15,6 +15,7 @@
*/
#include "hw.h"
+#include "ar9003_phy.h"
/**
* ar9003_hw_set_channel - set channel on single-chip device
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
new file mode 100644
index 0000000..420bd3b
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -0,0 +1,804 @@
+/*
+ * Copyright (c) 2002-2010 Atheros Communications, Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef AR9003_PHY_H
+#define AR9003_PHY_H
+
+/*
+ * Channel Register Map
+ */
+#define AR_CHAN_BASE 0x9800
+
+#define AR_PHY_TIMING1 AR_CHAN_BASE + 0x0
+#define AR_PHY_TIMING2 AR_CHAN_BASE + 0x4
+#define AR_PHY_TIMING3 AR_CHAN_BASE + 0x8
+#define AR_PHY_TIMING4 AR_CHAN_BASE + 0xc
+#define AR_PHY_TIMING5 AR_CHAN_BASE + 0x10
+#define AR_PHY_TIMING6 AR_CHAN_BASE + 0x14
+#define AR_PHY_TIMING11 AR_CHAN_BASE + 0x18
+#define AR_PHY_SPUR_REG AR_CHAN_BASE + 0x1c
+#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_BASE + 0xdc
+#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_BASE + 0xb0
+
+#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
+#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
+
+#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
+#define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN_S 31
+
+#define AR_PHY_FIND_SIG_LOW AR_CHAN_BASE + 0x20
+
+#define AR_PHY_SFCORR AR_CHAN_BASE + 0x24
+#define AR_PHY_SFCORR_LOW AR_CHAN_BASE + 0x28
+#define AR_PHY_SFCORR_EXT AR_CHAN_BASE + 0x2c
+
+#define AR_PHY_EXT_CCA AR_CHAN_BASE + 0x30
+#define AR_PHY_RADAR_0 AR_CHAN_BASE + 0x34
+#define AR_PHY_RADAR_1 AR_CHAN_BASE + 0x38
+#define AR_PHY_RADAR_EXT AR_CHAN_BASE + 0x3c
+#define AR_PHY_MULTICHAIN_CTRL AR_CHAN_BASE + 0x80
+#define AR_PHY_PERCHAIN_CSD AR_CHAN_BASE + 0x84
+
+#define AR_PHY_TX_PHASE_RAMP_0 AR_CHAN_BASE + 0xd0
+#define AR_PHY_ADC_GAIN_DC_CORR_0 AR_CHAN_BASE + 0xd4
+#define AR_PHY_IQ_ADC_MEAS_0_B0 AR_CHAN_BASE + 0xc0
+#define AR_PHY_IQ_ADC_MEAS_1_B0 AR_CHAN_BASE + 0xc4
+#define AR_PHY_IQ_ADC_MEAS_2_B0 AR_CHAN_BASE + 0xc8
+#define AR_PHY_IQ_ADC_MEAS_3_B0 AR_CHAN_BASE + 0xcc
+
+/* The following registers changed position from AR9300 1.0 to AR9300 2.0 */
+#define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
+#define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
+#define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
+#define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
+#define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
+#define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
+
+#define AR_PHY_TX_CRC AR_CHAN_BASE + 0xa0
+#define AR_PHY_TST_DAC_CONST AR_CHAN_BASE + 0xa4
+#define AR_PHY_SPUR_REPORT_0 AR_CHAN_BASE + 0xa8
+#define AR_PHY_CHAN_INFO_TAB_0 AR_CHAN_BASE + 0x300
+
+/*
+ * Channel Field Definitions
+ */
+#define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
+#define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
+#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
+#define AR_PHY_TIMING3_DSC_MAN_S 17
+#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
+#define AR_PHY_TIMING3_DSC_EXP_S 13
+#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
+#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
+#define AR_PHY_TIMING4_DO_CAL 0x10000
+#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
+#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
+#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
+#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
+#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
+#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
+#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
+#define AR_PHY_SFCORR_M2COUNT_THR_S 0
+#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
+#define AR_PHY_SFCORR_M1_THRESH_S 17
+#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
+#define AR_PHY_SFCORR_M2_THRESH_S 24
+#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
+#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
+#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
+#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
+#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
+#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
+#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
+#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
+#define AR_PHY_EXT_CCA_THRESH62_S 16
+#define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
+#define AR_PHY_EXT_MINCCA_PWR_S 16
+#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
+#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
+#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
+#define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
+#define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
+#define AR_PHY_TIMING5_CYCPWR_THR1A_S 16
+#define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
+#define AR_PHY_TIMING5_RSSI_THR1A_S 16
+#define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
+#define AR_PHY_RADAR_0_ENA 0x00000001
+#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
+#define AR_PHY_RADAR_0_INBAND 0x0000003e
+#define AR_PHY_RADAR_0_INBAND_S 1
+#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
+#define AR_PHY_RADAR_0_PRSSI_S 6
+#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
+#define AR_PHY_RADAR_0_HEIGHT_S 12
+#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
+#define AR_PHY_RADAR_0_RRSSI_S 18
+#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
+#define AR_PHY_RADAR_0_FIRPWR_S 24
+#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
+#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
+#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
+#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
+#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
+#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
+#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
+#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
+#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
+#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
+#define AR_PHY_RADAR_1_MAXLEN_S 0
+#define AR_PHY_RADAR_EXT_ENA 0x00004000
+#define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
+#define AR_PHY_RADAR_DC_PWR_THRESH_S 15
+#define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
+#define AR_PHY_RADAR_LB_DC_CAP_S 23
+#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
+#define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW_S 6
+#define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
+#define AR_PHY_FIND_SIG_LOW_FIRPWR_S 12
+#define AR_PHY_FIND_SIG_LOW_FIRPWR_SIGN_BIT 19
+#define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
+#define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
+#define AR_PHY_FIND_SIG_LOW_RELSTEP_SIGN_BIT 5
+#define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
+#define AR_PHY_CHAN_INFO_TAB_S2_READ_S 3
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF_S 7
+#define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF_S 15
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
+#define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF_S 22
+
+/*
+ * MRC Register Map
+ */
+#define AR_MRC_BASE 0x9c00
+
+#define AR_PHY_TIMING_3A AR_MRC_BASE + 0x0
+#define AR_PHY_LDPC_CNTL1 AR_MRC_BASE + 0x4
+#define AR_PHY_LDPC_CNTL2 AR_MRC_BASE + 0x8
+#define AR_PHY_PILOT_SPUR_MASK AR_MRC_BASE + 0xc
+#define AR_PHY_CHAN_SPUR_MASK AR_MRC_BASE + 0x10
+#define AR_PHY_SGI_DELTA AR_MRC_BASE + 0x14
+#define AR_PHY_ML_CNTL_1 AR_MRC_BASE + 0x18
+#define AR_PHY_ML_CNTL_2 AR_MRC_BASE + 0x1c
+#define AR_PHY_TST_ADC AR_MRC_BASE + 0x20
+
+/*
+ * MRC Feild Definitions
+ */
+#define AR_PHY_SGI_DSC_MAN 0x0007FFF0
+#define AR_PHY_SGI_DSC_MAN_S 4
+#define AR_PHY_SGI_DSC_EXP 0x0000000F
+#define AR_PHY_SGI_DSC_EXP_S 0
+/*
+ * BBB Register Map
+ */
+#define AR_BBB_BASE 0x9d00
+
+/*
+ * AGC Register Map
+ */
+#define AR_AGC_BASE 0x9e00
+
+#define AR_PHY_SETTLING AR_AGC_BASE + 0x0
+#define AR_PHY_FORCEMAX_GAINS_0 AR_AGC_BASE + 0x4
+#define AR_PHY_GAINS_MINOFF0 AR_AGC_BASE + 0x8
+#define AR_PHY_DESIRED_SZ AR_AGC_BASE + 0xc
+#define AR_PHY_FIND_SIG AR_AGC_BASE + 0x10
+#define AR_PHY_AGC AR_AGC_BASE + 0x14
+#define AR_PHY_EXT_ATTEN_CTL_0 AR_AGC_BASE + 0x18
+#define AR_PHY_CCA_0 AR_AGC_BASE + 0x1c
+#define AR_PHY_EXT_CCA0 AR_AGC_BASE + 0x20
+#define AR_PHY_RESTART AR_AGC_BASE + 0x24
+#define AR_PHY_MC_GAIN_CTRL AR_AGC_BASE + 0x28
+#define AR_PHY_EXTCHN_PWRTHR1 AR_AGC_BASE + 0x2c
+#define AR_PHY_EXT_CHN_WIN AR_AGC_BASE + 0x30
+#define AR_PHY_20_40_DET_THR AR_AGC_BASE + 0x34
+#define AR_PHY_RIFS_SRCH AR_AGC_BASE + 0x38
+#define AR_PHY_PEAK_DET_CTRL_1 AR_AGC_BASE + 0x3c
+#define AR_PHY_PEAK_DET_CTRL_2 AR_AGC_BASE + 0x40
+#define AR_PHY_RX_GAIN_BOUNDS_1 AR_AGC_BASE + 0x44
+#define AR_PHY_RX_GAIN_BOUNDS_2 AR_AGC_BASE + 0x48
+#define AR_PHY_RSSI_0 AR_AGC_BASE + 0x180
+#define AR_PHY_SPUR_CCK_REP0 AR_AGC_BASE + 0x184
+#define AR_PHY_CCK_DETECT AR_AGC_BASE + 0x1c0
+#define AR_PHY_DAG_CTRLCCK AR_AGC_BASE + 0x1c4
+#define AR_PHY_IQCORR_CTRL_CCK AR_AGC_BASE + 0x1c8
+
+#define AR_PHY_CCK_SPUR_MIT AR_AGC_BASE + 0x1cc
+#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
+#define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR_S 1
+#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
+#define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE_S 29
+#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
+#define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
+#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
+#define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ_S 9
+
+#define AR_PHY_RX_OCGAIN AR_AGC_BASE + 0x200
+
+#define AR_PHY_CCA_NOM_VAL_9300_2GHZ -110
+#define AR_PHY_CCA_NOM_VAL_9300_5GHZ -115
+#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ -125
+#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ -125
+#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
+#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
+
+/*
+ * AGC Field Definitions
+ */
+#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
+#define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN_S 18
+#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
+#define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN_S 10
+#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
+#define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN_S 17
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN_S 12
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB_S 6
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
+#define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
+#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
+#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
+#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
+#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
+#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
+#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
+#define AR_PHY_SETTLING_SWITCH 0x00003F80
+#define AR_PHY_SETTLING_SWITCH_S 7
+#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
+#define AR_PHY_DESIRED_SZ_ADC_S 0
+#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
+#define AR_PHY_DESIRED_SZ_PGA_S 8
+#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
+#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
+#define AR_PHY_MINCCA_PWR 0x1FF00000
+#define AR_PHY_MINCCA_PWR_S 20
+#define AR_PHY_CCA_THRESH62 0x0007F000
+#define AR_PHY_CCA_THRESH62_S 12
+#define AR9280_PHY_MINCCA_PWR 0x1FF00000
+#define AR9280_PHY_MINCCA_PWR_S 20
+#define AR9280_PHY_CCA_THRESH62 0x000FF000
+#define AR9280_PHY_CCA_THRESH62_S 12
+#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
+#define AR_PHY_EXT_CCA0_THRESH62_S 0
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
+#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
+#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
+#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
+
+#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
+#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR_S 9
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
+#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
+
+#define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
+#define AR_PHY_AGC_COARSE_LOW 0x00007F80
+#define AR_PHY_AGC_COARSE_LOW_S 7
+#define AR_PHY_AGC_COARSE_HIGH 0x003F8000
+#define AR_PHY_AGC_COARSE_HIGH_S 15
+#define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
+#define AR_PHY_AGC_COARSE_PWR_CONST_S 0
+#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
+#define AR_PHY_FIND_SIG_FIRSTEP_S 12
+#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
+#define AR_PHY_FIND_SIG_FIRPWR_S 18
+#define AR_PHY_FIND_SIG_FIRPWR_SIGN_BIT 25
+#define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
+#define AR_PHY_FIND_SIG_RELPWR_S 6
+#define AR_PHY_FIND_SIG_RELPWR_SIGN_BIT 11
+#define AR_PHY_FIND_SIG_RELSTEP 0x1f
+#define AR_PHY_FIND_SIG_RELSTEP_S 0
+#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT 5
+#define AR_PHY_RESTART_DIV_GC 0x001C0000
+#define AR_PHY_RESTART_DIV_GC_S 18
+#define AR_PHY_RESTART_ENA 0x01
+#define AR_PHY_DC_RESTART_DIS 0x40000000
+
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON_S 24
+#define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
+#define AR_PHY_TPC_OLPC_GAIN_DELTA_S 16
+
+#define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
+#define AR_PHY_TPC_6_ERROR_EST_MODE_S 24
+
+/*
+ * SM Register Map
+ */
+#define AR_SM_BASE 0xa200
+
+#define AR_PHY_D2_CHIP_ID AR_SM_BASE + 0x0
+#define AR_PHY_GEN_CTRL AR_SM_BASE + 0x4
+#define AR_PHY_MODE AR_SM_BASE + 0x8
+#define AR_PHY_ACTIVE AR_SM_BASE + 0xc
+#define AR_PHY_SPUR_MASK_A AR_SM_BASE + 0x20
+#define AR_PHY_SPUR_MASK_B AR_SM_BASE + 0x24
+#define AR_PHY_SPECTRAL_SCAN AR_SM_BASE + 0x28
+#define AR_PHY_RADAR_BW_FILTER AR_SM_BASE + 0x2c
+#define AR_PHY_SEARCH_START_DELAY AR_SM_BASE + 0x30
+#define AR_PHY_MAX_RX_LEN AR_SM_BASE + 0x34
+#define AR_PHY_FRAME_CTL AR_SM_BASE + 0x38
+#define AR_PHY_RFBUS_REQ AR_SM_BASE + 0x3c
+#define AR_PHY_RFBUS_GRANT AR_SM_BASE + 0x40
+#define AR_PHY_RIFS AR_SM_BASE + 0x44
+#define AR_PHY_RX_CLR_DELAY AR_SM_BASE + 0x50
+#define AR_PHY_RX_DELAY AR_SM_BASE + 0x54
+
+#define AR_PHY_XPA_TIMING_CTL AR_SM_BASE + 0x64
+#define AR_PHY_MISC_PA_CTL AR_SM_BASE + 0x80
+#define AR_PHY_SWITCH_CHAIN_0 AR_SM_BASE + 0x84
+#define AR_PHY_SWITCH_COM AR_SM_BASE + 0x88
+#define AR_PHY_SWITCH_COM_2 AR_SM_BASE + 0x8c
+#define AR_PHY_RX_CHAINMASK AR_SM_BASE + 0xa0
+#define AR_PHY_CAL_CHAINMASK AR_SM_BASE + 0xc0
+#define AR_PHY_AGC_CONTROL AR_SM_BASE + 0xc4
+#define AR_PHY_CALMODE AR_SM_BASE + 0xc8
+#define AR_PHY_FCAL_1 AR_SM_BASE + 0xcc
+#define AR_PHY_FCAL_2_0 AR_SM_BASE + 0xd0
+#define AR_PHY_DFT_TONE_CTL_0 AR_SM_BASE + 0xd4
+#define AR_PHY_CL_CAL_CTL AR_SM_BASE + 0xd8
+#define AR_PHY_CL_TAB_0 AR_SM_BASE + 0x100
+#define AR_PHY_SYNTH_CONTROL AR_SM_BASE + 0x140
+#define AR_PHY_ADDAC_CLK_SEL AR_SM_BASE + 0x144
+#define AR_PHY_PLL_CTL AR_SM_BASE + 0x148
+#define AR_PHY_ANALOG_SWAP AR_SM_BASE + 0x14c
+#define AR_PHY_ADDAC_PARA_CTL AR_SM_BASE + 0x150
+#define AR_PHY_XPA_CFG AR_SM_BASE + 0x158
+
+#define AR_PHY_TEST AR_SM_BASE + 0x160
+
+#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
+#define AR_PHY_TEST_BBB_OBS_SEL_S 19
+
+#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23
+#define AR_PHY_TEST_RX_OBS_SEL_BIT5 (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)
+
+#define AR_PHY_TEST_CHAIN_SEL 0xC0000000
+#define AR_PHY_TEST_CHAIN_SEL_S 30
+
+#define AR_PHY_TEST_CTL_STATUS AR_SM_BASE + 0x164
+#define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
+#define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
+#define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
+#define AR_PHY_TEST_CTL_TX_OBS_SEL_S 2
+#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
+#define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL_S 5
+#define AR_PHY_TEST_CTL_TSTADC_EN 0x100
+#define AR_PHY_TEST_CTL_TSTADC_EN_S 8
+#define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
+#define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10
+
+
+#define AR_PHY_TSTDAC AR_SM_BASE + 0x168
+
+#define AR_PHY_CHAN_STATUS AR_SM_BASE + 0x16c
+#define AR_PHY_CHAN_INFO_MEMORY AR_SM_BASE + 0x170
+#define AR_PHY_CHNINFO_NOISEPWR AR_SM_BASE + 0x174
+#define AR_PHY_CHNINFO_GAINDIFF AR_SM_BASE + 0x178
+#define AR_PHY_CHNINFO_FINETIM AR_SM_BASE + 0x17c
+#define AR_PHY_CHAN_INFO_GAIN_0 AR_SM_BASE + 0x180
+#define AR_PHY_SCRAMBLER_SEED AR_SM_BASE + 0x190
+#define AR_PHY_CCK_TX_CTRL AR_SM_BASE + 0x194
+
+#define AR_PHY_HEAVYCLIP_CTL AR_SM_BASE + 0x1a4
+#define AR_PHY_HEAVYCLIP_20 AR_SM_BASE + 0x1a8
+#define AR_PHY_HEAVYCLIP_40 AR_SM_BASE + 0x1ac
+#define AR_PHY_ILLEGAL_TXRATE AR_SM_BASE + 0x1b0
+
+#define AR_PHY_PWRTX_MAX AR_SM_BASE + 0x1f0
+#define AR_PHY_POWER_TX_SUB AR_SM_BASE + 0x1f4
+
+#define AR_PHY_TPC_4_B0 AR_SM_BASE + 0x204
+#define AR_PHY_TPC_5_B0 AR_SM_BASE + 0x208
+#define AR_PHY_TPC_6_B0 AR_SM_BASE + 0x20c
+#define AR_PHY_TPC_11_B0 AR_SM_BASE + 0x220
+#define AR_PHY_TPC_18 AR_SM_BASE + 0x23c
+#define AR_PHY_TPC_19 AR_SM_BASE + 0x240
+
+#define AR_PHY_TX_FORCED_GAIN AR_SM_BASE + 0x258
+
+#define AR_PHY_PDADC_TAB_0 AR_SM_BASE + 0x280
+
+#define AR_PHY_TX_IQCAL_CONTROL_1 AR_SM_BASE + 0x448
+#define AR_PHY_TX_IQCAL_START AR_SM_BASE + 0x440
+#define AR_PHY_TX_IQCAL_STATUS_B0 AR_SM_BASE + 0x48c
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0 AR_SM_BASE + 0x450
+
+#define AR_PHY_PANIC_WD_STATUS AR_SM_BASE + 0x5c0
+#define AR_PHY_PANIC_WD_CTL_1 AR_SM_BASE + 0x5c4
+#define AR_PHY_PANIC_WD_CTL_2 AR_SM_BASE + 0x5c8
+#define AR_PHY_BT_CTL AR_SM_BASE + 0x5cc
+#define AR_PHY_ONLY_WARMRESET AR_SM_BASE + 0x5d0
+#define AR_PHY_ONLY_CTL AR_SM_BASE + 0x5d4
+#define AR_PHY_ECO_CTRL AR_SM_BASE + 0x5dc
+#define AR_PHY_BB_THERM_ADC_1 AR_SM_BASE + 0x248
+
+#define AR_PHY_65NM_CH0_SYNTH4 0x1608c
+#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT 0x00000002
+#define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S 1
+#define AR_PHY_65NM_CH0_SYNTH7 0x16098
+#define AR_PHY_65NM_CH0_BIAS1 0x160c0
+#define AR_PHY_65NM_CH0_BIAS2 0x160c4
+#define AR_PHY_65NM_CH0_BIAS4 0x160cc
+#define AR_PHY_65NM_CH0_RXTX4 0x1610c
+#define AR_PHY_65NM_CH0_THERM 0x16290
+
+#define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000
+#define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
+#define AR_PHY_65NM_CH0_THERM_START 0x20000000
+#define AR_PHY_65NM_CH0_THERM_START_S 29
+#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT 0x0000ff00
+#define AR_PHY_65NM_CH0_THERM_SAR_ADC_OUT_S 8
+
+#define AR_PHY_65NM_CH0_RXTX1 0x16100
+#define AR_PHY_65NM_CH0_RXTX2 0x16104
+#define AR_PHY_65NM_CH1_RXTX1 0x16500
+#define AR_PHY_65NM_CH1_RXTX2 0x16504
+#define AR_PHY_65NM_CH2_RXTX1 0x16900
+#define AR_PHY_65NM_CH2_RXTX2 0x16904
+
+#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
+#define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S 19
+#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
+#define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT_S 22
+#define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
+#define AR_PHY_LNAGAIN_LONG_SHIFT_S 29
+#define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
+#define AR_PHY_MXRGAIN_LONG_SHIFT_S 24
+#define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
+#define AR_PHY_VGAGAIN_LONG_SHIFT_S 26
+#define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
+#define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
+#define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
+#define AR_PHY_MANRXGAIN_LONG_SHIFT_S 1
+
+/*
+ * SM Field Definitions
+ */
+#define AR_PHY_CL_CAL_ENABLE 0x00000002
+#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
+#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
+#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
+
+#define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
+
+#define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
+#define AR_PHY_FCAL20_CAP_STATUS_0_S 20
+
+#define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
+#define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
+#define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
+#define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
+#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
+#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
+#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
+#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
+#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
+#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
+#define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
+#define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
+#define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, not tx */
+#define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
+#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
+
+#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */
+#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */
+#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */
+#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */
+#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */
+#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */
+#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */
+#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */
+
+#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0
+#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6
+
+#define AR_PHY_CALMODE_IQ 0x00000000
+#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
+#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
+#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
+#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
+#define AR_PHY_MODE_OFDM 0x00000000
+#define AR_PHY_MODE_CCK 0x00000001
+#define AR_PHY_MODE_DYNAMIC 0x00000004
+#define AR_PHY_MODE_HALF 0x00000020
+#define AR_PHY_MODE_QUARTER 0x00000040
+#define AR_PHY_MAC_CLK_MODE 0x00000080
+#define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
+#define AR_PHY_MODE_SVD_HALF 0x00000200
+#define AR_PHY_ACTIVE_EN 0x00000001
+#define AR_PHY_ACTIVE_DIS 0x00000000
+#define AR_PHY_FORCE_XPA_CFG 0x000000001
+#define AR_PHY_FORCE_XPA_CFG_S 0
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF_S 24
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
+#define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF_S 16
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON_S 8
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
+#define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
+#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
+#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
+#define AR_PHY_TX_END_DATA_START 0x000000FF
+#define AR_PHY_TX_END_DATA_START_S 0
+#define AR_PHY_TX_END_PA_ON 0x0000FF00
+#define AR_PHY_TX_END_PA_ON_S 8
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
+#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
+#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
+#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
+#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
+#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
+#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
+#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
+#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
+#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
+#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
+#define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
+#define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
+#define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
+#define AR_PHY_TXGAIN_FORCE 0x00000001
+#define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
+#define AR_PHY_TXGAIN_FORCED_PADVGNRA_S 10
+#define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
+#define AR_PHY_TXGAIN_FORCED_PADVGNRB_S 14
+#define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
+#define AR_PHY_TXGAIN_FORCED_PADVGNRD_S 22
+#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
+#define AR_PHY_TXGAIN_FORCED_TXMXRGAIN_S 6
+#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
+#define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN_S 1
+
+#define AR_PHY_POWER_TX_RATE1 0x9934
+#define AR_PHY_POWER_TX_RATE2 0x9938
+#define AR_PHY_POWER_TX_RATE_MAX 0x993c
+#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
+#define PHY_AGC_CLR 0x10000000
+#define RFSILENT_BB 0x00002000
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
+#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
+#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
+#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
+#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
+#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
+#define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
+#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
+#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
+#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
+#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
+#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
+#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
+#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
+#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
+#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
+#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
+#define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
+#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
+#define AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_S 18
+#define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
+#define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
+
+#define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x00003fff
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S 0
+
+#define AR_PHY_TPC_18_THERM_CAL_VALUE 0xff
+#define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
+#define AR_PHY_TPC_19_ALPHA_THERM 0xff
+#define AR_PHY_TPC_19_ALPHA_THERM_S 0
+
+#define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
+#define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
+
+#define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
+#define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
+
+/*
+ * Channel 1 Register Map
+ */
+#define AR_CHAN1_BASE 0xa800
+
+#define AR_PHY_EXT_CCA_1 AR_CHAN1_BASE + 0x30
+#define AR_PHY_TX_PHASE_RAMP_1 AR_CHAN1_BASE + 0xd0
+#define AR_PHY_ADC_GAIN_DC_CORR_1 AR_CHAN1_BASE + 0xd4
+
+#define AR_PHY_SPUR_REPORT_1 AR_CHAN1_BASE + 0xa8
+#define AR_PHY_CHAN_INFO_TAB_1 AR_CHAN1_BASE + 0x300
+#define AR_PHY_RX_IQCAL_CORR_B1 AR_CHAN1_BASE + 0xdc
+
+/*
+ * Channel 1 Field Definitions
+ */
+#define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
+#define AR_PHY_CH1_EXT_MINCCA_PWR_S 16
+
+/*
+ * AGC 1 Register Map
+ */
+#define AR_AGC1_BASE 0xae00
+
+#define AR_PHY_FORCEMAX_GAINS_1 AR_AGC1_BASE + 0x4
+#define AR_PHY_EXT_ATTEN_CTL_1 AR_AGC1_BASE + 0x18
+#define AR_PHY_CCA_1 AR_AGC1_BASE + 0x1c
+#define AR_PHY_CCA_CTRL_1 AR_AGC1_BASE + 0x20
+#define AR_PHY_RSSI_1 AR_AGC1_BASE + 0x180
+#define AR_PHY_SPUR_CCK_REP_1 AR_AGC1_BASE + 0x184
+#define AR_PHY_RX_OCGAIN_2 AR_AGC1_BASE + 0x200
+
+/*
+ * AGC 1 Field Definitions
+ */
+#define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
+#define AR_PHY_CH1_MINCCA_PWR_S 20
+
+/*
+ * SM 1 Register Map
+ */
+#define AR_SM1_BASE 0xb200
+
+#define AR_PHY_SWITCH_CHAIN_1 AR_SM1_BASE + 0x84
+#define AR_PHY_FCAL_2_1 AR_SM1_BASE + 0xd0
+#define AR_PHY_DFT_TONE_CTL_1 AR_SM1_BASE + 0xd4
+#define AR_PHY_CL_TAB_1 AR_SM1_BASE + 0x100
+#define AR_PHY_CHAN_INFO_GAIN_1 AR_SM1_BASE + 0x180
+#define AR_PHY_TPC_4_B1 AR_SM1_BASE + 0x204
+#define AR_PHY_TPC_5_B1 AR_SM1_BASE + 0x208
+#define AR_PHY_TPC_6_B1 AR_SM1_BASE + 0x20c
+#define AR_PHY_TPC_11_B1 AR_SM1_BASE + 0x220
+#define AR_PHY_PDADC_TAB_1 AR_SM1_BASE + 0x240
+#define AR_PHY_TX_IQCAL_STATUS_B1 AR_SM1_BASE + 0x48c
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1 AR_SM1_BASE + 0x450
+
+/*
+ * Channel 2 Register Map
+ */
+#define AR_CHAN2_BASE 0xb800
+
+#define AR_PHY_EXT_CCA_2 AR_CHAN2_BASE + 0x30
+#define AR_PHY_TX_PHASE_RAMP_2 AR_CHAN2_BASE + 0xd0
+#define AR_PHY_ADC_GAIN_DC_CORR_2 AR_CHAN2_BASE + 0xd4
+
+#define AR_PHY_SPUR_REPORT_2 AR_CHAN2_BASE + 0xa8
+#define AR_PHY_CHAN_INFO_TAB_2 AR_CHAN2_BASE + 0x300
+#define AR_PHY_RX_IQCAL_CORR_B2 AR_CHAN2_BASE + 0xdc
+
+/*
+ * Channel 2 Field Definitions
+ */
+#define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
+#define AR_PHY_CH2_EXT_MINCCA_PWR_S 16
+/*
+ * AGC 2 Register Map
+ */
+#define AR_AGC2_BASE 0xbe00
+
+#define AR_PHY_FORCEMAX_GAINS_2 AR_AGC2_BASE + 0x4
+#define AR_PHY_EXT_ATTEN_CTL_2 AR_AGC2_BASE + 0x18
+#define AR_PHY_CCA_2 AR_AGC2_BASE + 0x1c
+#define AR_PHY_CCA_CTRL_2 AR_AGC2_BASE + 0x20
+#define AR_PHY_RSSI_2 AR_AGC2_BASE + 0x180
+
+/*
+ * AGC 2 Field Definitions
+ */
+#define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
+#define AR_PHY_CH2_MINCCA_PWR_S 20
+
+/*
+ * SM 2 Register Map
+ */
+#define AR_SM2_BASE 0xc200
+
+#define AR_PHY_SWITCH_CHAIN_2 AR_SM2_BASE + 0x84
+#define AR_PHY_FCAL_2_2 AR_SM2_BASE + 0xd0
+#define AR_PHY_DFT_TONE_CTL_2 AR_SM2_BASE + 0xd4
+#define AR_PHY_CL_TAB_2 AR_SM2_BASE + 0x100
+#define AR_PHY_CHAN_INFO_GAIN_2 AR_SM2_BASE + 0x180
+#define AR_PHY_TPC_4_B2 AR_SM2_BASE + 0x204
+#define AR_PHY_TPC_5_B2 AR_SM2_BASE + 0x208
+#define AR_PHY_TPC_6_B2 AR_SM2_BASE + 0x20c
+#define AR_PHY_TPC_11_B2 AR_SM2_BASE + 0x220
+#define AR_PHY_PDADC_TAB_2 AR_SM2_BASE + 0x240
+#define AR_PHY_TX_IQCAL_STATUS_B2 AR_SM2_BASE + 0x48c
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2 AR_SM2_BASE + 0x450
+
+#define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
+
+/*
+ * AGC 3 Register Map
+ */
+#define AR_AGC3_BASE 0xce00
+
+#define AR_PHY_RSSI_3 AR_AGC3_BASE + 0x180
+
+/*
+ * Misc helper defines
+ */
+#define AR_PHY_CHAIN_OFFSET (AR_CHAN1_BASE - AR_CHAN_BASE)
+
+#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (AR_PHY_ADC_GAIN_DC_CORR_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_NEW_ADC_DC_GAIN_CORR_9300_10(_i) (AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_SWITCH_CHAIN(_i) (AR_PHY_SWITCH_CHAIN_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_EXT_ATTEN_CTL(_i) (AR_PHY_EXT_ATTEN_CTL_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+
+#define AR_PHY_RXGAIN(_i) (AR_PHY_FORCEMAX_GAINS_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_TPCRG5(_i) (AR_PHY_TPC_5_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_PDADC_TAB(_i) (AR_PHY_PDADC_TAB_0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+
+#define AR_PHY_CAL_MEAS_0(_i) (AR_PHY_IQ_ADC_MEAS_0_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_1(_i) (AR_PHY_IQ_ADC_MEAS_1_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_2(_i) (AR_PHY_IQ_ADC_MEAS_2_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_3(_i) (AR_PHY_IQ_ADC_MEAS_3_B0 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_0_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_1_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_2_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
+#define AR_PHY_CAL_MEAS_3_9300_10(_i) (AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 + (AR_PHY_CHAIN_OFFSET * (_i)))
+
+#define AR_PHY_BB_PANIC_NON_IDLE_ENABLE 0x00000001
+#define AR_PHY_BB_PANIC_IDLE_ENABLE 0x00000002
+#define AR_PHY_BB_PANIC_IDLE_MASK 0xFFFF0000
+#define AR_PHY_BB_PANIC_NON_IDLE_MASK 0x0000FFFC
+
+#define AR_PHY_BB_PANIC_RST_ENABLE 0x00000002
+#define AR_PHY_BB_PANIC_IRQ_ENABLE 0x00000004
+#define AR_PHY_BB_PANIC_CNTL2_MASK 0xFFFFFFF9
+
+#define AR_PHY_BB_WD_STATUS 0x00000007
+#define AR_PHY_BB_WD_STATUS_S 0
+#define AR_PHY_BB_WD_DET_HANG 0x00000008
+#define AR_PHY_BB_WD_DET_HANG_S 3
+#define AR_PHY_BB_WD_RADAR_SM 0x000000F0
+#define AR_PHY_BB_WD_RADAR_SM_S 4
+#define AR_PHY_BB_WD_RX_OFDM_SM 0x00000F00
+#define AR_PHY_BB_WD_RX_OFDM_SM_S 8
+#define AR_PHY_BB_WD_RX_CCK_SM 0x0000F000
+#define AR_PHY_BB_WD_RX_CCK_SM_S 12
+#define AR_PHY_BB_WD_TX_OFDM_SM 0x000F0000
+#define AR_PHY_BB_WD_TX_OFDM_SM_S 16
+#define AR_PHY_BB_WD_TX_CCK_SM 0x00F00000
+#define AR_PHY_BB_WD_TX_CCK_SM_S 20
+#define AR_PHY_BB_WD_AGC_SM 0x0F000000
+#define AR_PHY_BB_WD_AGC_SM_S 24
+#define AR_PHY_BB_WD_SRCH_SM 0xF0000000
+#define AR_PHY_BB_WD_SRCH_SM_S 28
+
+#define AR_PHY_BB_WD_STATUS_CLR 0x00000008
+
+#endif /* AR9003_PHY_H */
--
1.6.3.3
next prev parent reply other threads:[~2010-04-08 19:27 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-08 19:25 [PATCH 000/102] ath9k: add AR9003 support Luis R. Rodriguez
2010-04-08 19:25 ` [PATCH 001/102] ath9k_hw: start building an abstraction layer for hardware routines Luis R. Rodriguez
2010-04-08 19:25 ` [PATCH 002/102] ath9k_hw: add silicon revision macros for AR9300 Luis R. Rodriguez
2010-04-08 20:57 ` Pavel Roskin
2010-04-08 19:25 ` [PATCH 003/102] ath9k_hw: add a macro for abstracting generic timer access Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 004/102] ath9k_hw: fix a missing hex prefix for a register mask Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 005/102] ath9k_hw: add simple register abstraction for some AR9300 registers Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 006/102] ath9k_hw: add support for GPIO differences on AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 007/102] ath9k_hw: AR9003 does not have AR_RC_AHB skip its setting Luis R. Rodriguez
2010-04-08 21:18 ` Pavel Roskin
2010-04-08 21:23 ` Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 008/102] ath9k_hw: remove wrapper ath9k_hw_write_regs() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 009/102] ath9k_hw: Move some RF ops to the private callbacks Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 010/102] ath9k_hw: skip PLL initialization on AR9003 on Power-On-Reset Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 011/102] ath9k_hw: add some comments for ath9k_set_power_network_sleep() Luis R. Rodriguez
2010-04-09 20:29 ` Pavel Roskin
2010-04-08 19:26 ` [PATCH 012/102] ath9k_hw: add a private callback for PLL control computation Luis R. Rodriguez
2010-04-13 19:54 ` John W. Linville
2010-04-13 20:15 ` Felix Fietkau
2010-04-13 21:42 ` Luis R. Rodriguez
2010-04-13 23:38 ` John W. Linville
2010-04-13 23:43 ` Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 013/102] ath9k_hw: Add the PCI IDs for AR9300 and fill up the pci_id_tables Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 014/102] ath9k_hw: Add AR9003 PHY support Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 015/102] ath9k_hw: move init config and default after chip is up Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 016/102] ath9k_hw: add the AR9003 ar9003_hw_macversion_supported() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 017/102] ath9k_hw: enable all ANI functionality for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 018/102] ath9k_hw: Add hw cap flag for EDMA for the AR9003 family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 019/102] ath9k_hw: Fill few hw cap for edma Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 020/102] ath9k_hw: Add abstraction for rx enable Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 021/102] ath9k_hw: Fill rx_enable() for the AR9003 hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 022/102] ath9k_hw: Add few routines for rx edma support Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 023/102] ath9k_hw: update the chip tests for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 024/102] ath9k_hw: prevent reset control register zeroing on AR9003 reset Luis R. Rodriguez
2010-04-08 19:26 ` Luis R. Rodriguez [this message]
2010-04-08 19:26 ` [PATCH 026/102] ath9k_hw: add common channel select helpers for ar900[23] Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 027/102] ath9k_hw: Set the channel on AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 028/102] ath9k_hw: Implement PLL control " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 029/102] ath9k_hw: Implement spur mitigation " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 030/102] ath9k_hw: split initvals.h by hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 031/102] ath9k_hw: run Lindent on intivals Luis R. Rodriguez
2010-04-09 20:48 ` Pavel Roskin
2010-04-09 21:32 ` Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 032/102] ath9k_hw: add initvals for the AR9003 hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 033/102] ath9k_hw: add helpers for processing the AR9003 INI Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 034/102] ath9k_hw: Split off ANI control to the PHY ops Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 035/102] ath9k_hw: add all the AR9003 PHY callbacks Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 036/102] ath9k_hw: Define tx control struct for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 037/102] ath9k_hw: Move code which populates ds_data to ath9k_hw Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 038/102] ath9k_hw: Add abstraction to set/get link pointer Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 039/102] ath9k: Use abstraction to get " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 040/102] ath9k: Use memcpy in ath_clone_txbuf() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 041/102] ath9k: Remove ATH9K_TX_SW_ABORTED and introduce a bool for this purpose Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 042/102] ath9k: Make bf_desc of ath_buf opaque Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 043/102] ath9k: Add Rx EDMA support Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 044/102] ath9k_hw: Split out the function for reading the noise floor Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 045/102] ath9k_hw: Get rid of eep_map and reorganize the functions Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 046/102] ath9k_hw: add a helper for Power Amplifier calibration for AR9002 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 047/102] ath9k_hw: add a helper for the OLC tem compensation " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 048/102] ath9k_hw: rename PA calib for AR9287 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 049/102] ath9k_hw: shift code for AR9280 OLC temp comp Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 050/102] ath9k_hw: move the AR9280 OLC temp comp to its own helper Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 051/102] ath9k_hw: simplify OLC temp compensation for AR9002 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 052/102] ath9k_hw: rename the PA calib routines to match their families Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 053/102] ath9k_hw: rename getNoiseFloorThresh() to ath9k_hw_loadnf() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 054/102] ath9k_hw: move the cal AR9100 calibration settings Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 055/102] ath9k_hw: split calib code by hardware families Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 056/102] ath9k_hw: add the AR9003 ar9003_hw_init_cal callback Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 057/102] ath9k_hw: add the config_pci_powersave AR9003 callback Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 058/102] ath9k_hw: split the generic hardware code by hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 059/102] ath9k_hw: move the cck channel 14 INI to the AR9002 hw code Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 060/102] ath9k_hw: move TX/RX gain INI stuff to its own hardware family code Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 061/102] ath9k_hw: Abstract the routine which returns interrupt status Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 062/102] ath9k_hw: Initialize interrupt mask for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 063/102] ath9k_hw: abstract the AR_PHY_AGC_CONTROL register access Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 064/102] ath9k_hw: abstract loading noisefloor Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 065/102] ath9k_hw: fill in the callbacks for calibration for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 066/102] ath9k_hw: add a helper for changing the TX/RX masks Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 067/102] ath9k_hw: complete AR9003 calibration Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 068/102] ath9k_hw: rename eep_AR9287_ops to eep_ar9287_ops Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 069/102] ath9k_hw: restore mac address reading logic Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 070/102] ath9k_hw: Implement AR9003 eeprom callbacks Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 071/102] ath9k_hw: add OFDM spur mitigation for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 072/102] ath9k_hw: Fill get_isr() " Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 073/102] ath9k_hw: move AR9280 PCI EEPROM fix to ar9002_hw.c Luis R. Rodriguez
2010-04-09 21:04 ` Pavel Roskin
2010-04-09 21:13 ` Felix Fietkau
2010-04-08 19:27 ` [PATCH 074/102] ath9k_hw: simplify the AR9280 PCI EEPROM fix Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 075/102] ath9k_hw: move the RF claim stuff to AR9002 hardware family Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 076/102] ath9k_hw: Configure Tx interrupt mitigation timer Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 077/102] ath9k_hw: add the AR9300 SREV hw name print Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 078/102] ath9k_hw: add TX/RX gain register initialization for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 079/102] ath9k_hw: Update ath9k_hw_set_dma for AR9300 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 080/102] ath9k_hw: Handle big-endian access for AR9300 EEPROM reads Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 081/102] ath9k_hw: skip asynch fifo enablement to AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 082/102] ath9k_hw: skip WEP aggregation enable code for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 083/102] ath9k_hw: Fix internal regulator setting on AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 084/102] ath9k: Load SW filtered NF values and start NF cal during full reset for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 085/102] ath9k_hw: Define abstraction for tx desc access Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 086/102] ath9k_hw: Add function to configure tx status ring buffer Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 087/102] ath9k_hw: Fill descriptor abstrations for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 088/102] ath9k: add RXLP and RXHP to debugfs counters Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 089/102] ath9k_hw: enable CRC check of descriptors for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 090/102] ath9k_hw: set cwmin and cwmax to 0 for for AR9003 upon txq reset Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 091/102] ath9k_hw: move AR9002 mac ops to its own file Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 092/102] ath9k: Setup appropriate tx desc for regular dma and edma Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 093/102] ath9k: Initialize and configure tx status for EDMA Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 094/102] ath9k_hw: Compute pointer checksum over the link descriptor Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 095/102] ath9k: Add frame onto hw tx fifo for edma Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 096/102] mac80211: add LDPC control flag Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 097/102] ath9k_hw: add LDPC support for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 098/102] ath9k: add LDPC support Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 099/102] ath9k: Enable TXOK and TXERR interrupts for TX EDMA Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 100/102] ath9k: Handle Tx interrupt for EDMA Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 101/102] ath9k_hw: Abort rx if hw is not coming out of full sleep in reset Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 102/102] ath9k_hw: add the PCI ID for the first AR9300 device Luis R. Rodriguez
2010-04-09 21:12 ` [PATCH 000/102] ath9k: add AR9003 support Pavel Roskin
2010-04-12 19:44 ` Luis R. Rodriguez
2010-04-13 19:58 ` John W. Linville
2010-04-13 20:08 ` Felix Fietkau
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