From: "Luis R. Rodriguez" <lrodriguez@atheros.com>
To: linville@tuxdriver.com
Cc: linux-wireless@vger.kernel.org,
"Luis R. Rodriguez" <lrodriguez@atheros.com>
Subject: [PATCH 071/102] ath9k_hw: add OFDM spur mitigation for AR9003
Date: Thu, 8 Apr 2010 15:27:07 -0400 [thread overview]
Message-ID: <1270754858-26266-72-git-send-email-lrodriguez@atheros.com> (raw)
In-Reply-To: <1270754858-26266-1-git-send-email-lrodriguez@atheros.com>
We add this now as OFDM spur mitigation required accessing
the EEPROM for the AR9003 devices.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
---
drivers/net/wireless/ath/ath9k/ar9002_phy.h | 2 -
drivers/net/wireless/ath/ath9k/ar9003_phy.c | 209 ++++++++++++++++++++++++++-
drivers/net/wireless/ath/ath9k/ar9003_phy.h | 54 +++++++
drivers/net/wireless/ath/ath9k/hw.h | 2 +
drivers/net/wireless/ath/ath9k/phy.h | 3 +
5 files changed, 267 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
index 65510ab..07be17a 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
@@ -289,8 +289,6 @@
#define AR_PHY_TIMING11 0x99a0
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
-#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
-#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index c60f39f..e9b8474 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -103,7 +103,8 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
*
* Spur mitigation for MRC CCK
*/
-static void ar9003_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
+static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
+ struct ath9k_channel *chan)
{
u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
int cur_bb_spur, negative = 0, cck_spur_freq;
@@ -153,6 +154,212 @@ static void ar9003_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *cha
AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
}
+/* Clean all spur register fields */
+static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
+{
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+ AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
+
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
+ REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+ AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+ AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
+ REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+ AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
+ REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+ AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
+ REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+ AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+ AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
+}
+
+static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
+ int freq_offset,
+ int spur_freq_sd,
+ int spur_delta_phase,
+ int spur_subchannel_sd)
+{
+ int mask_index = 0;
+
+ /* OFDM Spur mitigation */
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
+ REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
+ AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING11,
+ AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
+
+ if (REG_READ_FIELD(ah, AR_PHY_MODE,
+ AR_PHY_MODE_DYNAMIC) == 0x1)
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
+
+ mask_index = (freq_offset << 4) / 5;
+ if (mask_index < 0)
+ mask_index = mask_index - 1;
+
+ mask_index = mask_index & 0x7f;
+
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_TIMING4,
+ AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
+ REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+ AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+ AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
+ REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+ AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
+ REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
+ AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
+ REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
+ AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
+ AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
+ REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
+ AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
+}
+
+static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
+ struct ath9k_channel *chan,
+ int freq_offset)
+{
+ int spur_freq_sd = 0;
+ int spur_subchannel_sd = 0;
+ int spur_delta_phase = 0;
+
+ if (IS_CHAN_HT40(chan)) {
+ if (freq_offset < 0) {
+ if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+ AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
+ spur_subchannel_sd = 1;
+ else
+ spur_subchannel_sd = 0;
+
+ spur_freq_sd = ((freq_offset + 10) << 9) / 11;
+
+ } else {
+ if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+ AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
+ spur_subchannel_sd = 0;
+ else
+ spur_subchannel_sd = 1;
+
+ spur_freq_sd = ((freq_offset - 10) << 9) / 11;
+
+ }
+
+ spur_delta_phase = (freq_offset << 17) / 5;
+
+ } else {
+ spur_subchannel_sd = 0;
+ spur_freq_sd = (freq_offset << 9) /11;
+ spur_delta_phase = (freq_offset << 18) / 5;
+ }
+
+ spur_freq_sd = spur_freq_sd & 0x3ff;
+ spur_delta_phase = spur_delta_phase & 0xfffff;
+
+ ar9003_hw_spur_ofdm(ah,
+ freq_offset,
+ spur_freq_sd,
+ spur_delta_phase,
+ spur_subchannel_sd);
+}
+
+/* Spur mitigation for OFDM */
+static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+{
+ int synth_freq;
+ int range = 10;
+ int freq_offset = 0;
+ int mode;
+ u8* spurChansPtr;
+ unsigned int i;
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+ if (IS_CHAN_5GHZ(chan)) {
+ spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
+ mode = 0;
+ }
+ else {
+ spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
+ mode = 1;
+ }
+
+ if (spurChansPtr[0] == 0)
+ return; /* No spur in the mode */
+
+ if (IS_CHAN_HT40(chan)) {
+ range = 19;
+ if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+ AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
+ synth_freq = chan->channel - 10;
+ else
+ synth_freq = chan->channel + 10;
+ } else {
+ range = 10;
+ synth_freq = chan->channel;
+ }
+
+ ar9003_hw_spur_ofdm_clear(ah);
+
+ for (i = 0; spurChansPtr[i] && i < 5; i++) {
+ freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
+ if (abs(freq_offset) < range) {
+ ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
+ break;
+ }
+ }
+}
+
+static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+{
+ ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
+ ar9003_hw_spur_mitigate_ofdm(ah, chan);
+}
+
static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
struct ath9k_channel *chan)
{
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 1aeeba3..e330382 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -33,6 +33,30 @@
#define AR_PHY_RX_IQCAL_CORR_B0 AR_CHAN_BASE + 0xdc
#define AR_PHY_TX_IQCAL_CONTROL_3 AR_CHAN_BASE + 0xb0
+#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
+
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
+#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
+
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC_S 30
+
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
+#define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR_S 31
+
+#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
+#define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT_S 26
+
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
+#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM_S 17
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
+#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
+#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
+#define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI_S 8
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
+#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
+
#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
#define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN_S 29
@@ -84,6 +108,17 @@
#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
#define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX_S 12
#define AR_PHY_TIMING4_DO_CAL 0x10000
+
+#define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
+#define AR_PHY_TIMING4_ENABLE_PILOT_MASK_S 28
+#define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
+#define AR_PHY_TIMING4_ENABLE_CHAN_MASK_S 29
+
+#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
+#define AR_PHY_TIMING4_ENABLE_SPUR_FILTER_S 30
+#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
+#define AR_PHY_TIMING4_ENABLE_SPUR_RSSI_S 31
+
#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
@@ -107,6 +142,8 @@
#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
+#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
+#define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD_S 28
#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
#define AR_PHY_EXT_CCA_THRESH62_S 16
@@ -184,6 +221,16 @@
#define AR_PHY_ML_CNTL_2 AR_MRC_BASE + 0x1c
#define AR_PHY_TST_ADC AR_MRC_BASE + 0x20
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_S 5
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
+#define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
+
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_S 5
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
+#define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
+
/*
* MRC Feild Definitions
*/
@@ -372,6 +419,11 @@
#define AR_PHY_ADDAC_PARA_CTL AR_SM_BASE + 0x150
#define AR_PHY_XPA_CFG AR_SM_BASE + 0x158
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_S 10
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
+#define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
+
#define AR_PHY_TEST AR_SM_BASE + 0x160
#define AR_PHY_TEST_BBB_OBS_SEL 0x780000
@@ -499,6 +551,7 @@
#define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
#define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
#define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
+#define AR_PHY_GC_DYN2040_PRI_CH_S 4
#define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
#define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
#define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
@@ -516,6 +569,7 @@
#define AR_PHY_MODE_OFDM 0x00000000
#define AR_PHY_MODE_CCK 0x00000001
#define AR_PHY_MODE_DYNAMIC 0x00000004
+#define AR_PHY_MODE_DYNAMIC_S 2
#define AR_PHY_MODE_HALF 0x00000020
#define AR_PHY_MODE_QUARTER 0x00000040
#define AR_PHY_MAC_CLK_MODE 0x00000080
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 3c48399..84b8922 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -76,6 +76,8 @@
#define REG_RMW_FIELD(_a, _r, _f, _v) \
REG_WRITE(_a, _r, \
(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
+#define REG_READ_FIELD(_a, _r, _f) \
+ (((REG_READ(_a, _r) & _f) >> _f##_S))
#define REG_SET_BIT(_a, _r, _f) \
REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
#define REG_CLR_BIT(_a, _r, _f) \
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 7d397fd..e724c2c 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -59,4 +59,7 @@
(_bank)[i] = INI_RA((_iniarray), i, _col);; \
} while (0)
+#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
+#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
+
#endif
--
1.6.3.3
next prev parent reply other threads:[~2010-04-08 19:27 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-04-08 19:25 [PATCH 000/102] ath9k: add AR9003 support Luis R. Rodriguez
2010-04-08 19:25 ` [PATCH 001/102] ath9k_hw: start building an abstraction layer for hardware routines Luis R. Rodriguez
2010-04-08 19:25 ` [PATCH 002/102] ath9k_hw: add silicon revision macros for AR9300 Luis R. Rodriguez
2010-04-08 20:57 ` Pavel Roskin
2010-04-08 19:25 ` [PATCH 003/102] ath9k_hw: add a macro for abstracting generic timer access Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 004/102] ath9k_hw: fix a missing hex prefix for a register mask Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 005/102] ath9k_hw: add simple register abstraction for some AR9300 registers Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 006/102] ath9k_hw: add support for GPIO differences on AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 007/102] ath9k_hw: AR9003 does not have AR_RC_AHB skip its setting Luis R. Rodriguez
2010-04-08 21:18 ` Pavel Roskin
2010-04-08 21:23 ` Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 008/102] ath9k_hw: remove wrapper ath9k_hw_write_regs() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 009/102] ath9k_hw: Move some RF ops to the private callbacks Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 010/102] ath9k_hw: skip PLL initialization on AR9003 on Power-On-Reset Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 011/102] ath9k_hw: add some comments for ath9k_set_power_network_sleep() Luis R. Rodriguez
2010-04-09 20:29 ` Pavel Roskin
2010-04-08 19:26 ` [PATCH 012/102] ath9k_hw: add a private callback for PLL control computation Luis R. Rodriguez
2010-04-13 19:54 ` John W. Linville
2010-04-13 20:15 ` Felix Fietkau
2010-04-13 21:42 ` Luis R. Rodriguez
2010-04-13 23:38 ` John W. Linville
2010-04-13 23:43 ` Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 013/102] ath9k_hw: Add the PCI IDs for AR9300 and fill up the pci_id_tables Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 014/102] ath9k_hw: Add AR9003 PHY support Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 015/102] ath9k_hw: move init config and default after chip is up Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 016/102] ath9k_hw: add the AR9003 ar9003_hw_macversion_supported() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 017/102] ath9k_hw: enable all ANI functionality for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 018/102] ath9k_hw: Add hw cap flag for EDMA for the AR9003 family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 019/102] ath9k_hw: Fill few hw cap for edma Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 020/102] ath9k_hw: Add abstraction for rx enable Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 021/102] ath9k_hw: Fill rx_enable() for the AR9003 hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 022/102] ath9k_hw: Add few routines for rx edma support Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 023/102] ath9k_hw: update the chip tests for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 024/102] ath9k_hw: prevent reset control register zeroing on AR9003 reset Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 025/102] ath9k_hw: Add AR9003 PHY register definitions Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 026/102] ath9k_hw: add common channel select helpers for ar900[23] Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 027/102] ath9k_hw: Set the channel on AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 028/102] ath9k_hw: Implement PLL control " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 029/102] ath9k_hw: Implement spur mitigation " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 030/102] ath9k_hw: split initvals.h by hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 031/102] ath9k_hw: run Lindent on intivals Luis R. Rodriguez
2010-04-09 20:48 ` Pavel Roskin
2010-04-09 21:32 ` Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 032/102] ath9k_hw: add initvals for the AR9003 hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 033/102] ath9k_hw: add helpers for processing the AR9003 INI Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 034/102] ath9k_hw: Split off ANI control to the PHY ops Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 035/102] ath9k_hw: add all the AR9003 PHY callbacks Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 036/102] ath9k_hw: Define tx control struct for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 037/102] ath9k_hw: Move code which populates ds_data to ath9k_hw Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 038/102] ath9k_hw: Add abstraction to set/get link pointer Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 039/102] ath9k: Use abstraction to get " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 040/102] ath9k: Use memcpy in ath_clone_txbuf() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 041/102] ath9k: Remove ATH9K_TX_SW_ABORTED and introduce a bool for this purpose Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 042/102] ath9k: Make bf_desc of ath_buf opaque Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 043/102] ath9k: Add Rx EDMA support Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 044/102] ath9k_hw: Split out the function for reading the noise floor Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 045/102] ath9k_hw: Get rid of eep_map and reorganize the functions Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 046/102] ath9k_hw: add a helper for Power Amplifier calibration for AR9002 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 047/102] ath9k_hw: add a helper for the OLC tem compensation " Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 048/102] ath9k_hw: rename PA calib for AR9287 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 049/102] ath9k_hw: shift code for AR9280 OLC temp comp Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 050/102] ath9k_hw: move the AR9280 OLC temp comp to its own helper Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 051/102] ath9k_hw: simplify OLC temp compensation for AR9002 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 052/102] ath9k_hw: rename the PA calib routines to match their families Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 053/102] ath9k_hw: rename getNoiseFloorThresh() to ath9k_hw_loadnf() Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 054/102] ath9k_hw: move the cal AR9100 calibration settings Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 055/102] ath9k_hw: split calib code by hardware families Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 056/102] ath9k_hw: add the AR9003 ar9003_hw_init_cal callback Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 057/102] ath9k_hw: add the config_pci_powersave AR9003 callback Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 058/102] ath9k_hw: split the generic hardware code by hardware family Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 059/102] ath9k_hw: move the cck channel 14 INI to the AR9002 hw code Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 060/102] ath9k_hw: move TX/RX gain INI stuff to its own hardware family code Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 061/102] ath9k_hw: Abstract the routine which returns interrupt status Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 062/102] ath9k_hw: Initialize interrupt mask for AR9003 Luis R. Rodriguez
2010-04-08 19:26 ` [PATCH 063/102] ath9k_hw: abstract the AR_PHY_AGC_CONTROL register access Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 064/102] ath9k_hw: abstract loading noisefloor Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 065/102] ath9k_hw: fill in the callbacks for calibration for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 066/102] ath9k_hw: add a helper for changing the TX/RX masks Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 067/102] ath9k_hw: complete AR9003 calibration Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 068/102] ath9k_hw: rename eep_AR9287_ops to eep_ar9287_ops Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 069/102] ath9k_hw: restore mac address reading logic Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 070/102] ath9k_hw: Implement AR9003 eeprom callbacks Luis R. Rodriguez
2010-04-08 19:27 ` Luis R. Rodriguez [this message]
2010-04-08 19:27 ` [PATCH 072/102] ath9k_hw: Fill get_isr() for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 073/102] ath9k_hw: move AR9280 PCI EEPROM fix to ar9002_hw.c Luis R. Rodriguez
2010-04-09 21:04 ` Pavel Roskin
2010-04-09 21:13 ` Felix Fietkau
2010-04-08 19:27 ` [PATCH 074/102] ath9k_hw: simplify the AR9280 PCI EEPROM fix Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 075/102] ath9k_hw: move the RF claim stuff to AR9002 hardware family Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 076/102] ath9k_hw: Configure Tx interrupt mitigation timer Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 077/102] ath9k_hw: add the AR9300 SREV hw name print Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 078/102] ath9k_hw: add TX/RX gain register initialization for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 079/102] ath9k_hw: Update ath9k_hw_set_dma for AR9300 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 080/102] ath9k_hw: Handle big-endian access for AR9300 EEPROM reads Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 081/102] ath9k_hw: skip asynch fifo enablement to AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 082/102] ath9k_hw: skip WEP aggregation enable code for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 083/102] ath9k_hw: Fix internal regulator setting on AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 084/102] ath9k: Load SW filtered NF values and start NF cal during full reset for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 085/102] ath9k_hw: Define abstraction for tx desc access Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 086/102] ath9k_hw: Add function to configure tx status ring buffer Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 087/102] ath9k_hw: Fill descriptor abstrations for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 088/102] ath9k: add RXLP and RXHP to debugfs counters Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 089/102] ath9k_hw: enable CRC check of descriptors for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 090/102] ath9k_hw: set cwmin and cwmax to 0 for for AR9003 upon txq reset Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 091/102] ath9k_hw: move AR9002 mac ops to its own file Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 092/102] ath9k: Setup appropriate tx desc for regular dma and edma Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 093/102] ath9k: Initialize and configure tx status for EDMA Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 094/102] ath9k_hw: Compute pointer checksum over the link descriptor Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 095/102] ath9k: Add frame onto hw tx fifo for edma Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 096/102] mac80211: add LDPC control flag Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 097/102] ath9k_hw: add LDPC support for AR9003 Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 098/102] ath9k: add LDPC support Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 099/102] ath9k: Enable TXOK and TXERR interrupts for TX EDMA Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 100/102] ath9k: Handle Tx interrupt for EDMA Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 101/102] ath9k_hw: Abort rx if hw is not coming out of full sleep in reset Luis R. Rodriguez
2010-04-08 19:27 ` [PATCH 102/102] ath9k_hw: add the PCI ID for the first AR9300 device Luis R. Rodriguez
2010-04-09 21:12 ` [PATCH 000/102] ath9k: add AR9003 support Pavel Roskin
2010-04-12 19:44 ` Luis R. Rodriguez
2010-04-13 19:58 ` John W. Linville
2010-04-13 20:08 ` Felix Fietkau
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