* [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
@ 2011-05-06 7:14 Lin Ming
2011-05-06 7:38 ` Ingo Molnar
2011-05-06 7:40 ` [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events tip-bot for Lin Ming
0 siblings, 2 replies; 15+ messages in thread
From: Lin Ming @ 2011-05-06 7:14 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar; +Cc: linux-kernel
Extend the Intel SandyBridge PMU driver with definitions
for generic front-end and back-end stall events.
( As commit 3011203 says, these are only approximations. )
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index c1ec7a5..61cbf48 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
x86_pmu.event_constraints = intel_snb_event_constraints;
x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+ /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+ intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+ /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+ intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+
pr_cont("SandyBridge events, ");
break;
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
2011-05-06 7:14 [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events Lin Ming
@ 2011-05-06 7:38 ` Ingo Molnar
2011-05-06 7:43 ` Lin Ming
2011-05-06 9:19 ` [PATCH] perf events, x86: Implement Sandybridge last-level cache events Ingo Molnar
2011-05-06 7:40 ` [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events tip-bot for Lin Ming
1 sibling, 2 replies; 15+ messages in thread
From: Ingo Molnar @ 2011-05-06 7:38 UTC (permalink / raw)
To: Lin Ming
Cc: Peter Zijlstra, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
* Lin Ming <ming.m.lin@intel.com> wrote:
> Extend the Intel SandyBridge PMU driver with definitions
> for generic front-end and back-end stall events.
>
> ( As commit 3011203 says, these are only approximations. )
>
> Signed-off-by: Lin Ming <ming.m.lin@intel.com>
> ---
> arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index c1ec7a5..61cbf48 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
>
> x86_pmu.event_constraints = intel_snb_event_constraints;
> x86_pmu.pebs_constraints = intel_snb_pebs_events;
> +
> + /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
> + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
> + /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
> + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
> +
Nice!
Could you check Intel Atom perhaps as well, does it have any useful event to
approximate this?
Thanks,
Ingo
^ permalink raw reply [flat|nested] 15+ messages in thread
* [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
2011-05-06 7:14 [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events Lin Ming
2011-05-06 7:38 ` Ingo Molnar
@ 2011-05-06 7:40 ` tip-bot for Lin Ming
2011-05-06 15:51 ` Steven Rostedt
1 sibling, 1 reply; 15+ messages in thread
From: tip-bot for Lin Ming @ 2011-05-06 7:40 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, acme, hpa, mingo, a.p.zijlstra, efault, fweisbec,
rostedt, ming.m.lin, tglx, mingo
Commit-ID: e04d1b23f9706186187dcb0be1a752e48dcc540b
Gitweb: http://git.kernel.org/tip/e04d1b23f9706186187dcb0be1a752e48dcc540b
Author: Lin Ming <ming.m.lin@intel.com>
AuthorDate: Fri, 6 May 2011 07:14:02 +0000
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 6 May 2011 09:37:03 +0200
perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
Extend the Intel SandyBridge PMU driver with definitions
for generic front-end and back-end stall events.
( As commit 3011203 "perf events, x86: Add Westmere stalled-cycles-frontend/backend
events" says, these are only approximations. )
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Steven Rostedt <rostedt@goodmis.org>
Link: http://lkml.kernel.org/r/1304666042-17577-1-git-send-email-ming.m.lin@intel.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index e61539b..7cf2ec5 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1474,6 +1474,12 @@ static __init int intel_pmu_init(void)
x86_pmu.event_constraints = intel_snb_event_constraints;
x86_pmu.pebs_constraints = intel_snb_pebs_events;
+
+ /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
+ intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
+ /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
+ intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
+
pr_cont("SandyBridge events, ");
break;
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
2011-05-06 7:38 ` Ingo Molnar
@ 2011-05-06 7:43 ` Lin Ming
2011-05-06 13:44 ` Lin Ming
2011-05-06 9:19 ` [PATCH] perf events, x86: Implement Sandybridge last-level cache events Ingo Molnar
1 sibling, 1 reply; 15+ messages in thread
From: Lin Ming @ 2011-05-06 7:43 UTC (permalink / raw)
To: Ingo Molnar
Cc: Peter Zijlstra, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Fri, 2011-05-06 at 15:38 +0800, Ingo Molnar wrote:
> * Lin Ming <ming.m.lin@intel.com> wrote:
>
> > Extend the Intel SandyBridge PMU driver with definitions
> > for generic front-end and back-end stall events.
> >
> > ( As commit 3011203 says, these are only approximations. )
> >
> > Signed-off-by: Lin Ming <ming.m.lin@intel.com>
> > ---
> > arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++++
> > 1 files changed, 6 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> > index c1ec7a5..61cbf48 100644
> > --- a/arch/x86/kernel/cpu/perf_event_intel.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> > @@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
> >
> > x86_pmu.event_constraints = intel_snb_event_constraints;
> > x86_pmu.pebs_constraints = intel_snb_pebs_events;
> > +
> > + /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
> > + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
> > + /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
> > + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
> > +
>
> Nice!
>
> Could you check Intel Atom perhaps as well, does it have any useful event to
> approximate this?
OK, let me check.
>
> Thanks,
>
> Ingo
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-06 7:38 ` Ingo Molnar
2011-05-06 7:43 ` Lin Ming
@ 2011-05-06 9:19 ` Ingo Molnar
2011-05-06 13:47 ` Lin Ming
1 sibling, 1 reply; 15+ messages in thread
From: Ingo Molnar @ 2011-05-06 9:19 UTC (permalink / raw)
To: Lin Ming
Cc: Peter Zijlstra, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
Btw., there's another missing Intel SandyBridge related perf events feature as
well which was not implemented with the Intel offcore bits.
Peter did a raw first cut - entirely untested, see it below. Would you be
interested in testing it on Intel SandyBridge hw and sending (the working
version) to lkml with your Signed-off-by if the events looks good to you in
some real tests (i.e. are counting real LL cache events)?
Thanks,
Ingo
------------------->
Subject: perf events, x86: Implement Sandybridge last-level cache events
From: Peter Zijlstra <peterz@infradead.org>
Date: Fri May 06 11:15:30 CEST 2011
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/kernel/cpu/perf_event_intel.c | 68 +++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
Index: tip/arch/x86/kernel/cpu/perf_event_intel.c
===================================================================
--- tip.orig/arch/x86/kernel/cpu/perf_event_intel.c
+++ tip/arch/x86/kernel/cpu/perf_event_intel.c
@@ -150,6 +150,72 @@ static u64 intel_pmu_event_map(int hw_ev
return intel_perfmon_event_map[hw_event];
}
+/*
+ * Sandy Bridge MSR_OFFCORE_RESPONSE bits;
+ * See IA32 SDM Vol 3B 30.8.5
+ */
+
+#define SNB_DMND_DATA_RD (1 << 0)
+#define SNB_DMND_RFO (1 << 1)
+#define SNB_DMND_IFETCH (1 << 2)
+#define SNB_DMND_WB (1 << 3)
+#define SNB_PF_DATA_RD (1 << 4)
+#define SNB_PF_DATA_RFO (1 << 5)
+#define SNB_PF_IFETCH (1 << 6)
+#define SNB_PF_LLC_DATA_RD (1 << 7)
+#define SNB_PF_LLC_RFO (1 << 8)
+#define SNB_PF_LLC_IFETCH (1 << 9)
+#define SNB_BUS_LOCKS (1 << 10)
+#define SNB_STRM_ST (1 << 11)
+ /* hole */
+#define SNB_OFFCORE_OTHER (1 << 15)
+#define SNB_COMMON (1 << 16)
+#define SNB_NO_SUPP (1 << 17)
+#define SNB_LLC_HITM (1 << 18)
+#define SNB_LLC_HITE (1 << 19)
+#define SNB_LLC_HITS (1 << 20)
+#define SNB_LLC_HITF (1 << 21)
+ /* hole */
+#define SNB_SNP_NONE (1 << 31)
+#define SNB_SNP_NOT_NEEDED (1 << 32)
+#define SNB_SNP_MISS (1 << 33)
+#define SNB_SNP_NO_FWD (1 << 34)
+#define SNB_SNP_FWD (1 << 35)
+#define SNB_HITM (1 << 36)
+#define SNB_NON_DRAM (1 << 37)
+
+#define SNB_DMND_READ (SNB_DMND_DATA_RD)
+#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_DMND_WB|SNB_STRM_ST)
+#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_DATA_RFO)
+
+#define SNB_L3_HIT ()
+#define SNB_L3_MISS ()
+#define SNB_L3_ACCESS (SNB_L3_HIT|SNB_L3_MISS)
+
+#define SNB_ALL_DRAM ()
+#define SNB_REMOTE_DRAM ()
+
+static __initconst const u64 snb_hw_cache_extra_regs
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL ) ] = {
+ [ C(OP_READ) ] = {
+ [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
+ [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
+ },
+ [ C(OP_WRITE) ] = {
+ [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
+ [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
+ },
+ [ C(OP_PREFETCH) ] = {
+ [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
+ [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
+ },
+ }
+};
+
static __initconst const u64 snb_hw_cache_event_ids
[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -1497,6 +1563,8 @@ static __init int intel_pmu_init(void)
case 42: /* SandyBridge */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
+ memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
+ sizeof(hw_cache_extra_regs));
intel_pmu_lbr_init_nhm();
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
2011-05-06 7:43 ` Lin Ming
@ 2011-05-06 13:44 ` Lin Ming
0 siblings, 0 replies; 15+ messages in thread
From: Lin Ming @ 2011-05-06 13:44 UTC (permalink / raw)
To: Ingo Molnar
Cc: Peter Zijlstra, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Fri, 2011-05-06 at 15:43 +0800, Lin Ming wrote:
> On Fri, 2011-05-06 at 15:38 +0800, Ingo Molnar wrote:
> > * Lin Ming <ming.m.lin@intel.com> wrote:
> >
> > > Extend the Intel SandyBridge PMU driver with definitions
> > > for generic front-end and back-end stall events.
> > >
> > > ( As commit 3011203 says, these are only approximations. )
> > >
> > > Signed-off-by: Lin Ming <ming.m.lin@intel.com>
> > > ---
> > > arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++++
> > > 1 files changed, 6 insertions(+), 0 deletions(-)
> > >
> > > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> > > index c1ec7a5..61cbf48 100644
> > > --- a/arch/x86/kernel/cpu/perf_event_intel.c
> > > +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> > > @@ -1485,6 +1485,12 @@ static __init int intel_pmu_init(void)
> > >
> > > x86_pmu.event_constraints = intel_snb_event_constraints;
> > > x86_pmu.pebs_constraints = intel_snb_pebs_events;
> > > +
> > > + /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
> > > + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
> > > + /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
> > > + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
> > > +
> >
> > Nice!
> >
> > Could you check Intel Atom perhaps as well, does it have any useful event to
> > approximate this?
>
> OK, let me check.
Checked, but don't find this kind of event.
>
> >
> > Thanks,
> >
> > Ingo
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-06 9:19 ` [PATCH] perf events, x86: Implement Sandybridge last-level cache events Ingo Molnar
@ 2011-05-06 13:47 ` Lin Ming
2011-05-09 8:45 ` Lin Ming
0 siblings, 1 reply; 15+ messages in thread
From: Lin Ming @ 2011-05-06 13:47 UTC (permalink / raw)
To: Ingo Molnar
Cc: Peter Zijlstra, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Fri, 2011-05-06 at 17:19 +0800, Ingo Molnar wrote:
> Btw., there's another missing Intel SandyBridge related perf events feature as
> well which was not implemented with the Intel offcore bits.
>
> Peter did a raw first cut - entirely untested, see it below. Would you be
> interested in testing it on Intel SandyBridge hw and sending (the working
> version) to lkml with your Signed-off-by if the events looks good to you in
> some real tests (i.e. are counting real LL cache events)?
OK, but I can't access SandyBridge machine at home now.
Will try it next Monday.
>
> Thanks,
>
> Ingo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
2011-05-06 7:40 ` [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events tip-bot for Lin Ming
@ 2011-05-06 15:51 ` Steven Rostedt
2011-05-06 19:08 ` Ingo Molnar
0 siblings, 1 reply; 15+ messages in thread
From: Steven Rostedt @ 2011-05-06 15:51 UTC (permalink / raw)
To: mingo, hpa, acme, linux-kernel, a.p.zijlstra, efault, fweisbec,
ming.m.lin, tglx, mingo
Cc: linux-tip-commits
On Fri, 2011-05-06 at 07:40 +0000, tip-bot for Lin Ming wrote:
> Commit-ID: e04d1b23f9706186187dcb0be1a752e48dcc540b
> Gitweb: http://git.kernel.org/tip/e04d1b23f9706186187dcb0be1a752e48dcc540b
> Author: Lin Ming <ming.m.lin@intel.com>
> AuthorDate: Fri, 6 May 2011 07:14:02 +0000
> Committer: Ingo Molnar <mingo@elte.hu>
> CommitDate: Fri, 6 May 2011 09:37:03 +0200
>
> perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
>
> Extend the Intel SandyBridge PMU driver with definitions
> for generic front-end and back-end stall events.
>
> ( As commit 3011203 "perf events, x86: Add Westmere stalled-cycles-frontend/backend
> events" says, these are only approximations. )
I now get the following build error:
In file included from /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event.c:1449:0:
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c: In function 'intel_pmu_init':
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_FRONTEND' undeclared (first use in this fun
ction)
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: note: each undeclared identifier is reported only once for each function it appe
ars in
/home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1481:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_BACKEND' undeclared (first use in this func
tion)
Config can be found here:
http://rostedt.homelinux.com/private/config-sandy-failed
-- Steve
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
2011-05-06 15:51 ` Steven Rostedt
@ 2011-05-06 19:08 ` Ingo Molnar
0 siblings, 0 replies; 15+ messages in thread
From: Ingo Molnar @ 2011-05-06 19:08 UTC (permalink / raw)
To: Steven Rostedt
Cc: mingo, hpa, acme, linux-kernel, a.p.zijlstra, efault, fweisbec,
ming.m.lin, tglx, linux-tip-commits
* Steven Rostedt <rostedt@goodmis.org> wrote:
> On Fri, 2011-05-06 at 07:40 +0000, tip-bot for Lin Ming wrote:
> > Commit-ID: e04d1b23f9706186187dcb0be1a752e48dcc540b
> > Gitweb: http://git.kernel.org/tip/e04d1b23f9706186187dcb0be1a752e48dcc540b
> > Author: Lin Ming <ming.m.lin@intel.com>
> > AuthorDate: Fri, 6 May 2011 07:14:02 +0000
> > Committer: Ingo Molnar <mingo@elte.hu>
> > CommitDate: Fri, 6 May 2011 09:37:03 +0200
> >
> > perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events
> >
> > Extend the Intel SandyBridge PMU driver with definitions
> > for generic front-end and back-end stall events.
> >
> > ( As commit 3011203 "perf events, x86: Add Westmere stalled-cycles-frontend/backend
> > events" says, these are only approximations. )
>
> I now get the following build error:
>
> In file included from /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event.c:1449:0:
> /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c: In function 'intel_pmu_init':
> /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_FRONTEND' undeclared (first use in this fun
> ction)
> /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1479:27: note: each undeclared identifier is reported only once for each function it appe
> ars in
> /home/rostedt/work/autotest/nobackup/linux-test.git/arch/x86/kernel/cpu/perf_event_intel.c:1481:27: error: 'PERF_COUNT_HW_STALLED_CYCLES_BACKEND' undeclared (first use in this func
> tion)
>
> Config can be found here:
>
> http://rostedt.homelinux.com/private/config-sandy-failed
Ok, could you check latest perf/core (57d524154ffe), does it work better?
Thanks,
Ingo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-06 13:47 ` Lin Ming
@ 2011-05-09 8:45 ` Lin Ming
0 siblings, 0 replies; 15+ messages in thread
From: Lin Ming @ 2011-05-09 8:45 UTC (permalink / raw)
To: Ingo Molnar
Cc: Peter Zijlstra, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Fri, 2011-05-06 at 21:47 +0800, Lin Ming wrote:
> On Fri, 2011-05-06 at 17:19 +0800, Ingo Molnar wrote:
> > Btw., there's another missing Intel SandyBridge related perf events feature as
> > well which was not implemented with the Intel offcore bits.
> >
> > Peter did a raw first cut - entirely untested, see it below. Would you be
> > interested in testing it on Intel SandyBridge hw and sending (the working
> > version) to lkml with your Signed-off-by if the events looks good to you in
> > some real tests (i.e. are counting real LL cache events)?
>
> OK, but I can't access SandyBridge machine at home now.
> Will try it next Monday.
The updated and tested patch at:
http://lkml.org/lkml/2011/5/9/80
Please help to review the definitions for SNB_L3_HIT/_MISS_/ACCESS.
I'm really unsure for that.
Thanks,
Lin Ming
>
> >
> > Thanks,
> >
> > Ingo
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-10 14:29 ` Peter Zijlstra
@ 2011-05-10 15:29 ` Ingo Molnar
0 siblings, 0 replies; 15+ messages in thread
From: Ingo Molnar @ 2011-05-10 15:29 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Lin Ming, Andi Kleen, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
* Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
> On Tue, 2011-05-10 at 22:17 +0800, Lin Ming wrote:
> >
> > I'm also not sure if the bits combination do count exactly
> > L3_HIT/_MISS.
> >
> <snip manual bits>
>
> > May need some micro-benchmarks to verify it.
>
> either that or ask for clarification internally.
Well, please run micro-benchmarks to verify it in any case! Having more
clarification than that will also be useful.
Thanks,
Ingo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-10 14:17 ` Lin Ming
@ 2011-05-10 14:29 ` Peter Zijlstra
2011-05-10 15:29 ` Ingo Molnar
0 siblings, 1 reply; 15+ messages in thread
From: Peter Zijlstra @ 2011-05-10 14:29 UTC (permalink / raw)
To: Lin Ming
Cc: Ingo Molnar, Andi Kleen, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Tue, 2011-05-10 at 22:17 +0800, Lin Ming wrote:
>
> I'm also not sure if the bits combination do count exactly
> L3_HIT/_MISS.
>
<snip manual bits>
> May need some micro-benchmarks to verify it.
either that or ask for clarification internally.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-10 10:08 ` Peter Zijlstra
@ 2011-05-10 14:17 ` Lin Ming
2011-05-10 14:29 ` Peter Zijlstra
0 siblings, 1 reply; 15+ messages in thread
From: Lin Ming @ 2011-05-10 14:17 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Ingo Molnar, Andi Kleen, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Tue, 2011-05-10 at 18:08 +0800, Peter Zijlstra wrote:
> On Mon, 2011-05-09 at 16:39 +0800, Lin Ming wrote:
>
> >
> > +/*
> > + * Sandy Bridge MSR_OFFCORE_RESPONSE bits;
> > + * See IA32 SDM Vol 3B 30.8.5
> > + */
> > +
> > +#define SNB_DMND_DATA_RD (1ULL << 0)
> > +#define SNB_DMND_RFO (1ULL << 1)
> > +#define SNB_DMND_IFETCH (1ULL << 2)
> > +#define SNB_DMND_WB (1ULL << 3)
> > +#define SNB_PF_DATA_RD (1ULL << 4)
> > +#define SNB_PF_DATA_RFO (1ULL << 5)
> > +#define SNB_PF_IFETCH (1ULL << 6)
> > +#define SNB_PF_LLC_DATA_RD (1ULL << 7)
> > +#define SNB_PF_LLC_RFO (1ULL << 8)
> > +#define SNB_PF_LLC_IFETCH (1ULL << 9)
> > +#define SNB_BUS_LOCKS (1ULL << 10)
> > +#define SNB_STRM_ST (1ULL << 11)
> > + /* hole */
> > +#define SNB_OFFCORE_OTHER (1ULL << 15)
> > +#define SNB_COMMON (1ULL << 16)
> > +#define SNB_NO_SUPP (1ULL << 17)
> > +#define SNB_LLC_HITM (1ULL << 18)
> > +#define SNB_LLC_HITE (1ULL << 19)
> > +#define SNB_LLC_HITS (1ULL << 20)
> > +#define SNB_LLC_HITF (1ULL << 21)
> > + /* hole */
> > +#define SNB_SNP_NONE (1ULL << 31)
> > +#define SNB_SNP_NOT_NEEDED (1ULL << 32)
> > +#define SNB_SNP_MISS (1ULL << 33)
> > +#define SNB_SNP_NO_FWD (1ULL << 34)
> > +#define SNB_SNP_FWD (1ULL << 35)
> > +#define SNB_HITM (1ULL << 36)
> > +#define SNB_NON_DRAM (1ULL << 37)
> > +
> > +#define SNB_DMND_READ (SNB_DMND_DATA_RD)
> > +#define SNB_DMND_WRITE (SNB_DMND_RFO | SNB_DMND_WB|SNB_STRM_ST)
> > +#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD | SNB_PF_DATA_RFO)
> > +
> > +#define SNB_SUPPLIER_INFO (SNB_NO_SUPP | SNB_LLC_HITM | SNB_LLC_HITE | \
> > + SNB_LLC_HITS | SNB_LLC_HITF)
> > +
> > +#define SNB_L3_HIT (SNB_SUPPLIER_INFO | SNB_SNP_NOT_NEEDED | SNB_SNP_NO_FWD | SNB_HITM)
> > +#define SNB_L3_MISS (SNB_SUPPLIER_INFO | SNB_SNP_MISS | SNB_SNP_FWD | SNB_NON_DRAM)
> > +#define SNB_L3_ACCESS (SNB_L3_HIT | SNB_L3_MISS)
>
> I would very much like to know how these bits work.. Since the SDM
> doesn't explain anything could you please add a big comment explaining
> things?
I'm also not sure if the bits combination do count exactly L3_HIT/_MISS.
The manual has below statements,
"To specify a complete offcore response filter, software must properly
program bits in the request and response type fields. A valid request
type must have at least one bit set in the non-reserved bits of 15:0. A
valid response type must be a non-zero value of the following
expression:
ANY | [(‘OR’ of Supplier Info Bits) & (‘OR’ of Snoop Info Bits)]
If “ANY“ bit is set, the supplier and snoop info bits are ignored."
So I defined SNB_L3_HIT and SNB_L3_MISS with ANY bit cleared, and
Supplier Info Bits and Snoop Info Bits set.
But again, I'm not sure if the combination is correct.
May need some micro-benchmarks to verify it.
Thanks,
Lin Ming
>
> Otherwise the patch looks good, but unverifiable so for me.
>
> > +static __initconst const u64 snb_hw_cache_extra_regs
> > + [PERF_COUNT_HW_CACHE_MAX]
> > + [PERF_COUNT_HW_CACHE_OP_MAX]
> > + [PERF_COUNT_HW_CACHE_RESULT_MAX] =
> > +{
> > + [ C(LL ) ] = {
> > + [ C(OP_READ) ] = {
> > + [ C(RESULT_ACCESS) ] = SNB_DMND_READ | SNB_L3_ACCESS,
> > + [ C(RESULT_MISS) ] = SNB_DMND_READ | SNB_L3_MISS,
> > + },
> > + [ C(OP_WRITE) ] = {
> > + [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE | SNB_L3_ACCESS,
> > + [ C(RESULT_MISS) ] = SNB_DMND_WRITE | SNB_L3_MISS,
> > + },
> > + [ C(OP_PREFETCH) ] = {
> > + [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH | SNB_L3_ACCESS,
> > + [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH | SNB_L3_MISS,
> > + },
> > + }
> > +};
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH] perf events, x86: Implement Sandybridge last-level cache events
2011-05-09 8:39 [PATCH] perf events, x86: Implement Sandybridge last-level cache events Lin Ming
@ 2011-05-10 10:08 ` Peter Zijlstra
2011-05-10 14:17 ` Lin Ming
0 siblings, 1 reply; 15+ messages in thread
From: Peter Zijlstra @ 2011-05-10 10:08 UTC (permalink / raw)
To: Lin Ming
Cc: Ingo Molnar, Andi Kleen, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
On Mon, 2011-05-09 at 16:39 +0800, Lin Ming wrote:
>
> +/*
> + * Sandy Bridge MSR_OFFCORE_RESPONSE bits;
> + * See IA32 SDM Vol 3B 30.8.5
> + */
> +
> +#define SNB_DMND_DATA_RD (1ULL << 0)
> +#define SNB_DMND_RFO (1ULL << 1)
> +#define SNB_DMND_IFETCH (1ULL << 2)
> +#define SNB_DMND_WB (1ULL << 3)
> +#define SNB_PF_DATA_RD (1ULL << 4)
> +#define SNB_PF_DATA_RFO (1ULL << 5)
> +#define SNB_PF_IFETCH (1ULL << 6)
> +#define SNB_PF_LLC_DATA_RD (1ULL << 7)
> +#define SNB_PF_LLC_RFO (1ULL << 8)
> +#define SNB_PF_LLC_IFETCH (1ULL << 9)
> +#define SNB_BUS_LOCKS (1ULL << 10)
> +#define SNB_STRM_ST (1ULL << 11)
> + /* hole */
> +#define SNB_OFFCORE_OTHER (1ULL << 15)
> +#define SNB_COMMON (1ULL << 16)
> +#define SNB_NO_SUPP (1ULL << 17)
> +#define SNB_LLC_HITM (1ULL << 18)
> +#define SNB_LLC_HITE (1ULL << 19)
> +#define SNB_LLC_HITS (1ULL << 20)
> +#define SNB_LLC_HITF (1ULL << 21)
> + /* hole */
> +#define SNB_SNP_NONE (1ULL << 31)
> +#define SNB_SNP_NOT_NEEDED (1ULL << 32)
> +#define SNB_SNP_MISS (1ULL << 33)
> +#define SNB_SNP_NO_FWD (1ULL << 34)
> +#define SNB_SNP_FWD (1ULL << 35)
> +#define SNB_HITM (1ULL << 36)
> +#define SNB_NON_DRAM (1ULL << 37)
> +
> +#define SNB_DMND_READ (SNB_DMND_DATA_RD)
> +#define SNB_DMND_WRITE (SNB_DMND_RFO | SNB_DMND_WB|SNB_STRM_ST)
> +#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD | SNB_PF_DATA_RFO)
> +
> +#define SNB_SUPPLIER_INFO (SNB_NO_SUPP | SNB_LLC_HITM | SNB_LLC_HITE | \
> + SNB_LLC_HITS | SNB_LLC_HITF)
> +
> +#define SNB_L3_HIT (SNB_SUPPLIER_INFO | SNB_SNP_NOT_NEEDED | SNB_SNP_NO_FWD | SNB_HITM)
> +#define SNB_L3_MISS (SNB_SUPPLIER_INFO | SNB_SNP_MISS | SNB_SNP_FWD | SNB_NON_DRAM)
> +#define SNB_L3_ACCESS (SNB_L3_HIT | SNB_L3_MISS)
I would very much like to know how these bits work.. Since the SDM
doesn't explain anything could you please add a big comment explaining
things?
Otherwise the patch looks good, but unverifiable so for me.
> +static __initconst const u64 snb_hw_cache_extra_regs
> + [PERF_COUNT_HW_CACHE_MAX]
> + [PERF_COUNT_HW_CACHE_OP_MAX]
> + [PERF_COUNT_HW_CACHE_RESULT_MAX] =
> +{
> + [ C(LL ) ] = {
> + [ C(OP_READ) ] = {
> + [ C(RESULT_ACCESS) ] = SNB_DMND_READ | SNB_L3_ACCESS,
> + [ C(RESULT_MISS) ] = SNB_DMND_READ | SNB_L3_MISS,
> + },
> + [ C(OP_WRITE) ] = {
> + [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE | SNB_L3_ACCESS,
> + [ C(RESULT_MISS) ] = SNB_DMND_WRITE | SNB_L3_MISS,
> + },
> + [ C(OP_PREFETCH) ] = {
> + [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH | SNB_L3_ACCESS,
> + [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH | SNB_L3_MISS,
> + },
> + }
> +};
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH] perf events, x86: Implement Sandybridge last-level cache events
@ 2011-05-09 8:39 Lin Ming
2011-05-10 10:08 ` Peter Zijlstra
0 siblings, 1 reply; 15+ messages in thread
From: Lin Ming @ 2011-05-09 8:39 UTC (permalink / raw)
To: Ingo Molnar
Cc: Peter Zijlstra, Andi Kleen, linux-kernel, Mike Galbraith,
Arnaldo Carvalho de Melo, Frédéric Weisbecker,
Steven Rostedt
Originally from: Peter Zijlstra <peterz@infradead.org>
Implement Sandybridge last-level cache events with offcore events.
$ ./perf stat -e LLC-loads -e LLC-load-misses \
-e LLC-stores -e LLC-store-misses \
-e LLC-prefetches -e LLC-prefetch-misses \
-- dd if=/dev/zero of=/dev/null
Performance counter stats for 'dd if=/dev/zero of=/dev/null':
21,150 LLC-loads
191 LLC-load-misses
4,749 LLC-stores
1,919 LLC-store-misses
11,584 LLC-prefetches
174 LLC-prefetch-misses
6.155113700 seconds time elapsed
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 77 ++++++++++++++++++++++++++++++++
1 files changed, 77 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 41178c8..b39b819 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -137,6 +137,13 @@ static struct event_constraint intel_westmere_percore_constraints[] __read_mostl
EVENT_CONSTRAINT_END
};
+static struct extra_reg intel_snb_extra_regs[] __read_mostly =
+{
+ INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffff),
+ INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffff),
+ EVENT_EXTRA_END
+};
+
static struct event_constraint intel_gen_event_constraints[] __read_mostly =
{
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
@@ -150,6 +157,72 @@ static u64 intel_pmu_event_map(int hw_event)
return intel_perfmon_event_map[hw_event];
}
+/*
+ * Sandy Bridge MSR_OFFCORE_RESPONSE bits;
+ * See IA32 SDM Vol 3B 30.8.5
+ */
+
+#define SNB_DMND_DATA_RD (1ULL << 0)
+#define SNB_DMND_RFO (1ULL << 1)
+#define SNB_DMND_IFETCH (1ULL << 2)
+#define SNB_DMND_WB (1ULL << 3)
+#define SNB_PF_DATA_RD (1ULL << 4)
+#define SNB_PF_DATA_RFO (1ULL << 5)
+#define SNB_PF_IFETCH (1ULL << 6)
+#define SNB_PF_LLC_DATA_RD (1ULL << 7)
+#define SNB_PF_LLC_RFO (1ULL << 8)
+#define SNB_PF_LLC_IFETCH (1ULL << 9)
+#define SNB_BUS_LOCKS (1ULL << 10)
+#define SNB_STRM_ST (1ULL << 11)
+ /* hole */
+#define SNB_OFFCORE_OTHER (1ULL << 15)
+#define SNB_COMMON (1ULL << 16)
+#define SNB_NO_SUPP (1ULL << 17)
+#define SNB_LLC_HITM (1ULL << 18)
+#define SNB_LLC_HITE (1ULL << 19)
+#define SNB_LLC_HITS (1ULL << 20)
+#define SNB_LLC_HITF (1ULL << 21)
+ /* hole */
+#define SNB_SNP_NONE (1ULL << 31)
+#define SNB_SNP_NOT_NEEDED (1ULL << 32)
+#define SNB_SNP_MISS (1ULL << 33)
+#define SNB_SNP_NO_FWD (1ULL << 34)
+#define SNB_SNP_FWD (1ULL << 35)
+#define SNB_HITM (1ULL << 36)
+#define SNB_NON_DRAM (1ULL << 37)
+
+#define SNB_DMND_READ (SNB_DMND_DATA_RD)
+#define SNB_DMND_WRITE (SNB_DMND_RFO | SNB_DMND_WB|SNB_STRM_ST)
+#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD | SNB_PF_DATA_RFO)
+
+#define SNB_SUPPLIER_INFO (SNB_NO_SUPP | SNB_LLC_HITM | SNB_LLC_HITE | \
+ SNB_LLC_HITS | SNB_LLC_HITF)
+
+#define SNB_L3_HIT (SNB_SUPPLIER_INFO | SNB_SNP_NOT_NEEDED | SNB_SNP_NO_FWD | SNB_HITM)
+#define SNB_L3_MISS (SNB_SUPPLIER_INFO | SNB_SNP_MISS | SNB_SNP_FWD | SNB_NON_DRAM)
+#define SNB_L3_ACCESS (SNB_L3_HIT | SNB_L3_MISS)
+
+static __initconst const u64 snb_hw_cache_extra_regs
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL ) ] = {
+ [ C(OP_READ) ] = {
+ [ C(RESULT_ACCESS) ] = SNB_DMND_READ | SNB_L3_ACCESS,
+ [ C(RESULT_MISS) ] = SNB_DMND_READ | SNB_L3_MISS,
+ },
+ [ C(OP_WRITE) ] = {
+ [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE | SNB_L3_ACCESS,
+ [ C(RESULT_MISS) ] = SNB_DMND_WRITE | SNB_L3_MISS,
+ },
+ [ C(OP_PREFETCH) ] = {
+ [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH | SNB_L3_ACCESS,
+ [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH | SNB_L3_MISS,
+ },
+ }
+};
+
static __initconst const u64 snb_hw_cache_event_ids
[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -1497,11 +1570,15 @@ static __init int intel_pmu_init(void)
case 42: /* SandyBridge */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
+ memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
+ sizeof(hw_cache_extra_regs));
intel_pmu_lbr_init_nhm();
x86_pmu.event_constraints = intel_snb_event_constraints;
+ x86_pmu.percore_constraints = intel_westmere_percore_constraints;
x86_pmu.pebs_constraints = intel_snb_pebs_events;
+ x86_pmu.extra_regs = intel_snb_extra_regs;
/* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
--
1.7.4.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2011-05-10 15:29 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-05-06 7:14 [PATCH] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events Lin Ming
2011-05-06 7:38 ` Ingo Molnar
2011-05-06 7:43 ` Lin Ming
2011-05-06 13:44 ` Lin Ming
2011-05-06 9:19 ` [PATCH] perf events, x86: Implement Sandybridge last-level cache events Ingo Molnar
2011-05-06 13:47 ` Lin Ming
2011-05-09 8:45 ` Lin Ming
2011-05-06 7:40 ` [tip:perf/core] perf events, x86: Add SandyBridge stalled-cycles-frontend/backend events tip-bot for Lin Ming
2011-05-06 15:51 ` Steven Rostedt
2011-05-06 19:08 ` Ingo Molnar
2011-05-09 8:39 [PATCH] perf events, x86: Implement Sandybridge last-level cache events Lin Ming
2011-05-10 10:08 ` Peter Zijlstra
2011-05-10 14:17 ` Lin Ming
2011-05-10 14:29 ` Peter Zijlstra
2011-05-10 15:29 ` Ingo Molnar
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