From: Catalin Marinas <catalin.marinas@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Subject: [PATCH v5 13/19] ARM: LPAE: Add context switching support Date: Sun, 8 May 2011 13:51:32 +0100 [thread overview] Message-ID: <1304859098-10760-14-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1304859098-10760-1-git-send-email-catalin.marinas@arm.com> With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm/mm/context.c | 19 +++++++++++++++++-- arch/arm/mm/proc-v7.S | 10 ++++++++-- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index b0ee9ba..fcdb101 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -22,6 +22,21 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; DEFINE_PER_CPU(struct mm_struct *, current_mm); #endif +#ifdef CONFIG_ARM_LPAE +#define cpu_set_asid(asid) { \ + unsigned long ttbl, ttbh; \ + asm volatile( \ + " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ + " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \ + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ + : "=&r" (ttbl), "=&r" (ttbh) \ + : "r" (asid & ~ASID_MASK)); \ +} +#else +#define cpu_set_asid(asid) \ + asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +#endif + /* * We fork()ed a process, and we need a new context for the child * to run in. We reserve version 0 for initial tasks so we will @@ -37,7 +52,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { /* set the reserved ASID before flushing the TLB */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); + cpu_set_asid(0); isb(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { @@ -99,7 +114,7 @@ static void reset_context(void *info) set_mm_context(mm, asid); /* set the new ASID */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id)); + cpu_set_asid(mm->context.id); isb(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 0996713..ad22628 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -115,8 +115,13 @@ ENDPROC(cpu_v7_dcache_clean_area) */ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU - mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mov r2, #0 +#ifdef CONFIG_ARM_LPAE + and r3, r1, #0xff + mov r3, r3, lsl #(48 - 32) @ ASID + mcrr p15, 0, r0, r3, c2 @ set TTB 0 +#else /* !CONFIG_ARM_LPAE */ ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 @@ -127,12 +132,13 @@ ENTRY(cpu_v7_switch_mm) #endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 isb #ifdef CONFIG_ARM_ERRATA_754322 dsb #endif mcr p15, 0, r1, c13, c0, 1 @ set context ID +#endif /* CONFIG_ARM_LPAE */ isb #endif mov pc, lr
WARNING: multiple messages have this Message-ID (diff)
From: catalin.marinas@arm.com (Catalin Marinas) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 13/19] ARM: LPAE: Add context switching support Date: Sun, 8 May 2011 13:51:32 +0100 [thread overview] Message-ID: <1304859098-10760-14-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1304859098-10760-1-git-send-email-catalin.marinas@arm.com> With LPAE, TTBRx registers are 64-bit. The ASID is stored in TTBR0 rather than a separate Context ID register. This patch makes the necessary changes to handle context switching on LPAE. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm/mm/context.c | 19 +++++++++++++++++-- arch/arm/mm/proc-v7.S | 10 ++++++++-- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index b0ee9ba..fcdb101 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -22,6 +22,21 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION; DEFINE_PER_CPU(struct mm_struct *, current_mm); #endif +#ifdef CONFIG_ARM_LPAE +#define cpu_set_asid(asid) { \ + unsigned long ttbl, ttbh; \ + asm volatile( \ + " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \ + " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \ + " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \ + : "=&r" (ttbl), "=&r" (ttbh) \ + : "r" (asid & ~ASID_MASK)); \ +} +#else +#define cpu_set_asid(asid) \ + asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid)) +#endif + /* * We fork()ed a process, and we need a new context for the child * to run in. We reserve version 0 for initial tasks so we will @@ -37,7 +52,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) static void flush_context(void) { /* set the reserved ASID before flushing the TLB */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0)); + cpu_set_asid(0); isb(); local_flush_tlb_all(); if (icache_is_vivt_asid_tagged()) { @@ -99,7 +114,7 @@ static void reset_context(void *info) set_mm_context(mm, asid); /* set the new ASID */ - asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id)); + cpu_set_asid(mm->context.id); isb(); } diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 0996713..ad22628 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -115,8 +115,13 @@ ENDPROC(cpu_v7_dcache_clean_area) */ ENTRY(cpu_v7_switch_mm) #ifdef CONFIG_MMU - mov r2, #0 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id + mov r2, #0 +#ifdef CONFIG_ARM_LPAE + and r3, r1, #0xff + mov r3, r3, lsl #(48 - 32) @ ASID + mcrr p15, 0, r0, r3, c2 @ set TTB 0 +#else /* !CONFIG_ARM_LPAE */ ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) ALT_UP(orr r0, r0, #TTB_FLAGS_UP) #ifdef CONFIG_ARM_ERRATA_430973 @@ -127,12 +132,13 @@ ENTRY(cpu_v7_switch_mm) #endif mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID isb -1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 + mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 isb #ifdef CONFIG_ARM_ERRATA_754322 dsb #endif mcr p15, 0, r1, c13, c0, 1 @ set context ID +#endif /* CONFIG_ARM_LPAE */ isb #endif mov pc, lr
next prev parent reply other threads:[~2011-05-08 12:53 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2011-05-08 12:51 [PATCH v5 00/19] ARM: Add support for the Large Physical Address Extensions Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 01/19] ARM: LPAE: Use long long printk format for displaying the pud Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 02/19] ARM: LPAE: add ISBs around MMU enabling code Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 21:41 ` Russell King - ARM Linux 2011-05-08 21:41 ` Russell King - ARM Linux 2011-05-09 10:22 ` Catalin Marinas 2011-05-09 10:22 ` Catalin Marinas 2011-05-09 10:32 ` Russell King - ARM Linux 2011-05-09 10:32 ` Russell King - ARM Linux 2011-05-09 10:59 ` Catalin Marinas 2011-05-09 10:59 ` Catalin Marinas 2011-05-09 12:05 ` Russell King - ARM Linux 2011-05-09 12:05 ` Russell King - ARM Linux 2011-05-09 13:36 ` Catalin Marinas 2011-05-09 13:36 ` Catalin Marinas 2011-05-09 15:01 ` Catalin Marinas 2011-05-09 15:01 ` Catalin Marinas 2011-05-09 15:34 ` Russell King - ARM Linux 2011-05-09 15:34 ` Russell King - ARM Linux 2011-05-09 15:38 ` Catalin Marinas 2011-05-09 15:38 ` Catalin Marinas 2011-05-09 15:48 ` Russell King - ARM Linux 2011-05-09 15:48 ` Russell King - ARM Linux 2011-05-09 16:02 ` Catalin Marinas 2011-05-09 16:02 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 03/19] ARM: LPAE: Use unsigned long for __phys_to_virt and __virt_to_phys Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 21:44 ` Russell King - ARM Linux 2011-05-08 21:44 ` Russell King - ARM Linux 2011-05-16 17:28 ` Catalin Marinas 2011-05-16 17:28 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 04/19] ARM: LPAE: Make TTBR1 always point to swapper_pg_dir on ARMv7 Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 05/19] ARM: LPAE: Use PMD_(SHIFT|SIZE|MASK) instead of PGDIR_* Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 06/19] ARM: LPAE: Factor out 2-level page table definitions into separate files Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 07/19] ARM: LPAE: Add (pte|pmd|pgd|pgprot)val_t type definitions as u32 Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 08/19] ARM: LPAE: Use a mask for physical addresses in page table entries Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 09/19] ARM: LPAE: Introduce the 3-level page table format definitions Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 10/19] ARM: LPAE: Page table maintenance for the 3-level format Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 11/19] ARM: LPAE: MMU setup for the 3-level page table format Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 12/19] ARM: LPAE: Add fault handling support Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas [this message] 2011-05-08 12:51 ` [PATCH v5 13/19] ARM: LPAE: Add context switching support Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 14/19] ARM: LPAE: Add identity mapping support for the 3-level page table format Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 15/19] ARM: LPAE: Add support for cpu_v7_do_(suspend|resume) Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-18 7:27 ` Tony Lindgren 2011-05-18 7:27 ` Tony Lindgren 2011-05-20 13:21 ` Catalin Marinas 2011-05-20 13:21 ` Catalin Marinas 2011-05-20 15:17 ` Jean-Christophe PLAGNIOL-VILLARD 2011-05-20 15:17 ` Jean-Christophe PLAGNIOL-VILLARD 2011-05-20 18:09 ` Nicolas Pitre 2011-05-20 18:09 ` Nicolas Pitre 2011-05-22 21:09 ` Catalin Marinas 2011-05-22 21:09 ` Catalin Marinas 2011-05-24 6:26 ` Tony Lindgren 2011-05-24 6:26 ` Tony Lindgren 2011-05-08 12:51 ` [PATCH v5 16/19] ARM: LPAE: Use generic dma_addr_t type definition Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 17/19] ARM: LPAE: mark memory banks with start > ULONG_MAX as highmem Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 18/19] ARM: LPAE: add support for ATAG_MEM64 Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 19/19] ARM: LPAE: Add the Kconfig entries Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-11 10:23 ` [PATCH 20/19] ARM: LPAE: Invalidate the TLB before freeing the PMD Catalin Marinas 2011-05-11 10:23 ` Catalin Marinas 2011-05-11 10:31 ` Sergei Shtylyov 2011-05-11 10:31 ` Sergei Shtylyov 2011-05-11 10:40 ` Catalin Marinas 2011-05-11 10:40 ` Catalin Marinas 2011-05-11 10:54 ` Russell King - ARM Linux 2011-05-11 10:54 ` Russell King - ARM Linux 2011-05-11 13:40 ` Catalin Marinas 2011-05-11 13:40 ` Catalin Marinas 2011-05-11 14:00 ` Russell King - ARM Linux 2011-05-11 14:00 ` Russell King - ARM Linux 2011-05-11 15:58 ` Catalin Marinas 2011-05-11 15:58 ` Catalin Marinas 2011-05-23 16:54 ` [PATCH v5 00/19] ARM: Add support for the Large Physical Address Extensions Russell King - ARM Linux 2011-05-23 16:54 ` Russell King - ARM Linux 2011-05-23 17:22 ` Catalin Marinas 2011-05-23 17:22 ` Catalin Marinas 2011-05-24 10:04 ` Catalin Marinas 2011-05-24 10:04 ` Catalin Marinas 2011-05-26 21:15 ` Catalin Marinas 2011-05-26 21:15 ` Catalin Marinas 2011-05-26 21:44 ` Russell King - ARM Linux 2011-05-26 21:44 ` Russell King - ARM Linux 2011-05-27 9:09 ` Catalin Marinas 2011-05-27 9:09 ` Catalin Marinas
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