From: Catalin Marinas <catalin.marinas@arm.com> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Russell King - ARM Linux <linux@arm.linux.org.uk>, Will Deacon <will.deacon@arm.com> Subject: [PATCH v5 02/19] ARM: LPAE: add ISBs around MMU enabling code Date: Sun, 8 May 2011 13:51:21 +0100 [thread overview] Message-ID: <1304859098-10760-3-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1304859098-10760-1-git-send-email-catalin.marinas@arm.com> From: Will Deacon <will.deacon@arm.com> Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm/include/asm/assembler.h | 11 +++++++++++ arch/arm/kernel/head.S | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index bc2d2d7..2bcc456 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -184,6 +184,17 @@ #endif /* + * Instruction barrier + */ + .macro instr_sync +#if __LINUX_ARM_ARCH__ >= 7 + isb +#elif __LINUX_ARM_ARCH__ == 6 + mcr p15, 0, r0, c7, c5, 4 +#endif + .endm + +/* * SMP data memory barrier */ .macro smp_dmb mode diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index c9173cf..ea8fae7 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -385,8 +385,10 @@ ENDPROC(__enable_mmu) .align 5 __turn_mmu_on: mov r0, r0 + instr_sync mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg + instr_sync mov r3, r3 mov r3, r13 mov pc, r3
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From: catalin.marinas@arm.com (Catalin Marinas) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 02/19] ARM: LPAE: add ISBs around MMU enabling code Date: Sun, 8 May 2011 13:51:21 +0100 [thread overview] Message-ID: <1304859098-10760-3-git-send-email-catalin.marinas@arm.com> (raw) In-Reply-To: <1304859098-10760-1-git-send-email-catalin.marinas@arm.com> From: Will Deacon <will.deacon@arm.com> Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the *virtual* address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> --- arch/arm/include/asm/assembler.h | 11 +++++++++++ arch/arm/kernel/head.S | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index bc2d2d7..2bcc456 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -184,6 +184,17 @@ #endif /* + * Instruction barrier + */ + .macro instr_sync +#if __LINUX_ARM_ARCH__ >= 7 + isb +#elif __LINUX_ARM_ARCH__ == 6 + mcr p15, 0, r0, c7, c5, 4 +#endif + .endm + +/* * SMP data memory barrier */ .macro smp_dmb mode diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index c9173cf..ea8fae7 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -385,8 +385,10 @@ ENDPROC(__enable_mmu) .align 5 __turn_mmu_on: mov r0, r0 + instr_sync mcr p15, 0, r0, c1, c0, 0 @ write control reg mrc p15, 0, r3, c0, c0, 0 @ read id reg + instr_sync mov r3, r3 mov r3, r13 mov pc, r3
next prev parent reply other threads:[~2011-05-08 12:55 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2011-05-08 12:51 [PATCH v5 00/19] ARM: Add support for the Large Physical Address Extensions Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 01/19] ARM: LPAE: Use long long printk format for displaying the pud Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas [this message] 2011-05-08 12:51 ` [PATCH v5 02/19] ARM: LPAE: add ISBs around MMU enabling code Catalin Marinas 2011-05-08 21:41 ` Russell King - ARM Linux 2011-05-08 21:41 ` Russell King - ARM Linux 2011-05-09 10:22 ` Catalin Marinas 2011-05-09 10:22 ` Catalin Marinas 2011-05-09 10:32 ` Russell King - ARM Linux 2011-05-09 10:32 ` Russell King - ARM Linux 2011-05-09 10:59 ` Catalin Marinas 2011-05-09 10:59 ` Catalin Marinas 2011-05-09 12:05 ` Russell King - ARM Linux 2011-05-09 12:05 ` Russell King - ARM Linux 2011-05-09 13:36 ` Catalin Marinas 2011-05-09 13:36 ` Catalin Marinas 2011-05-09 15:01 ` Catalin Marinas 2011-05-09 15:01 ` Catalin Marinas 2011-05-09 15:34 ` Russell King - ARM Linux 2011-05-09 15:34 ` Russell King - ARM Linux 2011-05-09 15:38 ` Catalin Marinas 2011-05-09 15:38 ` Catalin Marinas 2011-05-09 15:48 ` Russell King - ARM Linux 2011-05-09 15:48 ` Russell King - ARM Linux 2011-05-09 16:02 ` Catalin Marinas 2011-05-09 16:02 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 03/19] ARM: LPAE: Use unsigned long for __phys_to_virt and __virt_to_phys Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 21:44 ` Russell King - ARM Linux 2011-05-08 21:44 ` Russell King - ARM Linux 2011-05-16 17:28 ` Catalin Marinas 2011-05-16 17:28 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 04/19] ARM: LPAE: Make TTBR1 always point to swapper_pg_dir on ARMv7 Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 05/19] ARM: LPAE: Use PMD_(SHIFT|SIZE|MASK) instead of PGDIR_* Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 06/19] ARM: LPAE: Factor out 2-level page table definitions into separate files Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 07/19] ARM: LPAE: Add (pte|pmd|pgd|pgprot)val_t type definitions as u32 Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 08/19] ARM: LPAE: Use a mask for physical addresses in page table entries Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 09/19] ARM: LPAE: Introduce the 3-level page table format definitions Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 10/19] ARM: LPAE: Page table maintenance for the 3-level format Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 11/19] ARM: LPAE: MMU setup for the 3-level page table format Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 12/19] ARM: LPAE: Add fault handling support Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 13/19] ARM: LPAE: Add context switching support Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 14/19] ARM: LPAE: Add identity mapping support for the 3-level page table format Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 15/19] ARM: LPAE: Add support for cpu_v7_do_(suspend|resume) Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-18 7:27 ` Tony Lindgren 2011-05-18 7:27 ` Tony Lindgren 2011-05-20 13:21 ` Catalin Marinas 2011-05-20 13:21 ` Catalin Marinas 2011-05-20 15:17 ` Jean-Christophe PLAGNIOL-VILLARD 2011-05-20 15:17 ` Jean-Christophe PLAGNIOL-VILLARD 2011-05-20 18:09 ` Nicolas Pitre 2011-05-20 18:09 ` Nicolas Pitre 2011-05-22 21:09 ` Catalin Marinas 2011-05-22 21:09 ` Catalin Marinas 2011-05-24 6:26 ` Tony Lindgren 2011-05-24 6:26 ` Tony Lindgren 2011-05-08 12:51 ` [PATCH v5 16/19] ARM: LPAE: Use generic dma_addr_t type definition Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 17/19] ARM: LPAE: mark memory banks with start > ULONG_MAX as highmem Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 18/19] ARM: LPAE: add support for ATAG_MEM64 Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-08 12:51 ` [PATCH v5 19/19] ARM: LPAE: Add the Kconfig entries Catalin Marinas 2011-05-08 12:51 ` Catalin Marinas 2011-05-11 10:23 ` [PATCH 20/19] ARM: LPAE: Invalidate the TLB before freeing the PMD Catalin Marinas 2011-05-11 10:23 ` Catalin Marinas 2011-05-11 10:31 ` Sergei Shtylyov 2011-05-11 10:31 ` Sergei Shtylyov 2011-05-11 10:40 ` Catalin Marinas 2011-05-11 10:40 ` Catalin Marinas 2011-05-11 10:54 ` Russell King - ARM Linux 2011-05-11 10:54 ` Russell King - ARM Linux 2011-05-11 13:40 ` Catalin Marinas 2011-05-11 13:40 ` Catalin Marinas 2011-05-11 14:00 ` Russell King - ARM Linux 2011-05-11 14:00 ` Russell King - ARM Linux 2011-05-11 15:58 ` Catalin Marinas 2011-05-11 15:58 ` Catalin Marinas 2011-05-23 16:54 ` [PATCH v5 00/19] ARM: Add support for the Large Physical Address Extensions Russell King - ARM Linux 2011-05-23 16:54 ` Russell King - ARM Linux 2011-05-23 17:22 ` Catalin Marinas 2011-05-23 17:22 ` Catalin Marinas 2011-05-24 10:04 ` Catalin Marinas 2011-05-24 10:04 ` Catalin Marinas 2011-05-26 21:15 ` Catalin Marinas 2011-05-26 21:15 ` Catalin Marinas 2011-05-26 21:44 ` Russell King - ARM Linux 2011-05-26 21:44 ` Russell King - ARM Linux 2011-05-27 9:09 ` Catalin Marinas 2011-05-27 9:09 ` Catalin Marinas
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