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* [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
@ 2011-08-30 23:04 Kumar Gala
  2011-08-30 23:04 ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
  2011-09-16 14:57 ` [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries Kumar Gala
  0 siblings, 2 replies; 6+ messages in thread
From: Kumar Gala @ 2011-08-30 23:04 UTC (permalink / raw)
  To: u-boot

We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p2041rdb/tlb.c |   34 +++++++++++++++++++---------------
 1 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/board/freescale/p2041rdb/tlb.c b/board/freescale/p2041rdb/tlb.c
index 43f28ed..1ee0493 100644
--- a/board/freescale/p2041rdb/tlb.c
+++ b/board/freescale/p2041rdb/tlb.c
@@ -27,23 +27,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
 		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
 	/* TLB 1 */
@@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* *I*G* - CCSRBAR */
 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
 	/* *I*G* - Flash, localbus */
@@ -75,43 +75,47 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
 		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
 		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 
 	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_1M, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
 		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      MAS3_SW|MAS3_SR, 0,
 		      0, 11, BOOKE_PAGESZ_1M, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_1M, 1),
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 13, BOOKE_PAGESZ_4M, 1),
 #endif
 };
-- 
1.5.6.5

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  2011-08-30 23:04 [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries Kumar Gala
@ 2011-08-30 23:04 ` Kumar Gala
  2011-08-30 23:04   ` [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files Kumar Gala
  2011-09-16 14:57   ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
  2011-09-16 14:57 ` [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries Kumar Gala
  1 sibling, 2 replies; 6+ messages in thread
From: Kumar Gala @ 2011-08-30 23:04 UTC (permalink / raw)
  To: u-boot

We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
P5020DS.  There is a significant amount of commonality shared between
these boards that we can refactor into common code:

* Initial LAW setup
* Initial TLB setup
* PCI setup

We start by moving the shared code between P3041DS, P4080DS, and P5020DS
into a common directory to be shared with other P-Series CoreNet boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/common/Makefile                    |   13 +++++++-
 board/freescale/common/p_corenet/Makefile          |   31 ++++++++++++++++++++
 .../{corenet_ds => common/p_corenet}/law.c         |    0 
 .../{corenet_ds => common/p_corenet}/pci.c         |    0 
 .../{corenet_ds => common/p_corenet}/tlb.c         |    0 
 board/freescale/corenet_ds/Makefile                |    3 --
 6 files changed, 42 insertions(+), 5 deletions(-)
 create mode 100644 board/freescale/common/p_corenet/Makefile
 rename board/freescale/{corenet_ds => common/p_corenet}/law.c (100%)
 rename board/freescale/{corenet_ds => common/p_corenet}/pci.c (100%)
 rename board/freescale/{corenet_ds => common/p_corenet}/tlb.c (100%)

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 9bdf45b..79f9de2 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -53,12 +53,21 @@ COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
 
+# deal with common files for P-series corenet based devices
+SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
+SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SUBLIB	:= $(addprefix $(obj),$(SUBLIB-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SUBLIB)
+	$(call cmd_link_o_target, $(OBJS) $(SUBLIB))
 
-$(LIB):	$(obj).depend $(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
+$(SUBLIB): $(obj).depend
+	$(MAKE) -C $(dir $(subst $(obj),,$@))
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile
new file mode 100644
index 0000000..a76f590
--- /dev/null
+++ b/board/freescale/common/p_corenet/Makefile
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2002-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB	= libp_corenet.o
+
+COBJS-y			+= law.o
+COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-y			+= tlb.o
+
+include $(TOPDIR)/post/rules.mk
diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/common/p_corenet/law.c
similarity index 100%
rename from board/freescale/corenet_ds/law.c
rename to board/freescale/common/p_corenet/law.c
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/common/p_corenet/pci.c
similarity index 100%
rename from board/freescale/corenet_ds/pci.c
rename to board/freescale/common/p_corenet/pci.c
diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/common/p_corenet/tlb.c
similarity index 100%
rename from board/freescale/corenet_ds/tlb.c
rename to board/freescale/common/p_corenet/tlb.c
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index c377c39..7e33007 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -34,9 +34,6 @@ COBJS-$(CONFIG_P5020DS)	+= eth_hydra.o
 COBJS-$(CONFIG_P3041DS)	+= p3041ds_ddr.o
 COBJS-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
 COBJS-$(CONFIG_P5020DS)	+= p5020ds_ddr.o
-COBJS-$(CONFIG_PCI)	+= pci.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
-- 
1.5.6.5

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  2011-08-30 23:04 ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
@ 2011-08-30 23:04   ` Kumar Gala
  2011-09-16 14:57     ` Kumar Gala
  2011-09-16 14:57   ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
  1 sibling, 1 reply; 6+ messages in thread
From: Kumar Gala @ 2011-08-30 23:04 UTC (permalink / raw)
  To: u-boot

The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.

The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/common/Makefile        |    1 +
 board/freescale/common/p_corenet/law.c |    5 ++
 board/freescale/common/p_corenet/tlb.c |    7 ++
 board/freescale/p2041rdb/Makefile      |    3 -
 board/freescale/p2041rdb/law.c         |   37 ----------
 board/freescale/p2041rdb/pci.c         |   39 ----------
 board/freescale/p2041rdb/tlb.c         |  123 --------------------------------
 7 files changed, 13 insertions(+), 202 deletions(-)
 delete mode 100644 board/freescale/p2041rdb/law.c
 delete mode 100644 board/freescale/p2041rdb/pci.c
 delete mode 100644 board/freescale/p2041rdb/tlb.c

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 79f9de2..b27f054 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -54,6 +54,7 @@ COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P5020DS)		+= ics307_clk.o
 
 # deal with common files for P-series corenet based devices
+SUBLIB-$(CONFIG_P2041RDB)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P3041DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P4080DS)	+= p_corenet/libp_corenet.o
 SUBLIB-$(CONFIG_P5020DS)	+= p_corenet/libp_corenet.o
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 58f23c5..09ef561 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -35,7 +35,12 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
 #endif
+#ifdef PIXIS_BASE_PHYS
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
+#ifdef CPLD_BASE_PHYS
+	SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	/* Limit DCSR to 32M to access NPC Trace Buffer */
 	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 5e48d6c..6a0026a 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -44,10 +44,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 		      MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
+#ifdef CPLD_BASE
+	SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
+		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
 
+#ifdef PIXIS_BASE
 	SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
 		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
+#endif
 
 	/* TLB 1 */
 	/* *I*** - Covers boot page */
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index b4cb83e..8d4da3a 100644
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -30,9 +30,6 @@ COBJS-y	+= $(BOARD).o
 COBJS-y += cpld.o
 COBJS-y	+= ddr.o
 COBJS-y	+= eth.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-COBJS-$(CONFIG_PCI) += pci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/freescale/p2041rdb/law.c b/board/freescale/p2041rdb/law.c
deleted file mode 100644
index 127a478..0000000
--- a/board/freescale/p2041rdb/law.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
-	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
-	SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2041rdb/pci.c b/board/freescale/p2041rdb/pci.c
deleted file mode 100644
index 1ab4cdf..0000000
--- a/board/freescale/p2041rdb/pci.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, bd_t *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
diff --git a/board/freescale/p2041rdb/tlb.c b/board/freescale/p2041rdb/tlb.c
deleted file mode 100644
index 1ee0493..0000000
--- a/board/freescale/p2041rdb/tlb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-	/*
-	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
-	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 0, BOOKE_PAGESZ_1M, 1),
-#else
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_16M, 1),
-
-	/* *I*G* - Flash, localbus */
-	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_1G, 1),
-
-	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-		      CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_256M, 1),
-
-	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 6, BOOKE_PAGESZ_256K, 1),
-
-	/* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 9, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
-		      MAS3_SW|MAS3_SR, 0,
-		      0, 11, BOOKE_PAGESZ_1M, 1),
-	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
-		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 12, BOOKE_PAGESZ_1M, 1),
-#endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 13, BOOKE_PAGESZ_4M, 1),
-#endif
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
-- 
1.5.6.5

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files
  2011-08-30 23:04   ` [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files Kumar Gala
@ 2011-09-16 14:57     ` Kumar Gala
  0 siblings, 0 replies; 6+ messages in thread
From: Kumar Gala @ 2011-09-16 14:57 UTC (permalink / raw)
  To: u-boot


On Aug 30, 2011, at 6:04 PM, Kumar Gala wrote:

> The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
> other P-Series CoreNet platforms.
> 
> The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
> CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
> TLB and LAW setup tables.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/common/Makefile        |    1 +
> board/freescale/common/p_corenet/law.c |    5 ++
> board/freescale/common/p_corenet/tlb.c |    7 ++
> board/freescale/p2041rdb/Makefile      |    3 -
> board/freescale/p2041rdb/law.c         |   37 ----------
> board/freescale/p2041rdb/pci.c         |   39 ----------
> board/freescale/p2041rdb/tlb.c         |  123 --------------------------------
> 7 files changed, 13 insertions(+), 202 deletions(-)
> delete mode 100644 board/freescale/p2041rdb/law.c
> delete mode 100644 board/freescale/p2041rdb/pci.c
> delete mode 100644 board/freescale/p2041rdb/tlb.c

applied to 85xx 'next'

- k

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
  2011-08-30 23:04 [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries Kumar Gala
  2011-08-30 23:04 ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
@ 2011-09-16 14:57 ` Kumar Gala
  1 sibling, 0 replies; 6+ messages in thread
From: Kumar Gala @ 2011-09-16 14:57 UTC (permalink / raw)
  To: u-boot


On Aug 30, 2011, at 6:04 PM, Kumar Gala wrote:

> We shouldn't be setting execute permissions on TLB entries that will not
> actually have any code run from them.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/p2041rdb/tlb.c |   34 +++++++++++++++++++---------------
> 1 files changed, 19 insertions(+), 15 deletions(-)

applied to 85xx 'next'

- k

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
  2011-08-30 23:04 ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
  2011-08-30 23:04   ` [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files Kumar Gala
@ 2011-09-16 14:57   ` Kumar Gala
  1 sibling, 0 replies; 6+ messages in thread
From: Kumar Gala @ 2011-09-16 14:57 UTC (permalink / raw)
  To: u-boot


On Aug 30, 2011, at 6:04 PM, Kumar Gala wrote:

> We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
> are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
> P5020DS.  There is a significant amount of commonality shared between
> these boards that we can refactor into common code:
> 
> * Initial LAW setup
> * Initial TLB setup
> * PCI setup
> 
> We start by moving the shared code between P3041DS, P4080DS, and P5020DS
> into a common directory to be shared with other P-Series CoreNet boards.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/common/Makefile                    |   13 +++++++-
> board/freescale/common/p_corenet/Makefile          |   31 ++++++++++++++++++++
> .../{corenet_ds => common/p_corenet}/law.c         |    0 
> .../{corenet_ds => common/p_corenet}/pci.c         |    0 
> .../{corenet_ds => common/p_corenet}/tlb.c         |    0 
> board/freescale/corenet_ds/Makefile                |    3 --
> 6 files changed, 42 insertions(+), 5 deletions(-)
> create mode 100644 board/freescale/common/p_corenet/Makefile
> rename board/freescale/{corenet_ds => common/p_corenet}/law.c (100%)
> rename board/freescale/{corenet_ds => common/p_corenet}/pci.c (100%)
> rename board/freescale/{corenet_ds => common/p_corenet}/tlb.c (100%)

applied to 85xx 'next'

- k

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-09-16 14:57 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-08-30 23:04 [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries Kumar Gala
2011-08-30 23:04 ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
2011-08-30 23:04   ` [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files Kumar Gala
2011-09-16 14:57     ` Kumar Gala
2011-09-16 14:57   ` [U-Boot] [PATCH] powerpc/85xx: refactor common P-Series CoreNet files for FSL boards Kumar Gala
2011-09-16 14:57 ` [U-Boot] [PATCH] powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries Kumar Gala

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