* [PATCH v2 00/10]HDMI: Split hdmi.c in DSS to seperate OMAP dependent
@ 2011-08-29 6:14 mythripk
2011-08-29 6:14 ` [PATCH v2 01/10] OMAP4: DSS: HDMI: HDMI clean up to pass base_address mythripk
0 siblings, 1 reply; 23+ messages in thread
From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw)
To: tomi.valkeinen, linux-omap; +Cc: Mythri P K
From: Mythri P K <mythripk@ti.com>
HDMI IP block is common between TI OMAP4 Procerssor and Netra processor although
the Display subsytem is different.Also the IP block in future OMAP may differ
from the one existing in OMAP4. Thus to reuse the code between these two
processors , and maintain the multi omap build functionality in DSS.
HDMI IP dependant code is seperated out from hdmi.c and moved to
new library file hdmi_ti_4xxx_ip.c.From the DSS dependent HDMI code only the
function pointer to functionality/features offered by HDMI is called.
This patch series does the split and also renames hdmi_omap4_panel.c to
hdmi_panel.c as that file has nothing specific to OMAP4 and can be reused for
other OMAP family of processors as well.
This patch series is based on Tomi's LO-DSS2 master branch.
changes since V1: Function pointer approach to call the HDMI IP functions from
DSS HDMI
Mythri P K (10):
OMAP4: DSS: HDMI: HDMI clean up to pass base_address dynamically
to IP dependant functions of HDMI
OMAP4: DSS: HDMI: Move pll and video configuration info to ip_data
structure
OMAP4: DSS: HDMI: Use specific HDMI timings structure instead of OMAP
DSS timings
OMAP4: DSS: HDMI: Move the common header file definition to
Include/video
OMAP4 : DSS : HDMI : Move the EDID portion from HDMI IP header
OMAP4: DSS2: HDMI: Split the HDMI driver to DSS and IP
specific portion.
OMAP4: DSS2: HDMI: Provide a wrapper API to configure PLL and
PHY configuration
OMAP4: DSS2: HDMI: Function pointer approach to call HDMI IP
driver function from DSS
MAP4: DSS: HDMI: Rename the functions in HDMI IP library to IP
specific name
OMAP4: DSS: Rename hdmi_omap4_panel.c to hdmi_panel.c
drivers/video/omap2/dss/Makefile | 2 +-
drivers/video/omap2/dss/dss.h | 10 -
drivers/video/omap2/dss/dss_features.c | 24 +-
drivers/video/omap2/dss/dss_features.h | 1 +
drivers/video/omap2/dss/hdmi.c | 925 +++-----------------
drivers/video/omap2/dss/hdmi.h | 631 -------------
.../omap2/dss/{hdmi_omap4_panel.c => hdmi_panel.c} | 0
drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c | 776 ++++++++++++++++
drivers/video/omap2/dss/hdmi_ti_4xxx_ip.h | 582 ++++++++++++
include/video/omapdss.h | 19 +
include/video/omaphdmi.h | 95 ++
11 files changed, 1642 insertions(+), 1423 deletions(-)
delete mode 100644 drivers/video/omap2/dss/hdmi.h
rename drivers/video/omap2/dss/{hdmi_omap4_panel.c => hdmi_panel.c} (100%)
create mode 100644 drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c
create mode 100644 drivers/video/omap2/dss/hdmi_ti_4xxx_ip.h
create mode 100644 include/video/omaphdmi.h
--
1.7.5.4
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v2 01/10] OMAP4: DSS: HDMI: HDMI clean up to pass base_address 2011-08-29 6:14 [PATCH v2 00/10]HDMI: Split hdmi.c in DSS to seperate OMAP dependent mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration mythripk 0 siblings, 1 reply; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> As the base_address of the HDMI might differ across SoC's, offset of the HDMI logical blocks and base address got from the platform data are passed dynamically to the functions that modify HDMI IP registers. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/hdmi.c | 501 +++++++++++++++++++++++----------------- drivers/video/omap2/dss/hdmi.h | 292 ++++++++++++------------ 2 files changed, 435 insertions(+), 358 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index b8e02e4..544f93e 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -43,11 +43,17 @@ #include "hdmi.h" #include "dss_features.h" +#define HDMI_WP 0x0 +#define HDMI_CORE_SYS 0x400 +#define HDMI_CORE_AV 0x900 +#define HDMI_PLLCTRL 0x200 +#define HDMI_PHY 0x300 + static struct { struct mutex lock; struct omap_display_platform_data *pdata; struct platform_device *pdev; - void __iomem *base_wp; /* HDMI wrapper */ + struct hdmi_ip_data hdmi_data; int code; int mode; u8 edid[HDMI_EDID_MAX_LENGTH]; @@ -145,21 +151,49 @@ static const int code_vesa[85] = { static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; -static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val) +static inline void hdmi_write_reg(void __iomem *base_addr, + const struct hdmi_reg idx, u32 val) +{ + __raw_writel(val, base_addr + idx.idx); +} + +static inline u32 hdmi_read_reg(void __iomem *base_addr, + const struct hdmi_reg idx) +{ + return __raw_readl(base_addr + idx.idx); +} + +static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp; +} + +static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data) { - __raw_writel(val, hdmi.base_wp + idx.idx); + return ip_data->base_wp + ip_data->phy_offset; } -static inline u32 hdmi_read_reg(const struct hdmi_reg idx) +static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data) { - return __raw_readl(hdmi.base_wp + idx.idx); + return ip_data->base_wp + ip_data->pll_offset; } -static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx, +static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp + ip_data->core_av_offset; +} + +static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp + ip_data->core_sys_offset; +} + +static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, + const struct hdmi_reg idx, int b2, int b1, u32 val) { u32 t = 0; - while (val != REG_GET(idx, b2, b1)) { + while (val != REG_GET(base_addr, idx, b2, b1)) { udelay(1); if (t++ > 10000) return !val; @@ -195,21 +229,23 @@ int hdmi_init_display(struct omap_dss_device *dssdev) return 0; } -static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, +static int hdmi_pll_init(struct hdmi_ip_data *ip_data, + enum hdmi_clk_refsel refsel, int dcofreq, struct hdmi_pll_info *fmt, u16 sd) { u32 r; + void __iomem *pll_base = hdmi_pll_base(ip_data); /* PLL start always use manual mode */ - REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0); + REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); - r = hdmi_read_reg(PLLCTRL_CFG1); + r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ - hdmi_write_reg(PLLCTRL_CFG1, r); + hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); - r = hdmi_read_reg(PLLCTRL_CFG2); + r = hdmi_read_reg(pll_base, PLLCTRL_CFG2); r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ @@ -217,38 +253,40 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, if (dcofreq) { /* divider programming for frequency beyond 1000Mhz */ - REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10); + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10); r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ } else { r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ } - hdmi_write_reg(PLLCTRL_CFG2, r); + hdmi_write_reg(pll_base, PLLCTRL_CFG2, r); - r = hdmi_read_reg(PLLCTRL_CFG4); + r = hdmi_read_reg(pll_base, PLLCTRL_CFG4); r = FLD_MOD(r, fmt->regm2, 24, 18); r = FLD_MOD(r, fmt->regmf, 17, 0); - hdmi_write_reg(PLLCTRL_CFG4, r); + hdmi_write_reg(pll_base, PLLCTRL_CFG4, r); /* go now */ - REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0); + REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0); /* wait for bit change */ - if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) { + if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO, + 0, 0, 1) != 1) { DSSERR("PLL GO bit not set\n"); return -ETIMEDOUT; } /* Wait till the lock bit is set in PLL status */ - if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { + if (hdmi_wait_for_bit_change(pll_base, + PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { DSSWARN("cannot lock PLL\n"); DSSWARN("CFG1 0x%x\n", - hdmi_read_reg(PLLCTRL_CFG1)); + hdmi_read_reg(pll_base, PLLCTRL_CFG1)); DSSWARN("CFG2 0x%x\n", - hdmi_read_reg(PLLCTRL_CFG2)); + hdmi_read_reg(pll_base, PLLCTRL_CFG2)); DSSWARN("CFG4 0x%x\n", - hdmi_read_reg(PLLCTRL_CFG4)); + hdmi_read_reg(pll_base, PLLCTRL_CFG4)); return -ETIMEDOUT; } @@ -258,13 +296,14 @@ static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, } /* PHY_PWR_CMD */ -static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val) +static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val) { /* Command for power control of HDMI PHY */ - REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6); + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6); /* Status of the power control of HDMI PHY */ - if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) { + if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), + HDMI_WP_PWR_CTRL, 5, 4, val) != val) { DSSERR("Failed to set PHY power mode to %d\n", val); return -ETIMEDOUT; } @@ -273,13 +312,14 @@ static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val) } /* PLL_PWR_CMD */ -static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val) +int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val) { /* Command for power control of HDMI PLL */ - REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2); + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); /* wait till PHY_PWR_STATUS is set */ - if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) { + if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, + 1, 0, val) != val) { DSSERR("Failed to set PHY_PWR_STATUS\n"); return -ETIMEDOUT; } @@ -287,13 +327,14 @@ static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val) return 0; } -static int hdmi_pll_reset(void) +static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) { /* SYSRESET controlled by power FSM */ - REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3); + REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3); /* READ 0x0 reset is in progress */ - if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { + if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data), + PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { DSSERR("Failed to sysreset PLL\n"); return -ETIMEDOUT; } @@ -301,15 +342,16 @@ static int hdmi_pll_reset(void) return 0; } -static int hdmi_phy_init(void) +static int hdmi_phy_init(struct hdmi_ip_data *ip_data) { u16 r = 0; + void __iomem *phy_base = hdmi_phy_base(ip_data); - r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON); + r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); if (r) return r; - r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON); + r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); if (r) return r; @@ -317,65 +359,68 @@ static int hdmi_phy_init(void) * Read address 0 in order to get the SCP reset done completed * Dummy access performed to make sure reset is done */ - hdmi_read_reg(HDMI_TXPHY_TX_CTRL); + hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL); /* * Write to phy address 0 to configure the clock * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field */ - REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); + REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ - hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); + hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); /* Setup max LDO voltage */ - REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); + REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); /* Write to phy address 3 to change the polarity control */ - REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); + REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); return 0; } -static int hdmi_pll_program(struct hdmi_pll_info *fmt) +static int hdmi_pll_program(struct hdmi_ip_data *ip_data, + struct hdmi_pll_info *fmt) { u16 r = 0; enum hdmi_clk_refsel refsel; - r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); + r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); if (r) return r; - r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); + r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); if (r) return r; - r = hdmi_pll_reset(); + r = hdmi_pll_reset(ip_data); if (r) return r; refsel = HDMI_REFSEL_SYSCLK; - r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); + r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); if (r) return r; return 0; } -static void hdmi_phy_off(void) +static void hdmi_phy_off(struct hdmi_ip_data *ip_data) { - hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF); + hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); } -static int hdmi_core_ddc_edid(u8 *pedid, int ext) +static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, + u8 *pedid, int ext) { u32 i, j; char checksum = 0; u32 offset = 0; + void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); /* Turn on CLK for DDC */ - REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0); + REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0); /* * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / @@ -386,21 +431,21 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext) if (!ext) { /* Clk SCL Devices */ - REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); /* HDMI_CORE_DDC_STATUS_IN_PROG */ - if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, - 4, 4, 0) != 0) { + if (hdmi_wait_for_bit_change(core_sys_base, + HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { DSSERR("Failed to program DDC\n"); return -ETIMEDOUT; } /* Clear FIFO */ - REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); /* HDMI_CORE_DDC_STATUS_IN_PROG */ - if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, - 4, 4, 0) != 0) { + if (hdmi_wait_for_bit_change(core_sys_base, + HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { DSSERR("Failed to program DDC\n"); return -ETIMEDOUT; } @@ -411,44 +456,45 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext) } /* Load Segment Address Register */ - REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0); /* Load Slave Address Register */ - REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); /* Load Offset Address Register */ - REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); /* Load Byte Count */ - REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); - REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); /* Set DDC_CMD */ if (ext) - REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); else - REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); /* HDMI_CORE_DDC_STATUS_BUS_LOW */ - if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) { + if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { DSSWARN("I2C Bus Low?\n"); return -EIO; } /* HDMI_CORE_DDC_STATUS_NO_ACK */ - if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) { + if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { DSSWARN("I2C No Ack\n"); return -EIO; } i = ext * 128; j = 0; - while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) || - (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && - j < 128) { + while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) || + (REG_GET(core_sys_base, + HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) { - if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) { + if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) { /* FIFO not empty */ - pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0); + pedid[i++] = REG_GET(core_sys_base, + HDMI_CORE_DDC_DATA, 7, 0); j++; } } @@ -464,12 +510,12 @@ static int hdmi_core_ddc_edid(u8 *pedid, int ext) return 0; } -static int read_edid(u8 *pedid, u16 max_length) +static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) { int r = 0, n = 0, i = 0; int max_ext_blocks = (max_length / 128) - 1; - r = hdmi_core_ddc_edid(pedid, 0); + r = hdmi_core_ddc_edid(ip_data, pedid, 0); if (r) { return r; } else { @@ -485,7 +531,7 @@ static int read_edid(u8 *pedid, u16 max_length) n = max_ext_blocks; for (i = 1; i <= n; i++) { - r = hdmi_core_ddc_edid(pedid, i); + r = hdmi_core_ddc_edid(ip_data, pedid, i); if (r) return r; } @@ -655,8 +701,8 @@ static void hdmi_read_edid(struct omap_video_timings *dp) memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); if (!hdmi.edid_set) - ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH); - + ret = read_edid(&hdmi.hdmi_data, hdmi.edid, + HDMI_EDID_MAX_LENGTH); if (!ret) { if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { /* search for timings of default resolution */ @@ -722,41 +768,44 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, repeat_cfg->generic_pkt_repeat = 0; } -static void hdmi_core_powerdown_disable(void) +static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data) { DSSDBG("Enter hdmi_core_powerdown_disable\n"); - REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0); + REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0); } -static void hdmi_core_swreset_release(void) +static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data) { DSSDBG("Enter hdmi_core_swreset_release\n"); - REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0); + REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0); } -static void hdmi_core_swreset_assert(void) +static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data) { DSSDBG("Enter hdmi_core_swreset_assert\n"); - REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0); + REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0); } -/* DSS_HDMI_CORE_VIDEO_CONFIG */ -static void hdmi_core_video_config(struct hdmi_core_video_config *cfg) +/* HDMI_CORE_VIDEO_CONFIG */ +static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, + struct hdmi_core_video_config *cfg) { u32 r = 0; + void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); /* sys_ctrl1 default configuration not tunable */ - r = hdmi_read_reg(HDMI_CORE_CTRL1); + r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1); r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); - hdmi_write_reg(HDMI_CORE_CTRL1, r); + hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r); - REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); + REG_FLD_MOD(core_sys_base, + HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); /* Vid_Mode */ - r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE); + r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); /* dither truncation configuration */ if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { @@ -766,106 +815,108 @@ static void hdmi_core_video_config(struct hdmi_core_video_config *cfg) r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); r = FLD_MOD(r, 0, 5, 5); } - hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r); + hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); /* HDMI_Ctrl */ - r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL); + r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); r = FLD_MOD(r, cfg->pkt_mode, 5, 3); r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); - hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r); + hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); /* TMDS_CTRL */ - REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL, - cfg->tclk_sel_clkmult, 6, 5); + REG_FLD_MOD(core_sys_base, + HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); } -static void hdmi_core_aux_infoframe_avi_config( +static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data, struct hdmi_core_infoframe_avi info_avi) { u32 val; char sum = 0, checksum = 0; + void __iomem *av_base = hdmi_av_base(ip_data); sum += 0x82 + 0x002 + 0x00D; - hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082); - hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002); - hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); val = (info_avi.db1_format << 5) | (info_avi.db1_active_info << 4) | (info_avi.db1_bar_info_dv << 2) | (info_avi.db1_scan_info); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); sum += val; val = (info_avi.db2_colorimetry << 6) | (info_avi.db2_aspect_ratio << 4) | (info_avi.db2_active_fmt_ar); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); sum += val; val = (info_avi.db3_itc << 7) | (info_avi.db3_ec << 4) | (info_avi.db3_q_range << 2) | (info_avi.db3_nup_scaling); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); sum += val; - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), + info_avi.db4_videocode); sum += info_avi.db4_videocode; val = info_avi.db5_pixel_repeat; - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); sum += val; val = info_avi.db6_7_line_eoftop & 0x00FF; - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); sum += val; val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); sum += val; val = info_avi.db8_9_line_sofbottom & 0x00FF; - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); sum += val; val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); sum += val; val = info_avi.db10_11_pixel_eofleft & 0x00FF; - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); sum += val; val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); sum += val; val = info_avi.db12_13_pixel_sofright & 0x00FF; - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); sum += val; val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); - hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); sum += val; checksum = 0x100 - sum; - hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); } -static void hdmi_core_av_packet_config( +static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data, struct hdmi_core_packet_enable_repeat repeat_cfg) { /* enable/repeat the infoframe */ - hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1, + hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1, (repeat_cfg.audio_pkt << 5) | (repeat_cfg.audio_pkt_repeat << 4) | (repeat_cfg.avi_infoframe << 1) | (repeat_cfg.avi_infoframe_repeat)); /* enable/repeat the packet */ - hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2, + hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2, (repeat_cfg.gen_cntrl_pkt << 3) | (repeat_cfg.gen_cntrl_pkt_repeat << 2) | (repeat_cfg.generic_pkt << 1) | @@ -897,9 +948,9 @@ static void hdmi_wp_init(struct omap_video_timings *timings, } -static void hdmi_wp_video_start(bool start) +static void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start) { - REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31); + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31); } static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, @@ -918,33 +969,34 @@ static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, timings->vsw = param->timings.timings.vsw; } -static void hdmi_wp_video_config_format( +static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, struct hdmi_video_format *video_fmt) { u32 l = 0; - REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8); + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, + video_fmt->packing_mode, 10, 8); l |= FLD_VAL(video_fmt->y_res, 31, 16); l |= FLD_VAL(video_fmt->x_res, 15, 0); - hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l); } -static void hdmi_wp_video_config_interface( +static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data, struct hdmi_video_interface *video_int) { u32 r; DSSDBG("Enter hdmi_wp_video_config_interface\n"); - r = hdmi_read_reg(HDMI_WP_VIDEO_CFG); + r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); r = FLD_MOD(r, video_int->vsp, 7, 7); r = FLD_MOD(r, video_int->hsp, 6, 6); r = FLD_MOD(r, video_int->interlacing, 3, 3); r = FLD_MOD(r, video_int->tm, 1, 0); - hdmi_write_reg(HDMI_WP_VIDEO_CFG, r); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); } -static void hdmi_wp_video_config_timing( +static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, struct omap_video_timings *timings) { u32 timing_h = 0; @@ -955,15 +1007,16 @@ static void hdmi_wp_video_config_timing( timing_h |= FLD_VAL(timings->hbp, 31, 20); timing_h |= FLD_VAL(timings->hfp, 19, 8); timing_h |= FLD_VAL(timings->hsw, 7, 0); - hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h); timing_v |= FLD_VAL(timings->vbp, 31, 20); timing_v |= FLD_VAL(timings->vfp, 19, 8); timing_v |= FLD_VAL(timings->vsw, 7, 0); - hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); } -static void hdmi_basic_configure(struct hdmi_config *cfg) +static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, + struct hdmi_config *cfg) { /* HDMI */ struct omap_video_timings video_timing; @@ -984,36 +1037,36 @@ static void hdmi_basic_configure(struct hdmi_config *cfg) hdmi_wp_video_init_format(&video_format, &video_timing, cfg); - hdmi_wp_video_config_timing(&video_timing); + hdmi_wp_video_config_timing(ip_data, &video_timing); /* video config */ video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; - hdmi_wp_video_config_format(&video_format); + hdmi_wp_video_config_format(ip_data, &video_format); video_interface.vsp = cfg->timings.vsync_pol; video_interface.hsp = cfg->timings.hsync_pol; video_interface.interlacing = cfg->interlace; video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ - hdmi_wp_video_config_interface(&video_interface); + hdmi_wp_video_config_interface(ip_data, &video_interface); /* * configure core video part * set software reset in the core */ - hdmi_core_swreset_assert(); + hdmi_core_swreset_assert(ip_data); /* power down off */ - hdmi_core_powerdown_disable(); + hdmi_core_powerdown_disable(ip_data); v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; v_core_cfg.hdmi_dvi = cfg->cm.mode; - hdmi_core_video_config(&v_core_cfg); + hdmi_core_video_config(ip_data, &v_core_cfg); /* release software reset in the core */ - hdmi_core_swreset_release(); + hdmi_core_swreset_release(ip_data); /* * configure packet @@ -1038,7 +1091,7 @@ static void hdmi_basic_configure(struct hdmi_config *cfg) avi_cfg.db10_11_pixel_eofleft = 0; avi_cfg.db12_13_pixel_sofright = 0; - hdmi_core_aux_infoframe_avi_config(avi_cfg); + hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg); /* enable/repeat the infoframe */ repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; @@ -1046,7 +1099,7 @@ static void hdmi_basic_configure(struct hdmi_config *cfg) /* wakeup */ repeat_cfg.audio_pkt = HDMI_PACKETENABLE; repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; - hdmi_core_av_packet_config(repeat_cfg); + hdmi_core_av_packet_config(ip_data, repeat_cfg); } static void update_hdmi_timings(struct hdmi_config *cfg, @@ -1136,16 +1189,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi_compute_pll(dssdev, phy, &pll_data); - hdmi_wp_video_start(0); + hdmi_wp_video_start(&hdmi.hdmi_data, 0); - /* config the PLL and PHY first */ - r = hdmi_pll_program(&pll_data); + /* config the PLL and PHY hdmi_set_pll_pwrfirst */ + r = hdmi_pll_program(&hdmi.hdmi_data, &pll_data); if (r) { DSSDBG("Failed to lock PLL\n"); goto err; } - r = hdmi_phy_init(); + r = hdmi_phy_init(&hdmi.hdmi_data); if (r) { DSSDBG("Failed to start PHY\n"); goto err; @@ -1153,7 +1206,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi.cfg.cm.mode = hdmi.mode; hdmi.cfg.cm.code = hdmi.code; - hdmi_basic_configure(&hdmi.cfg); + hdmi_basic_configure(&hdmi.hdmi_data, &hdmi.cfg); /* Make selection of HDMI in DSS */ dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); @@ -1175,7 +1228,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); - hdmi_wp_video_start(1); + hdmi_wp_video_start(&hdmi.hdmi_data, 1); return 0; err: @@ -1187,9 +1240,9 @@ static void hdmi_power_off(struct omap_dss_device *dssdev) { dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); - hdmi_wp_video_start(0); - hdmi_phy_off(); - hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); + hdmi_wp_video_start(&hdmi.hdmi_data, 0); + hdmi_phy_off(&hdmi.hdmi_data); + hdmi_set_pll_pwr(&hdmi.hdmi_data, HDMI_PLLPWRCMD_ALLOFF); hdmi_runtime_put(); hdmi.edid_set = 0; @@ -1287,14 +1340,14 @@ void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) -static void hdmi_wp_audio_config_format( - struct hdmi_audio_format *aud_fmt) +static void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data, + struct hdmi_audio_format *aud_fmt) { u32 r; DSSDBG("Enter hdmi_wp_audio_config_format\n"); - r = hdmi_read_reg(HDMI_WP_AUDIO_CFG); + r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG); r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24); r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16); r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5); @@ -1303,68 +1356,76 @@ static void hdmi_wp_audio_config_format( r = FLD_MOD(r, aud_fmt->sample_order, 2, 2); r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1); r = FLD_MOD(r, aud_fmt->sample_size, 0, 0); - hdmi_write_reg(HDMI_WP_AUDIO_CFG, r); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r); } -static void hdmi_wp_audio_config_dma(struct hdmi_audio_dma *aud_dma) +static void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data, + struct hdmi_audio_dma *aud_dma) { u32 r; DSSDBG("Enter hdmi_wp_audio_config_dma\n"); - r = hdmi_read_reg(HDMI_WP_AUDIO_CFG2); + r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2); r = FLD_MOD(r, aud_dma->transfer_size, 15, 8); r = FLD_MOD(r, aud_dma->block_size, 7, 0); - hdmi_write_reg(HDMI_WP_AUDIO_CFG2, r); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r); - r = hdmi_read_reg(HDMI_WP_AUDIO_CTRL); + r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL); r = FLD_MOD(r, aud_dma->mode, 9, 9); r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0); - hdmi_write_reg(HDMI_WP_AUDIO_CTRL, r); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r); } -static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg) +static void hdmi_core_audio_config(struct hdmi_ip_data *ip_data, + struct hdmi_core_audio_config *cfg) { u32 r; + void __iomem *av_base = hdmi_av_base(ip_data); /* audio clock recovery parameters */ - r = hdmi_read_reg(HDMI_CORE_AV_ACR_CTRL); + r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); r = FLD_MOD(r, cfg->use_mclk, 2, 2); r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); r = FLD_MOD(r, cfg->cts_mode, 0, 0); - hdmi_write_reg(HDMI_CORE_AV_ACR_CTRL, r); + hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); - REG_FLD_MOD(HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); - REG_FLD_MOD(HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); - REG_FLD_MOD(HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { - REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); - REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); - REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); + REG_FLD_MOD(av_base, + HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); + REG_FLD_MOD(av_base, + HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); } else { /* * HDMI IP uses this configuration to divide the MCLK to * update CTS value. */ - REG_FLD_MOD(HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); + REG_FLD_MOD(av_base, + HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); /* Configure clock for audio packets */ - REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_1, - cfg->aud_par_busclk, 7, 0); - REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_2, - (cfg->aud_par_busclk >> 8), 7, 0); - REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_3, - (cfg->aud_par_busclk >> 16), 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, + cfg->aud_par_busclk, 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, + (cfg->aud_par_busclk >> 8), 7, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, + (cfg->aud_par_busclk >> 16), 7, 0); } /* Override of SPDIF sample frequency with value in I2S_CHST4 */ - REG_FLD_MOD(HDMI_CORE_AV_SPDIF_CTRL, cfg->fs_override, 1, 1); + REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, + cfg->fs_override, 1, 1); /* I2S parameters */ - REG_FLD_MOD(HDMI_CORE_AV_I2S_CHST4, cfg->freq_sample, 3, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4, + cfg->freq_sample, 3, 0); - r = hdmi_read_reg(HDMI_CORE_AV_I2S_IN_CTRL); + r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7); r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5); @@ -1373,69 +1434,72 @@ static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg) r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); - hdmi_write_reg(HDMI_CORE_AV_I2S_IN_CTRL, r); + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); - r = hdmi_read_reg(HDMI_CORE_AV_I2S_CHST5); + r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5); r = FLD_MOD(r, cfg->freq_sample, 7, 4); r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1); r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0); - hdmi_write_reg(HDMI_CORE_AV_I2S_CHST5, r); + hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r); - REG_FLD_MOD(HDMI_CORE_AV_I2S_IN_LEN, cfg->i2s_cfg.in_length_bits, 3, 0); + REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, + cfg->i2s_cfg.in_length_bits, 3, 0); /* Audio channels and mode parameters */ - REG_FLD_MOD(HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); - r = hdmi_read_reg(HDMI_CORE_AV_AUD_MODE); + REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); + r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); r = FLD_MOD(r, cfg->en_spdif, 1, 1); - hdmi_write_reg(HDMI_CORE_AV_AUD_MODE, r); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); } -static void hdmi_core_audio_infoframe_config( +static void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data, struct hdmi_core_infoframe_audio *info_aud) { u8 val; u8 sum = 0, checksum = 0; + void __iomem *av_base = hdmi_av_base(ip_data); /* * Set audio info frame type, version and length as * described in HDMI 1.4a Section 8.2.2 specification. * Checksum calculation is defined in Section 5.3.5. */ - hdmi_write_reg(HDMI_CORE_AV_AUDIO_TYPE, 0x84); - hdmi_write_reg(HDMI_CORE_AV_AUDIO_VERS, 0x01); - hdmi_write_reg(HDMI_CORE_AV_AUDIO_LEN, 0x0a); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); sum += 0x84 + 0x001 + 0x00a; val = (info_aud->db1_coding_type << 4) | (info_aud->db1_channel_count - 1); - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(0), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val); sum += val; val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size; - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(1), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val); sum += val; - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(2), 0x00); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00); val = info_aud->db4_channel_alloc; - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(3), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val); sum += val; val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3); - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(4), val); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val); sum += val; - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(5), 0x00); - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(6), 0x00); - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(7), 0x00); - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(8), 0x00); - hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(9), 0x00); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); + hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); checksum = 0x100 - sum; - hdmi_write_reg(HDMI_CORE_AV_AUDIO_CHSUM, checksum); + hdmi_write_reg(av_base, + HDMI_CORE_AV_AUDIO_CHSUM, checksum); /* * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing @@ -1443,7 +1507,8 @@ static void hdmi_core_audio_infoframe_config( */ } -static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts) +static int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data, + u32 sample_freq, u32 *n, u32 *cts) { u32 r; u32 deep_color = 0; @@ -1455,7 +1520,7 @@ static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts) * Obtain current deep color configuration. This needed * to calculate the TMDS clock based on the pixel clock. */ - r = REG_GET(HDMI_WP_VIDEO_CFG, 1, 0); + r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0); switch (r) { case 1: /* No deep color selected */ deep_color = 100; @@ -1499,7 +1564,8 @@ static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts) return 0; } -static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, +static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data, + struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { @@ -1553,7 +1619,7 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } - err = hdmi_config_audio_acr(params_rate(params), &n, &cts); + err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts); if (err < 0) return err; @@ -1569,8 +1635,8 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; audio_dma.fifo_threshold = 0x20; /* in number of samples */ - hdmi_wp_audio_config_dma(&audio_dma); - hdmi_wp_audio_config_format(&audio_format); + hdmi_wp_audio_config_dma(ip_data, &audio_dma); + hdmi_wp_audio_config_format(ip_data, &audio_format); /* * I2S config @@ -1614,7 +1680,7 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, /* Use parallel audio interface */ core_cfg.en_parallel_aud_input = true; - hdmi_core_audio_config(&core_cfg); + hdmi_core_audio_config(ip_data, &core_cfg); /* * Configure packet @@ -1628,29 +1694,36 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream, aud_if_cfg.db5_downmix_inh = false; aud_if_cfg.db5_lsv = 0; - hdmi_core_audio_infoframe_config(&aud_if_cfg); + hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg); return 0; } -static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, - struct snd_soc_dai *dai) +static int hdmi_audio_trigger(struct hdmi_ip_data *ip_data, + struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *dai) { int err = 0; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 1, 0, 0); - REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 31, 31); - REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 30, 30); + REG_FLD_MOD(hdmi_av_base(ip_data), + HDMI_CORE_AV_AUD_MODE, 1, 0, 0); + REG_FLD_MOD(hdmi_wp_base(ip_data), + HDMI_WP_AUDIO_CTRL, 1, 31, 31); + REG_FLD_MOD(hdmi_wp_base(ip_data), + HDMI_WP_AUDIO_CTRL, 1, 30, 30); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 0, 0, 0); - REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 30, 30); - REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 31, 31); + REG_FLD_MOD(hdmi_av_base(ip_data), + HDMI_CORE_AV_AUD_MODE, 0, 0, 0); + REG_FLD_MOD(hdmi_wp_base(ip_data), + HDMI_WP_AUDIO_CTRL, 0, 30, 30); + REG_FLD_MOD(hdmi_wp_base(ip_data), + HDMI_WP_AUDIO_CTRL, 0, 31, 31); break; default: err = -EINVAL; @@ -1730,20 +1803,26 @@ static int omapdss_hdmihw_probe(struct platform_device *pdev) } /* Base address taken from platform */ - hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem)); - if (!hdmi.base_wp) { + hdmi.hdmi_data.base_wp = ioremap(hdmi_mem->start, + resource_size(hdmi_mem)); + if (!hdmi.hdmi_data.base_wp) { DSSERR("can't ioremap WP\n"); return -ENOMEM; } r = hdmi_get_clocks(pdev); if (r) { - iounmap(hdmi.base_wp); + iounmap(hdmi.hdmi_data.base_wp); return r; } pm_runtime_enable(&pdev->dev); + hdmi.hdmi_data.core_sys_offset = HDMI_CORE_SYS; + hdmi.hdmi_data.core_av_offset = HDMI_CORE_AV; + hdmi.hdmi_data.pll_offset = HDMI_PLLCTRL; + hdmi.hdmi_data.phy_offset = HDMI_PHY; + hdmi_panel_init(); #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ @@ -1773,7 +1852,7 @@ static int omapdss_hdmihw_remove(struct platform_device *pdev) hdmi_put_clocks(); - iounmap(hdmi.base_wp); + iounmap(hdmi.hdmi_data.base_wp); return 0; } diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index c885f9c..ee37bd9 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -24,174 +24,163 @@ #include <linux/string.h> #include <video/omapdss.h> -#define HDMI_WP 0x0 -#define HDMI_CORE_SYS 0x400 -#define HDMI_CORE_AV 0x900 -#define HDMI_PLLCTRL 0x200 -#define HDMI_PHY 0x300 - struct hdmi_reg { u16 idx; }; #define HDMI_REG(idx) ((const struct hdmi_reg) { idx }) /* HDMI Wrapper */ -#define HDMI_WP_REG(idx) HDMI_REG(HDMI_WP + idx) - -#define HDMI_WP_REVISION HDMI_WP_REG(0x0) -#define HDMI_WP_SYSCONFIG HDMI_WP_REG(0x10) -#define HDMI_WP_IRQSTATUS_RAW HDMI_WP_REG(0x24) -#define HDMI_WP_IRQSTATUS HDMI_WP_REG(0x28) -#define HDMI_WP_PWR_CTRL HDMI_WP_REG(0x40) -#define HDMI_WP_IRQENABLE_SET HDMI_WP_REG(0x2C) -#define HDMI_WP_VIDEO_CFG HDMI_WP_REG(0x50) -#define HDMI_WP_VIDEO_SIZE HDMI_WP_REG(0x60) -#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68) -#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C) -#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70) -#define HDMI_WP_AUDIO_CFG HDMI_WP_REG(0x80) -#define HDMI_WP_AUDIO_CFG2 HDMI_WP_REG(0x84) -#define HDMI_WP_AUDIO_CTRL HDMI_WP_REG(0x88) -#define HDMI_WP_AUDIO_DATA HDMI_WP_REG(0x8C) + +#define HDMI_WP_REVISION HDMI_REG(0x0) +#define HDMI_WP_SYSCONFIG HDMI_REG(0x10) +#define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24) +#define HDMI_WP_IRQSTATUS HDMI_REG(0x28) +#define HDMI_WP_PWR_CTRL HDMI_REG(0x40) +#define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C) +#define HDMI_WP_VIDEO_CFG HDMI_REG(0x50) +#define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60) +#define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68) +#define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C) +#define HDMI_WP_WP_CLK HDMI_REG(0x70) +#define HDMI_WP_AUDIO_CFG HDMI_REG(0x80) +#define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84) +#define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88) +#define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C) /* HDMI IP Core System */ -#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx) - -#define HDMI_CORE_SYS_VND_IDL HDMI_CORE_SYS_REG(0x0) -#define HDMI_CORE_SYS_DEV_IDL HDMI_CORE_SYS_REG(0x8) -#define HDMI_CORE_SYS_DEV_IDH HDMI_CORE_SYS_REG(0xC) -#define HDMI_CORE_SYS_DEV_REV HDMI_CORE_SYS_REG(0x10) -#define HDMI_CORE_SYS_SRST HDMI_CORE_SYS_REG(0x14) -#define HDMI_CORE_CTRL1 HDMI_CORE_SYS_REG(0x20) -#define HDMI_CORE_SYS_SYS_STAT HDMI_CORE_SYS_REG(0x24) -#define HDMI_CORE_SYS_VID_ACEN HDMI_CORE_SYS_REG(0x124) -#define HDMI_CORE_SYS_VID_MODE HDMI_CORE_SYS_REG(0x128) -#define HDMI_CORE_SYS_INTR_STATE HDMI_CORE_SYS_REG(0x1C0) -#define HDMI_CORE_SYS_INTR1 HDMI_CORE_SYS_REG(0x1C4) -#define HDMI_CORE_SYS_INTR2 HDMI_CORE_SYS_REG(0x1C8) -#define HDMI_CORE_SYS_INTR3 HDMI_CORE_SYS_REG(0x1CC) -#define HDMI_CORE_SYS_INTR4 HDMI_CORE_SYS_REG(0x1D0) -#define HDMI_CORE_SYS_UMASK1 HDMI_CORE_SYS_REG(0x1D4) -#define HDMI_CORE_SYS_TMDS_CTRL HDMI_CORE_SYS_REG(0x208) -#define HDMI_CORE_SYS_DE_DLY HDMI_CORE_SYS_REG(0xC8) -#define HDMI_CORE_SYS_DE_CTRL HDMI_CORE_SYS_REG(0xCC) -#define HDMI_CORE_SYS_DE_TOP HDMI_CORE_SYS_REG(0xD0) -#define HDMI_CORE_SYS_DE_CNTL HDMI_CORE_SYS_REG(0xD8) -#define HDMI_CORE_SYS_DE_CNTH HDMI_CORE_SYS_REG(0xDC) -#define HDMI_CORE_SYS_DE_LINL HDMI_CORE_SYS_REG(0xE0) -#define HDMI_CORE_SYS_DE_LINH_1 HDMI_CORE_SYS_REG(0xE4) + +#define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0) +#define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8) +#define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC) +#define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10) +#define HDMI_CORE_SYS_SRST HDMI_REG(0x14) +#define HDMI_CORE_CTRL1 HDMI_REG(0x20) +#define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24) +#define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124) +#define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128) +#define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0) +#define HDMI_CORE_SYS_INTR1 HDMI_REG(0x1C4) +#define HDMI_CORE_SYS_INTR2 HDMI_REG(0x1C8) +#define HDMI_CORE_SYS_INTR3 HDMI_REG(0x1CC) +#define HDMI_CORE_SYS_INTR4 HDMI_REG(0x1D0) +#define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4) +#define HDMI_CORE_SYS_TMDS_CTRL HDMI_REG(0x208) +#define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8) +#define HDMI_CORE_SYS_DE_CTRL HDMI_REG(0xCC) +#define HDMI_CORE_SYS_DE_TOP HDMI_REG(0xD0) +#define HDMI_CORE_SYS_DE_CNTL HDMI_REG(0xD8) +#define HDMI_CORE_SYS_DE_CNTH HDMI_REG(0xDC) +#define HDMI_CORE_SYS_DE_LINL HDMI_REG(0xE0) +#define HDMI_CORE_SYS_DE_LINH_1 HDMI_REG(0xE4) #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 #define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 /* HDMI DDC E-DID */ -#define HDMI_CORE_DDC_CMD HDMI_CORE_SYS_REG(0x3CC) -#define HDMI_CORE_DDC_STATUS HDMI_CORE_SYS_REG(0x3C8) -#define HDMI_CORE_DDC_ADDR HDMI_CORE_SYS_REG(0x3B4) -#define HDMI_CORE_DDC_OFFSET HDMI_CORE_SYS_REG(0x3BC) -#define HDMI_CORE_DDC_COUNT1 HDMI_CORE_SYS_REG(0x3C0) -#define HDMI_CORE_DDC_COUNT2 HDMI_CORE_SYS_REG(0x3C4) -#define HDMI_CORE_DDC_DATA HDMI_CORE_SYS_REG(0x3D0) -#define HDMI_CORE_DDC_SEGM HDMI_CORE_SYS_REG(0x3B8) +#define HDMI_CORE_DDC_CMD HDMI_REG(0x3CC) +#define HDMI_CORE_DDC_STATUS HDMI_REG(0x3C8) +#define HDMI_CORE_DDC_ADDR HDMI_REG(0x3B4) +#define HDMI_CORE_DDC_OFFSET HDMI_REG(0x3BC) +#define HDMI_CORE_DDC_COUNT1 HDMI_REG(0x3C0) +#define HDMI_CORE_DDC_COUNT2 HDMI_REG(0x3C4) +#define HDMI_CORE_DDC_DATA HDMI_REG(0x3D0) +#define HDMI_CORE_DDC_SEGM HDMI_REG(0x3B8) /* HDMI IP Core Audio Video */ -#define HDMI_CORE_AV_REG(idx) HDMI_REG(HDMI_CORE_AV + idx) - -#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) -#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) -#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) -#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) -#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) -#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) -#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) -#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) -#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x110) -#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15) -#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190) -#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27) -#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x210) -#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_CORE_AV_REG(10) -#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290) -#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27) -#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300) -#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_CORE_AV_REG(31) -#define HDMI_CORE_AV_GEN2_DBYTE HDMI_CORE_AV_REG(0x380) -#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_CORE_AV_REG(31) -#define HDMI_CORE_AV_ACR_CTRL HDMI_CORE_AV_REG(0x4) -#define HDMI_CORE_AV_FREQ_SVAL HDMI_CORE_AV_REG(0x8) -#define HDMI_CORE_AV_N_SVAL1 HDMI_CORE_AV_REG(0xC) -#define HDMI_CORE_AV_N_SVAL2 HDMI_CORE_AV_REG(0x10) -#define HDMI_CORE_AV_N_SVAL3 HDMI_CORE_AV_REG(0x14) -#define HDMI_CORE_AV_CTS_SVAL1 HDMI_CORE_AV_REG(0x18) -#define HDMI_CORE_AV_CTS_SVAL2 HDMI_CORE_AV_REG(0x1C) -#define HDMI_CORE_AV_CTS_SVAL3 HDMI_CORE_AV_REG(0x20) -#define HDMI_CORE_AV_CTS_HVAL1 HDMI_CORE_AV_REG(0x24) -#define HDMI_CORE_AV_CTS_HVAL2 HDMI_CORE_AV_REG(0x28) -#define HDMI_CORE_AV_CTS_HVAL3 HDMI_CORE_AV_REG(0x2C) -#define HDMI_CORE_AV_AUD_MODE HDMI_CORE_AV_REG(0x50) -#define HDMI_CORE_AV_SPDIF_CTRL HDMI_CORE_AV_REG(0x54) -#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_CORE_AV_REG(0x60) -#define HDMI_CORE_AV_SWAP_I2S HDMI_CORE_AV_REG(0x64) -#define HDMI_CORE_AV_SPDIF_ERTH HDMI_CORE_AV_REG(0x6C) -#define HDMI_CORE_AV_I2S_IN_MAP HDMI_CORE_AV_REG(0x70) -#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_CORE_AV_REG(0x74) -#define HDMI_CORE_AV_I2S_CHST0 HDMI_CORE_AV_REG(0x78) -#define HDMI_CORE_AV_I2S_CHST1 HDMI_CORE_AV_REG(0x7C) -#define HDMI_CORE_AV_I2S_CHST2 HDMI_CORE_AV_REG(0x80) -#define HDMI_CORE_AV_I2S_CHST4 HDMI_CORE_AV_REG(0x84) -#define HDMI_CORE_AV_I2S_CHST5 HDMI_CORE_AV_REG(0x88) -#define HDMI_CORE_AV_ASRC HDMI_CORE_AV_REG(0x8C) -#define HDMI_CORE_AV_I2S_IN_LEN HDMI_CORE_AV_REG(0x90) -#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) -#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_CORE_AV_REG(0xC0) -#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_CORE_AV_REG(0xCC) -#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_CORE_AV_REG(0xD0) -#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_CORE_AV_REG(0xD4) -#define HDMI_CORE_AV_TEST_TXCTRL HDMI_CORE_AV_REG(0xF0) -#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) -#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) -#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) -#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) -#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) -#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) -#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) -#define HDMI_CORE_AV_SPD_TYPE HDMI_CORE_AV_REG(0x180) -#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184) -#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188) -#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C) -#define HDMI_CORE_AV_AUDIO_TYPE HDMI_CORE_AV_REG(0x200) -#define HDMI_CORE_AV_AUDIO_VERS HDMI_CORE_AV_REG(0x204) -#define HDMI_CORE_AV_AUDIO_LEN HDMI_CORE_AV_REG(0x208) -#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_CORE_AV_REG(0x20C) -#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280) -#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284) -#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288) -#define HDMI_CORE_AV_MPEG_CHSUM HDMI_CORE_AV_REG(0x28C) -#define HDMI_CORE_AV_CP_BYTE1 HDMI_CORE_AV_REG(0x37C) -#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_CORE_AV_REG(0x3FC) + +#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC) +#define HDMI_CORE_AV_DPD HDMI_REG(0xF4) +#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8) +#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC) +#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100) +#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104) +#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108) +#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C) +#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_REG(n * 4 + 0x110) +#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_REG(15) +#define HDMI_CORE_AV_SPD_DBYTE HDMI_REG(0x190) +#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_REG(27) +#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_REG(n * 4 + 0x210) +#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_REG(10) +#define HDMI_CORE_AV_MPEG_DBYTE HDMI_REG(0x290) +#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_REG(27) +#define HDMI_CORE_AV_GEN_DBYTE HDMI_REG(0x300) +#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_REG(31) +#define HDMI_CORE_AV_GEN2_DBYTE HDMI_REG(0x380) +#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_REG(31) +#define HDMI_CORE_AV_ACR_CTRL HDMI_REG(0x4) +#define HDMI_CORE_AV_FREQ_SVAL HDMI_REG(0x8) +#define HDMI_CORE_AV_N_SVAL1 HDMI_REG(0xC) +#define HDMI_CORE_AV_N_SVAL2 HDMI_REG(0x10) +#define HDMI_CORE_AV_N_SVAL3 HDMI_REG(0x14) +#define HDMI_CORE_AV_CTS_SVAL1 HDMI_REG(0x18) +#define HDMI_CORE_AV_CTS_SVAL2 HDMI_REG(0x1C) +#define HDMI_CORE_AV_CTS_SVAL3 HDMI_REG(0x20) +#define HDMI_CORE_AV_CTS_HVAL1 HDMI_REG(0x24) +#define HDMI_CORE_AV_CTS_HVAL2 HDMI_REG(0x28) +#define HDMI_CORE_AV_CTS_HVAL3 HDMI_REG(0x2C) +#define HDMI_CORE_AV_AUD_MODE HDMI_REG(0x50) +#define HDMI_CORE_AV_SPDIF_CTRL HDMI_REG(0x54) +#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_REG(0x60) +#define HDMI_CORE_AV_SWAP_I2S HDMI_REG(0x64) +#define HDMI_CORE_AV_SPDIF_ERTH HDMI_REG(0x6C) +#define HDMI_CORE_AV_I2S_IN_MAP HDMI_REG(0x70) +#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_REG(0x74) +#define HDMI_CORE_AV_I2S_CHST0 HDMI_REG(0x78) +#define HDMI_CORE_AV_I2S_CHST1 HDMI_REG(0x7C) +#define HDMI_CORE_AV_I2S_CHST2 HDMI_REG(0x80) +#define HDMI_CORE_AV_I2S_CHST4 HDMI_REG(0x84) +#define HDMI_CORE_AV_I2S_CHST5 HDMI_REG(0x88) +#define HDMI_CORE_AV_ASRC HDMI_REG(0x8C) +#define HDMI_CORE_AV_I2S_IN_LEN HDMI_REG(0x90) +#define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC) +#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_REG(0xC0) +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_REG(0xCC) +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_REG(0xD0) +#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_REG(0xD4) +#define HDMI_CORE_AV_TEST_TXCTRL HDMI_REG(0xF0) +#define HDMI_CORE_AV_DPD HDMI_REG(0xF4) +#define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8) +#define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC) +#define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100) +#define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104) +#define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108) +#define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C) +#define HDMI_CORE_AV_SPD_TYPE HDMI_REG(0x180) +#define HDMI_CORE_AV_SPD_VERS HDMI_REG(0x184) +#define HDMI_CORE_AV_SPD_LEN HDMI_REG(0x188) +#define HDMI_CORE_AV_SPD_CHSUM HDMI_REG(0x18C) +#define HDMI_CORE_AV_AUDIO_TYPE HDMI_REG(0x200) +#define HDMI_CORE_AV_AUDIO_VERS HDMI_REG(0x204) +#define HDMI_CORE_AV_AUDIO_LEN HDMI_REG(0x208) +#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_REG(0x20C) +#define HDMI_CORE_AV_MPEG_TYPE HDMI_REG(0x280) +#define HDMI_CORE_AV_MPEG_VERS HDMI_REG(0x284) +#define HDMI_CORE_AV_MPEG_LEN HDMI_REG(0x288) +#define HDMI_CORE_AV_MPEG_CHSUM HDMI_REG(0x28C) +#define HDMI_CORE_AV_CP_BYTE1 HDMI_REG(0x37C) +#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_REG(0x3FC) #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4 /* PLL */ -#define HDMI_PLL_REG(idx) HDMI_REG(HDMI_PLLCTRL + idx) -#define PLLCTRL_PLL_CONTROL HDMI_PLL_REG(0x0) -#define PLLCTRL_PLL_STATUS HDMI_PLL_REG(0x4) -#define PLLCTRL_PLL_GO HDMI_PLL_REG(0x8) -#define PLLCTRL_CFG1 HDMI_PLL_REG(0xC) -#define PLLCTRL_CFG2 HDMI_PLL_REG(0x10) -#define PLLCTRL_CFG3 HDMI_PLL_REG(0x14) -#define PLLCTRL_CFG4 HDMI_PLL_REG(0x20) +#define PLLCTRL_PLL_CONTROL HDMI_REG(0x0) +#define PLLCTRL_PLL_STATUS HDMI_REG(0x4) +#define PLLCTRL_PLL_GO HDMI_REG(0x8) +#define PLLCTRL_CFG1 HDMI_REG(0xC) +#define PLLCTRL_CFG2 HDMI_REG(0x10) +#define PLLCTRL_CFG3 HDMI_REG(0x14) +#define PLLCTRL_CFG4 HDMI_REG(0x20) /* HDMI PHY */ -#define HDMI_PHY_REG(idx) HDMI_REG(HDMI_PHY + idx) -#define HDMI_TXPHY_TX_CTRL HDMI_PHY_REG(0x0) -#define HDMI_TXPHY_DIGITAL_CTRL HDMI_PHY_REG(0x4) -#define HDMI_TXPHY_POWER_CTRL HDMI_PHY_REG(0x8) -#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_PHY_REG(0xC) +#define HDMI_TXPHY_TX_CTRL HDMI_REG(0x0) +#define HDMI_TXPHY_DIGITAL_CTRL HDMI_REG(0x4) +#define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8) +#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC) /* HDMI EDID Length */ #define HDMI_EDID_MAX_LENGTH 256 @@ -203,10 +192,11 @@ struct hdmi_reg { u16 idx; }; #define OMAP_HDMI_TIMINGS_NB 34 -#define REG_FLD_MOD(idx, val, start, end) \ - hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end)) -#define REG_GET(idx, start, end) \ - FLD_GET(hdmi_read_reg(idx), start, end) +#define REG_FLD_MOD(base, idx, val, start, end) \ + hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ + val, start, end)) +#define REG_GET(base, idx, start, end) \ + FLD_GET(hdmi_read_reg(base, idx), start, end) /* HDMI timing structure */ struct hdmi_timings { @@ -568,6 +558,14 @@ struct hdmi_video_interface { int tm; /* Timing mode */ }; +struct hdmi_ip_data { + void __iomem *base_wp; /* HDMI wrapper */ + unsigned long core_sys_offset; + unsigned long core_av_offset; + unsigned long pll_offset; + unsigned long phy_offset; +}; + struct hdmi_cm { int code; int mode; -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration 2011-08-29 6:14 ` [PATCH v2 01/10] OMAP4: DSS: HDMI: HDMI clean up to pass base_address mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure mythripk 2011-09-01 8:27 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration Tomi Valkeinen 0 siblings, 2 replies; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> As the pll and the video configuration info are part of the ip_data those structures are moved to the ip_data strtucure.Also the functions are modified accordingly to take care of this movement. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/hdmi.c | 34 +++++++++++++++------------------- drivers/video/omap2/dss/hdmi.h | 18 ++++++++++-------- 2 files changed, 25 insertions(+), 27 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 544f93e..084a47e 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -59,7 +59,6 @@ static struct { u8 edid[HDMI_EDID_MAX_LENGTH]; u8 edid_set; bool custom_set; - struct hdmi_config cfg; struct clk *sys_clk; } hdmi; @@ -230,11 +229,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev) } static int hdmi_pll_init(struct hdmi_ip_data *ip_data, - enum hdmi_clk_refsel refsel, int dcofreq, - struct hdmi_pll_info *fmt, u16 sd) + enum hdmi_clk_refsel refsel) { u32 r; void __iomem *pll_base = hdmi_pll_base(ip_data); + struct hdmi_pll_info *fmt = &ip_data->pll_data; /* PLL start always use manual mode */ REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); @@ -251,9 +250,9 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data, r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ - if (dcofreq) { + if (fmt->dcofreq) { /* divider programming for frequency beyond 1000Mhz */ - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10); + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ } else { r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ @@ -379,8 +378,7 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data) return 0; } -static int hdmi_pll_program(struct hdmi_ip_data *ip_data, - struct hdmi_pll_info *fmt) +static int hdmi_pll_program(struct hdmi_ip_data *ip_data) { u16 r = 0; enum hdmi_clk_refsel refsel; @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, refsel = HDMI_REFSEL_SYSCLK; - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); + r = hdmi_pll_init(ip_data, refsel); if (r) return r; @@ -1015,8 +1013,7 @@ static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); } -static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, - struct hdmi_config *cfg) +static void hdmi_basic_configure(struct hdmi_ip_data *ip_data) { /* HDMI */ struct omap_video_timings video_timing; @@ -1026,6 +1023,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, struct hdmi_core_infoframe_avi avi_cfg; struct hdmi_core_video_config v_core_cfg; struct hdmi_core_packet_enable_repeat repeat_cfg; + struct hdmi_config *cfg = &ip_data->cfg; hdmi_wp_init(&video_timing, &video_format, &video_interface); @@ -1034,8 +1032,7 @@ static void hdmi_basic_configure(struct hdmi_ip_data *ip_data, &avi_cfg, &repeat_cfg); - hdmi_wp_video_init_format(&video_format, - &video_timing, cfg); + hdmi_wp_video_init_format(&video_format, &video_timing, cfg); hdmi_wp_video_config_timing(ip_data, &video_timing); @@ -1161,7 +1158,6 @@ static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, static int hdmi_power_on(struct omap_dss_device *dssdev) { int r, code = 0; - struct hdmi_pll_info pll_data; struct omap_video_timings *p; unsigned long phy; @@ -1183,16 +1179,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) } code = get_timings_index(); dssdev->panel.timings = cea_vesa_timings[code].timings; - update_hdmi_timings(&hdmi.cfg, p, code); + update_hdmi_timings(&hdmi.hdmi_data.cfg, p, code); phy = p->pixel_clock; - hdmi_compute_pll(dssdev, phy, &pll_data); + hdmi_compute_pll(dssdev, phy, &hdmi.hdmi_data.pll_data); hdmi_wp_video_start(&hdmi.hdmi_data, 0); /* config the PLL and PHY hdmi_set_pll_pwrfirst */ - r = hdmi_pll_program(&hdmi.hdmi_data, &pll_data); + r = hdmi_pll_program(&hdmi.hdmi_data); if (r) { DSSDBG("Failed to lock PLL\n"); goto err; @@ -1204,9 +1200,9 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) goto err; } - hdmi.cfg.cm.mode = hdmi.mode; - hdmi.cfg.cm.code = hdmi.code; - hdmi_basic_configure(&hdmi.hdmi_data, &hdmi.cfg); + hdmi.hdmi_data.cfg.cm.mode = hdmi.mode; + hdmi.hdmi_data.cfg.cm.code = hdmi.code; + hdmi_basic_configure(&hdmi.hdmi_data); /* Make selection of HDMI in DSS */ dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index ee37bd9..c0f4c2a 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -558,14 +558,6 @@ struct hdmi_video_interface { int tm; /* Timing mode */ }; -struct hdmi_ip_data { - void __iomem *base_wp; /* HDMI wrapper */ - unsigned long core_sys_offset; - unsigned long core_av_offset; - unsigned long pll_offset; - unsigned long phy_offset; -}; - struct hdmi_cm { int code; int mode; @@ -577,6 +569,16 @@ struct hdmi_config { struct hdmi_cm cm; }; +struct hdmi_ip_data { + void __iomem *base_wp; /* HDMI wrapper */ + unsigned long core_sys_offset; + unsigned long core_av_offset; + unsigned long pll_offset; + unsigned long phy_offset; + struct hdmi_config cfg; + struct hdmi_pll_info pll_data; +}; + struct hdmi_audio_format { enum hdmi_stereo_channels stereo_channels; u8 active_chnnls_msk; -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure 2011-08-29 6:14 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file mythripk 2011-09-01 8:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure Tomi Valkeinen 2011-09-01 8:27 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration Tomi Valkeinen 1 sibling, 2 replies; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> Define new HDMI timings structure to replace the OMAP DSS timing strucutre in hdmi.c to have the HDMI include defintion out of DSS. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/hdmi.c | 22 +++++++++++++++++++--- drivers/video/omap2/dss/hdmi.h | 15 ++++++++++++++- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 084a47e..ba1ad06 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -537,6 +537,20 @@ static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) return 0; } +static void copy_hdmi_to_dss_timings(struct hdmi_video_timings hdmi_timings, + struct omap_video_timings *timings) +{ + timings->x_res = hdmi_timings.x_res; + timings->y_res = hdmi_timings.y_res; + timings->pixel_clock = hdmi_timings.pixel_clock; + timings->hbp = hdmi_timings.hbp; + timings->hfp = hdmi_timings.hfp; + timings->hsw = hdmi_timings.hsw; + timings->vbp = hdmi_timings.vbp; + timings->vfp = hdmi_timings.vfp; + timings->vsw = hdmi_timings.vsw; +} + static int get_timings_index(void) { int code; @@ -561,7 +575,7 @@ static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) { int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; int timing_vsync = 0, timing_hsync = 0; - struct omap_video_timings temp; + struct hdmi_video_timings temp; struct hdmi_cm cm = {-1}; DSSDBG("hdmi_get_code\n"); @@ -719,7 +733,8 @@ static void hdmi_read_edid(struct omap_video_timings *dp) code = get_timings_index(); - *dp = cea_vesa_timings[code].timings; + copy_hdmi_to_dss_timings(cea_vesa_timings[code].timings, dp); + } static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, @@ -1178,7 +1193,8 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi_read_edid(p); } code = get_timings_index(); - dssdev->panel.timings = cea_vesa_timings[code].timings; + copy_hdmi_to_dss_timings(cea_vesa_timings[code].timings, + &dssdev->panel.timings); update_hdmi_timings(&hdmi.hdmi_data.cfg, p, code); phy = p->pixel_clock; diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index c0f4c2a..7046ff3 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -198,9 +198,22 @@ struct hdmi_reg { u16 idx; }; #define REG_GET(base, idx, start, end) \ FLD_GET(hdmi_read_reg(base, idx), start, end) +struct hdmi_video_timings { + u16 x_res; + u16 y_res; + /* Unit: KHz */ + u32 pixel_clock; + u16 hsw; + u16 hfp; + u16 hbp; + u16 vsw; + u16 vfp; + u16 vbp; +}; + /* HDMI timing structure */ struct hdmi_timings { - struct omap_video_timings timings; + struct hdmi_video_timings timings; int vsync_pol; int hsync_pol; }; -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file 2011-08-29 6:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 05/10] OMAP4 : DSS : HDMI : Move the EDID portion from HDMI mythripk 2011-09-01 9:00 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file Tomi Valkeinen 2011-09-01 8:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure Tomi Valkeinen 1 sibling, 2 replies; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> Some of the header file definitions of HDMI IP are needed by audio driver thus moving the common defintion to more generic Include/video. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/dss.h | 10 ----- drivers/video/omap2/dss/hdmi.c | 1 + drivers/video/omap2/dss/hdmi.h | 53 ------------------------ include/video/omaphdmi.h | 86 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+), 63 deletions(-) create mode 100644 include/video/omaphdmi.h diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index a095a62..7c9565f 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h @@ -150,16 +150,6 @@ struct dsi_clock_info { bool use_sys_clk; }; -/* HDMI PLL structure */ -struct hdmi_pll_info { - u16 regn; - u16 regm; - u32 regmf; - u16 regm2; - u16 regsd; - u16 dcofreq; -}; - struct seq_file; struct platform_device; diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index ba1ad06..39d1a7e 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -33,6 +33,7 @@ #include <linux/pm_runtime.h> #include <linux/clk.h> #include <video/omapdss.h> +#include <video/omaphdmi.h> #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) #include <sound/soc.h> diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index 7046ff3..0a3342b 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -198,39 +198,12 @@ struct hdmi_reg { u16 idx; }; #define REG_GET(base, idx, start, end) \ FLD_GET(hdmi_read_reg(base, idx), start, end) -struct hdmi_video_timings { - u16 x_res; - u16 y_res; - /* Unit: KHz */ - u32 pixel_clock; - u16 hsw; - u16 hfp; - u16 hbp; - u16 vsw; - u16 vfp; - u16 vbp; -}; - -/* HDMI timing structure */ -struct hdmi_timings { - struct hdmi_video_timings timings; - int vsync_pol; - int hsync_pol; -}; - enum hdmi_phy_pwr { HDMI_PHYPWRCMD_OFF = 0, HDMI_PHYPWRCMD_LDOON = 1, HDMI_PHYPWRCMD_TXON = 2 }; -enum hdmi_pll_pwr { - HDMI_PLLPWRCMD_ALLOFF = 0, - HDMI_PLLPWRCMD_PLLONLY = 1, - HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, - HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 -}; - enum hdmi_clk_refsel { HDMI_REFSEL_PCLK = 0, HDMI_REFSEL_REF1 = 1, @@ -266,11 +239,6 @@ enum hdmi_core_packet_mode { HDMI_PACKETMODE48BITPERPIXEL = 7 }; -enum hdmi_core_hdmi_dvi { - HDMI_DVI = 0, - HDMI_HDMI = 1 -}; - enum hdmi_core_tclkselclkmult { HDMI_FPLL05IDCK = 0, HDMI_FPLL10IDCK = 1, @@ -571,27 +539,6 @@ struct hdmi_video_interface { int tm; /* Timing mode */ }; -struct hdmi_cm { - int code; - int mode; -}; - -struct hdmi_config { - struct hdmi_timings timings; - u16 interlace; - struct hdmi_cm cm; -}; - -struct hdmi_ip_data { - void __iomem *base_wp; /* HDMI wrapper */ - unsigned long core_sys_offset; - unsigned long core_av_offset; - unsigned long pll_offset; - unsigned long phy_offset; - struct hdmi_config cfg; - struct hdmi_pll_info pll_data; -}; - struct hdmi_audio_format { enum hdmi_stereo_channels stereo_channels; u8 active_chnnls_msk; diff --git a/include/video/omaphdmi.h b/include/video/omaphdmi.h new file mode 100644 index 0000000..bd51529 --- /dev/null +++ b/include/video/omaphdmi.h @@ -0,0 +1,86 @@ +/* + * omaphdmi.h + * + * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. + * + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _OMAP_OMAPHDMI_H +#define _OMAP_OMAPHDMI_H + +enum hdmi_pll_pwr { + HDMI_PLLPWRCMD_ALLOFF = 0, + HDMI_PLLPWRCMD_PLLONLY = 1, + HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, + HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 +}; + +enum hdmi_core_hdmi_dvi { + HDMI_DVI = 0, + HDMI_HDMI = 1 +}; + +struct hdmi_video_timings { + u16 x_res; + u16 y_res; + /* Unit: KHz */ + u32 pixel_clock; + u16 hsw; + u16 hfp; + u16 hbp; + u16 vsw; + u16 vfp; + u16 vbp; +}; + +/* HDMI timing structure */ +struct hdmi_timings { + struct hdmi_video_timings timings; + int vsync_pol; + int hsync_pol; +}; + +struct hdmi_cm { + int code; + int mode; +}; + +struct hdmi_config { + struct hdmi_timings timings; + u16 interlace; + struct hdmi_cm cm; +}; + +/* HDMI PLL structure */ +struct hdmi_pll_info { + u16 regn; + u16 regm; + u32 regmf; + u16 regm2; + u16 regsd; + u16 dcofreq; +}; + +struct hdmi_ip_data { + void __iomem *base_wp; /* HDMI wrapper */ + unsigned long core_sys_offset; + unsigned long core_av_offset; + unsigned long pll_offset; + unsigned long phy_offset; + struct hdmi_config cfg; + struct hdmi_pll_info pll_data; +}; +#endif -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 05/10] OMAP4 : DSS : HDMI : Move the EDID portion from HDMI 2011-08-29 6:14 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 06/10] OMAP4: DSS2: HDMI: Split the HDMI driver to DSS and IP mythripk 2011-09-01 9:00 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file Tomi Valkeinen 1 sibling, 1 reply; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> Clean up to move the EDID definition to hdmi.c from the header file which is IP dependent. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/hdmi.c | 10 ++++++++++ drivers/video/omap2/dss/hdmi.h | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 39d1a7e..e9e07e2 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -50,6 +50,16 @@ #define HDMI_PLLCTRL 0x200 #define HDMI_PHY 0x300 +/* HDMI EDID Length move this */ +#define HDMI_EDID_MAX_LENGTH 256 +#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 +#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 +#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 +#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 +#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 + +#define OMAP_HDMI_TIMINGS_NB 34 + static struct { struct mutex lock; struct omap_display_platform_data *pdata; diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index 0a3342b..4b0fab3 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h @@ -182,16 +182,6 @@ struct hdmi_reg { u16 idx; }; #define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8) #define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC) -/* HDMI EDID Length */ -#define HDMI_EDID_MAX_LENGTH 256 -#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 -#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 -#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 -#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 -#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 - -#define OMAP_HDMI_TIMINGS_NB 34 - #define REG_FLD_MOD(base, idx, val, start, end) \ hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ val, start, end)) -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 06/10] OMAP4: DSS2: HDMI: Split the HDMI driver to DSS and IP 2011-08-29 6:14 ` [PATCH v2 05/10] OMAP4 : DSS : HDMI : Move the EDID portion from HDMI mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure mythripk 0 siblings, 1 reply; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> Splitting HDMI IP dependent IP configuring code from HDMI DSS dependent code and moving to a new IP file. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/Makefile | 2 +- drivers/video/omap2/dss/hdmi.c | 737 ------------------- drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c | 770 ++++++++++++++++++++ .../video/omap2/dss/{hdmi.h => hdmi_ti_4xxx_ip.h} | 9 +- include/video/omaphdmi.h | 7 + 5 files changed, 783 insertions(+), 742 deletions(-) create mode 100644 drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c rename drivers/video/omap2/dss/{hdmi.h => hdmi_ti_4xxx_ip.h} (99%) diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile index 10d9d3b..3ffe98f 100644 --- a/drivers/video/omap2/dss/Makefile +++ b/drivers/video/omap2/dss/Makefile @@ -6,4 +6,4 @@ omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \ - hdmi_omap4_panel.o + hdmi_omap4_panel.o hdmi_ti_4xxx_ip.o diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index e9e07e2..8baf4cf 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -41,7 +41,6 @@ #endif #include "dss.h" -#include "hdmi.h" #include "dss_features.h" #define HDMI_WP 0x0 @@ -161,56 +160,6 @@ static const int code_vesa[85] = { static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; -static inline void hdmi_write_reg(void __iomem *base_addr, - const struct hdmi_reg idx, u32 val) -{ - __raw_writel(val, base_addr + idx.idx); -} - -static inline u32 hdmi_read_reg(void __iomem *base_addr, - const struct hdmi_reg idx) -{ - return __raw_readl(base_addr + idx.idx); -} - -static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data) -{ - return ip_data->base_wp; -} - -static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data) -{ - return ip_data->base_wp + ip_data->phy_offset; -} - -static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data) -{ - return ip_data->base_wp + ip_data->pll_offset; -} - -static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data) -{ - return ip_data->base_wp + ip_data->core_av_offset; -} - -static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data) -{ - return ip_data->base_wp + ip_data->core_sys_offset; -} - -static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, - const struct hdmi_reg idx, - int b2, int b1, u32 val) -{ - u32 t = 0; - while (val != REG_GET(base_addr, idx, b2, b1)) { - udelay(1); - if (t++ > 10000) - return !val; - } - return val; -} - static int hdmi_runtime_get(void) { int r; @@ -239,315 +188,6 @@ int hdmi_init_display(struct omap_dss_device *dssdev) return 0; } -static int hdmi_pll_init(struct hdmi_ip_data *ip_data, - enum hdmi_clk_refsel refsel) -{ - u32 r; - void __iomem *pll_base = hdmi_pll_base(ip_data); - struct hdmi_pll_info *fmt = &ip_data->pll_data; - - /* PLL start always use manual mode */ - REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); - - r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); - r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ - r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ - - hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); - - r = hdmi_read_reg(pll_base, PLLCTRL_CFG2); - - r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ - r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ - r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ - - if (fmt->dcofreq) { - /* divider programming for frequency beyond 1000Mhz */ - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); - r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ - } else { - r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ - } - - hdmi_write_reg(pll_base, PLLCTRL_CFG2, r); - - r = hdmi_read_reg(pll_base, PLLCTRL_CFG4); - r = FLD_MOD(r, fmt->regm2, 24, 18); - r = FLD_MOD(r, fmt->regmf, 17, 0); - - hdmi_write_reg(pll_base, PLLCTRL_CFG4, r); - - /* go now */ - REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0); - - /* wait for bit change */ - if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO, - 0, 0, 1) != 1) { - DSSERR("PLL GO bit not set\n"); - return -ETIMEDOUT; - } - - /* Wait till the lock bit is set in PLL status */ - if (hdmi_wait_for_bit_change(pll_base, - PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { - DSSWARN("cannot lock PLL\n"); - DSSWARN("CFG1 0x%x\n", - hdmi_read_reg(pll_base, PLLCTRL_CFG1)); - DSSWARN("CFG2 0x%x\n", - hdmi_read_reg(pll_base, PLLCTRL_CFG2)); - DSSWARN("CFG4 0x%x\n", - hdmi_read_reg(pll_base, PLLCTRL_CFG4)); - return -ETIMEDOUT; - } - - DSSDBG("PLL locked!\n"); - - return 0; -} - -/* PHY_PWR_CMD */ -static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val) -{ - /* Command for power control of HDMI PHY */ - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6); - - /* Status of the power control of HDMI PHY */ - if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), - HDMI_WP_PWR_CTRL, 5, 4, val) != val) { - DSSERR("Failed to set PHY power mode to %d\n", val); - return -ETIMEDOUT; - } - - return 0; -} - -/* PLL_PWR_CMD */ -int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val) -{ - /* Command for power control of HDMI PLL */ - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); - - /* wait till PHY_PWR_STATUS is set */ - if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, - 1, 0, val) != val) { - DSSERR("Failed to set PHY_PWR_STATUS\n"); - return -ETIMEDOUT; - } - - return 0; -} - -static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) -{ - /* SYSRESET controlled by power FSM */ - REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3); - - /* READ 0x0 reset is in progress */ - if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data), - PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { - DSSERR("Failed to sysreset PLL\n"); - return -ETIMEDOUT; - } - - return 0; -} - -static int hdmi_phy_init(struct hdmi_ip_data *ip_data) -{ - u16 r = 0; - void __iomem *phy_base = hdmi_phy_base(ip_data); - - r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); - if (r) - return r; - - r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); - if (r) - return r; - - /* - * Read address 0 in order to get the SCP reset done completed - * Dummy access performed to make sure reset is done - */ - hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL); - - /* - * Write to phy address 0 to configure the clock - * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field - */ - REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); - - /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ - hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); - - /* Setup max LDO voltage */ - REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); - - /* Write to phy address 3 to change the polarity control */ - REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); - - return 0; -} - -static int hdmi_pll_program(struct hdmi_ip_data *ip_data) -{ - u16 r = 0; - enum hdmi_clk_refsel refsel; - - r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); - if (r) - return r; - - r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); - if (r) - return r; - - r = hdmi_pll_reset(ip_data); - if (r) - return r; - - refsel = HDMI_REFSEL_SYSCLK; - - r = hdmi_pll_init(ip_data, refsel); - if (r) - return r; - - return 0; -} - -static void hdmi_phy_off(struct hdmi_ip_data *ip_data) -{ - hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); -} - -static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, - u8 *pedid, int ext) -{ - u32 i, j; - char checksum = 0; - u32 offset = 0; - void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); - - /* Turn on CLK for DDC */ - REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0); - - /* - * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / - * right shifted values( The behavior is not consistent and seen only - * with some TV's) - */ - usleep_range(800, 1000); - - if (!ext) { - /* Clk SCL Devices */ - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); - - /* HDMI_CORE_DDC_STATUS_IN_PROG */ - if (hdmi_wait_for_bit_change(core_sys_base, - HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { - DSSERR("Failed to program DDC\n"); - return -ETIMEDOUT; - } - - /* Clear FIFO */ - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); - - /* HDMI_CORE_DDC_STATUS_IN_PROG */ - if (hdmi_wait_for_bit_change(core_sys_base, - HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { - DSSERR("Failed to program DDC\n"); - return -ETIMEDOUT; - } - - } else { - if (ext % 2 != 0) - offset = 0x80; - } - - /* Load Segment Address Register */ - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0); - - /* Load Slave Address Register */ - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); - - /* Load Offset Address Register */ - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); - - /* Load Byte Count */ - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); - - /* Set DDC_CMD */ - if (ext) - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); - else - REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); - - /* HDMI_CORE_DDC_STATUS_BUS_LOW */ - if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { - DSSWARN("I2C Bus Low?\n"); - return -EIO; - } - /* HDMI_CORE_DDC_STATUS_NO_ACK */ - if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { - DSSWARN("I2C No Ack\n"); - return -EIO; - } - - i = ext * 128; - j = 0; - while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) || - (REG_GET(core_sys_base, - HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) { - - if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) { - /* FIFO not empty */ - pedid[i++] = REG_GET(core_sys_base, - HDMI_CORE_DDC_DATA, 7, 0); - j++; - } - } - - for (j = 0; j < 128; j++) - checksum += pedid[j]; - - if (checksum != 0) { - DSSERR("E-EDID checksum failed!!\n"); - return -EIO; - } - - return 0; -} - -static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) -{ - int r = 0, n = 0, i = 0; - int max_ext_blocks = (max_length / 128) - 1; - - r = hdmi_core_ddc_edid(ip_data, pedid, 0); - if (r) { - return r; - } else { - n = pedid[0x7e]; - - /* - * README: need to comply with max_length set by the caller. - * Better implementation should be to allocate necessary - * memory to store EDID according to nb_block field found - * in first block - */ - if (n > max_ext_blocks) - n = max_ext_blocks; - - for (i = 1; i <= n; i++) { - r = hdmi_core_ddc_edid(ip_data, pedid, i); - if (r) - return r; - } - } - return 0; -} - static void copy_hdmi_to_dss_timings(struct hdmi_video_timings hdmi_timings, struct omap_video_timings *timings) { @@ -748,383 +388,6 @@ static void hdmi_read_edid(struct omap_video_timings *dp) } -static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, - struct hdmi_core_infoframe_avi *avi_cfg, - struct hdmi_core_packet_enable_repeat *repeat_cfg) -{ - DSSDBG("Enter hdmi_core_init\n"); - - /* video core */ - video_cfg->ip_bus_width = HDMI_INPUT_8BIT; - video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; - video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; - video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; - video_cfg->hdmi_dvi = HDMI_DVI; - video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; - - /* info frame */ - avi_cfg->db1_format = 0; - avi_cfg->db1_active_info = 0; - avi_cfg->db1_bar_info_dv = 0; - avi_cfg->db1_scan_info = 0; - avi_cfg->db2_colorimetry = 0; - avi_cfg->db2_aspect_ratio = 0; - avi_cfg->db2_active_fmt_ar = 0; - avi_cfg->db3_itc = 0; - avi_cfg->db3_ec = 0; - avi_cfg->db3_q_range = 0; - avi_cfg->db3_nup_scaling = 0; - avi_cfg->db4_videocode = 0; - avi_cfg->db5_pixel_repeat = 0; - avi_cfg->db6_7_line_eoftop = 0 ; - avi_cfg->db8_9_line_sofbottom = 0; - avi_cfg->db10_11_pixel_eofleft = 0; - avi_cfg->db12_13_pixel_sofright = 0; - - /* packet enable and repeat */ - repeat_cfg->audio_pkt = 0; - repeat_cfg->audio_pkt_repeat = 0; - repeat_cfg->avi_infoframe = 0; - repeat_cfg->avi_infoframe_repeat = 0; - repeat_cfg->gen_cntrl_pkt = 0; - repeat_cfg->gen_cntrl_pkt_repeat = 0; - repeat_cfg->generic_pkt = 0; - repeat_cfg->generic_pkt_repeat = 0; -} - -static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data) -{ - DSSDBG("Enter hdmi_core_powerdown_disable\n"); - REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0); -} - -static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data) -{ - DSSDBG("Enter hdmi_core_swreset_release\n"); - REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0); -} - -static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data) -{ - DSSDBG("Enter hdmi_core_swreset_assert\n"); - REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0); -} - -/* HDMI_CORE_VIDEO_CONFIG */ -static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, - struct hdmi_core_video_config *cfg) -{ - u32 r = 0; - void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); - - /* sys_ctrl1 default configuration not tunable */ - r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1); - r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); - r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); - r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); - r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); - hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r); - - REG_FLD_MOD(core_sys_base, - HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); - - /* Vid_Mode */ - r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); - - /* dither truncation configuration */ - if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { - r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); - r = FLD_MOD(r, 1, 5, 5); - } else { - r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); - r = FLD_MOD(r, 0, 5, 5); - } - hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); - - /* HDMI_Ctrl */ - r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); - r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); - r = FLD_MOD(r, cfg->pkt_mode, 5, 3); - r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); - hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); - - /* TMDS_CTRL */ - REG_FLD_MOD(core_sys_base, - HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); -} - -static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data, - struct hdmi_core_infoframe_avi info_avi) -{ - u32 val; - char sum = 0, checksum = 0; - void __iomem *av_base = hdmi_av_base(ip_data); - - sum += 0x82 + 0x002 + 0x00D; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); - - val = (info_avi.db1_format << 5) | - (info_avi.db1_active_info << 4) | - (info_avi.db1_bar_info_dv << 2) | - (info_avi.db1_scan_info); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); - sum += val; - - val = (info_avi.db2_colorimetry << 6) | - (info_avi.db2_aspect_ratio << 4) | - (info_avi.db2_active_fmt_ar); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); - sum += val; - - val = (info_avi.db3_itc << 7) | - (info_avi.db3_ec << 4) | - (info_avi.db3_q_range << 2) | - (info_avi.db3_nup_scaling); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); - sum += val; - - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), - info_avi.db4_videocode); - sum += info_avi.db4_videocode; - - val = info_avi.db5_pixel_repeat; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); - sum += val; - - val = info_avi.db6_7_line_eoftop & 0x00FF; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); - sum += val; - - val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); - sum += val; - - val = info_avi.db8_9_line_sofbottom & 0x00FF; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); - sum += val; - - val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); - sum += val; - - val = info_avi.db10_11_pixel_eofleft & 0x00FF; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); - sum += val; - - val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); - sum += val; - - val = info_avi.db12_13_pixel_sofright & 0x00FF; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); - sum += val; - - val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); - sum += val; - - checksum = 0x100 - sum; - hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); -} - -static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data, - struct hdmi_core_packet_enable_repeat repeat_cfg) -{ - /* enable/repeat the infoframe */ - hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1, - (repeat_cfg.audio_pkt << 5) | - (repeat_cfg.audio_pkt_repeat << 4) | - (repeat_cfg.avi_infoframe << 1) | - (repeat_cfg.avi_infoframe_repeat)); - - /* enable/repeat the packet */ - hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2, - (repeat_cfg.gen_cntrl_pkt << 3) | - (repeat_cfg.gen_cntrl_pkt_repeat << 2) | - (repeat_cfg.generic_pkt << 1) | - (repeat_cfg.generic_pkt_repeat)); -} - -static void hdmi_wp_init(struct omap_video_timings *timings, - struct hdmi_video_format *video_fmt, - struct hdmi_video_interface *video_int) -{ - DSSDBG("Enter hdmi_wp_init\n"); - - timings->hbp = 0; - timings->hfp = 0; - timings->hsw = 0; - timings->vbp = 0; - timings->vfp = 0; - timings->vsw = 0; - - video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; - video_fmt->y_res = 0; - video_fmt->x_res = 0; - - video_int->vsp = 0; - video_int->hsp = 0; - - video_int->interlacing = 0; - video_int->tm = 0; /* HDMI_TIMING_SLAVE */ - -} - -static void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start) -{ - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31); -} - -static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, - struct omap_video_timings *timings, struct hdmi_config *param) -{ - DSSDBG("Enter hdmi_wp_video_init_format\n"); - - video_fmt->y_res = param->timings.timings.y_res; - video_fmt->x_res = param->timings.timings.x_res; - - timings->hbp = param->timings.timings.hbp; - timings->hfp = param->timings.timings.hfp; - timings->hsw = param->timings.timings.hsw; - timings->vbp = param->timings.timings.vbp; - timings->vfp = param->timings.timings.vfp; - timings->vsw = param->timings.timings.vsw; -} - -static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, - struct hdmi_video_format *video_fmt) -{ - u32 l = 0; - - REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, - video_fmt->packing_mode, 10, 8); - - l |= FLD_VAL(video_fmt->y_res, 31, 16); - l |= FLD_VAL(video_fmt->x_res, 15, 0); - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l); -} - -static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data, - struct hdmi_video_interface *video_int) -{ - u32 r; - DSSDBG("Enter hdmi_wp_video_config_interface\n"); - - r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); - r = FLD_MOD(r, video_int->vsp, 7, 7); - r = FLD_MOD(r, video_int->hsp, 6, 6); - r = FLD_MOD(r, video_int->interlacing, 3, 3); - r = FLD_MOD(r, video_int->tm, 1, 0); - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); -} - -static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, - struct omap_video_timings *timings) -{ - u32 timing_h = 0; - u32 timing_v = 0; - - DSSDBG("Enter hdmi_wp_video_config_timing\n"); - - timing_h |= FLD_VAL(timings->hbp, 31, 20); - timing_h |= FLD_VAL(timings->hfp, 19, 8); - timing_h |= FLD_VAL(timings->hsw, 7, 0); - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h); - - timing_v |= FLD_VAL(timings->vbp, 31, 20); - timing_v |= FLD_VAL(timings->vfp, 19, 8); - timing_v |= FLD_VAL(timings->vsw, 7, 0); - hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); -} - -static void hdmi_basic_configure(struct hdmi_ip_data *ip_data) -{ - /* HDMI */ - struct omap_video_timings video_timing; - struct hdmi_video_format video_format; - struct hdmi_video_interface video_interface; - /* HDMI core */ - struct hdmi_core_infoframe_avi avi_cfg; - struct hdmi_core_video_config v_core_cfg; - struct hdmi_core_packet_enable_repeat repeat_cfg; - struct hdmi_config *cfg = &ip_data->cfg; - - hdmi_wp_init(&video_timing, &video_format, - &video_interface); - - hdmi_core_init(&v_core_cfg, - &avi_cfg, - &repeat_cfg); - - hdmi_wp_video_init_format(&video_format, &video_timing, cfg); - - hdmi_wp_video_config_timing(ip_data, &video_timing); - - /* video config */ - video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; - - hdmi_wp_video_config_format(ip_data, &video_format); - - video_interface.vsp = cfg->timings.vsync_pol; - video_interface.hsp = cfg->timings.hsync_pol; - video_interface.interlacing = cfg->interlace; - video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ - - hdmi_wp_video_config_interface(ip_data, &video_interface); - - /* - * configure core video part - * set software reset in the core - */ - hdmi_core_swreset_assert(ip_data); - - /* power down off */ - hdmi_core_powerdown_disable(ip_data); - - v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; - v_core_cfg.hdmi_dvi = cfg->cm.mode; - - hdmi_core_video_config(ip_data, &v_core_cfg); - - /* release software reset in the core */ - hdmi_core_swreset_release(ip_data); - - /* - * configure packet - * info frame video see doc CEA861-D page 65 - */ - avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; - avi_cfg.db1_active_info = - HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; - avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; - avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; - avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; - avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; - avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; - avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; - avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; - avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; - avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; - avi_cfg.db4_videocode = cfg->cm.code; - avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; - avi_cfg.db6_7_line_eoftop = 0; - avi_cfg.db8_9_line_sofbottom = 0; - avi_cfg.db10_11_pixel_eofleft = 0; - avi_cfg.db12_13_pixel_sofright = 0; - - hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg); - - /* enable/repeat the infoframe */ - repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; - repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; - /* wakeup */ - repeat_cfg.audio_pkt = HDMI_PACKETENABLE; - repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; - hdmi_core_av_packet_config(ip_data, repeat_cfg); -} - static void update_hdmi_timings(struct hdmi_config *cfg, struct omap_video_timings *timings, int code) { diff --git a/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c new file mode 100644 index 0000000..a582522 --- /dev/null +++ b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c @@ -0,0 +1,770 @@ +/* + * hdmi_ti_4xxx_ip.c + * + * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library + * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ + * Authors: Yong Zhi + * Mythri pk <mythripk@ti.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/string.h> + +#include "hdmi_ti_4xxx_ip.h" +#include "dss.h" + +static inline void hdmi_write_reg(void __iomem *base_addr, + const struct hdmi_reg idx, u32 val) +{ + __raw_writel(val, base_addr + idx.idx); +} + +static inline u32 hdmi_read_reg(void __iomem *base_addr, + const struct hdmi_reg idx) +{ + return __raw_readl(base_addr + idx.idx); +} + +static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp; +} + +static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp + ip_data->phy_offset; +} + +static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp + ip_data->pll_offset; +} + +static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp + ip_data->core_av_offset; +} + +static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data) +{ + return ip_data->base_wp + ip_data->core_sys_offset; +} + +static inline int hdmi_wait_for_bit_change(void __iomem *base_addr, + const struct hdmi_reg idx, + int b2, int b1, u32 val) +{ + u32 t = 0; + while (val != REG_GET(base_addr, idx, b2, b1)) { + udelay(1); + if (t++ > 10000) + return !val; + } + return val; +} + +static int hdmi_pll_init(struct hdmi_ip_data *ip_data, + enum hdmi_clk_refsel refsel) +{ + u32 r; + void __iomem *pll_base = hdmi_pll_base(ip_data); + struct hdmi_pll_info *fmt = &ip_data->pll_data; + + /* PLL start always use manual mode */ + REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); + + r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); + r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ + r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ + + hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); + + r = hdmi_read_reg(pll_base, PLLCTRL_CFG2); + + r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ + r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ + r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ + + if (fmt->dcofreq) { + /* divider programming for frequency beyond 1000Mhz */ + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); + r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ + } else { + r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ + } + + hdmi_write_reg(pll_base, PLLCTRL_CFG2, r); + + r = hdmi_read_reg(pll_base, PLLCTRL_CFG4); + r = FLD_MOD(r, fmt->regm2, 24, 18); + r = FLD_MOD(r, fmt->regmf, 17, 0); + + hdmi_write_reg(pll_base, PLLCTRL_CFG4, r); + + /* go now */ + REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0); + + /* wait for bit change */ + if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO, + 0, 0, 1) != 1) { + pr_err("PLL GO bit not set\n"); + return -ETIMEDOUT; + } + + /* Wait till the lock bit is set in PLL status */ + if (hdmi_wait_for_bit_change(pll_base, + PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { + pr_err("cannot lock PLL\n"); + pr_err("CFG1 0x%x\n", + hdmi_read_reg(pll_base, PLLCTRL_CFG1)); + pr_err("CFG2 0x%x\n", + hdmi_read_reg(pll_base, PLLCTRL_CFG2)); + pr_err("CFG4 0x%x\n", + hdmi_read_reg(pll_base, PLLCTRL_CFG4)); + return -ETIMEDOUT; + } + + pr_debug("PLL locked!\n"); + + return 0; +} + +/* PHY_PWR_CMD */ +static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val) +{ + /* Command for power control of HDMI PHY */ + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6); + + /* Status of the power control of HDMI PHY */ + if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), + HDMI_WP_PWR_CTRL, 5, 4, val) != val) { + pr_err("Failed to set PHY power mode to %d\n", val); + return -ETIMEDOUT; + } + + return 0; +} + +/* PLL_PWR_CMD */ +int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val) +{ + /* Command for power control of HDMI PLL */ + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); + + /* wait till PHY_PWR_STATUS is set */ +if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, + 1, 0, val) != val) { + pr_err("Failed to set PLL_PWR_STATUS\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) +{ + /* SYSRESET controlled by power FSM */ + REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3); + + /* READ 0x0 reset is in progress */ + if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data), + PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { + pr_err("Failed to sysreset PLL\n"); + return -ETIMEDOUT; + } + + return 0; +} + +int hdmi_pll_program(struct hdmi_ip_data *ip_data) +{ + u16 r = 0; + enum hdmi_clk_refsel refsel; + + r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); + if (r) + return r; + + r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); + if (r) + return r; + + r = hdmi_pll_reset(ip_data); + if (r) + return r; + + refsel = HDMI_REFSEL_SYSCLK; + + r = hdmi_pll_init(ip_data, refsel); + if (r) + return r; + + return 0; +} + +int hdmi_phy_init(struct hdmi_ip_data *ip_data) +{ + u16 r = 0; + void __iomem *phy_base = hdmi_phy_base(ip_data); + + r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON); + if (r) + return r; + + r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON); + if (r) + return r; + + /* + * Read address 0 in order to get the SCP reset done completed + * Dummy access performed to make sure reset is done + */ + hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL); + + /* + * Write to phy address 0 to configure the clock + * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field + */ + REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); + + /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ + hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); + + /* Setup max LDO voltage */ + REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); + + /* Write to phy address 3 to change the polarity control */ + REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); + + return 0; +} + +void hdmi_phy_off(struct hdmi_ip_data *ip_data) +{ + hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); +} + +static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, + u8 *pedid, int ext) +{ + u32 i, j; + char checksum = 0; + u32 offset = 0; + void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); + + /* Turn on CLK for DDC */ + REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0); + + /* + * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / + * right shifted values( The behavior is not consistent and seen only + * with some TV's) + */ + usleep_range(800, 1000); + + if (!ext) { + /* Clk SCL Devices */ + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); + + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(core_sys_base, + HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { + pr_err("Failed to program DDC\n"); + return -ETIMEDOUT; + } + + /* Clear FIFO */ + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); + + /* HDMI_CORE_DDC_STATUS_IN_PROG */ + if (hdmi_wait_for_bit_change(core_sys_base, + HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) { + pr_err("Failed to program DDC\n"); + return -ETIMEDOUT; + } + + } else { + if (ext % 2 != 0) + offset = 0x80; + } + + /* Load Segment Address Register */ + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0); + + /* Load Slave Address Register */ + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); + + /* Load Offset Address Register */ + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); + + /* Load Byte Count */ + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); + + /* Set DDC_CMD */ + if (ext) + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); + else + REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); + + /* HDMI_CORE_DDC_STATUS_BUS_LOW */ + if (REG_GET(core_sys_base, + HDMI_CORE_DDC_STATUS, 6, 6) == 1) { + pr_err("I2C Bus Low?\n"); + return -EIO; + } + /* HDMI_CORE_DDC_STATUS_NO_ACK */ + if (REG_GET(core_sys_base, + HDMI_CORE_DDC_STATUS, 5, 5) == 1) { + pr_err("I2C No Ack\n"); + return -EIO; + } + + i = ext * 128; + j = 0; + while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) || + (REG_GET(core_sys_base, + HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) { + + if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) { + /* FIFO not empty */ + pedid[i++] = REG_GET(core_sys_base, + HDMI_CORE_DDC_DATA, 7, 0); + j++; + } + } + + for (j = 0; j < 128; j++) + checksum += pedid[j]; + + if (checksum != 0) { + pr_err("E-EDID checksum failed!!\n"); + return -EIO; + } + + return 0; +} + +int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) +{ + int r = 0, n = 0, i = 0; + int max_ext_blocks = (max_length / 128) - 1; + + r = hdmi_core_ddc_edid(ip_data, pedid, 0); + if (r) { + return r; + } else { + n = pedid[0x7e]; + + /* + * README: need to comply with max_length set by the caller. + * Better implementation should be to allocate necessary + * memory to store EDID according to nb_block field found + * in first block + */ + if (n > max_ext_blocks) + n = max_ext_blocks; + + for (i = 1; i <= n; i++) { + r = hdmi_core_ddc_edid(ip_data, pedid, i); + if (r) + return r; + } + } + return 0; +} + +static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, + struct hdmi_core_infoframe_avi *avi_cfg, + struct hdmi_core_packet_enable_repeat *repeat_cfg) +{ + pr_debug("Enter hdmi_core_init\n"); + + /* video core */ + video_cfg->ip_bus_width = HDMI_INPUT_8BIT; + video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; + video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; + video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; + video_cfg->hdmi_dvi = HDMI_DVI; + video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; + + /* info frame */ + avi_cfg->db1_format = 0; + avi_cfg->db1_active_info = 0; + avi_cfg->db1_bar_info_dv = 0; + avi_cfg->db1_scan_info = 0; + avi_cfg->db2_colorimetry = 0; + avi_cfg->db2_aspect_ratio = 0; + avi_cfg->db2_active_fmt_ar = 0; + avi_cfg->db3_itc = 0; + avi_cfg->db3_ec = 0; + avi_cfg->db3_q_range = 0; + avi_cfg->db3_nup_scaling = 0; + avi_cfg->db4_videocode = 0; + avi_cfg->db5_pixel_repeat = 0; + avi_cfg->db6_7_line_eoftop = 0 ; + avi_cfg->db8_9_line_sofbottom = 0; + avi_cfg->db10_11_pixel_eofleft = 0; + avi_cfg->db12_13_pixel_sofright = 0; + + /* packet enable and repeat */ + repeat_cfg->audio_pkt = 0; + repeat_cfg->audio_pkt_repeat = 0; + repeat_cfg->avi_infoframe = 0; + repeat_cfg->avi_infoframe_repeat = 0; + repeat_cfg->gen_cntrl_pkt = 0; + repeat_cfg->gen_cntrl_pkt_repeat = 0; + repeat_cfg->generic_pkt = 0; + repeat_cfg->generic_pkt_repeat = 0; +} + +static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data) +{ + pr_debug("Enter hdmi_core_powerdown_disable\n"); + REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0); +} + +static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data) +{ + pr_debug("Enter hdmi_core_swreset_release\n"); + REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0); +} + +static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data) +{ + pr_debug("Enter hdmi_core_swreset_assert\n"); + REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0); +} + +/* HDMI_CORE_VIDEO_CONFIG */ +static void hdmi_core_video_config(struct hdmi_ip_data *ip_data, + struct hdmi_core_video_config *cfg) +{ + u32 r = 0; + void __iomem *core_sys_base = hdmi_core_sys_base(ip_data); + + /* sys_ctrl1 default configuration not tunable */ + r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1); + r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); + r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); + r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); + r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); + hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r); + + REG_FLD_MOD(core_sys_base, + HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); + + /* Vid_Mode */ + r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); + + /* dither truncation configuration */ + if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { + r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); + r = FLD_MOD(r, 1, 5, 5); + } else { + r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); + r = FLD_MOD(r, 0, 5, 5); + } + hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); + + /* HDMI_Ctrl */ + r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL); + r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); + r = FLD_MOD(r, cfg->pkt_mode, 5, 3); + r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); + hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r); + + /* TMDS_CTRL */ + REG_FLD_MOD(core_sys_base, + HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); +} + +static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data, + struct hdmi_core_infoframe_avi info_avi) +{ + u32 val; + char sum = 0, checksum = 0; + void __iomem *av_base = hdmi_av_base(ip_data); + + sum += 0x82 + 0x002 + 0x00D; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); + + val = (info_avi.db1_format << 5) | + (info_avi.db1_active_info << 4) | + (info_avi.db1_bar_info_dv << 2) | + (info_avi.db1_scan_info); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); + sum += val; + + val = (info_avi.db2_colorimetry << 6) | + (info_avi.db2_aspect_ratio << 4) | + (info_avi.db2_active_fmt_ar); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); + sum += val; + + val = (info_avi.db3_itc << 7) | + (info_avi.db3_ec << 4) | + (info_avi.db3_q_range << 2) | + (info_avi.db3_nup_scaling); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); + sum += val; + + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), + info_avi.db4_videocode); + sum += info_avi.db4_videocode; + + val = info_avi.db5_pixel_repeat; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); + sum += val; + + val = info_avi.db6_7_line_eoftop & 0x00FF; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); + sum += val; + + val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); + sum += val; + + val = info_avi.db8_9_line_sofbottom & 0x00FF; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); + sum += val; + + val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); + sum += val; + + val = info_avi.db10_11_pixel_eofleft & 0x00FF; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); + sum += val; + + val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); + sum += val; + + val = info_avi.db12_13_pixel_sofright & 0x00FF; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); + sum += val; + + val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); + sum += val; + + checksum = 0x100 - sum; + hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); +} + +static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data, + struct hdmi_core_packet_enable_repeat repeat_cfg) +{ + /* enable/repeat the infoframe */ + hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1, + (repeat_cfg.audio_pkt << 5) | + (repeat_cfg.audio_pkt_repeat << 4) | + (repeat_cfg.avi_infoframe << 1) | + (repeat_cfg.avi_infoframe_repeat)); + + /* enable/repeat the packet */ + hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2, + (repeat_cfg.gen_cntrl_pkt << 3) | + (repeat_cfg.gen_cntrl_pkt_repeat << 2) | + (repeat_cfg.generic_pkt << 1) | + (repeat_cfg.generic_pkt_repeat)); +} + +static void hdmi_wp_init(struct omap_video_timings *timings, + struct hdmi_video_format *video_fmt, + struct hdmi_video_interface *video_int) +{ + pr_debug("Enter hdmi_wp_init\n"); + + timings->hbp = 0; + timings->hfp = 0; + timings->hsw = 0; + timings->vbp = 0; + timings->vfp = 0; + timings->vsw = 0; + + video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; + video_fmt->y_res = 0; + video_fmt->x_res = 0; + + video_int->vsp = 0; + video_int->hsp = 0; + + video_int->interlacing = 0; + video_int->tm = 0; /* HDMI_TIMING_SLAVE */ + +} + +void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start) +{ + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31); +} + +static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, + struct omap_video_timings *timings, struct hdmi_config *param) +{ + pr_debug("Enter hdmi_wp_video_init_format\n"); + + video_fmt->y_res = param->timings.timings.y_res; + video_fmt->x_res = param->timings.timings.x_res; + + timings->hbp = param->timings.timings.hbp; + timings->hfp = param->timings.timings.hfp; + timings->hsw = param->timings.timings.hsw; + timings->vbp = param->timings.timings.vbp; + timings->vfp = param->timings.timings.vfp; + timings->vsw = param->timings.timings.vsw; +} + +static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data, + struct hdmi_video_format *video_fmt) +{ + u32 l = 0; + + REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, + video_fmt->packing_mode, 10, 8); + + l |= FLD_VAL(video_fmt->y_res, 31, 16); + l |= FLD_VAL(video_fmt->x_res, 15, 0); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l); +} + +static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data, + struct hdmi_video_interface *video_int) +{ + u32 r; + pr_debug("Enter hdmi_wp_video_config_interface\n"); + + r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG); + r = FLD_MOD(r, video_int->vsp, 7, 7); + r = FLD_MOD(r, video_int->hsp, 6, 6); + r = FLD_MOD(r, video_int->interlacing, 3, 3); + r = FLD_MOD(r, video_int->tm, 1, 0); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r); +} + +static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, + struct omap_video_timings *timings) +{ + u32 timing_h = 0; + u32 timing_v = 0; + + pr_debug("Enter hdmi_wp_video_config_timing\n"); + + timing_h |= FLD_VAL(timings->hbp, 31, 20); + timing_h |= FLD_VAL(timings->hfp, 19, 8); + timing_h |= FLD_VAL(timings->hsw, 7, 0); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h); + + timing_v |= FLD_VAL(timings->vbp, 31, 20); + timing_v |= FLD_VAL(timings->vfp, 19, 8); + timing_v |= FLD_VAL(timings->vsw, 7, 0); + hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); +} + +void hdmi_basic_configure(struct hdmi_ip_data *ip_data) +{ + /* HDMI */ + struct omap_video_timings video_timing; + struct hdmi_video_format video_format; + struct hdmi_video_interface video_interface; + /* HDMI core */ + struct hdmi_core_infoframe_avi avi_cfg; + struct hdmi_core_video_config v_core_cfg; + struct hdmi_core_packet_enable_repeat repeat_cfg; + struct hdmi_config *cfg = &ip_data->cfg; + + hdmi_wp_init(&video_timing, &video_format, + &video_interface); + + hdmi_core_init(&v_core_cfg, + &avi_cfg, + &repeat_cfg); + + hdmi_wp_video_init_format(&video_format, &video_timing, cfg); + + hdmi_wp_video_config_timing(ip_data, &video_timing); + + /* video config */ + video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; + + hdmi_wp_video_config_format(ip_data, &video_format); + + video_interface.vsp = cfg->timings.vsync_pol; + video_interface.hsp = cfg->timings.hsync_pol; + video_interface.interlacing = cfg->interlace; + video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ + + hdmi_wp_video_config_interface(ip_data, &video_interface); + + /* + * configure core video part + * set software reset in the core + */ + hdmi_core_swreset_assert(ip_data); + + /* power down off */ + hdmi_core_powerdown_disable(ip_data); + + v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; + v_core_cfg.hdmi_dvi = cfg->cm.mode; + + hdmi_core_video_config(ip_data, &v_core_cfg); + + /* release software reset in the core */ + hdmi_core_swreset_release(ip_data); + + /* + * configure packet + * info frame video see doc CEA861-D page 65 + */ + avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; + avi_cfg.db1_active_info = + HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; + avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; + avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; + avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; + avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; + avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; + avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; + avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; + avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; + avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; + avi_cfg.db4_videocode = cfg->cm.code; + avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; + avi_cfg.db6_7_line_eoftop = 0; + avi_cfg.db8_9_line_sofbottom = 0; + avi_cfg.db10_11_pixel_eofleft = 0; + avi_cfg.db12_13_pixel_sofright = 0; + + hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg); + + /* enable/repeat the infoframe */ + repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; + repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; + /* wakeup */ + repeat_cfg.audio_pkt = HDMI_PACKETENABLE; + repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; + hdmi_core_av_packet_config(ip_data, repeat_cfg); +} diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.h similarity index 99% rename from drivers/video/omap2/dss/hdmi.h rename to drivers/video/omap2/dss/hdmi_ti_4xxx_ip.h index 4b0fab3..8d87cda 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.h @@ -1,7 +1,7 @@ /* - * hdmi.h + * hdmi_ti_4xxx_ip.h * - * HDMI driver definition for TI OMAP4 processors. + * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors. * * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ * @@ -18,11 +18,12 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef _OMAP4_DSS_HDMI_H_ -#define _OMAP4_DSS_HDMI_H_ +#ifndef _HDMI_TI_4xxx_H_ +#define _HDMI_TI_4xxx_H_ #include <linux/string.h> #include <video/omapdss.h> +#include <video/omaphdmi.h> struct hdmi_reg { u16 idx; }; diff --git a/include/video/omaphdmi.h b/include/video/omaphdmi.h index bd51529..9d4bc36 100644 --- a/include/video/omaphdmi.h +++ b/include/video/omaphdmi.h @@ -83,4 +83,11 @@ struct hdmi_ip_data { struct hdmi_config cfg; struct hdmi_pll_info pll_data; }; +int hdmi_phy_init(struct hdmi_ip_data *ip_data); +void hdmi_phy_off(struct hdmi_ip_data *ip_data); +int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length); +void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start); +int hdmi_pll_program(struct hdmi_ip_data *ip_data); +int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val); +void hdmi_basic_configure(struct hdmi_ip_data *ip_data); #endif -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure 2011-08-29 6:14 ` [PATCH v2 06/10] OMAP4: DSS2: HDMI: Split the HDMI driver to DSS and IP mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call mythripk 2011-09-01 8:38 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure Tomi Valkeinen 0 siblings, 2 replies; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> Instead of DSS knowing of the interior IP driver function provide a wrapper API to configure. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/hdmi.c | 8 ++++---- drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c | 11 ++++++++--- include/video/omaphdmi.h | 8 ++++---- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index 8baf4cf..fb7d66f 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -478,13 +478,13 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi_wp_video_start(&hdmi.hdmi_data, 0); /* config the PLL and PHY hdmi_set_pll_pwrfirst */ - r = hdmi_pll_program(&hdmi.hdmi_data); + r = hdmi_pll_enable(&hdmi.hdmi_data); if (r) { DSSDBG("Failed to lock PLL\n"); goto err; } - r = hdmi_phy_init(&hdmi.hdmi_data); + r = hdmi_phy_enable(&hdmi.hdmi_data); if (r) { DSSDBG("Failed to start PHY\n"); goto err; @@ -527,8 +527,8 @@ static void hdmi_power_off(struct omap_dss_device *dssdev) dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); hdmi_wp_video_start(&hdmi.hdmi_data, 0); - hdmi_phy_off(&hdmi.hdmi_data); - hdmi_set_pll_pwr(&hdmi.hdmi_data, HDMI_PLLPWRCMD_ALLOFF); + hdmi_phy_disable(&hdmi.hdmi_data); + hdmi_pll_disable(&hdmi.hdmi_data); hdmi_runtime_put(); hdmi.edid_set = 0; diff --git a/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c index a582522..f64e06c 100644 --- a/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c +++ b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c @@ -194,7 +194,7 @@ static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) return 0; } -int hdmi_pll_program(struct hdmi_ip_data *ip_data) +int hdmi_pll_enable(struct hdmi_ip_data *ip_data) { u16 r = 0; enum hdmi_clk_refsel refsel; @@ -220,7 +220,12 @@ int hdmi_pll_program(struct hdmi_ip_data *ip_data) return 0; } -int hdmi_phy_init(struct hdmi_ip_data *ip_data) +void hdmi_pll_disable(struct hdmi_ip_data *ip_data) +{ + hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); +} + +int hdmi_phy_enable(struct hdmi_ip_data *ip_data) { u16 r = 0; void __iomem *phy_base = hdmi_phy_base(ip_data); @@ -257,7 +262,7 @@ int hdmi_phy_init(struct hdmi_ip_data *ip_data) return 0; } -void hdmi_phy_off(struct hdmi_ip_data *ip_data) +void hdmi_phy_disable(struct hdmi_ip_data *ip_data) { hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); } diff --git a/include/video/omaphdmi.h b/include/video/omaphdmi.h index 9d4bc36..88b1ccb 100644 --- a/include/video/omaphdmi.h +++ b/include/video/omaphdmi.h @@ -83,11 +83,11 @@ struct hdmi_ip_data { struct hdmi_config cfg; struct hdmi_pll_info pll_data; }; -int hdmi_phy_init(struct hdmi_ip_data *ip_data); -void hdmi_phy_off(struct hdmi_ip_data *ip_data); +int hdmi_phy_enable(struct hdmi_ip_data *ip_data); +void hdmi_phy_disable(struct hdmi_ip_data *ip_data); int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length); void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start); -int hdmi_pll_program(struct hdmi_ip_data *ip_data); -int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val); +int hdmi_pll_enable(struct hdmi_ip_data *ip_data); +void hdmi_pll_disable(struct hdmi_ip_data *ip_data); void hdmi_basic_configure(struct hdmi_ip_data *ip_data); #endif -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call 2011-08-29 6:14 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:14 ` [PATCH v2 09/10] MAP4: DSS: HDMI: Rename the functions in HDMI IP mythripk 2011-09-01 8:55 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call Tomi Valkeinen 2011-09-01 8:38 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure Tomi Valkeinen 1 sibling, 2 replies; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> To make the current hdmi DSS driver compatible with future OMAP with different IP blocks , add HDMI as a feature in dss_features and abstract the internal function in hdmi dss driver. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/dss_features.c | 24 +++++++++++++++++++++++- drivers/video/omap2/dss/dss_features.h | 1 + drivers/video/omap2/dss/hdmi.c | 22 +++++++++++----------- include/video/omapdss.h | 19 +++++++++++++++++++ include/video/omaphdmi.h | 1 + 5 files changed, 55 insertions(+), 12 deletions(-) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index b63c5f8..edf2929 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -429,6 +429,26 @@ static const struct omap_dss_features omap4_dss_features = { .burst_size_unit = 16, }; +const struct omap_hdmi_ip_driver *omap_hdmi_functions; + +/* HDMI OMAP4 Functions*/ +const struct omap_hdmi_ip_driver omap4_hdmi_functions = { + + .video_configure = hdmi_basic_configure, + .phy_enable = hdmi_phy_enable, + .phy_disable = hdmi_phy_disable, + .read_edid = read_edid, + .pll_enable = hdmi_pll_enable, + .pll_disable = hdmi_pll_disable, + .video_enable = hdmi_wp_video_start, +}; + +void dss_hdmi_features_init(struct hdmi_ip_data *ip_data) +{ + if (cpu_is_omap44xx()) + ip_data->hdmi_ops = &omap4_hdmi_functions; +} + /* Functions returning values related to a DSS feature */ int dss_feat_get_num_mgrs(void) { @@ -512,8 +532,10 @@ void dss_features_init(void) omap_current_dss_features = &omap3430_dss_features; else if (omap_rev() == OMAP4430_REV_ES1_0) omap_current_dss_features = &omap4430_es1_0_dss_features; - else if (cpu_is_omap44xx()) + else if (cpu_is_omap44xx()) { omap_current_dss_features = &omap4_dss_features; + omap_hdmi_functions = &omap4_hdmi_functions; + } else DSSWARN("Unsupported OMAP version"); } diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h index 4271e96..ca64b21 100644 --- a/drivers/video/omap2/dss/dss_features.h +++ b/drivers/video/omap2/dss/dss_features.h @@ -99,4 +99,5 @@ u32 dss_feat_get_burst_size_unit(void); /* in bytes */ bool dss_has_feature(enum dss_feat_id id); void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); void dss_features_init(void); +void dss_hdmi_features_init(struct hdmi_ip_data *ip_data); #endif diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index fb7d66f..c508cf6 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c @@ -184,7 +184,7 @@ static void hdmi_runtime_put(void) int hdmi_init_display(struct omap_dss_device *dssdev) { DSSDBG("init_display\n"); - + dss_hdmi_features_init(&hdmi.hdmi_data); return 0; } @@ -364,8 +364,8 @@ static void hdmi_read_edid(struct omap_video_timings *dp) memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); if (!hdmi.edid_set) - ret = read_edid(&hdmi.hdmi_data, hdmi.edid, - HDMI_EDID_MAX_LENGTH); + ret = hdmi.hdmi_data.hdmi_ops->read_edid(&hdmi.hdmi_data, + hdmi.edid, HDMI_EDID_MAX_LENGTH); if (!ret) { if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { /* search for timings of default resolution */ @@ -475,16 +475,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi_compute_pll(dssdev, phy, &hdmi.hdmi_data.pll_data); - hdmi_wp_video_start(&hdmi.hdmi_data, 0); + hdmi.hdmi_data.hdmi_ops->video_enable(&hdmi.hdmi_data, 0); /* config the PLL and PHY hdmi_set_pll_pwrfirst */ - r = hdmi_pll_enable(&hdmi.hdmi_data); + r = hdmi.hdmi_data.hdmi_ops->pll_enable(&hdmi.hdmi_data); if (r) { DSSDBG("Failed to lock PLL\n"); goto err; } - r = hdmi_phy_enable(&hdmi.hdmi_data); + r = hdmi.hdmi_data.hdmi_ops->phy_enable(&hdmi.hdmi_data); if (r) { DSSDBG("Failed to start PHY\n"); goto err; @@ -492,7 +492,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) hdmi.hdmi_data.cfg.cm.mode = hdmi.mode; hdmi.hdmi_data.cfg.cm.code = hdmi.code; - hdmi_basic_configure(&hdmi.hdmi_data); + hdmi.hdmi_data.hdmi_ops->video_configure(&hdmi.hdmi_data); /* Make selection of HDMI in DSS */ dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); @@ -514,7 +514,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); - hdmi_wp_video_start(&hdmi.hdmi_data, 1); + hdmi.hdmi_data.hdmi_ops->video_enable(&hdmi.hdmi_data, 1); return 0; err: @@ -526,9 +526,9 @@ static void hdmi_power_off(struct omap_dss_device *dssdev) { dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); - hdmi_wp_video_start(&hdmi.hdmi_data, 0); - hdmi_phy_disable(&hdmi.hdmi_data); - hdmi_pll_disable(&hdmi.hdmi_data); + hdmi.hdmi_data.hdmi_ops->video_enable(&hdmi.hdmi_data, 0); + hdmi.hdmi_data.hdmi_ops->phy_disable(&hdmi.hdmi_data); + hdmi.hdmi_data.hdmi_ops->pll_disable(&hdmi.hdmi_data); hdmi_runtime_put(); hdmi.edid_set = 0; diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 9398dd3..bf2aeba 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -21,6 +21,7 @@ #include <linux/list.h> #include <linux/kobject.h> #include <linux/device.h> +#include <video/omaphdmi.h> #define DISPC_IRQ_FRAMEDONE (1 << 0) #define DISPC_IRQ_VSYNC (1 << 1) @@ -555,6 +556,24 @@ struct omap_dss_driver { u32 (*get_wss)(struct omap_dss_device *dssdev); }; +struct omap_hdmi_ip_driver { + + void (*video_configure)(struct hdmi_ip_data *ip_data); + + int (*phy_enable)(struct hdmi_ip_data *ip_data); + + void (*phy_disable)(struct hdmi_ip_data *ip_data); + + int (*read_edid)(struct hdmi_ip_data *ip_data, + u8 *pedid, u16 max_length); + + int (*pll_enable)(struct hdmi_ip_data *ip_data); + + void (*pll_disable)(struct hdmi_ip_data *ip_data); + + void (*video_enable)(struct hdmi_ip_data *ip_data, bool start); +}; + int omap_dss_register_driver(struct omap_dss_driver *); void omap_dss_unregister_driver(struct omap_dss_driver *); diff --git a/include/video/omaphdmi.h b/include/video/omaphdmi.h index 88b1ccb..a740237 100644 --- a/include/video/omaphdmi.h +++ b/include/video/omaphdmi.h @@ -80,6 +80,7 @@ struct hdmi_ip_data { unsigned long core_av_offset; unsigned long pll_offset; unsigned long phy_offset; + const struct omap_hdmi_ip_driver *hdmi_ops; struct hdmi_config cfg; struct hdmi_pll_info pll_data; }; -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 09/10] MAP4: DSS: HDMI: Rename the functions in HDMI IP 2011-08-29 6:14 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call mythripk @ 2011-08-29 6:14 ` mythripk 2011-08-29 6:15 ` [PATCH v2 10/10] OMAP4: DSS: Rename hdmi_omap4_panel.c to hdmi_panel.c mythripk 2011-09-01 8:55 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call Tomi Valkeinen 1 sibling, 1 reply; 23+ messages in thread From: mythripk @ 2011-08-29 6:14 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> Functions that are included in the generic video include of HDMI TI OMAP4, TI8xx etc IP library is renamed to have IP specific names so that it will not conflict with similar function from other IP. Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/dss_features.c | 14 +++++++------- drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c | 15 ++++++++------- include/video/omaphdmi.h | 15 ++++++++------- 3 files changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c index edf2929..c1ef0d6 100644 --- a/drivers/video/omap2/dss/dss_features.c +++ b/drivers/video/omap2/dss/dss_features.c @@ -434,13 +434,13 @@ const struct omap_hdmi_ip_driver *omap_hdmi_functions; /* HDMI OMAP4 Functions*/ const struct omap_hdmi_ip_driver omap4_hdmi_functions = { - .video_configure = hdmi_basic_configure, - .phy_enable = hdmi_phy_enable, - .phy_disable = hdmi_phy_disable, - .read_edid = read_edid, - .pll_enable = hdmi_pll_enable, - .pll_disable = hdmi_pll_disable, - .video_enable = hdmi_wp_video_start, + .video_configure = hdmi_ti_4xxx_basic_configure, + .phy_enable = hdmi_ti_4xxx_phy_enable, + .phy_disable = hdmi_ti_4xxx_phy_disable, + .read_edid = hdmi_ti_4xxx_read_edid, + .pll_enable = hdmi_ti_4xxx_pll_enable, + .pll_disable = hdmi_ti_4xxx_pll_disable, + .video_enable = hdmi_ti_4xxx_wp_video_start, }; void dss_hdmi_features_init(struct hdmi_ip_data *ip_data) diff --git a/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c index f64e06c..3ce99b0 100644 --- a/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c +++ b/drivers/video/omap2/dss/hdmi_ti_4xxx_ip.c @@ -194,7 +194,7 @@ static int hdmi_pll_reset(struct hdmi_ip_data *ip_data) return 0; } -int hdmi_pll_enable(struct hdmi_ip_data *ip_data) +int hdmi_ti_4xxx_pll_enable(struct hdmi_ip_data *ip_data) { u16 r = 0; enum hdmi_clk_refsel refsel; @@ -220,12 +220,12 @@ int hdmi_pll_enable(struct hdmi_ip_data *ip_data) return 0; } -void hdmi_pll_disable(struct hdmi_ip_data *ip_data) +void hdmi_ti_4xxx_pll_disable(struct hdmi_ip_data *ip_data) { hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF); } -int hdmi_phy_enable(struct hdmi_ip_data *ip_data) +int hdmi_ti_4xxx_phy_enable(struct hdmi_ip_data *ip_data) { u16 r = 0; void __iomem *phy_base = hdmi_phy_base(ip_data); @@ -262,7 +262,7 @@ int hdmi_phy_enable(struct hdmi_ip_data *ip_data) return 0; } -void hdmi_phy_disable(struct hdmi_ip_data *ip_data) +void hdmi_ti_4xxx_phy_disable(struct hdmi_ip_data *ip_data) { hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF); } @@ -368,7 +368,8 @@ static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data, return 0; } -int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) +int hdmi_ti_4xxx_read_edid(struct hdmi_ip_data *ip_data, + u8 *pedid, u16 max_length) { int r = 0, n = 0, i = 0; int max_ext_blocks = (max_length / 128) - 1; @@ -621,7 +622,7 @@ static void hdmi_wp_init(struct omap_video_timings *timings, } -void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start) +void hdmi_ti_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start) { REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31); } @@ -688,7 +689,7 @@ static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data, hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v); } -void hdmi_basic_configure(struct hdmi_ip_data *ip_data) +void hdmi_ti_4xxx_basic_configure(struct hdmi_ip_data *ip_data) { /* HDMI */ struct omap_video_timings video_timing; diff --git a/include/video/omaphdmi.h b/include/video/omaphdmi.h index a740237..9548284 100644 --- a/include/video/omaphdmi.h +++ b/include/video/omaphdmi.h @@ -84,11 +84,12 @@ struct hdmi_ip_data { struct hdmi_config cfg; struct hdmi_pll_info pll_data; }; -int hdmi_phy_enable(struct hdmi_ip_data *ip_data); -void hdmi_phy_disable(struct hdmi_ip_data *ip_data); -int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length); -void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start); -int hdmi_pll_enable(struct hdmi_ip_data *ip_data); -void hdmi_pll_disable(struct hdmi_ip_data *ip_data); -void hdmi_basic_configure(struct hdmi_ip_data *ip_data); +int hdmi_ti_4xxx_phy_enable(struct hdmi_ip_data *ip_data); +void hdmi_ti_4xxx_phy_disable(struct hdmi_ip_data *ip_data); +int hdmi_ti_4xxx_read_edid(struct hdmi_ip_data *ip_data, + u8 *pedid, u16 max_length); +void hdmi_ti_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start); +int hdmi_ti_4xxx_pll_enable(struct hdmi_ip_data *ip_data); +void hdmi_ti_4xxx_pll_disable(struct hdmi_ip_data *ip_data); +void hdmi_ti_4xxx_basic_configure(struct hdmi_ip_data *ip_data); #endif -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 10/10] OMAP4: DSS: Rename hdmi_omap4_panel.c to hdmi_panel.c 2011-08-29 6:14 ` [PATCH v2 09/10] MAP4: DSS: HDMI: Rename the functions in HDMI IP mythripk @ 2011-08-29 6:15 ` mythripk 0 siblings, 0 replies; 23+ messages in thread From: mythripk @ 2011-08-29 6:15 UTC (permalink / raw) To: tomi.valkeinen, linux-omap; +Cc: Mythri P K From: Mythri P K <mythripk@ti.com> As the panel driver will remain generic across OMAP's renaming it to hdmi_panel.c Signed-off-by: Mythri P K <mythripk@ti.com> --- drivers/video/omap2/dss/Makefile | 2 +- .../omap2/dss/{hdmi_omap4_panel.c => hdmi_panel.c} | 0 2 files changed, 1 insertions(+), 1 deletions(-) rename drivers/video/omap2/dss/{hdmi_omap4_panel.c => hdmi_panel.c} (100%) diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile index 3ffe98f..5fd9ed4 100644 --- a/drivers/video/omap2/dss/Makefile +++ b/drivers/video/omap2/dss/Makefile @@ -6,4 +6,4 @@ omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \ - hdmi_omap4_panel.o hdmi_ti_4xxx_ip.o + hdmi_panel.o hdmi_ti_4xxx_ip.o diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_panel.c similarity index 100% rename from drivers/video/omap2/dss/hdmi_omap4_panel.c rename to drivers/video/omap2/dss/hdmi_panel.c -- 1.7.5.4 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call 2011-08-29 6:14 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call mythripk 2011-08-29 6:14 ` [PATCH v2 09/10] MAP4: DSS: HDMI: Rename the functions in HDMI IP mythripk @ 2011-09-01 8:55 ` Tomi Valkeinen 1 sibling, 0 replies; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-01 8:55 UTC (permalink / raw) To: mythripk; +Cc: linux-omap On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > From: Mythri P K <mythripk@ti.com> > > To make the current hdmi DSS driver compatible with future OMAP with different > IP blocks , add HDMI as a feature in dss_features and abstract the internal > function in hdmi dss driver. No space before comma. The description could use some improvement, HDMI is not "a feature in dss_features", and I don't understand what the rest of the sentence means. > Signed-off-by: Mythri P K <mythripk@ti.com> > --- > drivers/video/omap2/dss/dss_features.c | 24 +++++++++++++++++++++++- > drivers/video/omap2/dss/dss_features.h | 1 + > drivers/video/omap2/dss/hdmi.c | 22 +++++++++++----------- > include/video/omapdss.h | 19 +++++++++++++++++++ > include/video/omaphdmi.h | 1 + > 5 files changed, 55 insertions(+), 12 deletions(-) > > diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c > index b63c5f8..edf2929 100644 > --- a/drivers/video/omap2/dss/dss_features.c > +++ b/drivers/video/omap2/dss/dss_features.c > @@ -429,6 +429,26 @@ static const struct omap_dss_features omap4_dss_features = { > .burst_size_unit = 16, > }; > > +const struct omap_hdmi_ip_driver *omap_hdmi_functions; Should be static, but considering you never use this variable, except to assign it once, it should be removed. > + > +/* HDMI OMAP4 Functions*/ > +const struct omap_hdmi_ip_driver omap4_hdmi_functions = { Should be static. > + > + .video_configure = hdmi_basic_configure, > + .phy_enable = hdmi_phy_enable, > + .phy_disable = hdmi_phy_disable, > + .read_edid = read_edid, > + .pll_enable = hdmi_pll_enable, > + .pll_disable = hdmi_pll_disable, > + .video_enable = hdmi_wp_video_start, > +}; Check that this compiles if HDMI is disabled. > + > +void dss_hdmi_features_init(struct hdmi_ip_data *ip_data) Perhaps something like dss_init_hdmi_ip_data() would be better? > +{ > + if (cpu_is_omap44xx()) > + ip_data->hdmi_ops = &omap4_hdmi_functions; > +} > + > /* Functions returning values related to a DSS feature */ > int dss_feat_get_num_mgrs(void) > { > @@ -512,8 +532,10 @@ void dss_features_init(void) > omap_current_dss_features = &omap3430_dss_features; > else if (omap_rev() == OMAP4430_REV_ES1_0) > omap_current_dss_features = &omap4430_es1_0_dss_features; > - else if (cpu_is_omap44xx()) > + else if (cpu_is_omap44xx()) { > omap_current_dss_features = &omap4_dss_features; > + omap_hdmi_functions = &omap4_hdmi_functions; No need for this code. > + } > else > DSSWARN("Unsupported OMAP version"); > } > diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h > index 4271e96..ca64b21 100644 > --- a/drivers/video/omap2/dss/dss_features.h > +++ b/drivers/video/omap2/dss/dss_features.h > @@ -99,4 +99,5 @@ u32 dss_feat_get_burst_size_unit(void); /* in bytes */ > bool dss_has_feature(enum dss_feat_id id); > void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); > void dss_features_init(void); > +void dss_hdmi_features_init(struct hdmi_ip_data *ip_data); > #endif > diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c > index fb7d66f..c508cf6 100644 > --- a/drivers/video/omap2/dss/hdmi.c > +++ b/drivers/video/omap2/dss/hdmi.c > @@ -184,7 +184,7 @@ static void hdmi_runtime_put(void) > int hdmi_init_display(struct omap_dss_device *dssdev) > { > DSSDBG("init_display\n"); > - > + dss_hdmi_features_init(&hdmi.hdmi_data); > return 0; > } > > @@ -364,8 +364,8 @@ static void hdmi_read_edid(struct omap_video_timings *dp) > memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); > > if (!hdmi.edid_set) > - ret = read_edid(&hdmi.hdmi_data, hdmi.edid, > - HDMI_EDID_MAX_LENGTH); > + ret = hdmi.hdmi_data.hdmi_ops->read_edid(&hdmi.hdmi_data, > + hdmi.edid, HDMI_EDID_MAX_LENGTH); hdmi_ops could be just "ops", there's no possibility to confuse it with some other ops. > if (!ret) { > if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { > /* search for timings of default resolution */ > @@ -475,16 +475,16 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) > > hdmi_compute_pll(dssdev, phy, &hdmi.hdmi_data.pll_data); > > - hdmi_wp_video_start(&hdmi.hdmi_data, 0); > + hdmi.hdmi_data.hdmi_ops->video_enable(&hdmi.hdmi_data, 0); > > /* config the PLL and PHY hdmi_set_pll_pwrfirst */ > - r = hdmi_pll_enable(&hdmi.hdmi_data); > + r = hdmi.hdmi_data.hdmi_ops->pll_enable(&hdmi.hdmi_data); > if (r) { > DSSDBG("Failed to lock PLL\n"); > goto err; > } > > - r = hdmi_phy_enable(&hdmi.hdmi_data); > + r = hdmi.hdmi_data.hdmi_ops->phy_enable(&hdmi.hdmi_data); > if (r) { > DSSDBG("Failed to start PHY\n"); > goto err; > @@ -492,7 +492,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) > > hdmi.hdmi_data.cfg.cm.mode = hdmi.mode; > hdmi.hdmi_data.cfg.cm.code = hdmi.code; > - hdmi_basic_configure(&hdmi.hdmi_data); > + hdmi.hdmi_data.hdmi_ops->video_configure(&hdmi.hdmi_data); > > /* Make selection of HDMI in DSS */ > dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); > @@ -514,7 +514,7 @@ static int hdmi_power_on(struct omap_dss_device *dssdev) > > dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1); > > - hdmi_wp_video_start(&hdmi.hdmi_data, 1); > + hdmi.hdmi_data.hdmi_ops->video_enable(&hdmi.hdmi_data, 1); > > return 0; > err: > @@ -526,9 +526,9 @@ static void hdmi_power_off(struct omap_dss_device *dssdev) > { > dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0); > > - hdmi_wp_video_start(&hdmi.hdmi_data, 0); > - hdmi_phy_disable(&hdmi.hdmi_data); > - hdmi_pll_disable(&hdmi.hdmi_data); > + hdmi.hdmi_data.hdmi_ops->video_enable(&hdmi.hdmi_data, 0); > + hdmi.hdmi_data.hdmi_ops->phy_disable(&hdmi.hdmi_data); > + hdmi.hdmi_data.hdmi_ops->pll_disable(&hdmi.hdmi_data); > hdmi_runtime_put(); > > hdmi.edid_set = 0; > diff --git a/include/video/omapdss.h b/include/video/omapdss.h > index 9398dd3..bf2aeba 100644 > --- a/include/video/omapdss.h > +++ b/include/video/omapdss.h > @@ -21,6 +21,7 @@ > #include <linux/list.h> > #include <linux/kobject.h> > #include <linux/device.h> > +#include <video/omaphdmi.h> Why do you add this? > > #define DISPC_IRQ_FRAMEDONE (1 << 0) > #define DISPC_IRQ_VSYNC (1 << 1) > @@ -555,6 +556,24 @@ struct omap_dss_driver { > u32 (*get_wss)(struct omap_dss_device *dssdev); > }; > > +struct omap_hdmi_ip_driver { The naming is somewhat confusing. Why not just name it omap_hdmi_ip_ops? > + > + void (*video_configure)(struct hdmi_ip_data *ip_data); > + > + int (*phy_enable)(struct hdmi_ip_data *ip_data); > + > + void (*phy_disable)(struct hdmi_ip_data *ip_data); > + > + int (*read_edid)(struct hdmi_ip_data *ip_data, > + u8 *pedid, u16 max_length); > + > + int (*pll_enable)(struct hdmi_ip_data *ip_data); > + > + void (*pll_disable)(struct hdmi_ip_data *ip_data); > + > + void (*video_enable)(struct hdmi_ip_data *ip_data, bool start); > +}; > + > int omap_dss_register_driver(struct omap_dss_driver *); > void omap_dss_unregister_driver(struct omap_dss_driver *); > > diff --git a/include/video/omaphdmi.h b/include/video/omaphdmi.h > index 88b1ccb..a740237 100644 > --- a/include/video/omaphdmi.h > +++ b/include/video/omaphdmi.h > @@ -80,6 +80,7 @@ struct hdmi_ip_data { > unsigned long core_av_offset; > unsigned long pll_offset; > unsigned long phy_offset; > + const struct omap_hdmi_ip_driver *hdmi_ops; > struct hdmi_config cfg; > struct hdmi_pll_info pll_data; > }; ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure 2011-08-29 6:14 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure mythripk 2011-08-29 6:14 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call mythripk @ 2011-09-01 8:38 ` Tomi Valkeinen 1 sibling, 0 replies; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-01 8:38 UTC (permalink / raw) To: mythripk; +Cc: linux-omap On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > From: Mythri P K <mythripk@ti.com> > > Instead of DSS knowing of the interior IP driver function provide > a wrapper API to configure. This commit message doesn't make much sense. What you do in this patch is just rename the functions, and add the hdmi_pll_disable function. Tomi ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file 2011-08-29 6:14 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file mythripk 2011-08-29 6:14 ` [PATCH v2 05/10] OMAP4 : DSS : HDMI : Move the EDID portion from HDMI mythripk @ 2011-09-01 9:00 ` Tomi Valkeinen 2011-09-02 5:15 ` K, Mythri P 1 sibling, 1 reply; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-01 9:00 UTC (permalink / raw) To: mythripk; +Cc: linux-omap On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > From: Mythri P K <mythripk@ti.com> > > Some of the header file definitions of HDMI IP are needed by audio driver thus > moving the common defintion to more generic Include/video. > > Signed-off-by: Mythri P K <mythripk@ti.com> > --- > drivers/video/omap2/dss/dss.h | 10 ----- > drivers/video/omap2/dss/hdmi.c | 1 + > drivers/video/omap2/dss/hdmi.h | 53 ------------------------ > include/video/omaphdmi.h | 86 ++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 87 insertions(+), 63 deletions(-) > create mode 100644 include/video/omaphdmi.h As the functions will be renamed to hdmi_ti_4xxx_*, perhaps the header file is a bit misnamed. Also, please first do the changes/renamings/etc, and only then move the finished header file to include/video/ to prevent unnecessary changes in include/video. Tomi ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file 2011-09-01 9:00 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file Tomi Valkeinen @ 2011-09-02 5:15 ` K, Mythri P 2011-09-02 5:24 ` Tomi Valkeinen 0 siblings, 1 reply; 23+ messages in thread From: K, Mythri P @ 2011-09-02 5:15 UTC (permalink / raw) To: Tomi Valkeinen; +Cc: linux-omap Hi, On Thu, Sep 1, 2011 at 2:30 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: >> From: Mythri P K <mythripk@ti.com> >> >> Some of the header file definitions of HDMI IP are needed by audio driver thus >> moving the common defintion to more generic Include/video. >> >> Signed-off-by: Mythri P K <mythripk@ti.com> >> --- >> drivers/video/omap2/dss/dss.h | 10 ----- >> drivers/video/omap2/dss/hdmi.c | 1 + >> drivers/video/omap2/dss/hdmi.h | 53 ------------------------ >> include/video/omaphdmi.h | 86 ++++++++++++++++++++++++++++++++++++++++ >> 4 files changed, 87 insertions(+), 63 deletions(-) >> create mode 100644 include/video/omaphdmi.h > > As the functions will be renamed to hdmi_ti_4xxx_*, perhaps the header > file is a bit misnamed. > > Also, please first do the changes/renamings/etc, and only then move the > finished header file to include/video/ to prevent unnecessary changes in > include/video. > The Include/video hdmi header file is a generic file that can be used across 4 ,5 and Netra. Actually even the hdmi_ti_5xxx_ definitions would come in this header so what do you think it can be named as ? , If you have any better name for hdmi_ti_4xxx_ip as well please suggest would be happy to take it , as it doesn't sound that intuitive to me as well. > Tomi > > > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file 2011-09-02 5:15 ` K, Mythri P @ 2011-09-02 5:24 ` Tomi Valkeinen 2011-09-02 5:27 ` K, Mythri P 0 siblings, 1 reply; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-02 5:24 UTC (permalink / raw) To: K, Mythri P; +Cc: linux-omap On Fri, 2011-09-02 at 10:45 +0530, K, Mythri P wrote: > Hi, > > On Thu, Sep 1, 2011 at 2:30 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > >> From: Mythri P K <mythripk@ti.com> > >> > >> Some of the header file definitions of HDMI IP are needed by audio driver thus > >> moving the common defintion to more generic Include/video. > >> > >> Signed-off-by: Mythri P K <mythripk@ti.com> > >> --- > >> drivers/video/omap2/dss/dss.h | 10 ----- > >> drivers/video/omap2/dss/hdmi.c | 1 + > >> drivers/video/omap2/dss/hdmi.h | 53 ------------------------ > >> include/video/omaphdmi.h | 86 ++++++++++++++++++++++++++++++++++++++++ > >> 4 files changed, 87 insertions(+), 63 deletions(-) > >> create mode 100644 include/video/omaphdmi.h > > > > As the functions will be renamed to hdmi_ti_4xxx_*, perhaps the header > > file is a bit misnamed. > > > > Also, please first do the changes/renamings/etc, and only then move the > > finished header file to include/video/ to prevent unnecessary changes in > > include/video. > > > The Include/video hdmi header file is a generic file that can be used > across 4 ,5 and Netra. Actually even the hdmi_ti_5xxx_ definitions > would come in this header so what do you think it can be named as ? , > If you have any better name for hdmi_ti_4xxx_ip as well please suggest > would be happy to take it , as it doesn't sound that intuitive to me > as well. Well, I think whatever the header name is, it should somehow match the functions and the .c file. So if the functions and the .c file in this case are hdmi_ti_4xxx, then it'd be logical for the .h file to be named similarly. So, if it will contain functions for other IPs also, perhaps just leave the 4xxx out of it and name it hdmi_ti.h. Then the functions could be named hdmi_ti_4xxx_yyy(), and accordingly the .c file can be hdmi_ti_4xxx.c. Or, perhaps ti_hdmi.h (and funcs & .c files accordingly) would be more "standard", as it's quite usual to name drivers etc. starting with the company name. Tomi ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file 2011-09-02 5:24 ` Tomi Valkeinen @ 2011-09-02 5:27 ` K, Mythri P 0 siblings, 0 replies; 23+ messages in thread From: K, Mythri P @ 2011-09-02 5:27 UTC (permalink / raw) To: Tomi Valkeinen; +Cc: linux-omap Hi, On Fri, Sep 2, 2011 at 10:54 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > On Fri, 2011-09-02 at 10:45 +0530, K, Mythri P wrote: >> Hi, >> >> On Thu, Sep 1, 2011 at 2:30 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: >> > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: >> >> From: Mythri P K <mythripk@ti.com> >> >> >> >> Some of the header file definitions of HDMI IP are needed by audio driver thus >> >> moving the common defintion to more generic Include/video. >> >> >> >> Signed-off-by: Mythri P K <mythripk@ti.com> >> >> --- >> >> drivers/video/omap2/dss/dss.h | 10 ----- >> >> drivers/video/omap2/dss/hdmi.c | 1 + >> >> drivers/video/omap2/dss/hdmi.h | 53 ------------------------ >> >> include/video/omaphdmi.h | 86 ++++++++++++++++++++++++++++++++++++++++ >> >> 4 files changed, 87 insertions(+), 63 deletions(-) >> >> create mode 100644 include/video/omaphdmi.h >> > >> > As the functions will be renamed to hdmi_ti_4xxx_*, perhaps the header >> > file is a bit misnamed. >> > >> > Also, please first do the changes/renamings/etc, and only then move the >> > finished header file to include/video/ to prevent unnecessary changes in >> > include/video. >> > >> The Include/video hdmi header file is a generic file that can be used >> across 4 ,5 and Netra. Actually even the hdmi_ti_5xxx_ definitions >> would come in this header so what do you think it can be named as ? , >> If you have any better name for hdmi_ti_4xxx_ip as well please suggest >> would be happy to take it , as it doesn't sound that intuitive to me >> as well. > > Well, I think whatever the header name is, it should somehow match the > functions and the .c file. So if the functions and the .c file in this > case are hdmi_ti_4xxx, then it'd be logical for the .h file to be named > similarly. > > So, if it will contain functions for other IPs also, perhaps just leave > the 4xxx out of it and name it hdmi_ti.h. Then the functions could be > named hdmi_ti_4xxx_yyy(), and accordingly the .c file can be > hdmi_ti_4xxx.c. > > Or, perhaps ti_hdmi.h (and funcs & .c files accordingly) would be more > "standard", as it's quite usual to name drivers etc. starting with the > company name. > Thanks i shall change it to ti_hdmi.h and rename functions accordingly. Thanks and regards, Mythri. > Tomi > > > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure 2011-08-29 6:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure mythripk 2011-08-29 6:14 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file mythripk @ 2011-09-01 8:14 ` Tomi Valkeinen 2011-09-02 5:09 ` K, Mythri P 1 sibling, 1 reply; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-01 8:14 UTC (permalink / raw) To: mythripk; +Cc: linux-omap On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > From: Mythri P K <mythripk@ti.com> > > Define new HDMI timings structure to replace the OMAP DSS timing strucutre in > hdmi.c to have the HDMI include defintion out of DSS. structure and definition typoed. And the point is not to remove hdmi stuff from dss, but dss stuff from hdmi. The generic hdmi driver cannot use omap dss specific stuff. > Signed-off-by: Mythri P K <mythripk@ti.com> > --- > drivers/video/omap2/dss/hdmi.c | 22 +++++++++++++++++++--- > drivers/video/omap2/dss/hdmi.h | 15 ++++++++++++++- > 2 files changed, 33 insertions(+), 4 deletions(-) > > diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c > index 084a47e..ba1ad06 100644 > --- a/drivers/video/omap2/dss/hdmi.c > +++ b/drivers/video/omap2/dss/hdmi.c > @@ -537,6 +537,20 @@ static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) > return 0; > } > > +static void copy_hdmi_to_dss_timings(struct hdmi_video_timings hdmi_timings, > + struct omap_video_timings *timings) Pass hdmi_timings as a const pointer. Tomi ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure 2011-09-01 8:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure Tomi Valkeinen @ 2011-09-02 5:09 ` K, Mythri P 0 siblings, 0 replies; 23+ messages in thread From: K, Mythri P @ 2011-09-02 5:09 UTC (permalink / raw) To: Tomi Valkeinen; +Cc: linux-omap Hi, On Thu, Sep 1, 2011 at 1:44 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: >> From: Mythri P K <mythripk@ti.com> >> >> Define new HDMI timings structure to replace the OMAP DSS timing strucutre in >> hdmi.c to have the HDMI include defintion out of DSS. > > structure and definition typoed. And the point is not to remove hdmi > stuff from dss, but dss stuff from hdmi. The generic hdmi driver cannot > use omap dss specific stuff. > >> Signed-off-by: Mythri P K <mythripk@ti.com> >> --- >> drivers/video/omap2/dss/hdmi.c | 22 +++++++++++++++++++--- >> drivers/video/omap2/dss/hdmi.h | 15 ++++++++++++++- >> 2 files changed, 33 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c >> index 084a47e..ba1ad06 100644 >> --- a/drivers/video/omap2/dss/hdmi.c >> +++ b/drivers/video/omap2/dss/hdmi.c >> @@ -537,6 +537,20 @@ static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length) >> return 0; >> } >> >> +static void copy_hdmi_to_dss_timings(struct hdmi_video_timings hdmi_timings, >> + struct omap_video_timings *timings) > > Pass hdmi_timings as a const pointer. > Ok. > Tomi > > > Thanks and regards, Mythri -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration 2011-08-29 6:14 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration mythripk 2011-08-29 6:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure mythripk @ 2011-09-01 8:27 ` Tomi Valkeinen 2011-09-02 5:11 ` K, Mythri P 1 sibling, 1 reply; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-01 8:27 UTC (permalink / raw) To: mythripk; +Cc: linux-omap On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > From: Mythri P K <mythripk@ti.com> > > As the pll and the video configuration info are part of the ip_data those > structures are moved to the ip_data strtucure.Also the functions are modified > accordingly to take care of this movement. structure typoed, and use a space after period. > Signed-off-by: Mythri P K <mythripk@ti.com> > --- > drivers/video/omap2/dss/hdmi.c | 34 +++++++++++++++------------------- > drivers/video/omap2/dss/hdmi.h | 18 ++++++++++-------- > 2 files changed, 25 insertions(+), 27 deletions(-) > > diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c > index 544f93e..084a47e 100644 > --- a/drivers/video/omap2/dss/hdmi.c > +++ b/drivers/video/omap2/dss/hdmi.c > @@ -59,7 +59,6 @@ static struct { > u8 edid[HDMI_EDID_MAX_LENGTH]; > u8 edid_set; > bool custom_set; > - struct hdmi_config cfg; > > struct clk *sys_clk; > } hdmi; > @@ -230,11 +229,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev) > } > > static int hdmi_pll_init(struct hdmi_ip_data *ip_data, > - enum hdmi_clk_refsel refsel, int dcofreq, > - struct hdmi_pll_info *fmt, u16 sd) > + enum hdmi_clk_refsel refsel) > { > u32 r; > void __iomem *pll_base = hdmi_pll_base(ip_data); > + struct hdmi_pll_info *fmt = &ip_data->pll_data; > > /* PLL start always use manual mode */ > REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); > @@ -251,9 +250,9 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data, > r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ > r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ > > - if (dcofreq) { > + if (fmt->dcofreq) { > /* divider programming for frequency beyond 1000Mhz */ > - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10); > + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); > r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ > } else { > r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ > @@ -379,8 +378,7 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data) > return 0; > } > > -static int hdmi_pll_program(struct hdmi_ip_data *ip_data, > - struct hdmi_pll_info *fmt) > +static int hdmi_pll_program(struct hdmi_ip_data *ip_data) > { > u16 r = 0; > enum hdmi_clk_refsel refsel; > @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, > > refsel = HDMI_REFSEL_SYSCLK; > > - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); > + r = hdmi_pll_init(ip_data, refsel); I don't think I quite understood why refsel is not part of the pll info. And if it has to be hardcoded, you could as well do that in hdmi_pll_init(). Tomi ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration 2011-09-01 8:27 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration Tomi Valkeinen @ 2011-09-02 5:11 ` K, Mythri P 2011-09-02 5:13 ` Tomi Valkeinen 0 siblings, 1 reply; 23+ messages in thread From: K, Mythri P @ 2011-09-02 5:11 UTC (permalink / raw) To: Tomi Valkeinen; +Cc: linux-omap Hi, On Thu, Sep 1, 2011 at 1:57 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: >> From: Mythri P K <mythripk@ti.com> >> >> As the pll and the video configuration info are part of the ip_data those >> structures are moved to the ip_data strtucure.Also the functions are modified >> accordingly to take care of this movement. > > structure typoed, and use a space after period. > >> Signed-off-by: Mythri P K <mythripk@ti.com> >> --- >> drivers/video/omap2/dss/hdmi.c | 34 +++++++++++++++------------------- >> drivers/video/omap2/dss/hdmi.h | 18 ++++++++++-------- >> 2 files changed, 25 insertions(+), 27 deletions(-) >> >> diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c >> index 544f93e..084a47e 100644 >> --- a/drivers/video/omap2/dss/hdmi.c >> +++ b/drivers/video/omap2/dss/hdmi.c >> @@ -59,7 +59,6 @@ static struct { >> u8 edid[HDMI_EDID_MAX_LENGTH]; >> u8 edid_set; >> bool custom_set; >> - struct hdmi_config cfg; >> >> struct clk *sys_clk; >> } hdmi; >> @@ -230,11 +229,11 @@ int hdmi_init_display(struct omap_dss_device *dssdev) >> } >> >> static int hdmi_pll_init(struct hdmi_ip_data *ip_data, >> - enum hdmi_clk_refsel refsel, int dcofreq, >> - struct hdmi_pll_info *fmt, u16 sd) >> + enum hdmi_clk_refsel refsel) >> { >> u32 r; >> void __iomem *pll_base = hdmi_pll_base(ip_data); >> + struct hdmi_pll_info *fmt = &ip_data->pll_data; >> >> /* PLL start always use manual mode */ >> REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); >> @@ -251,9 +250,9 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data, >> r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ >> r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ >> >> - if (dcofreq) { >> + if (fmt->dcofreq) { >> /* divider programming for frequency beyond 1000Mhz */ >> - REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10); >> + REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); >> r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ >> } else { >> r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ >> @@ -379,8 +378,7 @@ static int hdmi_phy_init(struct hdmi_ip_data *ip_data) >> return 0; >> } >> >> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data, >> - struct hdmi_pll_info *fmt) >> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data) >> { >> u16 r = 0; >> enum hdmi_clk_refsel refsel; >> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, >> >> refsel = HDMI_REFSEL_SYSCLK; >> >> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); >> + r = hdmi_pll_init(ip_data, refsel); > > I don't think I quite understood why refsel is not part of the pll info. > And if it has to be hardcoded, you could as well do that in > hdmi_pll_init(). > Ok , yes that is better. > Tomi > > > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration 2011-09-02 5:11 ` K, Mythri P @ 2011-09-02 5:13 ` Tomi Valkeinen 2011-09-02 5:22 ` K, Mythri P 0 siblings, 1 reply; 23+ messages in thread From: Tomi Valkeinen @ 2011-09-02 5:13 UTC (permalink / raw) To: K, Mythri P; +Cc: linux-omap On Fri, 2011-09-02 at 10:41 +0530, K, Mythri P wrote: > Hi, > > On Thu, Sep 1, 2011 at 1:57 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: > >> From: Mythri P K <mythripk@ti.com> > >> > >> As the pll and the video configuration info are part of the ip_data those > >> structures are moved to the ip_data strtucure.Also the functions are modified > >> accordingly to take care of this movement. > > > > structure typoed, and use a space after period. > > > >> Signed-off-by: Mythri P K <mythripk@ti.com> > >> --- > >> drivers/video/omap2/dss/hdmi.c | 34 +++++++++++++++------------------- > >> drivers/video/omap2/dss/hdmi.h | 18 ++++++++++-------- > >> 2 files changed, 25 insertions(+), 27 deletions(-) > >> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data, > >> - struct hdmi_pll_info *fmt) > >> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data) > >> { > >> u16 r = 0; > >> enum hdmi_clk_refsel refsel; > >> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, > >> > >> refsel = HDMI_REFSEL_SYSCLK; > >> > >> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); > >> + r = hdmi_pll_init(ip_data, refsel); > > > > I don't think I quite understood why refsel is not part of the pll info. > > And if it has to be hardcoded, you could as well do that in > > hdmi_pll_init(). > > > Ok , yes that is better. So, why refsel is not part of the pll info? The HW doesn't support changing it? If so, is it only for OMAPs or for all SoCs? Tomi ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration 2011-09-02 5:13 ` Tomi Valkeinen @ 2011-09-02 5:22 ` K, Mythri P 0 siblings, 0 replies; 23+ messages in thread From: K, Mythri P @ 2011-09-02 5:22 UTC (permalink / raw) To: Tomi Valkeinen; +Cc: linux-omap Hi, On Fri, Sep 2, 2011 at 10:43 AM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: > On Fri, 2011-09-02 at 10:41 +0530, K, Mythri P wrote: >> Hi, >> >> On Thu, Sep 1, 2011 at 1:57 PM, Tomi Valkeinen <tomi.valkeinen@ti.com> wrote: >> > On Mon, 2011-08-29 at 11:44 +0530, mythripk@ti.com wrote: >> >> From: Mythri P K <mythripk@ti.com> >> >> >> >> As the pll and the video configuration info are part of the ip_data those >> >> structures are moved to the ip_data strtucure.Also the functions are modified >> >> accordingly to take care of this movement. >> > >> > structure typoed, and use a space after period. >> > >> >> Signed-off-by: Mythri P K <mythripk@ti.com> >> >> --- >> >> drivers/video/omap2/dss/hdmi.c | 34 +++++++++++++++------------------- >> >> drivers/video/omap2/dss/hdmi.h | 18 ++++++++++-------- >> >> 2 files changed, 25 insertions(+), 27 deletions(-) > >> >> -static int hdmi_pll_program(struct hdmi_ip_data *ip_data, >> >> - struct hdmi_pll_info *fmt) >> >> +static int hdmi_pll_program(struct hdmi_ip_data *ip_data) >> >> { >> >> u16 r = 0; >> >> enum hdmi_clk_refsel refsel; >> >> @@ -399,7 +397,7 @@ static int hdmi_pll_program(struct hdmi_ip_data *ip_data, >> >> >> >> refsel = HDMI_REFSEL_SYSCLK; >> >> >> >> - r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd); >> >> + r = hdmi_pll_init(ip_data, refsel); >> > >> > I don't think I quite understood why refsel is not part of the pll info. >> > And if it has to be hardcoded, you could as well do that in >> > hdmi_pll_init(). >> > >> Ok , yes that is better. > > So, why refsel is not part of the pll info? The HW doesn't support > changing it? If so, is it only for OMAPs or for all SoCs? It is a variable parameter ,H/w supports changing it but it is never tried, I was considering hard-coding it in the hdmi.c and passing it, so that there would be no hard-coding in IP functions. Thanks and regards, Mythri. > > Tomi > > > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2011-09-02 5:27 UTC | newest] Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2011-08-29 6:14 [PATCH v2 00/10]HDMI: Split hdmi.c in DSS to seperate OMAP dependent mythripk 2011-08-29 6:14 ` [PATCH v2 01/10] OMAP4: DSS: HDMI: HDMI clean up to pass base_address mythripk 2011-08-29 6:14 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration mythripk 2011-08-29 6:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure mythripk 2011-08-29 6:14 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file mythripk 2011-08-29 6:14 ` [PATCH v2 05/10] OMAP4 : DSS : HDMI : Move the EDID portion from HDMI mythripk 2011-08-29 6:14 ` [PATCH v2 06/10] OMAP4: DSS2: HDMI: Split the HDMI driver to DSS and IP mythripk 2011-08-29 6:14 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure mythripk 2011-08-29 6:14 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call mythripk 2011-08-29 6:14 ` [PATCH v2 09/10] MAP4: DSS: HDMI: Rename the functions in HDMI IP mythripk 2011-08-29 6:15 ` [PATCH v2 10/10] OMAP4: DSS: Rename hdmi_omap4_panel.c to hdmi_panel.c mythripk 2011-09-01 8:55 ` [PATCH v2 08/10] OMAP4: DSS2: HDMI: Function pointer approach to call Tomi Valkeinen 2011-09-01 8:38 ` [PATCH v2 07/10] OMAP4: DSS2: HDMI: Provide a wrapper API to configure Tomi Valkeinen 2011-09-01 9:00 ` [PATCH v2 04/10] OMAP4: DSS: HDMI: Move the common header file Tomi Valkeinen 2011-09-02 5:15 ` K, Mythri P 2011-09-02 5:24 ` Tomi Valkeinen 2011-09-02 5:27 ` K, Mythri P 2011-09-01 8:14 ` [PATCH v2 03/10] OMAP4: DSS: HDMI: Use specific HDMI timings structure Tomi Valkeinen 2011-09-02 5:09 ` K, Mythri P 2011-09-01 8:27 ` [PATCH v2 02/10] OMAP4: DSS: HDMI: Move pll and video configuration Tomi Valkeinen 2011-09-02 5:11 ` K, Mythri P 2011-09-02 5:13 ` Tomi Valkeinen 2011-09-02 5:22 ` K, Mythri P
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