[RFCv2] ValleyView support

[RFCv2] ValleyView support

[Jesse Barnes]

I incorporated all the comments so far but avoided the big ugly of the
display offset for now until we figure out what we want to do.

The code is also available in my drm-intel git tree on kernel.org under
the vlv-upstream branch.

Thanks,
Jesse

[PATCH 01/26] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

[Jesse Barnes]

It's only used by the main read/write functions, so we can keep it with
them.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    6 ++++++
 drivers/gpu/drm/i915/i915_drv.h |    6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0694e17..06533cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -979,6 +979,12 @@ MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL and additional rights");
 
+/* We give fast paths for the really cool registers */
+#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+       (((dev_priv)->info->gen >= 6) && \
+        ((reg) < 0x40000) &&            \
+        ((reg) != FORCEWAKE))
+
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 	u##x val = 0; \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0f19f5..83ace70 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1429,12 +1429,6 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
 
-/* We give fast paths for the really cool registers */
-#define NEEDS_FORCE_WAKE(dev_priv, reg) \
-	(((dev_priv)->info->gen >= 6) && \
-	 ((reg) < 0x40000) &&		 \
-	 ((reg) != FORCEWAKE))
-
 #define __i915_read(x, y) \
 	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
 
-- 
1.7.5.4

[PATCH 02/26] drm/i915: re-order GT IIR bit definitions

[Jesse Barnes]

They were all over the place, order them by position and add a few.

v2: add gen indications to the new bits (Ben)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..f3609f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3063,18 +3063,26 @@
 #define DE_PIPEB_VBLANK_IVB		(1<<5)
 #define DE_PIPEA_VBLANK_IVB		(1<<0)
 
+#define VLV_MASTER_IER			0x4400c /* Gunit master IER */
+#define   MASTER_INTERRUPT_ENABLE	(1<<31)
+
 #define DEISR   0x44000
 #define DEIMR   0x44004
 #define DEIIR   0x44008
 #define DEIER   0x4400c
 
 /* GT interrupt */
-#define GT_PIPE_NOTIFY		(1 << 4)
-#define GT_SYNC_STATUS          (1 << 2)
-#define GT_USER_INTERRUPT       (1 << 0)
-#define GT_BSD_USER_INTERRUPT   (1 << 5)
-#define GT_GEN6_BSD_USER_INTERRUPT	(1 << 12)
-#define GT_BLT_USER_INTERRUPT	(1 << 22)
+#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT	(1 << 26)
+#define GT_GEN6_BLT_CS_ERROR_INTERRUPT		(1 << 25)
+#define GT_BLT_USER_INTERRUPT			(1 << 22)
+#define GT_GEN6_BSD_CS_ERROR_INTERRUPT		(1 << 15)
+#define GT_GEN6_BSD_USER_INTERRUPT		(1 << 12)
+#define GT_BSD_USER_INTERRUPT			(1 << 5)
+#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT	(1 << 5)
+#define GT_PIPE_NOTIFY				(1 << 4)
+#define GT_RENDER_CS_ERROR_INTERRUPT		(1 << 3)
+#define GT_SYNC_STATUS				(1 << 2)
+#define GT_USER_INTERRUPT			(1 << 0)
 
 #define GTISR   0x44010
 #define GTIMR   0x44014
-- 
1.7.5.4

[PATCH 03/26] drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro

[Jesse Barnes]

For use by the rest of the ValleyView code.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |   18 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 2 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 06533cb..4a0e415 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -248,6 +248,24 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.has_llc = 1,
 };
 
+static const struct intel_device_info intel_valleyview_m_info = {
+	.gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_fbc = 0,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.is_valleyview = 1,
+};
+
+static const struct intel_device_info intel_valleyview_d_info = {
+	.gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_fbc = 0,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.is_valleyview = 1,
+};
+
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 83ace70..cacc8d3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -255,6 +255,7 @@ struct intel_device_info {
 	u8 is_broadwater:1;
 	u8 is_crestline:1;
 	u8 is_ivybridge:1;
+	u8 is_valleyview:1;
 	u8 has_fbc:1;
 	u8 has_pipe_cxsr:1;
 	u8 has_hotplug:1;
@@ -1001,6 +1002,7 @@ struct drm_i915_file_private {
 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
 #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
+#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 
 /*
-- 
1.7.5.4

[PATCH 04/26] drm/i915: ValleyView watermark support

[Jesse Barnes]

Add support for ValleyView watermark handling.  It's like Cantiga with a
few small differences (big FIFO mode and different WM limits).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |    9 +++++
 drivers/gpu/drm/i915/intel_display.c |   65 ++++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f3609f2..0540099 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1043,6 +1043,12 @@
 #define RAMCLK_GATE_D		0x6210		/* CRL only */
 #define DEUC			0x6214          /* CRL only */
 
+#define FW_BLC_SELF_VLV		0x6500
+#define  FW_CSPWRDWNEN		(1<<15)
+#define MI_ARB_VLV		0x6504
+#define  DISP_TRICKLE_FEED_DIS	(1<<2)
+#define CZCLK_CDCLK_FREQ_RATIO_VLV	0x6508
+
 /*
  * Palette regs
  */
@@ -2495,6 +2501,7 @@
 #define I915_FIFO_LINE_SIZE	64
 #define I830_FIFO_LINE_SIZE	32
 
+#define VALLEYVIEW_FIFO_SIZE	255
 #define G4X_FIFO_SIZE		127
 #define I965_FIFO_SIZE		512
 #define I945_FIFO_SIZE		127
@@ -2502,6 +2509,7 @@
 #define I855GM_FIFO_SIZE	127 /* In cachelines */
 #define I830_FIFO_SIZE		95
 
+#define VALLEYVIEW_MAX_WM	0xff
 #define G4X_MAX_WM		0x3f
 #define I915_MAX_WM		0x3f
 
@@ -2516,6 +2524,7 @@
 #define PINEVIEW_CURSOR_DFT_WM	0
 #define PINEVIEW_CURSOR_GUARD_WM	5
 
+#define VALLEYVIEW_CURSOR_MAX_WM 64
 #define I965_CURSOR_FIFO	64
 #define I965_CURSOR_MAX_WM	32
 #define I965_CURSOR_DFT_WM	8
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de1ba19..daa8853 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3606,6 +3606,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
 	2,
 	G4X_FIFO_LINE_SIZE,
 };
+static const struct intel_watermark_params valleyview_wm_info = {
+	VALLEYVIEW_FIFO_SIZE,
+	VALLEYVIEW_MAX_WM,
+	VALLEYVIEW_MAX_WM,
+	2,
+	G4X_FIFO_LINE_SIZE,
+};
+static const struct intel_watermark_params valleyview_cursor_wm_info = {
+	I965_CURSOR_FIFO,
+	VALLEYVIEW_CURSOR_MAX_WM,
+	I965_CURSOR_DFT_WM,
+	2,
+	G4X_FIFO_LINE_SIZE,
+};
 static const struct intel_watermark_params i965_cursor_wm_info = {
 	I965_CURSOR_FIFO,
 	I965_CURSOR_MAX_WM,
@@ -4130,6 +4144,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
 
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
+static void valleyview_update_wm(struct drm_device *dev)
+{
+	static const int sr_latency_ns = 12000;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
+	int plane_sr, cursor_sr;
+	unsigned int enabled = 0;
+
+	if (g4x_compute_wm0(dev, 0,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planea_wm, &cursora_wm))
+		enabled |= 1;
+
+	if (g4x_compute_wm0(dev, 1,
+			    &valleyview_wm_info, latency_ns,
+			    &valleyview_cursor_wm_info, latency_ns,
+			    &planeb_wm, &cursorb_wm))
+		enabled |= 2;
+
+	plane_sr = cursor_sr = 0;
+	if (single_plane_enabled(enabled) &&
+	    g4x_compute_srwm(dev, ffs(enabled) - 1,
+			     sr_latency_ns,
+			     &valleyview_wm_info,
+			     &valleyview_cursor_wm_info,
+			     &plane_sr, &cursor_sr))
+		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
+	else
+		I915_WRITE(FW_BLC_SELF_VLV,
+			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
+
+	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
+		      planea_wm, cursora_wm,
+		      planeb_wm, cursorb_wm,
+		      plane_sr, cursor_sr);
+
+	I915_WRITE(DSPFW1,
+		   (plane_sr << DSPFW_SR_SHIFT) |
+		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
+		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
+		   planea_wm);
+	I915_WRITE(DSPFW2,
+		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
+		   (cursora_wm << DSPFW_CURSORA_SHIFT));
+	I915_WRITE(DSPFW3,
+		   (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
+}
+
 static void g4x_update_wm(struct drm_device *dev)
 {
 	static const int sr_latency_ns = 12000;
@@ -8917,6 +8980,8 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.write_eld = ironlake_write_eld;
 		} else
 			dev_priv->display.update_wm = NULL;
+	} else if (IS_VALLEYVIEW(dev)) {
+		dev_priv->display.update_wm = valleyview_update_wm;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
-- 
1.7.5.4

[PATCH 05/26] drm/i915: PLL defines for VLV

[Jesse Barnes]

---
 drivers/gpu/drm/i915/i915_reg.h      |    9 +++++++++
 drivers/gpu/drm/i915/intel_display.c |   10 +++++++++-
 2 files changed, 18 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0540099..869c695 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -796,8 +796,11 @@
 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
 #define   DPLL_VCO_ENABLE		(1 << 31)
 #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
+#define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
 #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
+#define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
 #define   DPLL_VGA_MODE_DIS		(1 << 28)
+#define   DPLL_DUAL_PIPE_VLV		(1 << 26)
 #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
 #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
 #define   DPLL_MODE_MASK		(3 << 26)
@@ -808,6 +811,9 @@
 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
+#define   DPLL_VOLTAGE_LDO_VLV		(1<<14)
+#define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
+#define   DPLL_RATE_SWITCH_VLV		(1<<8)
 
 #define SRX_INDEX		0x3c4
 #define SRX_DATA		0x3c5
@@ -903,6 +909,9 @@
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
 #define _DPLL_B_MD 0x06020 /* 965+ only */
 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
+
+#define RAWCLK_FREQ_VLV			0x6024
+
 #define _FPA0	0x06040
 #define _FPA1	0x06044
 #define _FPB0	0x06048
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index daa8853..d72467f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3457,6 +3457,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
 	return true;
 }
 
+static int valleyview_get_display_clock_speed(struct drm_device *dev)
+{
+	return 400000; /* FIXME */
+}
+
 static int i945_get_display_clock_speed(struct drm_device *dev)
 {
 	return 400000;
@@ -8885,7 +8890,10 @@ static void intel_init_display(struct drm_device *dev)
 	}
 
 	/* Returns the core display clock speed */
-	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
+	if (IS_VALLEYVIEW(dev))
+		dev_priv->display.get_display_clock_speed =
+			valleyview_get_display_clock_speed;
+	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_I915G(dev))
-- 
1.7.5.4

[PATCH 06/26] drm/i915: interrupt bit definitions for VLV

[Jesse Barnes]

---
 drivers/gpu/drm/i915/i915_reg.h |   41 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 869c695..1af17e0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2435,23 +2435,30 @@
 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
 #define _PIPEASTAT		0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
+#define   SPRITE1_FLIPDONE_INT_EN_VLV		(1UL<<30)
 #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
 #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
 #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
+#define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL<<26)
 #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
 #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
 #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
 #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
+#define   SPRITE0_FLIP_DONE_INT_EN_VLV		(1UL<<26)
 #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
 #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
 #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
 #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
 #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
 #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
+#define   PIPEA_HBLANK_INT_EN_VLV		(1UL<<16)
 #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
+#define   SPRITE1_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
+#define   SPRITE0_FLIPDONE_INT_STATUS_VLV	(1UL<<15)
 #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
 #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
 #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
+#define   PLANE_FLIPDONE_INT_STATUS_VLV		(1UL<<10)
 #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
 #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
 #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
@@ -2476,6 +2483,40 @@
 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
+#define DPFLIPSTAT_VLV				0x70028
+#define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
+#define   PIPEB_HLINE_INT_EN			(1<<28)
+#define   PIPEB_VBLANK_INT_EN			(1<<27)
+#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
+#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
+#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
+#define   PIPEA_LINE_COMPARE_STATUS		(1<<21)
+#define   PIPEA_HLINE_INT_EN			(1<<20)
+#define   PIPEA_VBLANK_INT_EN			(1<<19)
+#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
+#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
+#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
+
+#define DPINVGTT				0x7002c /* VLV only */
+#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
+#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
+#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
+#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
+#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
+#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
+#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
+#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
+#define   DPINVGTT_EN_MASK			0xff0000
+#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
+#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
+#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
+#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
+#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
+#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
+#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
+#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
+#define   DPINVGTT_STATUS_MASK			0xff
+
 #define DSPARB			0x70030
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
-- 
1.7.5.4

[PATCH 07/26] drm/i915: add ValleyView clock gating init

[Jesse Barnes]

Set the same bits as IVB plus a few others.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |   18 +++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   46 ++++++++++++++++++++++++++++++++++
 2 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1af17e0..86de215 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -578,6 +578,9 @@
 #define   ECO_GATING_CX_ONLY	(1<<3)
 #define   ECO_FLIP_DONE		(1<<0)
 
+#define CACHE_MODE_1		0x7004 /* IVB+ */
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
+
 /* GEN6 interrupt control */
 #define GEN6_RENDER_HWSTAM	0x2098
 #define GEN6_RENDER_IMR		0x20a8
@@ -3178,6 +3181,20 @@
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
 #define  DISP_FBC_WM_DIS		(1<<15)
 
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
+# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
+
+#define GEN7_L3CNTLREG1				0xB01C
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+
+/* WaCatErrorRejectionIssue */
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
+#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
+
 /* PCH */
 
 /* south display engine interrupt */
@@ -3781,6 +3798,7 @@
 #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
 
 #define GEN6_UCGCTL2				0x9404
+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d72467f..22619c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8483,6 +8483,50 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 
+static void valleyview_init_clock_gating(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+	I915_WRITE(WM3_LP_ILK, 0);
+	I915_WRITE(WM2_LP_ILK, 0);
+	I915_WRITE(WM1_LP_ILK, 0);
+
+	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
+	 * This implements the WaDisableRCZUnitClockGating workaround.
+	 */
+	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+
+	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
+
+	I915_WRITE(IVB_CHICKEN3,
+		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
+		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
+
+	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
+	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+
+	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
+	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
+
+	/* This is required by WaCatErrorRejectionIssue */
+	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+
+	for_each_pipe(pipe) {
+		I915_WRITE(DSPCNTR(pipe),
+			   I915_READ(DSPCNTR(pipe)) |
+			   DISPPLANE_TRICKLE_FEED_DISABLE);
+		intel_flush_display_plane(dev_priv, pipe);
+	}
+}
+
 static void ironlake_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8990,6 +9034,8 @@ static void intel_init_display(struct drm_device *dev)
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.init_clock_gating =
+			valleyview_init_clock_gating;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
-- 
1.7.5.4

[PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView

[Jesse Barnes]

ValleyView and similar hardware (like CedarView) put some display
related registers like the PLL controls and dividers on a DPIO bus.  Add
simple indirect register access routines to get to those registers.

v2: move new wait_for macro to intel_drv.h (Ben)
    fix DPIO_PKT double write (Ben)
    add debugfs file

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_debugfs.c  |   48 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h      |    4 ++
 drivers/gpu/drm/i915/i915_reg.h      |   55 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |   61 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |   14 ++++++++
 5 files changed, 182 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index fdb7cce..5693de1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1502,6 +1502,53 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
 	return 0;
 }
 
+static int i915_dpio_info(struct seq_file *m, void *data)
+{
+	struct drm_info_node *node = (struct drm_info_node *) m->private;
+	struct drm_device *dev = node->minor->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int ret;
+
+
+	ret = mutex_lock_interruptible(&dev->mode_config.mutex);
+	if (ret)
+		return ret;
+
+	if (!IS_VALLEYVIEW(dev)) {
+		seq_printf(m, "unsupported\n");
+		return 0;
+	}
+
+	seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
+
+	seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_DIV_A));
+	seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_DIV_B));
+
+	seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
+	seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
+
+	seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
+	seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
+
+	seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
+	seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
+		   intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
+
+	seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
+		   intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
+
+	mutex_unlock(&dev->mode_config.mutex);
+
+	return 0;
+}
+
 static int
 i915_debugfs_common_open(struct inode *inode,
 			 struct file *filp)
@@ -1844,6 +1891,7 @@ static struct drm_info_list i915_debugfs_list[] = {
 	{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
 	{"i915_swizzle_info", i915_swizzle_info, 0},
 	{"i915_ppgtt_info", i915_ppgtt_info, 0},
+	{"i915_dpio", i915_dpio_info, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cacc8d3..2b8b32d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -355,6 +355,10 @@ typedef struct drm_i915_private {
 
 	/* protects the irq masks */
 	spinlock_t irq_lock;
+
+	/* DPIO indirect register protection */
+	spinlock_t dpio_lock;
+
 	/** Cached value of IMR to avoid reads in updating the bitfield */
 	u32 pipestat[2];
 	u32 irq_mask;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86de215..749e390 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -301,6 +301,61 @@
 #define  DEBUG_RESET_RENDER		(1<<8)
 #define  DEBUG_RESET_DISPLAY		(1<<9)
 
+/*
+ * DPIO - a special bus for various display related registers to hide behind:
+ *  0x800c: m1, m2, n, p1, p2, k dividers
+ *  0x8014: REF and SFR select
+ *  0x8014: N divider, VCO select
+ *  0x801c/3c: core clock bits
+ *  0x8048/68: low pass filter coefficients
+ *  0x8100: fast clock controls
+ */
+#define DPIO_PKT			0x2100
+#define  DPIO_RID			(0<<24)
+#define  DPIO_OP_WRITE			(1<<16)
+#define  DPIO_OP_READ			(0<<16)
+#define  DPIO_PORTID			(0x12<<8)
+#define  DPIO_BYTE			(0xf<<4)
+#define  DPIO_BUSY			(1<<0) /* status only */
+#define DPIO_DATA			0x2104
+#define DPIO_REG			0x2108
+#define DPIO_CTL			0x2110
+#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
+#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
+#define  DPIO_SFR_BYPASS		(1<<1)
+#define  DPIO_RESET			(1<<0)
+
+#define _DPIO_DIV_A			0x800c
+#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
+#define   DPIO_K_SHIFT			(24) /* 4 bits */
+#define   DPIO_P1_SHIFT			(21) /* 3 bits */
+#define   DPIO_P2_SHIFT			(16) /* 5 bits */
+#define   DPIO_N_SHIFT			(12) /* 4 bits */
+#define   DPIO_ENABLE_CALIBRATION	(1<<11)
+#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
+#define   DPIO_M2DIV_MASK		0xff
+#define _DPIO_DIV_B			0x802c
+#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
+
+#define _DPIO_REFSFR_A			0x8014
+#define   DPIO_REFSEL_OVERRIDE		27
+#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
+#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
+#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
+#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
+#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
+#define _DPIO_REFSFR_B			0x8034
+#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
+
+#define _DPIO_CORE_CLK_A		0x801c
+#define _DPIO_CORE_CLK_B		0x803c
+#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
+
+#define _DPIO_LFP_COEFF_A		0x8048
+#define _DPIO_LFP_COEFF_B		0x8068
+#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
+
+#define DPIO_FASTCLK_DISABLE		0x8100
 
 /*
  * Fence registers
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 22619c6..f27728c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -360,6 +360,64 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
 	.find_pll = intel_find_pll_ironlake_dp,
 };
 
+u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
+{
+	unsigned long flags;
+	u32 val = 0;
+
+	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+		DRM_ERROR("DPIO idle wait timed out\n");
+		goto out_unlock;
+	}
+
+	I915_WRITE(DPIO_REG, reg);
+	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
+		   DPIO_BYTE);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+		DRM_ERROR("DPIO read wait timed out\n");
+		goto out_unlock;
+	}
+	val = I915_READ(DPIO_DATA);
+
+out_unlock:
+	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+	return val;
+}
+
+static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
+			     u32 val)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
+		DRM_ERROR("DPIO idle wait timed out\n");
+		goto out_unlock;
+	}
+
+	I915_WRITE(DPIO_DATA, val);
+	I915_WRITE(DPIO_REG, reg);
+	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
+		   DPIO_BYTE);
+	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
+		DRM_ERROR("DPIO write wait timed out\n");
+
+out_unlock:
+	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
+}
+
+static void vlv_init_dpio(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Reset the DPIO config */
+	I915_WRITE(DPIO_CTL, 0);
+	POSTING_READ(DPIO_CTL);
+	I915_WRITE(DPIO_CTL, 1);
+	POSTING_READ(DPIO_CTL);
+}
+
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 						int refclk)
 {
@@ -9306,6 +9364,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_rc6(dev);
 
+	if (IS_VALLEYVIEW(dev))
+		vlv_init_dpio(dev);
+
 	mutex_unlock(&dev->struct_mutex);
 
 	/* Disable the irq before mode object teardown, for the irq might
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9cec6c3..07bcad0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -45,6 +45,18 @@
 	ret__;								\
 })
 
+#define wait_for_atomic_us(COND, US) ({ \
+	int i, ret__ = -ETIMEDOUT;	\
+	for (i = 0; i < (US); i++) {	\
+		if ((COND)) {		\
+			ret__ = 0;	\
+			break;		\
+		}			\
+		udelay(1);		\
+	}				\
+	ret__;				\
+})
+
 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
 
@@ -419,4 +431,6 @@ extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 				     struct drm_file *file_priv);
 
+extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
+
 #endif /* __INTEL_DRV_H__ */
-- 
1.7.5.4

[PATCH 09/26] drm/i915: split PLL update code out of i9xx_crtc_mode_set

[Jesse Barnes]

Makes it more readable and maintainable.  ValleyView will add its own
PLL update function in a later patch.

v2: split LVDS bits out of this patch (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |  291 ++++++++++++++++++++--------------
 1 files changed, 172 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f27728c..84480da 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5230,6 +5230,170 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	}
 }
 
+static void i9xx_update_pll(struct drm_crtc *crtc,
+			    struct drm_display_mode *mode,
+			    struct drm_display_mode *adjusted_mode,
+			    intel_clock_t *clock, intel_clock_t *reduced_clock,
+			    int num_connectors)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 dpll;
+	bool is_sdvo;
+
+	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
+		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+	dpll = DPLL_VGA_MODE_DIS;
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+		dpll |= DPLLB_MODE_LVDS;
+	else
+		dpll |= DPLLB_MODE_DAC_SERIAL;
+	if (is_sdvo) {
+		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+		if (pixel_multiplier > 1) {
+			if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+				dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+		}
+		dpll |= DPLL_DVO_HIGH_SPEED;
+	}
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		dpll |= DPLL_DVO_HIGH_SPEED;
+
+	/* compute bitmask from p1 value */
+	if (IS_PINEVIEW(dev))
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
+	else {
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+		if (IS_G4X(dev) && reduced_clock)
+			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+	}
+	switch (clock->p2) {
+	case 5:
+		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
+		break;
+	case 7:
+		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
+		break;
+	case 10:
+		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
+		break;
+	case 14:
+		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
+		break;
+	}
+	if (INTEL_INFO(dev)->gen >= 4)
+		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
+
+	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
+		dpll |= PLL_REF_INPUT_TVCLKINBC;
+	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
+		/* XXX: just matching BIOS for now */
+		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
+		dpll |= 3;
+	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+	else
+		dpll |= PLL_REF_INPUT_DREFCLK;
+
+	dpll |= DPLL_VCO_ENABLE;
+	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
+		intel_dp_set_m_n(crtc, mode, adjusted_mode);
+
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	if (INTEL_INFO(dev)->gen >= 4) {
+		u32 temp = 0;
+		if (is_sdvo) {
+			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+			if (temp > 1)
+				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+			else
+				temp = 0;
+		}
+		I915_WRITE(DPLL_MD(pipe), temp);
+	} else {
+		/* The pixel multiplier can only be updated once the
+		 * DPLL is enabled and the clocks are stable.
+		 *
+		 * So write it again.
+		 */
+		I915_WRITE(DPLL(pipe), dpll);
+	}
+}
+
+static void i8xx_update_pll(struct drm_crtc *crtc,
+			    struct drm_display_mode *adjusted_mode,
+			    intel_clock_t *clock,
+			    int num_connectors)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 dpll;
+
+	dpll = DPLL_VGA_MODE_DIS;
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+	} else {
+		if (clock->p1 == 2)
+			dpll |= PLL_P1_DIVIDE_BY_TWO;
+		else
+			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+		if (clock->p2 == 4)
+			dpll |= PLL_P2_DIVIDE_BY_4;
+	}
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
+		/* XXX: just matching BIOS for now */
+		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
+		dpll |= 3;
+	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+	else
+		dpll |= PLL_REF_INPUT_DREFCLK;
+
+	dpll |= DPLL_VCO_ENABLE;
+	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
+	 * This is an exception to the general rule that mode_set doesn't turn
+	 * things on.
+	 */
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+		intel_update_lvds(crtc, clock, adjusted_mode);
+
+	I915_WRITE(DPLL(pipe), dpll);
+
+	/* Wait for the clocks to stabilize. */
+	POSTING_READ(DPLL(pipe));
+	udelay(150);
+
+	/* The pixel multiplier can only be updated once the
+	 * DPLL is enabled and the clocks are stable.
+	 *
+	 * So write it again.
+	 */
+	I915_WRITE(DPLL(pipe), dpll);
+}
+
 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 			      struct drm_display_mode *mode,
 			      struct drm_display_mode *adjusted_mode,
@@ -5243,9 +5407,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	int plane = intel_crtc->plane;
 	int refclk, num_connectors = 0;
 	intel_clock_t clock, reduced_clock;
-	u32 dpll, dspcntr, pipeconf, vsyncshift;
-	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
-	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
+	u32 dspcntr, pipeconf, vsyncshift;
+	bool ok, has_reduced_clock = false, is_sdvo = false;
+	bool is_lvds = false, is_tv = false;
 	struct drm_mode_config *mode_config = &dev->mode_config;
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
@@ -5267,18 +5431,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 			if (encoder->needs_tv_clock)
 				is_tv = true;
 			break;
-		case INTEL_OUTPUT_DVO:
-			is_dvo = true;
-			break;
 		case INTEL_OUTPUT_TVOUT:
 			is_tv = true;
 			break;
-		case INTEL_OUTPUT_ANALOG:
-			is_crt = true;
-			break;
-		case INTEL_OUTPUT_DISPLAYPORT:
-			is_dp = true;
-			break;
 		}
 
 		num_connectors++;
@@ -5322,71 +5477,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
 				 &reduced_clock : NULL);
 
-	dpll = DPLL_VGA_MODE_DIS;
-
-	if (!IS_GEN2(dev)) {
-		if (is_lvds)
-			dpll |= DPLLB_MODE_LVDS;
-		else
-			dpll |= DPLLB_MODE_DAC_SERIAL;
-		if (is_sdvo) {
-			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
-			if (pixel_multiplier > 1) {
-				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
-					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
-			}
-			dpll |= DPLL_DVO_HIGH_SPEED;
-		}
-		if (is_dp)
-			dpll |= DPLL_DVO_HIGH_SPEED;
-
-		/* compute bitmask from p1 value */
-		if (IS_PINEVIEW(dev))
-			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
-		else {
-			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-			if (IS_G4X(dev) && has_reduced_clock)
-				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
-		}
-		switch (clock.p2) {
-		case 5:
-			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
-			break;
-		case 7:
-			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
-			break;
-		case 10:
-			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
-			break;
-		case 14:
-			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
-			break;
-		}
-		if (INTEL_INFO(dev)->gen >= 4)
-			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
-	} else {
-		if (is_lvds) {
-			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-		} else {
-			if (clock.p1 == 2)
-				dpll |= PLL_P1_DIVIDE_BY_TWO;
-			else
-				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-			if (clock.p2 == 4)
-				dpll |= PLL_P2_DIVIDE_BY_4;
-		}
-	}
-
-	if (is_sdvo && is_tv)
-		dpll |= PLL_REF_INPUT_TVCLKINBC;
-	else if (is_tv)
-		/* XXX: just matching BIOS for now */
-		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
-		dpll |= 3;
-	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
-		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+	if (IS_GEN2(dev))
+		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
 	else
-		dpll |= PLL_REF_INPUT_DREFCLK;
+		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
+				has_reduced_clock ? &reduced_clock : NULL,
+				num_connectors);
 
 	/* setup pipeconf */
 	pipeconf = I915_READ(PIPECONF(pipe));
@@ -5415,24 +5511,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	/* default to 8bpc */
 	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
-	if (is_dp) {
-		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
-			pipeconf |= PIPECONF_BPP_6 |
-				    PIPECONF_DITHER_EN |
-				    PIPECONF_DITHER_TYPE_SP;
-		}
-	}
-
-	dpll |= DPLL_VCO_ENABLE;
 
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
-	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
-
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
 	 * things on.
@@ -5485,35 +5567,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 		I915_WRITE(LVDS, temp);
 	}
 
-	if (is_dp) {
-		intel_dp_set_m_n(crtc, mode, adjusted_mode);
-	}
-
-	I915_WRITE(DPLL(pipe), dpll);
-
-	/* Wait for the clocks to stabilize. */
-	POSTING_READ(DPLL(pipe));
-	udelay(150);
-
-	if (INTEL_INFO(dev)->gen >= 4) {
-		temp = 0;
-		if (is_sdvo) {
-			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
-			if (temp > 1)
-				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-			else
-				temp = 0;
-		}
-		I915_WRITE(DPLL_MD(pipe), temp);
-	} else {
-		/* The pixel multiplier can only be updated once the
-		 * DPLL is enabled and the clocks are stable.
-		 *
-		 * So write it again.
-		 */
-		I915_WRITE(DPLL(pipe), dpll);
-	}
-
 	if (HAS_PIPE_CXSR(dev)) {
 		if (intel_crtc->lowfreq_avail) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
-- 
1.7.5.4

[PATCH 10/26] drm/i915: split LVDS update code out of i9xx_crtc_mode_set

[Jesse Barnes]

Just to make things clearer and reduce the size of this monstrosity.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |  117 ++++++++++++++++++----------------
 1 files changed, 63 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 84480da..adfa19b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5230,6 +5230,62 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
 	}
 }
 
+static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
+			      struct drm_display_mode *adjusted_mode)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 temp, lvds_sync = 0;
+
+	temp = I915_READ(LVDS);
+	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
+	if (pipe == 1) {
+		temp |= LVDS_PIPEB_SELECT;
+	} else {
+		temp &= ~LVDS_PIPEB_SELECT;
+	}
+	/* set the corresponsding LVDS_BORDER bit */
+	temp |= dev_priv->lvds_border_bits;
+	/* Set the B0-B3 data pairs corresponding to whether we're going to
+	 * set the DPLLs for dual-channel mode or not.
+	 */
+	if (clock->p2 == 7)
+		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
+	else
+		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
+
+	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
+	 * appropriately here, but we need to look more thoroughly into how
+	 * panels behave in the two modes.
+	 */
+	/* set the dithering flag on LVDS as needed */
+	if (INTEL_INFO(dev)->gen >= 4) {
+		if (dev_priv->lvds_dither)
+			temp |= LVDS_ENABLE_DITHER;
+		else
+			temp &= ~LVDS_ENABLE_DITHER;
+	}
+	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+		lvds_sync |= LVDS_HSYNC_POLARITY;
+	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+		lvds_sync |= LVDS_VSYNC_POLARITY;
+	if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
+	    != lvds_sync) {
+		char flags[2] = "-+";
+		DRM_INFO("Changing LVDS panel from "
+			 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
+			 flags[!(temp & LVDS_HSYNC_POLARITY)],
+			 flags[!(temp & LVDS_VSYNC_POLARITY)],
+			 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
+			 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
+		temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+		temp |= lvds_sync;
+	}
+	I915_WRITE(LVDS, temp);
+}
+
 static void i9xx_update_pll(struct drm_crtc *crtc,
 			    struct drm_display_mode *mode,
 			    struct drm_display_mode *adjusted_mode,
@@ -5305,6 +5361,13 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
 	POSTING_READ(DPLL(pipe));
 	udelay(150);
 
+	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
+	 * This is an exception to the general rule that mode_set doesn't turn
+	 * things on.
+	 */
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+		intel_update_lvds(crtc, clock, adjusted_mode);
+
 	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
 		intel_dp_set_m_n(crtc, mode, adjusted_mode);
 
@@ -5414,8 +5477,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	struct intel_encoder *encoder;
 	const intel_limit_t *limit;
 	int ret;
-	u32 temp;
-	u32 lvds_sync = 0;
 
 	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
 		if (encoder->base.crtc != crtc)
@@ -5515,58 +5576,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
 	drm_mode_debug_printmodeline(mode);
 
-	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
-	 * This is an exception to the general rule that mode_set doesn't turn
-	 * things on.
-	 */
-	if (is_lvds) {
-		temp = I915_READ(LVDS);
-		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
-		if (pipe == 1) {
-			temp |= LVDS_PIPEB_SELECT;
-		} else {
-			temp &= ~LVDS_PIPEB_SELECT;
-		}
-		/* set the corresponsding LVDS_BORDER bit */
-		temp |= dev_priv->lvds_border_bits;
-		/* Set the B0-B3 data pairs corresponding to whether we're going to
-		 * set the DPLLs for dual-channel mode or not.
-		 */
-		if (clock.p2 == 7)
-			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
-		else
-			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
-
-		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
-		 * appropriately here, but we need to look more thoroughly into how
-		 * panels behave in the two modes.
-		 */
-		/* set the dithering flag on LVDS as needed */
-		if (INTEL_INFO(dev)->gen >= 4) {
-			if (dev_priv->lvds_dither)
-				temp |= LVDS_ENABLE_DITHER;
-			else
-				temp &= ~LVDS_ENABLE_DITHER;
-		}
-		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
-			lvds_sync |= LVDS_HSYNC_POLARITY;
-		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
-			lvds_sync |= LVDS_VSYNC_POLARITY;
-		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
-		    != lvds_sync) {
-			char flags[2] = "-+";
-			DRM_INFO("Changing LVDS panel from "
-				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
-				 flags[!(temp & LVDS_HSYNC_POLARITY)],
-				 flags[!(temp & LVDS_VSYNC_POLARITY)],
-				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
-				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
-			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
-			temp |= lvds_sync;
-		}
-		I915_WRITE(LVDS, temp);
-	}
-
 	if (HAS_PIPE_CXSR(dev)) {
 		if (intel_crtc->lowfreq_avail) {
 			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
-- 
1.7.5.4

[PATCH 11/26] drm/i915: ValleyView mode setting limits and PLL functions

[Jesse Barnes]

Add some VLV limit structures and update the PLL code.

v2: resolve conflicts, Vijay to re-post with PLL valid checks and fixed limits

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |  231 +++++++++++++++++++++++++++++++++-
 2 files changed, 229 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 749e390..be11d39 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -869,6 +869,7 @@
 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
+#define   DPLL_LOCK_VLV			(1<<15)
 #define   DPLL_VOLTAGE_LDO_VLV		(1<<14)
 #define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
 #define   DPLL_RATE_SWITCH_VLV		(1<<8)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index adfa19b..6bed629 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -98,6 +98,10 @@ static bool
 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 			   int target, int refclk, intel_clock_t *match_clock,
 			   intel_clock_t *best_clock);
+static bool
+intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+			int target, int refclk, intel_clock_t *match_clock,
+			intel_clock_t *best_clock);
 
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
@@ -360,6 +364,48 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
 	.find_pll = intel_find_pll_ironlake_dp,
 };
 
+static const intel_limit_t intel_limits_vlv_dac = {
+	.dot = { .min = 25000, .max = 270000 },
+	.vco = { .min = 4000000, .max = 6000000 },
+	.n = { .min = 1, .max = 7 },
+	.m = { .min = 22, .max = 450 }, /* guess */
+	.m1 = { .min = 2, .max = 3 },
+	.m2 = { .min = 11, .max = 156 },
+	.p = { .min = 10, .max = 30 },
+	.p1 = { .min = 2, .max = 3 },
+	.p2 = { .dot_limit = 270000,
+		.p2_slow = 10, .p2_fast = 5 },
+	.find_pll = intel_vlv_find_best_pll,
+};
+
+static const intel_limit_t intel_limits_vlv_hdmi = {
+	.dot = { .min = 20000, .max = 165000 },
+	.vco = { .min = 5994000, .max = 4000000 },
+	.n = { .min = 1, .max = 7 },
+	.m = { .min = 60, .max = 300 }, /* guess */
+	.m1 = { .min = 2, .max = 3 },
+	.m2 = { .min = 11, .max = 156 },
+	.p = { .min = 10, .max = 30 },
+	.p1 = { .min = 2, .max = 3 },
+	.p2 = { .dot_limit = 270000,
+		.p2_slow = 10, .p2_fast = 5 },
+	.find_pll = intel_vlv_find_best_pll,
+};
+
+static const intel_limit_t intel_limits_vlv_dp = {
+	.dot = { .min = 162000, .max = 270000 },
+	.vco = { .min = 5994000, .max = 4000000 },
+	.n = { .min = 1, .max = 7 },
+	.m = { .min = 60, .max = 300 }, /* guess */
+	.m1 = { .min = 2, .max = 3 },
+	.m2 = { .min = 11, .max = 156 },
+	.p = { .min = 10, .max = 30 },
+	.p1 = { .min = 2, .max = 3 },
+	.p2 = { .dot_limit = 270000,
+		.p2_slow = 10, .p2_fast = 5 },
+	.find_pll = intel_vlv_find_best_pll,
+};
+
 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 {
 	unsigned long flags;
@@ -489,6 +535,13 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 			limit = &intel_limits_pineview_lvds;
 		else
 			limit = &intel_limits_pineview_sdvo;
+	} else if (IS_VALLEYVIEW(dev)) {
+		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
+			limit = &intel_limits_vlv_dac;
+		else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+			limit = &intel_limits_vlv_hdmi;
+		else
+			limit = &intel_limits_vlv_dp;
 	} else if (!IS_GEN2(dev)) {
 		if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i9xx_lvds;
@@ -764,6 +817,84 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 	return true;
 }
 
+static bool
+intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
+			int target, int refclk, intel_clock_t *match_clock,
+			intel_clock_t *best_clock)
+{
+	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
+	u32 m, n, fastclk, minvco, maxvco;
+	u32 updrate, minupdate, fracbits, p;
+	unsigned long bestppm, ppm, absppm;
+	int dotclk;
+
+	dotclk = target * 1000;
+
+	bestppm = 1000000;
+	ppm = 0;
+	absppm = 0;
+
+	fastclk = dotclk / (2*100);
+	minvco = limit->vco.min;
+	maxvco = limit->vco.max;
+	updrate = 0;
+	minupdate = 19200;
+	fracbits = 1;
+
+	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
+	bestm1 = bestm2 = bestp1 = bestp2 = 0;
+
+	for(n = 1; n <= ((refclk) / minupdate); n++) {
+		updrate = refclk / n;
+		for (p1 = 3; p1 > 1; p1--) {
+			for (p2 = 21; p2 > 0; p2--) {
+				if (p2 > 10)
+					p2 = p2 - 1;
+				p = p1 * p2;
+
+				for( m1=2; m1 <= 3; m1++) {
+					m2 = (((2*(fastclk * p * n / m1 )) +
+					       refclk) / (2*refclk));
+					m = m1 * m2;
+					vco = updrate * m;
+					if(vco >= minvco && vco < maxvco) {
+						ppm = 1000000 *((vco / p) -
+								fastclk) /
+							fastclk;
+						absppm = (ppm > 0)? ppm: (-ppm);
+						if (absppm < 100 &&
+						    ((p1 * p2) >
+						     (bestp1 * bestp2))) {
+							bestppm = 0;
+							bestn = n;
+							bestm1 = m1;
+							bestm2 = m2;
+							bestp1 = p1;
+							bestp2 = p2;
+						}
+						if (absppm < bestppm - 10) {
+							bestppm = absppm;
+							bestn = n;
+							bestm1 = m1;
+							bestm2 = m2;
+							bestp1 = p1;
+							bestp2 = p2;
+						}
+					}
+				}
+			} /* Next p2 */
+		} /* Next p1 */
+	}/* Next n */
+
+	best_clock->n = bestn;
+	best_clock->m1 = bestm1;
+	best_clock->m2 = bestm2;
+	best_clock->p1 = bestp1;
+	best_clock->p2 = bestp2;
+
+	return true;
+}
+
 /**
  * intel_wait_for_vblank - wait for vblank on a given pipe
  * @dev: drm device
@@ -1206,7 +1337,7 @@ static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	u32 val;
 
 	/* No really, not for ILK+ */
-	BUG_ON(dev_priv->info->gen >= 5);
+	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
 
 	/* PLL is protected by panel, make sure we can write it */
 	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
@@ -2951,6 +3082,7 @@ static void intel_clear_scanline_wait(struct drm_device *dev)
 		return;
 
 	ring = LP_RING(dev_priv);
+
 	tmp = I915_READ_CTL(ring);
 	if (tmp & RING_WAIT)
 		I915_WRITE_CTL(ring, tmp);
@@ -5154,14 +5286,38 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
 	return display_bpc != bpc;
 }
 
+static int vlv_get_refclk(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int refclk = 27000; /* for DP & HDMI */
+
+	return 100000; /* only one validated so far */
+
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
+		refclk = 96000;
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+		if (intel_panel_use_ssc(dev_priv))
+			refclk = 100000;
+		else
+			refclk = 96000;
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+		refclk = 100000;
+	}
+
+	return refclk;
+}
+
 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
 {
 	struct drm_device *dev = crtc->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int refclk;
 
-	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
-	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
+	if (IS_VALLEYVIEW(dev)) {
+		refclk = vlv_get_refclk(crtc);
+	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+		   intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
 		refclk = dev_priv->lvds_ssc_freq * 1000;
 		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
 			      refclk / 1000);
@@ -5286,6 +5442,72 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
 	I915_WRITE(LVDS, temp);
 }
 
+static void vlv_update_pll(struct drm_crtc *crtc,
+			   struct drm_display_mode *mode,
+			   struct drm_display_mode *adjusted_mode,
+			   intel_clock_t *clock, intel_clock_t *reduced_clock,
+			   int refclk, int num_connectors)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 dpll, mdiv, pdiv;
+	u32 bestn, bestm1, bestm2, bestp1, bestp2;
+	bool is_hdmi;
+
+	is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
+
+	bestn = clock->n;
+	bestm1 = clock->m1;
+	bestm2 = clock->m2;
+	bestp1 = clock->p1;
+	bestp2 = clock->p2;
+
+	/* Enable DPIO clock input */
+	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
+		DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
+	I915_WRITE(DPLL(pipe), dpll);
+	POSTING_READ(DPLL(pipe));
+
+	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
+	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
+	mdiv |= ((bestn << DPIO_N_SHIFT));
+	mdiv |= (1 << DPIO_POST_DIV_SHIFT);
+	mdiv |= (1 << DPIO_K_SHIFT);
+	mdiv |= DPIO_ENABLE_CALIBRATION;
+	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
+
+	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
+
+	pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
+		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
+		(8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
+	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
+
+	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
+
+	dpll |= DPLL_VCO_ENABLE;
+	I915_WRITE(DPLL(pipe), dpll);
+	POSTING_READ(DPLL(pipe));
+	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
+		DRM_ERROR("DPLL %d failed to lock\n", pipe);
+
+	if (is_hdmi) {
+		u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+
+		if (temp > 1)
+			temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+		else
+			temp = 0;
+
+		I915_WRITE(DPLL_MD(pipe), temp);
+		POSTING_READ(DPLL_MD(pipe));
+	}
+
+	intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
+}
+
 static void i9xx_update_pll(struct drm_crtc *crtc,
 			    struct drm_display_mode *mode,
 			    struct drm_display_mode *adjusted_mode,
@@ -5540,6 +5762,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	if (IS_GEN2(dev))
 		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
+	else if (IS_VALLEYVIEW(dev))
+		vlv_update_pll(crtc, mode, adjusted_mode, &clock, NULL,
+			       refclk, num_connectors);
 	else
 		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
 				has_reduced_clock ? &reduced_clock : NULL,
-- 
1.7.5.4

[PATCH 12/26] drm/i915: program drain latency regs on ValleyView

[Jesse Barnes]

From: Gajanan Bhat <gajanan.bhat@intel.com>

This patch adds support for programming drain latency registers of Pondicherry
memory arbiter of Valleyview.

v2: clarify function names (Daniel)
    fix summary typo (Daniel)

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h      |   16 +++++++
 drivers/gpu/drm/i915/intel_display.c |   76 ++++++++++++++++++++++++++++++++++
 2 files changed, 92 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index be11d39..57e8980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2605,6 +2605,22 @@
 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
 #define   DSPFW_HPLL_SR_MASK		(0x1ff)
 
+/* drain latency register values*/
+#define DRAIN_LATENCY_PRECISION_32	32
+#define DRAIN_LATENCY_PRECISION_16	16
+#define VLV_DDL1			0x70050
+#define DDL_CURSORA_PRECISION_32	(1<<31)
+#define DDL_CURSORA_PRECISION_16	(0<<31)
+#define DDL_CURSORA_SHIFT		24
+#define DDL_PLANEA_PRECISION_32		(1<<7)
+#define DDL_PLANEA_PRECISION_16		(0<<7)
+#define VLV_DDL2			0x70054
+#define DDL_CURSORB_PRECISION_32	(1<<31)
+#define DDL_CURSORB_PRECISION_16	(0<<31)
+#define DDL_CURSORB_SHIFT		24
+#define DDL_PLANEB_PRECISION_32		(1<<7)
+#define DDL_PLANEB_PRECISION_16		(0<<7)
+
 /* FIFO watermark sizes etc */
 #define G4X_FIFO_LINE_SIZE	64
 #define I915_FIFO_LINE_SIZE	64
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6bed629..4b5905c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4337,6 +4337,80 @@ static bool g4x_compute_srwm(struct drm_device *dev,
 			      display, cursor);
 }
 
+static int vlv_compute_drain_latency(struct drm_device *dev,
+				     int plane,
+				     int *plane_prec_mult,
+				     int *plane_dl,
+				     int *cursor_prec_mult,
+				     int *cursor_dl)
+{
+	struct drm_crtc *crtc;
+	int clock, pixel_size;
+	int entries;
+
+	crtc = intel_get_crtc_for_plane(dev, plane);
+	if (crtc->fb == NULL || !crtc->enabled)
+		return false;
+
+	clock = crtc->mode.clock;	/* VESA DOT Clock */
+	pixel_size = crtc->fb->bits_per_pixel / 8;	/* BPP */
+
+	entries = (clock / 1000) * pixel_size;
+	*plane_prec_mult = (entries > 256) ?
+		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+	*plane_dl = (64 * *plane_prec_mult * 4) / ((clock / 1000) * pixel_size);
+
+	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
+	*cursor_prec_mult = (entries > 256) ?
+		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
+	*cursor_dl = (64 * *cursor_prec_mult * 4) / ((clock / 1000) * 4);
+
+	return true;
+}
+
+/*
+ * Update drain latency registers of memory arbiter
+ *
+ * Valleyview SoC has a new memory arbiter and needs drain latency registers
+ * to be programmed. Each plane has a drain latency multiplier and a drain
+ * latency value.
+ */
+
+static void vlv_update_drain_latency(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int planea_prec, planea_dl, planeb_prec, planeb_dl;
+	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
+	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
+							either 16 or 32 */
+
+	/* For plane A, Cursor A */
+	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
+				      &cursor_prec_mult, &cursora_dl)) {
+		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
+		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
+
+		I915_WRITE(VLV_DDL1, cursora_prec |
+				(cursora_dl << DDL_CURSORA_SHIFT) |
+				planea_prec | planea_dl);
+	}
+
+	/* For plane B, Cursor B */
+	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
+				      &cursor_prec_mult, &cursorb_dl)) {
+		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
+		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
+			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
+
+		I915_WRITE(VLV_DDL2, cursorb_prec |
+				(cursorb_dl << DDL_CURSORB_SHIFT) |
+				planeb_prec | planeb_dl);
+	}
+}
+
 #define single_plane_enabled(mask) is_power_of_2(mask)
 
 static void valleyview_update_wm(struct drm_device *dev)
@@ -4347,6 +4421,8 @@ static void valleyview_update_wm(struct drm_device *dev)
 	int plane_sr, cursor_sr;
 	unsigned int enabled = 0;
 
+	vlv_update_drain_latency(dev);
+
 	if (g4x_compute_wm0(dev, 0,
 			    &valleyview_wm_info, latency_ns,
 			    &valleyview_cursor_wm_info, latency_ns,
-- 
1.7.5.4

[PATCH 13/26] drm/i915: Enable DP panel power sequencing for ValleyView

[Jesse Barnes]

From: Shobhit Kumar <shobhit.kumar@intel.com>

VLV supports two dp panels, there are two set of panel power sequence
registers which needed to be programmed based on the configured
pipe. This patch add supports for the same

Acked-by: Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Beeresh G <beeresh.g@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h |   12 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c |    8 +++++++-
 2 files changed, 19 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 57e8980..5c8658f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3734,6 +3734,18 @@
 
 #define BLC_PWM_PCH_CTL2	0xc8254
 
+#define PIPEA_PP_STATUS         0x61200
+#define PIPEA_PP_CONTROL        0x61204
+#define PIPEA_PP_ON_DELAYS      0x61208
+#define PIPEA_PP_OFF_DELAYS     0x6120c
+#define PIPEA_PP_DIVISOR        0x61210
+
+#define PIPEB_PP_STATUS         0x61300
+#define PIPEB_PP_CONTROL        0x61304
+#define PIPEB_PP_ON_DELAYS      0x61308
+#define PIPEB_PP_OFF_DELAYS     0x6130c
+#define PIPEB_PP_DIVISOR        0x61310
+
 #define PCH_PP_STATUS		0xc7200
 #define PCH_PP_CONTROL		0xc7204
 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 110552f..a831bb5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -311,7 +311,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dp->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
+	if (IS_VALLEYVIEW(dev)) {
+		if (I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT)
+			return (I915_READ(PIPEB_PP_STATUS) & PP_ON) != 0;
+		else
+			return (I915_READ(PIPEA_PP_STATUS) & PP_ON) != 0;
+	} else
+		return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 }
 
 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
-- 
1.7.5.4

[PATCH 14/26] drm/i915: Enable HDMI on ValleyView

[Jesse Barnes]

From: Shobhit Kumar <shobhit.kumar@intel.com>

HDMI register offsets are different in Valleyview. Add support for the
same.

v2: drop superfluous comments in HDMI init (Daniel)

Signed-off-by: Beeresh G <beeresh.g@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_reg.h   |   16 ++++++++++++++++
 drivers/gpu/drm/i915/intel_hdmi.c |   37 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 52 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5c8658f..d11540a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3469,6 +3469,21 @@
 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
 
+#define VLV_VIDEO_DIP_CTL_A		0x60220
+#define VLV_VIDEO_DIP_DATA_A		0x60208
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
+
+#define VLV_VIDEO_DIP_CTL_B		0x61170
+#define VLV_VIDEO_DIP_DATA_B		0x61174
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
+
+#define VLV_TVIDEO_DIP_CTL(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
+#define VLV_TVIDEO_DIP_DATA(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
+#define VLV_TVIDEO_DIP_GCP(pipe) \
+	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
 #define _TRANS_HSYNC_B           0xe1008
@@ -3689,6 +3704,7 @@
 #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
 
 /* or SDVOB */
+#define VLV_HDMIB 0x61140
 #define HDMIB   0xe1140
 #define  PORT_ENABLE    (1 << 31)
 #define  TRANSCODER(pipe)       ((pipe) << 30)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..1fab9cd 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -177,6 +177,37 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
 
 	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
 }
+
+static void vlv_write_infoframe(struct drm_encoder *encoder,
+				     struct dip_infoframe *frame)
+{
+	uint32_t *data = (uint32_t *)frame;
+	struct drm_device *dev = encoder->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_crtc *crtc = encoder->crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
+	unsigned i, len = DIP_HEADER_SIZE + frame->len;
+	u32 flags, val = I915_READ(reg);
+
+	intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+	flags = intel_infoframe_index(frame);
+
+	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
+
+	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+
+	for (i = 0; i < len; i += 4) {
+		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
+		data++;
+	}
+
+	flags |= intel_infoframe_flags(frame);
+
+	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+}
+
 static void intel_set_infoframe(struct drm_encoder *encoder,
 				struct dip_infoframe *frame)
 {
@@ -549,7 +580,11 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
 	if (!HAS_PCH_SPLIT(dev)) {
 		intel_hdmi->write_infoframe = i9xx_write_infoframe;
 		I915_WRITE(VIDEO_DIP_CTL, 0);
-	} else {
+	} else if (IS_VALLEYVIEW(dev)) {
+		intel_hdmi->write_infoframe = vlv_write_infoframe;
+		for_each_pipe(i)
+			I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0);
+	}  else {
 		intel_hdmi->write_infoframe = ironlake_write_infoframe;
 		for_each_pipe(i)
 			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
-- 
1.7.5.4

[PATCH 15/26] agp/intel: map more registers for use by the GTT code

[Jesse Barnes]

We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
register for doing so is above the range we normally map.  Map the whole
register space to make sure we can get it.

v2: only map the larger space on gen7+ (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-gtt.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac..269cb02 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
 static int i9xx_setup(void)
 {
 	u32 reg_addr;
+	int size = KB(512);
 
 	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
 
 	reg_addr &= 0xfff80000;
 
-	intel_private.registers = ioremap(reg_addr, 128 * 4096);
+	if (INTEL_GTT_GEN >= 7)
+		size = MB(2);
+
+	intel_private.registers = ioremap(reg_addr, size);
 	if (!intel_private.registers)
 		return -ENOMEM;
 
-- 
1.7.5.4

[PATCH 16/26] agp/intel: add ValleyView AGP driver

[Jesse Barnes]

But don't bind the PCI ID yet.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-agp.c |    1 +
 drivers/char/agp/intel-agp.h |    3 +++
 drivers/char/agp/intel-gtt.c |   23 +++++++++++++++++++++++
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 962e75d..74c2d92 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -907,6 +907,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
+	ID(PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB),
 	{ }
 };
 
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5da67f1..41d9ee1 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -96,6 +96,7 @@
 #define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
 
 #define GFX_FLSH_CNTL		0x2170 /* 915+ */
+#define GFX_FLSH_CNTL_VLV	0x101008
 
 #define I810_DRAM_CTL		0x3000
 #define I810_DRAM_ROW_0		0x00000001
@@ -234,6 +235,8 @@
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB		0x0F00 /* VLV1 */
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG		0x0F30
 
 int intel_gmch_probe(struct pci_dev *pdev,
 			       struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 269cb02..ccc0045 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1179,6 +1179,20 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
 	writel(addr | pte_flags, intel_private.gtt + entry);
 }
 
+static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
+				   unsigned int flags)
+{
+	u32 pte_flags;
+
+	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
+
+	/* gen6 has bit11-4 for physical addr bit39-32 */
+	addr |= (addr >> 28) & 0xff0;
+	writel(addr | pte_flags, intel_private.gtt + entry);
+
+	writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
+}
+
 static void gen6_cleanup(void)
 {
 }
@@ -1359,6 +1373,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
 	.check_flags = gen6_check_flags,
 	.chipset_flush = i9xx_chipset_flush,
 };
+static const struct intel_gtt_driver valleyview_gtt_driver = {
+	.gen = 7,
+	.setup = i9xx_setup,
+	.cleanup = gen6_cleanup,
+	.write_entry = valleyview_write_entry,
+	.dma_mask_size = 40,
+	.check_flags = gen6_check_flags,
+	.chipset_flush = i9xx_chipset_flush,
+};
 
 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
  * driver and gmch_driver must be non-null, and find_gmch will determine
-- 
1.7.5.4

[PATCH 17/26] agp/intel: bind ValleyView AGP driver

[Jesse Barnes]

With the code in place, we can bind this driver.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/char/agp/intel-gtt.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index ccc0045..08336ba 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1486,6 +1486,8 @@ static const struct intel_gtt_driver_description {
 	    "Ivybridge", &sandybridge_gtt_driver },
 	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
 	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
+	    "ValleyView", &valleyview_gtt_driver },
 	{ 0, NULL, NULL }
 };
 
-- 
1.7.5.4

[PATCH 18/26] drm/i915: add ValleyView specific CRT detect function

[Jesse Barnes]

Might be able to merge this back in at some point, but we're seeing bugs
with ADPA based detection, so keep it separate for now with explicit
hotplug trigger usage.

v2: drop superfluous debug message

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_crt.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4d3d736..0d50df8 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -212,6 +212,41 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 	return ret;
 }
 
+static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
+{
+	struct drm_device *dev = connector->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 adpa;
+	bool ret;
+	u32 save_adpa;
+
+	save_adpa = adpa = I915_READ(ADPA);
+	DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
+
+	adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
+
+	I915_WRITE(ADPA, adpa);
+
+	if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
+		     1000)) {
+		DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
+		I915_WRITE(ADPA, save_adpa);
+	}
+
+	/* Check the status to see if both blue and green are on now */
+	adpa = I915_READ(ADPA);
+	if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
+		ret = true;
+	else
+		ret = false;
+
+	DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
+
+	ret = true;
+
+	return ret;
+}
+
 /**
  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  *
@@ -231,6 +266,9 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 	if (HAS_PCH_SPLIT(dev))
 		return intel_ironlake_crt_detect_hotplug(connector);
 
+	if (IS_VALLEYVIEW(dev))
+		return valleyview_crt_detect_hotplug(connector);
+
 	/*
 	 * On 4 series desktop, CRT detect sequence need to be done twice
 	 * to get a reliable result.
-- 
1.7.5.4

[PATCH 19/26] drm/i915: add ValleyView specific force wake get/put functions

[Jesse Barnes]

ValleyView handles force wake differently than previous chipsets, so add
a couple of new functions for it.  But leave it disabled by default
until we test it (need a chip with the Punit enabled first).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c      |   28 +++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h      |    3 +++
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 4 files changed, 34 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4a0e415..3eac9b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -459,6 +459,31 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 	return ret;
 }
 
+void vlv_force_wake_get(struct drm_i915_private *dev_priv)
+{
+	int count;
+
+	count = 0;
+
+	/* Already awake? */
+	if ((I915_READ(0x130094) & 0xa1) == 0xa1)
+		return;
+
+	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffffffff);
+	POSTING_READ(FORCEWAKE_VLV);
+
+	count = 0;
+	while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0)
+		udelay(10);
+}
+
+void vlv_force_wake_put(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE_NOTRACE(FORCEWAKE_VLV, 0xffff0000);
+	/* FIXME: confirm VLV behavior with Punit folks */
+	POSTING_READ(FORCEWAKE_VLV);
+}
+
 static int i915_drm_freeze(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1001,7 +1026,8 @@ MODULE_LICENSE("GPL and additional rights");
 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
        (((dev_priv)->info->gen >= 6) && \
         ((reg) < 0x40000) &&            \
-        ((reg) != FORCEWAKE))
+        ((reg) != FORCEWAKE)) && \
+       (!IS_VALLEYVIEW((dev_priv)->dev))
 
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b8b32d..178a955 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1394,6 +1394,9 @@ extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
 
+extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
+extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
+
 /* overlay */
 #ifdef CONFIG_DEBUG_FS
 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d11540a..771e7150 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3882,6 +3882,8 @@
 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f<<22)
 
 #define  FORCEWAKE				0xA18C
+#define  FORCEWAKE_VLV				0x1300b0
+#define  FORCEWAKE_ACK_VLV			0x1300b4
 #define  FORCEWAKE_ACK				0x130090
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define  FORCEWAKE_MT_ACK			0x130040
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4b5905c..3f55f68 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9457,6 +9457,8 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.update_wm = valleyview_update_wm;
 		dev_priv->display.init_clock_gating =
 			valleyview_init_clock_gating;
+		dev_priv->display.force_wake_get = vlv_force_wake_get;
+		dev_priv->display.force_wake_put = vlv_force_wake_put;
 	} else if (IS_PINEVIEW(dev)) {
 		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
 					    dev_priv->is_ddr3,
-- 
1.7.5.4

[PATCH 20/26] drm/i915: ValleyView has limited cacheability

[Jesse Barnes]

The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
it does writes, so we can't use the cache bits the same way.

So map the status and pipe control pages as uncached on ValleyView, and
only set the pages to cached if we're on a supported platform.

v2: add clarifying comments and don't use the LLC flag for ioremap vs
    kmap (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |   45 ++++++++++++++++++++++++++-----
 1 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ca3972f..9b26c9d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
 {
 	struct pipe_control *pc;
 	struct drm_i915_gem_object *obj;
+	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
+	struct drm_device *dev;
 	int ret;
 
 	if (ring->private)
@@ -335,14 +337,24 @@ init_pipe_control(struct intel_ring_buffer *ring)
 		goto err;
 	}
 
-	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+	i915_gem_object_set_cache_level(obj, cache_level);
 
 	ret = i915_gem_object_pin(obj, 4096, true);
 	if (ret)
 		goto err_unref;
-
+	dev = obj->base.dev;
 	pc->gtt_offset = obj->gtt_offset;
-	pc->cpu_page =  kmap(obj->pages[0]);
+	/*
+	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
+	 * not GPU writes followed by CPU reads.  So we need to map status
+	 * pages as uncached.
+	 */
+	if (IS_VALLEYVIEW(dev))
+		pc->cpu_page = ioremap(dev->agp->base +
+				       obj->gtt_offset,
+				       PAGE_SIZE);
+	else
+		pc->cpu_page =  kmap(obj->pages[0]);
 	if (pc->cpu_page == NULL)
 		goto err_unpin;
 
@@ -364,12 +376,17 @@ cleanup_pipe_control(struct intel_ring_buffer *ring)
 {
 	struct pipe_control *pc = ring->private;
 	struct drm_i915_gem_object *obj;
+	struct drm_device *dev;
 
 	if (!ring->private)
 		return;
 
 	obj = pc->obj;
-	kunmap(obj->pages[0]);
+	dev = obj->base.dev;
+	if (IS_VALLEYVIEW(dev))
+		iounmap(pc->cpu_page);
+	else
+		kunmap(obj->pages[0]);
 	i915_gem_object_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
 
@@ -929,7 +946,10 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
 	if (obj == NULL)
 		return;
 
-	kunmap(obj->pages[0]);
+	if (IS_VALLEYVIEW(dev_priv->dev))
+		iounmap(ring->status_page.page_addr);
+	else
+		kunmap(obj->pages[0]);
 	i915_gem_object_unpin(obj);
 	drm_gem_object_unreference(&obj->base);
 	ring->status_page.obj = NULL;
@@ -942,6 +962,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
 	struct drm_device *dev = ring->dev;
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
+	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
 	int ret;
 
 	obj = i915_gem_alloc_object(dev, 4096);
@@ -951,7 +972,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
 		goto err;
 	}
 
-	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
+	i915_gem_object_set_cache_level(obj, cache_level);
 
 	ret = i915_gem_object_pin(obj, 4096, true);
 	if (ret != 0) {
@@ -959,7 +980,17 @@ static int init_status_page(struct intel_ring_buffer *ring)
 	}
 
 	ring->status_page.gfx_addr = obj->gtt_offset;
-	ring->status_page.page_addr = kmap(obj->pages[0]);
+	/*
+	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
+	 * not GPU writes followed by CPU reads.  So we need to map status
+	 * pages as uncached.
+	 */
+	if (IS_VALLEYVIEW(dev))
+		ring->status_page.page_addr = ioremap(dev->agp->base +
+						      obj->gtt_offset,
+						      PAGE_SIZE);
+	else
+		ring->status_page.page_addr = kmap(obj->pages[0]);
 	if (ring->status_page.page_addr == NULL) {
 		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 		goto err_unpin;
-- 
1.7.5.4

[PATCH 21/26] drm/i915: ValleyView IRQ support

[Jesse Barnes]

ValleyView has a new interrupt architecture; best to put it in a new set
of functions.  Also make sure the ring mask functions handle ValleyView.

FIXME: fix flipping; need to enable interrupts and call prepare/finish

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_debugfs.c     |   40 ++++-
 drivers/gpu/drm/i915/i915_irq.c         |  338 ++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h         |    7 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |    4 +-
 4 files changed, 383 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5693de1..ce024ee 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -468,7 +468,45 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 	if (ret)
 		return ret;
 
-	if (!HAS_PCH_SPLIT(dev)) {
+	if (IS_VALLEYVIEW(dev)) {
+		seq_printf(m, "Display IER:\t%08x\n",
+			   I915_READ(VLV_IER));
+		seq_printf(m, "Display IIR:\t%08x\n",
+			   I915_READ(VLV_IIR));
+		seq_printf(m, "Display IIR_RW:\t%08x\n",
+			   I915_READ(VLV_IIR_RW));
+		seq_printf(m, "Display IMR:\t%08x\n",
+			   I915_READ(VLV_IMR));
+		for_each_pipe(pipe)
+			seq_printf(m, "Pipe %c stat:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(PIPESTAT(pipe)));
+
+		seq_printf(m, "Master IER:\t%08x\n",
+			   I915_READ(VLV_MASTER_IER));
+
+		seq_printf(m, "Render IER:\t%08x\n",
+			   I915_READ(GTIER));
+		seq_printf(m, "Render IIR:\t%08x\n",
+			   I915_READ(GTIIR));
+		seq_printf(m, "Render IMR:\t%08x\n",
+			   I915_READ(GTIMR));
+
+		seq_printf(m, "PM IER:\t\t%08x\n",
+			   I915_READ(GEN6_PMIER));
+		seq_printf(m, "PM IIR:\t\t%08x\n",
+			   I915_READ(GEN6_PMIIR));
+		seq_printf(m, "PM IMR:\t\t%08x\n",
+			   I915_READ(GEN6_PMIMR));
+
+		seq_printf(m, "Port hotplug:\t%08x\n",
+			   I915_READ(PORT_HOTPLUG_EN));
+		seq_printf(m, "DPFLIPSTAT:\t%08x\n",
+			   I915_READ(VLV_DPFLIPSTAT));
+		seq_printf(m, "DPINVGTT:\t%08x\n",
+			   I915_READ(DPINVGTT));
+
+	} else if (!HAS_PCH_SPLIT(dev)) {
 		seq_printf(m, "Interrupt enable:    %08x\n",
 			   I915_READ(IER));
 		seq_printf(m, "Interrupt identity:  %08x\n",
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index afd4e03..91c238e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -118,6 +118,10 @@ void intel_enable_asle(struct drm_device *dev)
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	unsigned long irqflags;
 
+	/* FIXME: opregion/asle for VLV */
+	if (IS_VALLEYVIEW(dev))
+		return;
+
 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 
 	if (HAS_PCH_SPLIT(dev))
@@ -424,6 +428,119 @@ static void gen6_pm_rps_work(struct work_struct *work)
 	mutex_unlock(&dev_priv->dev->struct_mutex);
 }
 
+static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
+{
+	struct drm_device *dev = (struct drm_device *) arg;
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	u32 iir, gt_iir, pm_iir;
+	irqreturn_t ret = IRQ_NONE;
+	unsigned long irqflags;
+	int pipe;
+	u32 pipe_stats[I915_MAX_PIPES];
+	u32 vblank_status;
+	int vblank = 0;
+	bool blc_event;
+
+	atomic_inc(&dev_priv->irq_received);
+
+	vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
+		PIPE_VBLANK_INTERRUPT_STATUS;
+
+	while (true) {
+		iir = I915_READ(VLV_IIR);
+		gt_iir = I915_READ(GTIIR);
+		pm_iir = I915_READ(GEN6_PMIIR);
+
+		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
+			goto out;
+
+		ret = IRQ_HANDLED;
+
+		if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+			notify_ring(dev, &dev_priv->ring[RCS]);
+		if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
+			notify_ring(dev, &dev_priv->ring[VCS]);
+		if (gt_iir & GT_BLT_USER_INTERRUPT)
+			notify_ring(dev, &dev_priv->ring[BCS]);
+
+		if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
+			      GT_GEN6_BSD_CS_ERROR_INTERRUPT |
+			      GT_RENDER_CS_ERROR_INTERRUPT)) {
+			DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
+			i915_handle_error(dev, false);
+		}
+
+		spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+		for_each_pipe(pipe) {
+			int reg = PIPESTAT(pipe);
+			pipe_stats[pipe] = I915_READ(reg);
+
+			/*
+			 * Clear the PIPE*STAT regs before the IIR
+			 */
+			if (pipe_stats[pipe] & 0x8000ffff) {
+				if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+					DRM_DEBUG_DRIVER("pipe %c underrun\n",
+							 pipe_name(pipe));
+				I915_WRITE(reg, pipe_stats[pipe]);
+			}
+		}
+		spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+		/* Consume port.  Then clear IIR or we'll miss events */
+		if (iir & I915_DISPLAY_PORT_INTERRUPT) {
+			u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
+
+			DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
+					 hotplug_status);
+			if (hotplug_status & dev_priv->hotplug_supported_mask)
+				queue_work(dev_priv->wq,
+					   &dev_priv->hotplug_work);
+
+			I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
+			I915_READ(PORT_HOTPLUG_STAT);
+		}
+
+
+		if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
+			drm_handle_vblank(dev, 0);
+			vblank++;
+			if (!dev_priv->flip_pending_is_done) {
+				intel_finish_page_flip(dev, 0);
+			}
+		}
+
+		if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
+			drm_handle_vblank(dev, 1);
+			vblank++;
+			if (!dev_priv->flip_pending_is_done) {
+				intel_finish_page_flip(dev, 0);
+			}
+		}
+
+		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+			blc_event = true;
+
+		if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
+			unsigned long flags;
+			spin_lock_irqsave(&dev_priv->rps_lock, flags);
+			WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
+			dev_priv->pm_iir |= pm_iir;
+			I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
+			POSTING_READ(GEN6_PMIMR);
+			spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
+			queue_work(dev_priv->wq, &dev_priv->rps_work);
+		}
+
+		I915_WRITE(GTIIR, gt_iir);
+		I915_WRITE(GEN6_PMIIR, pm_iir);
+		I915_WRITE(VLV_IIR, iir);
+	}
+
+out:
+	return ret;
+}
+
 static void pch_irq_handler(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1582,6 +1699,32 @@ static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
 	return 0;
 }
 
+static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+	u32 dpfl, imr;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return -EINVAL;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	dpfl = I915_READ(VLV_DPFLIPSTAT);
+	imr = I915_READ(VLV_IMR);
+	if (pipe == 0) {
+		dpfl |= PIPEA_VBLANK_INT_EN;
+		imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
+	} else {
+		dpfl |= PIPEA_VBLANK_INT_EN;
+		imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
+	}
+	I915_WRITE(VLV_DPFLIPSTAT, dpfl);
+	I915_WRITE(VLV_IMR, imr);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+	return 0;
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -1623,6 +1766,28 @@ static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long irqflags;
+	u32 dpfl, imr;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+	dpfl = I915_READ(VLV_DPFLIPSTAT);
+	imr = I915_READ(VLV_IMR);
+	if (pipe == 0) {
+		dpfl &= ~PIPEA_VBLANK_INT_EN;
+		imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
+	} else {
+		dpfl &= ~PIPEB_VBLANK_INT_EN;
+		imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
+	}
+	I915_WRITE(VLV_IMR, imr);
+	I915_WRITE(VLV_DPFLIPSTAT, dpfl);
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
+
 /* Set the vblank monitor pipe
  */
 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
@@ -1832,6 +1997,53 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 	POSTING_READ(SDEIER);
 }
 
+static void valleyview_irq_preinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int pipe;
+
+	atomic_set(&dev_priv->irq_received, 0);
+
+	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+
+	/* VLV magic */
+	I915_WRITE(VLV_IMR, 0);
+	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
+	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
+	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
+
+	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+		/* Workaround stalls observed on Sandy Bridge GPUs by
+		 * making the blitter command streamer generate a
+		 * write to the Hardware Status Page for
+		 * MI_USER_INTERRUPT.  This appears to serialize the
+		 * previous seqno write out before the interrupt
+		 * happens.
+		 */
+		I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
+		I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
+	}
+
+	/* and GT */
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIMR, 0xffffffff);
+	I915_WRITE(GTIER, 0x0);
+	POSTING_READ(GTIER);
+
+	I915_WRITE(DPINVGTT, 0xff);
+
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	I915_WRITE(VLV_IMR, 0xffffffff);
+	I915_WRITE(VLV_IER, 0x0);
+	POSTING_READ(VLV_IER);
+}
+
 /*
  * Enable digital hotplug on the PCH, and configure the DP short pulse
  * duration to 2ms (which is the minimum in the Display Port spec)
@@ -1978,6 +2190,96 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static int valleyview_irq_postinstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	u32 render_irqs;
+	u32 enable_mask;
+	u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
+	u16 msid;
+
+	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
+	enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
+		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
+
+	dev_priv->irq_mask = ~enable_mask;
+
+
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+	DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+	dev_priv->pipestat[0] = 0;
+	dev_priv->pipestat[1] = 0;
+
+	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+
+	/* Hack for broken MSIs on VLV */
+	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
+	pci_read_config_word(dev->pdev, 0x98, &msid);
+	msid &= 0xff; /* mask out delivery bits */
+	msid |= (1<<14);
+	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
+
+	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
+	I915_WRITE(VLV_IER, enable_mask);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	I915_WRITE(PIPESTAT(0), 0xffff);
+	I915_WRITE(PIPESTAT(1), 0xffff);
+	POSTING_READ(VLV_IER);
+
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+
+	render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
+		GT_GEN6_BLT_CS_ERROR_INTERRUPT |
+		GT_BLT_USER_INTERRUPT |
+		GT_GEN6_BSD_USER_INTERRUPT |
+		GT_GEN6_BSD_CS_ERROR_INTERRUPT |
+		GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
+		GT_PIPE_NOTIFY |
+		GT_RENDER_CS_ERROR_INTERRUPT |
+		GT_SYNC_STATUS |
+		GT_USER_INTERRUPT;
+
+	dev_priv->gt_irq_mask = ~render_irqs;
+
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIIR, I915_READ(GTIIR));
+	I915_WRITE(GTIMR, 0);
+	I915_WRITE(GTIER, render_irqs);
+	POSTING_READ(GTIER);
+
+	/* ack & enable invalid PTE error interrupts */
+#if 0 /* FIXME: add support to irq handler for checking these bits */
+	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
+	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
+#endif
+
+	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
+#if 0 /* FIXME: check register definitions; some have moved */
+	/* Note HDMI and DP share bits */
+	if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+		hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+		hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+		hotplug_en |= HDMID_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+		hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+		hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+	if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
+		hotplug_en |= CRT_HOTPLUG_INT_EN;
+		hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+	}
+#endif
+
+	I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
+
+	return 0;
+}
+
 static void i915_driver_irq_preinstall(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2081,6 +2383,30 @@ static int i915_driver_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void valleyview_irq_uninstall(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int pipe;
+
+	if (!dev_priv)
+		return;
+
+	dev_priv->vblank_pipe = 0;
+
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	I915_WRITE(HWSTAM, 0xffffffff);
+	I915_WRITE(PORT_HOTPLUG_EN, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+	for_each_pipe(pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+	I915_WRITE(VLV_IIR, 0xffffffff);
+	I915_WRITE(VLV_IMR, 0xffffffff);
+	I915_WRITE(VLV_IER, 0x0);
+	POSTING_READ(VLV_IER);
+}
+
 static void ironlake_irq_uninstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -2136,7 +2462,8 @@ void intel_irq_init(struct drm_device *dev)
 {
 	dev->driver->get_vblank_counter = i915_get_vblank_counter;
 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
+	    IS_VALLEYVIEW(dev)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
 	}
@@ -2147,7 +2474,14 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->get_vblank_timestamp = NULL;
 	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_VALLEYVIEW(dev)) {
+		dev->driver->irq_handler = valleyview_irq_handler;
+		dev->driver->irq_preinstall = valleyview_irq_preinstall;
+		dev->driver->irq_postinstall = valleyview_irq_postinstall;
+		dev->driver->irq_uninstall = valleyview_irq_uninstall;
+		dev->driver->enable_vblank = valleyview_enable_vblank;
+		dev->driver->disable_vblank = valleyview_disable_vblank;
+	} else if (IS_IVYBRIDGE(dev)) {
 		/* Share pre & uninstall handlers with ILK/SNB */
 		dev->driver->irq_handler = ivybridge_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 771e7150..2de2d1b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -510,6 +510,11 @@
 #define IIR		0x020a4
 #define IMR		0x020a8
 #define ISR		0x020ac
+#define VLV_IIR_RW	0x182084
+#define VLV_IER		0x1820a0
+#define VLV_IIR		0x1820a4
+#define VLV_IMR		0x1820a8
+#define VLV_ISR		0x1820ac
 #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
 #define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
 #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
@@ -2542,7 +2547,7 @@
 #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
-#define DPFLIPSTAT_VLV				0x70028
+#define VLV_DPFLIPSTAT				0x70028
 #define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
 #define   PIPEB_HLINE_INT_EN			(1<<28)
 #define   PIPEB_VBLANK_INT_EN			(1<<27)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9b26c9d..e0ef448 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -704,7 +704,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
 
 	spin_lock(&ring->irq_lock);
 	if (ring->irq_refcount++ == 0) {
-		if (HAS_PCH_SPLIT(dev))
+		if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
 			ironlake_enable_irq(dev_priv,
 					    GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 		else
@@ -723,7 +723,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
 
 	spin_lock(&ring->irq_lock);
 	if (--ring->irq_refcount == 0) {
-		if (HAS_PCH_SPLIT(dev))
+		if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
 			ironlake_disable_irq(dev_priv,
 					     GT_USER_INTERRUPT |
 					     GT_PIPE_NOTIFY);
-- 
1.7.5.4

[PATCH 22/26] drm/i915: display regs are at 0x180000 on ValleyView

[Jesse Barnes]

Although internally the MMIO offsets for display regs haven't changed,
their visibility through the PCI BAR has been affected by the addition
of the Gunit, which occupies the low part of the address space.

Display regs on VLV are offset into the BAR by 0x180000, so we need to
add that for any display register offset.

This patch is a hack to do just that, but ultimately we need to split
our display and render code more cleanly and add accessor functions for
them.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |   80 ++++++++++++++++++++++++++++++++++++++-
 1 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3eac9b6..094baf3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1029,6 +1029,77 @@ MODULE_LICENSE("GPL and additional rights");
         ((reg) != FORCEWAKE)) && \
        (!IS_VALLEYVIEW((dev_priv)->dev))
 
+static bool IS_DISPLAYREG(u32 reg)
+{
+	if (reg >= RENDER_RING_BASE &&
+	    reg < RENDER_RING_BASE + 0xff)
+		return false;
+	if (reg >= GEN6_BSD_RING_BASE &&
+	    reg < GEN6_BSD_RING_BASE + 0xff)
+		return false;
+	if (reg >= BLT_RING_BASE &&
+	    reg < BLT_RING_BASE + 0xff)
+		return false;
+
+	if (reg == PGTBL_ER)
+		return false;
+
+	if (reg >= IPEIR_I965 &&
+	    reg < HWSTAM)
+		return false;
+
+	if (reg == MI_MODE)
+		return false;
+
+	if (reg == GFX_MODE_GEN7)
+		return false;
+
+	if (reg == RENDER_HWS_PGA_GEN7 ||
+	    reg == BSD_HWS_PGA_GEN7 ||
+	    reg == BLT_HWS_PGA_GEN7)
+		return false;
+
+	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
+	    reg == GEN6_BSD_RNCID)
+		return false;
+
+	if (reg == GEN6_BLITTER_ECOSKPD)
+		return false;
+
+	if (reg >= 0x4000c &&
+	    reg <= 0x4002c)
+		return false;
+
+	if (reg >= 0x4f000 &&
+	    reg <= 0x4f08f)
+		return false;
+
+	if (reg >= 0x4f100 &&
+	    reg <= 0x4f11f)
+		return false;
+
+	if (reg >= VLV_MASTER_IER &&
+	    reg <= GEN6_PMIER)
+		return false;
+
+	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
+	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
+		return false;
+
+	if (reg >= VLV_IIR_RW &&
+	    reg <= VLV_ISR)
+		return false;
+
+	if (reg == FORCEWAKE_VLV ||
+	    reg == FORCEWAKE_ACK_VLV)
+		return false;
+
+	if (reg == GEN6_GDRST)
+		return false;
+
+	return true;
+}
+
 #define __i915_read(x, y) \
 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 	u##x val = 0; \
@@ -1041,6 +1112,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 		if (dev_priv->forcewake_count == 0) \
 			dev_priv->display.force_wake_put(dev_priv); \
 		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
+	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
+		val = read##y(dev_priv->regs + reg + 0x180000);		\
 	} else { \
 		val = read##y(dev_priv->regs + reg); \
 	} \
@@ -1060,8 +1133,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
-	} \
-	write##y(val, dev_priv->regs + reg); \
+	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
+		write##y(val, dev_priv->regs + reg + 0x180000);		\
+	} else {							\
+		write##y(val, dev_priv->regs + reg);			\
+	}								\
 	if (unlikely(__fifo_ret)) { \
 		gen6_gt_check_fifodbg(dev_priv); \
 	} \
-- 
1.7.5.4

[PATCH 23/26] drm/i915: check for disabled interrupts on ValleyView

[Jesse Barnes]

Haven't seen this yet, but it doesn't hurt.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1f441f5..9cef64b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1951,6 +1951,8 @@ i915_wait_request(struct intel_ring_buffer *ring,
 	if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 		if (HAS_PCH_SPLIT(ring->dev))
 			ier = I915_READ(DEIER) | I915_READ(GTIER);
+		else if (IS_VALLEYVIEW(ring->dev))
+			ier = I915_READ(GTIER) | I915_READ(VLV_IER);
 		else
 			ier = I915_READ(IER);
 		if (!ier) {
-- 
1.7.5.4

[PATCH 24/26] drm/i915: add HDMI and DP port enumeration on ValleyView

[Jesse Barnes]

ValleyView is similar to IbexPeak here, but with different register
offsets.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3f55f68..ebbd37e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8288,6 +8288,24 @@ static void intel_setup_outputs(struct drm_device *dev)
 		if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
 			intel_dp_init(dev, PCH_DP_D);
 
+	} else if (IS_VALLEYVIEW(dev)) {
+		int found;
+
+		if (I915_READ(VLV_HDMIB) & PORT_DETECTED) {
+			/* SDVOB multiplex with HDMIB */
+			found = intel_sdvo_init(dev, VLV_HDMIB);
+			if (!found)
+				intel_hdmi_init(dev, VLV_HDMIB);
+			if (!found && (I915_READ(DP_B) & DP_DETECTED))
+				intel_dp_init(dev, DP_B);
+		}
+
+		if (I915_READ(SDVOC) & PORT_DETECTED)
+			intel_hdmi_init(dev, SDVOC);
+
+		/* Shares lanes with HDMI on SDVOC */
+		if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED))
+			intel_dp_init(dev, DP_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
-- 
1.7.5.4

[PATCH 25/26] drm/i915: disable turbo on ValleyView for now

[Jesse Barnes]

We'll probably need new init functions and will need to test it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_suspend.c  |    2 +-
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2b5eb22..2a52060 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -886,7 +886,7 @@ int i915_restore_state(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (INTEL_INFO(dev)->gen >= 6) {
+	if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
 		gen6_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
 	}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ebbd37e..5d8126e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9698,7 +9698,7 @@ void intel_modeset_init(struct drm_device *dev)
 		intel_init_emon(dev);
 	}
 
-	if (IS_GEN6(dev) || IS_GEN7(dev)) {
+	if ((IS_GEN6(dev) && IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
 		gen6_enable_rps(dev_priv);
 		gen6_update_ring_freq(dev_priv);
 	}
@@ -9741,7 +9741,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	if (IS_IRONLAKE_M(dev))
 		ironlake_disable_drps(dev);
-	if (IS_GEN6(dev) || IS_GEN7(dev))
+	if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
 		gen6_disable_rps(dev);
 
 	if (IS_IRONLAKE_M(dev))
-- 
1.7.5.4

[PATCH 26/26] drm/i915: bind driver to ValleyView chipsets

[Jesse Barnes]

With the code in place, we can bind the driver, should make bisect possible.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 094baf3..6cd7ebd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -310,6 +310,9 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 	{0, 0, 0}
 };
 
-- 
1.7.5.4

Re: [PATCH 01/26] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:43PM -0700, Jesse Barnes wrote:
> It's only used by the main read/write functions, so we can keep it with
> them.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    6 ++++++
>  drivers/gpu/drm/i915/i915_drv.h |    6 ------
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0694e17..06533cb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -979,6 +979,12 @@ MODULE_AUTHOR(DRIVER_AUTHOR);
>  MODULE_DESCRIPTION(DRIVER_DESC);
>  MODULE_LICENSE("GPL and additional rights");
>  
> +/* We give fast paths for the really cool registers */
> +#define NEEDS_FORCE_WAKE(dev_priv, reg) \
> +       (((dev_priv)->info->gen >= 6) && \
> +        ((reg) < 0x40000) &&            \
> +        ((reg) != FORCEWAKE))
> +
>  #define __i915_read(x, y) \
>  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  	u##x val = 0; \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c0f19f5..83ace70 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1429,12 +1429,6 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
>  void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
>  int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
>  
> -/* We give fast paths for the really cool registers */
> -#define NEEDS_FORCE_WAKE(dev_priv, reg) \
> -	(((dev_priv)->info->gen >= 6) && \
> -	 ((reg) < 0x40000) &&		 \
> -	 ((reg) != FORCEWAKE))
> -
>  #define __i915_read(x, y) \
>  	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
>  
> -- 

Any reason why you changed tabs to spaces on the macro? Also, you may as
well line the macro up a bit better if you end up redoing the patch. The
earlier macro had more stuff which could fit within 80 characters, but
now it should fit.

either way,
Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 02/26] drm/i915: re-order GT IIR bit definitions

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:44PM -0700, Jesse Barnes wrote:
> They were all over the place, order them by position and add a few.
> 
> v2: add gen indications to the new bits (Ben)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 03/26] drm/i915: add ValleyView driver structs and IS_VALLEYVIEW macro

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:45PM -0700, Jesse Barnes wrote:
> For use by the rest of the ValleyView code.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |   18 ++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h |    2 ++
>  2 files changed, 20 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 06533cb..4a0e415 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -248,6 +248,24 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.has_llc = 1,
>  };
>  
> +static const struct intel_device_info intel_valleyview_m_info = {
> +	.gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_fbc = 0,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.is_valleyview = 1,
> +};
> +
> +static const struct intel_device_info intel_valleyview_d_info = {
> +	.gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_fbc = 0,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.is_valleyview = 1,
> +};
> +
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
>  	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */

is intel_valleyview_d_info supposed to be is_mobile=1?

> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 83ace70..cacc8d3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -255,6 +255,7 @@ struct intel_device_info {
>  	u8 is_broadwater:1;
>  	u8 is_crestline:1;
>  	u8 is_ivybridge:1;
> +	u8 is_valleyview:1;
>  	u8 has_fbc:1;
>  	u8 has_pipe_cxsr:1;
>  	u8 has_hotplug:1;
> @@ -1001,6 +1002,7 @@ struct drm_i915_file_private {
>  #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
>  #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
>  #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
> +#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
>  
>  /*

Assuming you fix is_mobile, or confirm it to be correct
Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 07/26] drm/i915: add ValleyView clock gating init

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:49PM -0700, Jesse Barnes wrote:
> Set the same bits as IVB plus a few others.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   18 +++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   46 ++++++++++++++++++++++++++++++++++
>  2 files changed, 64 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1af17e0..86de215 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -578,6 +578,9 @@
>  #define   ECO_GATING_CX_ONLY	(1<<3)
>  #define   ECO_FLIP_DONE		(1<<0)
>  
> +#define CACHE_MODE_1		0x7004 /* IVB+ */
> +#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
> +
>  /* GEN6 interrupt control */
>  #define GEN6_RENDER_HWSTAM	0x2098
>  #define GEN6_RENDER_IMR		0x20a8

So bspec says this should be set for VLV and IVB. But in the series I
only see it defined and never set. So either set it, or kick it to the
curb. (I vote set it)

> @@ -3178,6 +3181,20 @@
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
>  #define  DISP_FBC_WM_DIS		(1<<15)
>  
> +/* GEN7 chicken */
> +#define GEN7_COMMON_SLICE_CHICKEN1		0x7010
> +# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
> +
> +#define GEN7_L3CNTLREG1				0xB01C
> +#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C4FFF8C
> +
> +#define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
> +#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +
> +/* WaCatErrorRejectionIssue */
> +#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> +#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> +
>  /* PCH */
>  
>  /* south display engine interrupt */

Note WaCatErrorRejectionIssue seems to apply for IVB as well.

> @@ -3781,6 +3798,7 @@
>  #define    GT_FIFO_NUM_RESERVED_ENTRIES		20
>  
>  #define GEN6_UCGCTL2				0x9404
> +# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
>  # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE		(1 << 12)
>  # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d72467f..22619c6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8483,6 +8483,50 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&dev_priv->dev->struct_mutex);
>  }
>  
> +static void valleyview_init_clock_gating(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +	uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> +
> +	I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
> +
> +	I915_WRITE(WM3_LP_ILK, 0);
> +	I915_WRITE(WM2_LP_ILK, 0);
> +	I915_WRITE(WM1_LP_ILK, 0);
> +
> +	/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> +	 * This implements the WaDisableRCZUnitClockGating workaround.
> +	 */
> +	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> +
> +	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
> +
> +	I915_WRITE(IVB_CHICKEN3,
> +		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> +		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
> +
> +	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
> +	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> +		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
> +
> +	/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
> +	I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
> +	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
> +
> +	/* This is required by WaCatErrorRejectionIssue */
> +	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> +		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> +		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
> +
> +	for_each_pipe(pipe) {
> +		I915_WRITE(DSPCNTR(pipe),
> +			   I915_READ(DSPCNTR(pipe)) |
> +			   DISPPLANE_TRICKLE_FEED_DISABLE);
> +		intel_flush_display_plane(dev_priv, pipe);
> +	}
> +}
> +
>  static void ironlake_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -8990,6 +9034,8 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.update_wm = NULL;
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		dev_priv->display.update_wm = valleyview_update_wm;
> +		dev_priv->display.init_clock_gating =
> +			valleyview_init_clock_gating;
>  	} else if (IS_PINEVIEW(dev)) {
>  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
>  					    dev_priv->is_ddr3,

You put valleyview_init_clock_gating above ironlake, when it should be
at least below gen6 (probably gen7, looking at the ordering of the rest
of the stuff). No comment on the actual content (important part) of the
patch yet.


Assuming you address my comments, this is:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 20/26] drm/i915: ValleyView has limited cacheability

[Jesse Barnes]

On Thu, 22 Mar 2012 14:39:02 -0700
Jesse Barnes <jbarnes@virtuousgeek.org> wrote:

> The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> it does writes, so we can't use the cache bits the same way.
> 
> So map the status and pipe control pages as uncached on ValleyView, and
> only set the pages to cached if we're on a supported platform.
> 
> v2: add clarifying comments and don't use the LLC flag for ioremap vs
>     kmap (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   45 ++++++++++++++++++++++++++-----
>  1 files changed, 38 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ca3972f..9b26c9d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
>  {
>  	struct pipe_control *pc;
>  	struct drm_i915_gem_object *obj;
> +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> +	struct drm_device *dev;
>  	int ret;
>  
>  	if (ring->private)
> @@ -335,14 +337,24 @@ init_pipe_control(struct intel_ring_buffer *ring)
>  		goto err;
>  	}
>  
> -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> +	i915_gem_object_set_cache_level(obj, cache_level);
>  
>  	ret = i915_gem_object_pin(obj, 4096, true);
>  	if (ret)
>  		goto err_unref;
> -
> +	dev = obj->base.dev;
>  	pc->gtt_offset = obj->gtt_offset;
> -	pc->cpu_page =  kmap(obj->pages[0]);
> +	/*
> +	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
> +	 * not GPU writes followed by CPU reads.  So we need to map status
> +	 * pages as uncached.
> +	 */
> +	if (IS_VALLEYVIEW(dev))
> +		pc->cpu_page = ioremap(dev->agp->base +
> +				       obj->gtt_offset,
> +				       PAGE_SIZE);
> +	else
> +		pc->cpu_page =  kmap(obj->pages[0]);
>  	if (pc->cpu_page == NULL)
>  		goto err_unpin;
>  
> @@ -364,12 +376,17 @@ cleanup_pipe_control(struct intel_ring_buffer *ring)
>  {
>  	struct pipe_control *pc = ring->private;
>  	struct drm_i915_gem_object *obj;
> +	struct drm_device *dev;
>  
>  	if (!ring->private)
>  		return;
>  
>  	obj = pc->obj;
> -	kunmap(obj->pages[0]);
> +	dev = obj->base.dev;
> +	if (IS_VALLEYVIEW(dev))
> +		iounmap(pc->cpu_page);
> +	else
> +		kunmap(obj->pages[0]);
>  	i915_gem_object_unpin(obj);
>  	drm_gem_object_unreference(&obj->base);
>  
> @@ -929,7 +946,10 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
>  	if (obj == NULL)
>  		return;
>  
> -	kunmap(obj->pages[0]);
> +	if (IS_VALLEYVIEW(dev_priv->dev))
> +		iounmap(ring->status_page.page_addr);
> +	else
> +		kunmap(obj->pages[0]);
>  	i915_gem_object_unpin(obj);
>  	drm_gem_object_unreference(&obj->base);
>  	ring->status_page.obj = NULL;
> @@ -942,6 +962,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  	struct drm_device *dev = ring->dev;
>  	drm_i915_private_t *dev_priv = dev->dev_private;
>  	struct drm_i915_gem_object *obj;
> +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;

So yeah earlier chipsets where this was ok but that don't set .has_llc
will be affected; I'll just change this to IS_VALLEYVIEW.

But on the plus side, if we applied this they probably wouldn't see
"missed irq" messages (if that ever happened on those chipsets). :)

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 04/26] drm/i915: ValleyView watermark support

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:46PM -0700, Jesse Barnes wrote:
> Add support for ValleyView watermark handling.  It's like Cantiga with a
> few small differences (big FIFO mode and different WM limits).
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    9 +++++
>  drivers/gpu/drm/i915/intel_display.c |   65 ++++++++++++++++++++++++++++++++++
>  2 files changed, 74 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f3609f2..0540099 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1043,6 +1043,12 @@
>  #define RAMCLK_GATE_D		0x6210		/* CRL only */
>  #define DEUC			0x6214          /* CRL only */
>  
> +#define FW_BLC_SELF_VLV		0x6500
> +#define  FW_CSPWRDWNEN		(1<<15)
> +#define MI_ARB_VLV		0x6504
> +#define  DISP_TRICKLE_FEED_DIS	(1<<2)
> +#define CZCLK_CDCLK_FREQ_RATIO_VLV	0x6508
> +
>  /*
>   * Palette regs
>   */

Seems like the bottom 3 of these aren't used anywhere.

> @@ -2495,6 +2501,7 @@
>  #define I915_FIFO_LINE_SIZE	64
>  #define I830_FIFO_LINE_SIZE	32
>  
> +#define VALLEYVIEW_FIFO_SIZE	255
>  #define G4X_FIFO_SIZE		127
>  #define I965_FIFO_SIZE		512
>  #define I945_FIFO_SIZE		127
> @@ -2502,6 +2509,7 @@
>  #define I855GM_FIFO_SIZE	127 /* In cachelines */
>  #define I830_FIFO_SIZE		95
>  
> +#define VALLEYVIEW_MAX_WM	0xff
>  #define G4X_MAX_WM		0x3f
>  #define I915_MAX_WM		0x3f
>  
> @@ -2516,6 +2524,7 @@
>  #define PINEVIEW_CURSOR_DFT_WM	0
>  #define PINEVIEW_CURSOR_GUARD_WM	5
>  
> +#define VALLEYVIEW_CURSOR_MAX_WM 64
>  #define I965_CURSOR_FIFO	64
>  #define I965_CURSOR_MAX_WM	32
>  #define I965_CURSOR_DFT_WM	8
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index de1ba19..daa8853 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3606,6 +3606,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
>  	2,
>  	G4X_FIFO_LINE_SIZE,
>  };
> +static const struct intel_watermark_params valleyview_wm_info = {
> +	VALLEYVIEW_FIFO_SIZE,
> +	VALLEYVIEW_MAX_WM,
> +	VALLEYVIEW_MAX_WM,
> +	2,
> +	G4X_FIFO_LINE_SIZE,
> +};
> +static const struct intel_watermark_params valleyview_cursor_wm_info = {
> +	I965_CURSOR_FIFO,
> +	VALLEYVIEW_CURSOR_MAX_WM,
> +	I965_CURSOR_DFT_WM,
> +	2,
> +	G4X_FIFO_LINE_SIZE,
> +};
>  static const struct intel_watermark_params i965_cursor_wm_info = {
>  	I965_CURSOR_FIFO,
>  	I965_CURSOR_MAX_WM,
> @@ -4130,6 +4144,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
>  
>  #define single_plane_enabled(mask) is_power_of_2(mask)
>  
> +static void valleyview_update_wm(struct drm_device *dev)
> +{
> +	static const int sr_latency_ns = 12000;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
> +	int plane_sr, cursor_sr;
> +	unsigned int enabled = 0;
> +
> +	if (g4x_compute_wm0(dev, 0,
> +			    &valleyview_wm_info, latency_ns,
> +			    &valleyview_cursor_wm_info, latency_ns,
> +			    &planea_wm, &cursora_wm))
> +		enabled |= 1;
> +
> +	if (g4x_compute_wm0(dev, 1,
> +			    &valleyview_wm_info, latency_ns,
> +			    &valleyview_cursor_wm_info, latency_ns,
> +			    &planeb_wm, &cursorb_wm))
> +		enabled |= 2;
> +
> +	plane_sr = cursor_sr = 0;
> +	if (single_plane_enabled(enabled) &&
> +	    g4x_compute_srwm(dev, ffs(enabled) - 1,
> +			     sr_latency_ns,
> +			     &valleyview_wm_info,
> +			     &valleyview_cursor_wm_info,
> +			     &plane_sr, &cursor_sr))
> +		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
> +	else
> +		I915_WRITE(FW_BLC_SELF_VLV,
> +			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
> +
> +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> +		      planea_wm, cursora_wm,
> +		      planeb_wm, cursorb_wm,
> +		      plane_sr, cursor_sr);
> +
> +	I915_WRITE(DSPFW1,
> +		   (plane_sr << DSPFW_SR_SHIFT) |
> +		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> +		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
> +		   planea_wm);
> +	I915_WRITE(DSPFW2,
> +		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
> +		   (cursora_wm << DSPFW_CURSORA_SHIFT));
> +	I915_WRITE(DSPFW3,
> +		   (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
> +}
> +
>  static void g4x_update_wm(struct drm_device *dev)
>  {
>  	static const int sr_latency_ns = 12000;
> @@ -8917,6 +8980,8 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.write_eld = ironlake_write_eld;
>  		} else
>  			dev_priv->display.update_wm = NULL;
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		dev_priv->display.update_wm = valleyview_update_wm;
>  	} else if (IS_PINEVIEW(dev)) {
>  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
>  					    dev_priv->is_ddr3,

Aside from the extraneous #defines
Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 05/26] drm/i915: PLL defines for VLV

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:47PM -0700, Jesse Barnes wrote:
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |    9 +++++++++
>  drivers/gpu/drm/i915/intel_display.c |   10 +++++++++-
>  2 files changed, 18 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0540099..869c695 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -796,8 +796,11 @@
>  #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
>  #define   DPLL_VCO_ENABLE		(1 << 31)
>  #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
> +#define   DPLL_EXT_BUFFER_ENABLE_VLV	(1 << 30)
>  #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
> +#define   DPLL_REFA_CLK_ENABLE_VLV	(1 << 29)
>  #define   DPLL_VGA_MODE_DIS		(1 << 28)
> +#define   DPLL_DUAL_PIPE_VLV		(1 << 26)
>  #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
>  #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
>  #define   DPLL_MODE_MASK		(3 << 26)

DPLL_DUAL_PIPE_VLV seems not used

> @@ -808,6 +811,9 @@
>  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
> +#define   DPLL_VOLTAGE_LDO_VLV		(1<<14)
> +#define   DPLL_INTEGRATED_CLOCK_VLV	(1<<13)
> +#define   DPLL_RATE_SWITCH_VLV		(1<<8)
>  
>  #define SRX_INDEX		0x3c4
>  #define SRX_DATA		0x3c5

DPLL_VOLTAGE_LDO_VLV, DPLL_RATE_SWITCH_VLV not used

> @@ -903,6 +909,9 @@
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
>  #define _DPLL_B_MD 0x06020 /* 965+ only */
>  #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
> +
> +#define RAWCLK_FREQ_VLV			0x6024
> +
>  #define _FPA0	0x06040
>  #define _FPA1	0x06044
>  #define _FPB0	0x06048

RAWCLK_FREQ_VLV not used

> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index daa8853..d72467f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3457,6 +3457,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
>  	return true;
>  }
>  
> +static int valleyview_get_display_clock_speed(struct drm_device *dev)
> +{
> +	return 400000; /* FIXME */
> +}
> +
>  static int i945_get_display_clock_speed(struct drm_device *dev)
>  {
>  	return 400000;
> @@ -8885,7 +8890,10 @@ static void intel_init_display(struct drm_device *dev)
>  	}
>  
>  	/* Returns the core display clock speed */
> -	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
> +	if (IS_VALLEYVIEW(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			valleyview_get_display_clock_speed;
> +	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
>  		dev_priv->display.get_display_clock_speed =
>  			i945_get_display_clock_speed;
>  	else if (IS_I915G(dev))

Assuming you address the extra #defines
Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:50PM -0700, Jesse Barnes wrote:
> ValleyView and similar hardware (like CedarView) put some display
> related registers like the PLL controls and dividers on a DPIO bus.  Add
> simple indirect register access routines to get to those registers.
> 
> v2: move new wait_for macro to intel_drv.h (Ben)
>     fix DPIO_PKT double write (Ben)
>     add debugfs file
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c  |   48 ++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h      |    4 ++
>  drivers/gpu/drm/i915/i915_reg.h      |   55 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   61 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h     |   14 ++++++++
>  5 files changed, 182 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fdb7cce..5693de1 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1502,6 +1502,53 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
>  	return 0;
>  }
>  
> +static int i915_dpio_info(struct seq_file *m, void *data)
> +{
> +	struct drm_info_node *node = (struct drm_info_node *) m->private;
> +	struct drm_device *dev = node->minor->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int ret;
> +
> +
> +	ret = mutex_lock_interruptible(&dev->mode_config.mutex);
> +	if (ret)
> +		return ret;
> +
> +	if (!IS_VALLEYVIEW(dev)) {
> +		seq_printf(m, "unsupported\n");
> +		return 0;
> +	}

Chris already caught this bug. and I see it fixed in your repo.

> +
> +	seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
> +
> +	seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_DIV_A));
> +	seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_DIV_B));
> +
> +	seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
> +	seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
> +
> +	seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
> +	seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
> +
> +	seq_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
> +	seq_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
> +
> +	seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
> +		   intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
> +
> +	mutex_unlock(&dev->mode_config.mutex);
> +
> +	return 0;
> +}
> +
>  static int
>  i915_debugfs_common_open(struct inode *inode,
>  			 struct file *filp)
> @@ -1844,6 +1891,7 @@ static struct drm_info_list i915_debugfs_list[] = {
>  	{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
>  	{"i915_swizzle_info", i915_swizzle_info, 0},
>  	{"i915_ppgtt_info", i915_ppgtt_info, 0},
> +	{"i915_dpio", i915_dpio_info, 0},
>  };
>  #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cacc8d3..2b8b32d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -355,6 +355,10 @@ typedef struct drm_i915_private {
>  
>  	/* protects the irq masks */
>  	spinlock_t irq_lock;
> +
> +	/* DPIO indirect register protection */
> +	spinlock_t dpio_lock;
> +
>  	/** Cached value of IMR to avoid reads in updating the bitfield */
>  	u32 pipestat[2];
>  	u32 irq_mask;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 86de215..749e390 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -301,6 +301,61 @@
>  #define  DEBUG_RESET_RENDER		(1<<8)
>  #define  DEBUG_RESET_DISPLAY		(1<<9)
>  
> +/*
> + * DPIO - a special bus for various display related registers to hide behind:
> + *  0x800c: m1, m2, n, p1, p2, k dividers
> + *  0x8014: REF and SFR select
> + *  0x8014: N divider, VCO select
> + *  0x801c/3c: core clock bits
> + *  0x8048/68: low pass filter coefficients
> + *  0x8100: fast clock controls
> + */
> +#define DPIO_PKT			0x2100
> +#define  DPIO_RID			(0<<24)
> +#define  DPIO_OP_WRITE			(1<<16)
> +#define  DPIO_OP_READ			(0<<16)
> +#define  DPIO_PORTID			(0x12<<8)
> +#define  DPIO_BYTE			(0xf<<4)
> +#define  DPIO_BUSY			(1<<0) /* status only */
> +#define DPIO_DATA			0x2104
> +#define DPIO_REG			0x2108
> +#define DPIO_CTL			0x2110
> +#define  DPIO_MODSEL1			(1<<3) /* if ref clk b == 27 */
> +#define  DPIO_MODSEL0			(1<<2) /* if ref clk a == 27 */
> +#define  DPIO_SFR_BYPASS		(1<<1)
> +#define  DPIO_RESET			(1<<0)
> +
> +#define _DPIO_DIV_A			0x800c
> +#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
> +#define   DPIO_K_SHIFT			(24) /* 4 bits */
> +#define   DPIO_P1_SHIFT			(21) /* 3 bits */
> +#define   DPIO_P2_SHIFT			(16) /* 5 bits */
> +#define   DPIO_N_SHIFT			(12) /* 4 bits */
> +#define   DPIO_ENABLE_CALIBRATION	(1<<11)
> +#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
> +#define   DPIO_M2DIV_MASK		0xff
> +#define _DPIO_DIV_B			0x802c
> +#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B)
> +
> +#define _DPIO_REFSFR_A			0x8014
> +#define   DPIO_REFSEL_OVERRIDE		27
> +#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
> +#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
> +#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
> +#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
> +#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
> +#define _DPIO_REFSFR_B			0x8034
> +#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B)
> +
> +#define _DPIO_CORE_CLK_A		0x801c
> +#define _DPIO_CORE_CLK_B		0x803c
> +#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B)
> +
> +#define _DPIO_LFP_COEFF_A		0x8048
> +#define _DPIO_LFP_COEFF_B		0x8068
> +#define DPIO_LFP_COEFF(pipe) _PIPE(pipe, _DPIO_LFP_COEFF_A, _DPIO_LFP_COEFF_B)
> +
> +#define DPIO_FASTCLK_DISABLE		0x8100
>  
>  /*
>   * Fence registers
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 22619c6..f27728c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -360,6 +360,64 @@ static const intel_limit_t intel_limits_ironlake_display_port = {
>  	.find_pll = intel_find_pll_ironlake_dp,
>  };
>  
> +u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
> +{
> +	unsigned long flags;
> +	u32 val = 0;
> +
> +	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> +		DRM_ERROR("DPIO idle wait timed out\n");
> +		goto out_unlock;
> +	}
> +
> +	I915_WRITE(DPIO_REG, reg);
> +	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
> +		   DPIO_BYTE);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> +		DRM_ERROR("DPIO read wait timed out\n");
> +		goto out_unlock;
> +	}
> +	val = I915_READ(DPIO_DATA);
> +
> +out_unlock:
> +	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
> +	return val;
> +}
> +
> +static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
> +			     u32 val)
> +{
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&dev_priv->dpio_lock, flags);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
> +		DRM_ERROR("DPIO idle wait timed out\n");
> +		goto out_unlock;
> +	}
> +
> +	I915_WRITE(DPIO_DATA, val);
> +	I915_WRITE(DPIO_REG, reg);
> +	I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
> +		   DPIO_BYTE);
> +	if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
> +		DRM_ERROR("DPIO write wait timed out\n");
> +
> +out_unlock:
> +	spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
> +}
> +
> +static void vlv_init_dpio(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* Reset the DPIO config */
> +	I915_WRITE(DPIO_CTL, 0);
> +	POSTING_READ(DPIO_CTL);
> +	I915_WRITE(DPIO_CTL, 1);
> +	POSTING_READ(DPIO_CTL);
> +}
> +
>  static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
>  						int refclk)
>  {
> @@ -9306,6 +9364,9 @@ void intel_modeset_cleanup(struct drm_device *dev)

What do you think about checking the busy bit at init time, and if it's
not clear we assume things are screwed and don't use dpio?

>  	if (IS_IRONLAKE_M(dev))
>  		ironlake_disable_rc6(dev);
>  
> +	if (IS_VALLEYVIEW(dev))
> +		vlv_init_dpio(dev);
> +
>  	mutex_unlock(&dev->struct_mutex);
>  
>  	/* Disable the irq before mode object teardown, for the irq might
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9cec6c3..07bcad0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -45,6 +45,18 @@
>  	ret__;								\
>  })
>  
> +#define wait_for_atomic_us(COND, US) ({ \
> +	int i, ret__ = -ETIMEDOUT;	\
> +	for (i = 0; i < (US); i++) {	\
> +		if ((COND)) {		\
> +			ret__ = 0;	\
> +			break;		\
> +		}			\
> +		udelay(1);		\
> +	}				\
> +	ret__;				\
> +})
> +
>  #define wait_for(COND, MS) _wait_for(COND, MS, 1)
>  #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
>  
> @@ -419,4 +431,6 @@ extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
>  extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
>  				     struct drm_file *file_priv);
>  
> +extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
> +
>  #endif /* __INTEL_DRV_H__ */

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 09/26] drm/i915: split PLL update code out of i9xx_crtc_mode_set

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:51PM -0700, Jesse Barnes wrote:
> Makes it more readable and maintainable.  ValleyView will add its own
> PLL update function in a later patch.
> 
> v2: split LVDS bits out of this patch (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |  291 ++++++++++++++++++++--------------
>  1 files changed, 172 insertions(+), 119 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f27728c..84480da 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5230,6 +5230,170 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>  	}
>  }
>  
> +static void i9xx_update_pll(struct drm_crtc *crtc,
> +			    struct drm_display_mode *mode,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
> +			    int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll;
> +	bool is_sdvo;
> +
> +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		dpll |= DPLLB_MODE_LVDS;
> +	else
> +		dpll |= DPLLB_MODE_DAC_SERIAL;
> +	if (is_sdvo) {
> +		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
> +		if (pixel_multiplier > 1) {
> +			if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> +				dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
> +		}
> +		dpll |= DPLL_DVO_HIGH_SPEED;
> +	}
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		dpll |= DPLL_DVO_HIGH_SPEED;
> +
> +	/* compute bitmask from p1 value */
> +	if (IS_PINEVIEW(dev))
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> +	else {
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +		if (IS_G4X(dev) && reduced_clock)
> +			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> +	}
> +	switch (clock->p2) {
> +	case 5:
> +		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
> +		break;
> +	case 7:
> +		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
> +		break;
> +	case 10:
> +		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
> +		break;
> +	case 14:
> +		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
> +		break;
> +	}
> +	if (INTEL_INFO(dev)->gen >= 4)
> +		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
> +
> +	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		dpll |= PLL_REF_INPUT_TVCLKINBC;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		/* XXX: just matching BIOS for now */
> +		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> +		dpll |= 3;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> +		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	else
> +		dpll |= PLL_REF_INPUT_DREFCLK;
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		u32 temp = 0;
> +		if (is_sdvo) {
> +			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> +			if (temp > 1)
> +				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +			else
> +				temp = 0;
> +		}
> +		I915_WRITE(DPLL_MD(pipe), temp);
> +	} else {
> +		/* The pixel multiplier can only be updated once the
> +		 * DPLL is enabled and the clocks are stable.
> +		 *
> +		 * So write it again.
> +		 */
> +		I915_WRITE(DPLL(pipe), dpll);
> +	}
> +}
> +
> +static void i8xx_update_pll(struct drm_crtc *crtc,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock,
> +			    int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll;
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +	} else {
> +		if (clock->p1 == 2)
> +			dpll |= PLL_P1_DIVIDE_BY_TWO;
> +		else
> +			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +		if (clock->p2 == 4)
> +			dpll |= PLL_P2_DIVIDE_BY_4;
> +	}
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		/* XXX: just matching BIOS for now */
> +		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> +		dpll |= 3;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> +		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	else
> +		dpll |= PLL_REF_INPUT_DREFCLK;
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> +	 * This is an exception to the general rule that mode_set doesn't turn
> +	 * things on.
> +	 */
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		intel_update_lvds(crtc, clock, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The pixel multiplier can only be updated once the
> +	 * DPLL is enabled and the clocks are stable.
> +	 *
> +	 * So write it again.
> +	 */
> +	I915_WRITE(DPLL(pipe), dpll);
> +}
> +
>  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  			      struct drm_display_mode *mode,
>  			      struct drm_display_mode *adjusted_mode,
> @@ -5243,9 +5407,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	int refclk, num_connectors = 0;
>  	intel_clock_t clock, reduced_clock;
> -	u32 dpll, dspcntr, pipeconf, vsyncshift;
> -	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
> -	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
> +	u32 dspcntr, pipeconf, vsyncshift;
> +	bool ok, has_reduced_clock = false, is_sdvo = false;
> +	bool is_lvds = false, is_tv = false;
>  	struct drm_mode_config *mode_config = &dev->mode_config;
>  	struct intel_encoder *encoder;
>  	const intel_limit_t *limit;
> @@ -5267,18 +5431,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  			if (encoder->needs_tv_clock)
>  				is_tv = true;
>  			break;
> -		case INTEL_OUTPUT_DVO:
> -			is_dvo = true;
> -			break;
>  		case INTEL_OUTPUT_TVOUT:
>  			is_tv = true;
>  			break;
> -		case INTEL_OUTPUT_ANALOG:
> -			is_crt = true;
> -			break;
> -		case INTEL_OUTPUT_DISPLAYPORT:
> -			is_dp = true;
> -			break;
>  		}
>  
>  		num_connectors++;
> @@ -5322,71 +5477,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
>  				 &reduced_clock : NULL);
>  
> -	dpll = DPLL_VGA_MODE_DIS;
> -
> -	if (!IS_GEN2(dev)) {
> -		if (is_lvds)
> -			dpll |= DPLLB_MODE_LVDS;
> -		else
> -			dpll |= DPLLB_MODE_DAC_SERIAL;
> -		if (is_sdvo) {
> -			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
> -			if (pixel_multiplier > 1) {
> -				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
> -			}
> -			dpll |= DPLL_DVO_HIGH_SPEED;
> -		}
> -		if (is_dp)
> -			dpll |= DPLL_DVO_HIGH_SPEED;
> -
> -		/* compute bitmask from p1 value */
> -		if (IS_PINEVIEW(dev))
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> -		else {
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -			if (IS_G4X(dev) && has_reduced_clock)
> -				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> -		}
> -		switch (clock.p2) {
> -		case 5:
> -			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
> -			break;
> -		case 7:
> -			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
> -			break;
> -		case 10:
> -			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
> -			break;
> -		case 14:
> -			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
> -			break;
> -		}
> -		if (INTEL_INFO(dev)->gen >= 4)
> -			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
> -	} else {
> -		if (is_lvds) {
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -		} else {
> -			if (clock.p1 == 2)
> -				dpll |= PLL_P1_DIVIDE_BY_TWO;
> -			else
> -				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -			if (clock.p2 == 4)
> -				dpll |= PLL_P2_DIVIDE_BY_4;
> -		}
> -	}
> -
> -	if (is_sdvo && is_tv)
> -		dpll |= PLL_REF_INPUT_TVCLKINBC;
> -	else if (is_tv)
> -		/* XXX: just matching BIOS for now */
> -		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> -		dpll |= 3;
> -	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> -		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	if (IS_GEN2(dev))
> +		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
>  	else
> -		dpll |= PLL_REF_INPUT_DREFCLK;
> +		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> +				has_reduced_clock ? &reduced_clock : NULL,
> +				num_connectors);
>  
>  	/* setup pipeconf */
>  	pipeconf = I915_READ(PIPECONF(pipe));
> @@ -5415,24 +5511,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	/* default to 8bpc */
>  	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
> -	if (is_dp) {
> -		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> -			pipeconf |= PIPECONF_BPP_6 |
> -				    PIPECONF_DITHER_EN |
> -				    PIPECONF_DITHER_TYPE_SP;
> -		}
> -	}
> -
> -	dpll |= DPLL_VCO_ENABLE;
>  
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
>  	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
>  	 * This is an exception to the general rule that mode_set doesn't turn
>  	 * things on.
> @@ -5485,35 +5567,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		I915_WRITE(LVDS, temp);
>  	}
>  
> -	if (is_dp) {
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> -	}
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	if (INTEL_INFO(dev)->gen >= 4) {
> -		temp = 0;
> -		if (is_sdvo) {
> -			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> -			if (temp > 1)
> -				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> -			else
> -				temp = 0;
> -		}
> -		I915_WRITE(DPLL_MD(pipe), temp);
> -	} else {
> -		/* The pixel multiplier can only be updated once the
> -		 * DPLL is enabled and the clocks are stable.
> -		 *
> -		 * So write it again.
> -		 */
> -		I915_WRITE(DPLL(pipe), dpll);
> -	}
> -
>  	if (HAS_PIPE_CXSR(dev)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");

Probably the best way to review this one is run a crapload of regression
tests. So I'd recommend a t-b from QA on this. Unless someone else wants
to review the painful diff.

Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 04/26] drm/i915: ValleyView watermark support

[Daniel Vetter]

On Thu, Mar 22, 2012 at 08:29:30PM -0700, Ben Widawsky wrote:
> On Thu, Mar 22, 2012 at 02:38:46PM -0700, Jesse Barnes wrote:
> > Add support for ValleyView watermark handling.  It's like Cantiga with a
> > few small differences (big FIFO mode and different WM limits).
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |    9 +++++
> >  drivers/gpu/drm/i915/intel_display.c |   65 ++++++++++++++++++++++++++++++++++
> >  2 files changed, 74 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f3609f2..0540099 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1043,6 +1043,12 @@
> >  #define RAMCLK_GATE_D		0x6210		/* CRL only */
> >  #define DEUC			0x6214          /* CRL only */
> >  
> > +#define FW_BLC_SELF_VLV		0x6500
> > +#define  FW_CSPWRDWNEN		(1<<15)
> > +#define MI_ARB_VLV		0x6504
> > +#define  DISP_TRICKLE_FEED_DIS	(1<<2)
> > +#define CZCLK_CDCLK_FREQ_RATIO_VLV	0x6508
> > +
> >  /*
> >   * Palette regs
> >   */
> 
> Seems like the bottom 3 of these aren't used anywhere.

I honestly don't mind a few extra #defines, as long as someone has
bothered to cross check them with bspec (to avoid another MI_WTF). At
least if they're sounding somewhat relevant.
-Daniel

> 
> > @@ -2495,6 +2501,7 @@
> >  #define I915_FIFO_LINE_SIZE	64
> >  #define I830_FIFO_LINE_SIZE	32
> >  
> > +#define VALLEYVIEW_FIFO_SIZE	255
> >  #define G4X_FIFO_SIZE		127
> >  #define I965_FIFO_SIZE		512
> >  #define I945_FIFO_SIZE		127
> > @@ -2502,6 +2509,7 @@
> >  #define I855GM_FIFO_SIZE	127 /* In cachelines */
> >  #define I830_FIFO_SIZE		95
> >  
> > +#define VALLEYVIEW_MAX_WM	0xff
> >  #define G4X_MAX_WM		0x3f
> >  #define I915_MAX_WM		0x3f
> >  
> > @@ -2516,6 +2524,7 @@
> >  #define PINEVIEW_CURSOR_DFT_WM	0
> >  #define PINEVIEW_CURSOR_GUARD_WM	5
> >  
> > +#define VALLEYVIEW_CURSOR_MAX_WM 64
> >  #define I965_CURSOR_FIFO	64
> >  #define I965_CURSOR_MAX_WM	32
> >  #define I965_CURSOR_DFT_WM	8
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index de1ba19..daa8853 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3606,6 +3606,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
> >  	2,
> >  	G4X_FIFO_LINE_SIZE,
> >  };
> > +static const struct intel_watermark_params valleyview_wm_info = {
> > +	VALLEYVIEW_FIFO_SIZE,
> > +	VALLEYVIEW_MAX_WM,
> > +	VALLEYVIEW_MAX_WM,
> > +	2,
> > +	G4X_FIFO_LINE_SIZE,
> > +};
> > +static const struct intel_watermark_params valleyview_cursor_wm_info = {
> > +	I965_CURSOR_FIFO,
> > +	VALLEYVIEW_CURSOR_MAX_WM,
> > +	I965_CURSOR_DFT_WM,
> > +	2,
> > +	G4X_FIFO_LINE_SIZE,
> > +};
> >  static const struct intel_watermark_params i965_cursor_wm_info = {
> >  	I965_CURSOR_FIFO,
> >  	I965_CURSOR_MAX_WM,
> > @@ -4130,6 +4144,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> >  
> >  #define single_plane_enabled(mask) is_power_of_2(mask)
> >  
> > +static void valleyview_update_wm(struct drm_device *dev)
> > +{
> > +	static const int sr_latency_ns = 12000;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
> > +	int plane_sr, cursor_sr;
> > +	unsigned int enabled = 0;
> > +
> > +	if (g4x_compute_wm0(dev, 0,
> > +			    &valleyview_wm_info, latency_ns,
> > +			    &valleyview_cursor_wm_info, latency_ns,
> > +			    &planea_wm, &cursora_wm))
> > +		enabled |= 1;
> > +
> > +	if (g4x_compute_wm0(dev, 1,
> > +			    &valleyview_wm_info, latency_ns,
> > +			    &valleyview_cursor_wm_info, latency_ns,
> > +			    &planeb_wm, &cursorb_wm))
> > +		enabled |= 2;
> > +
> > +	plane_sr = cursor_sr = 0;
> > +	if (single_plane_enabled(enabled) &&
> > +	    g4x_compute_srwm(dev, ffs(enabled) - 1,
> > +			     sr_latency_ns,
> > +			     &valleyview_wm_info,
> > +			     &valleyview_cursor_wm_info,
> > +			     &plane_sr, &cursor_sr))
> > +		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
> > +	else
> > +		I915_WRITE(FW_BLC_SELF_VLV,
> > +			   I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
> > +
> > +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> > +		      planea_wm, cursora_wm,
> > +		      planeb_wm, cursorb_wm,
> > +		      plane_sr, cursor_sr);
> > +
> > +	I915_WRITE(DSPFW1,
> > +		   (plane_sr << DSPFW_SR_SHIFT) |
> > +		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> > +		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > +		   planea_wm);
> > +	I915_WRITE(DSPFW2,
> > +		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
> > +		   (cursora_wm << DSPFW_CURSORA_SHIFT));
> > +	I915_WRITE(DSPFW3,
> > +		   (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
> > +}
> > +
> >  static void g4x_update_wm(struct drm_device *dev)
> >  {
> >  	static const int sr_latency_ns = 12000;
> > @@ -8917,6 +8980,8 @@ static void intel_init_display(struct drm_device *dev)
> >  			dev_priv->display.write_eld = ironlake_write_eld;
> >  		} else
> >  			dev_priv->display.update_wm = NULL;
> > +	} else if (IS_VALLEYVIEW(dev)) {
> > +		dev_priv->display.update_wm = valleyview_update_wm;
> >  	} else if (IS_PINEVIEW(dev)) {
> >  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
> >  					    dev_priv->is_ddr3,
> 
> Aside from the extraneous #defines
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 25/26] drm/i915: disable turbo on ValleyView for now

[Eugeni Dodonov]

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On Thu, Mar 22, 2012 at 18:39, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> We'll probably need new init functions and will need to test it.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>

This will be the same case for HSW I guess. And it is not the case of
adding a new feature check, like HAS_TURBO, because these platforms do have
turbo, but it is simple not ready to be enabled yet by default.

So for me,
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
Eugeni Dodonov
 <http://eugeni.dodonov.net/>

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Re: [PATCH 18/26] drm/i915: add ValleyView specific CRT detect function

[Eugeni Dodonov]

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On Thu, Mar 22, 2012 at 18:39, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> Might be able to merge this back in at some point, but we're seeing bugs
> with ADPA based detection, so keep it separate for now with explicit
> hotplug trigger usage.
>
> v2: drop superfluous debug message
>

[...]


> +
> +       DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa,
> ret);
> +
> +       ret = true;
>

I think this is on purpose, to be able to debug it further, but maybe it
would be worth to remove this assignment from this function and add a check
for real return code into intel_crt_detect_hotplug() block? Or maybe add a
/* FIXME */ comment at least? Otherwise, it feel that it could be too
error-prone to leave this assignment here by itself.

Other than that, it looks correct to me.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
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<http://eugeni.dodonov.net/>

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Re: [PATCH 19/26] drm/i915: add ValleyView specific force wake get/put functions

[Eugeni Dodonov]

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On Thu, Mar 22, 2012 at 18:39, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> ValleyView handles force wake differently than previous chipsets, so add
> a couple of new functions for it.  But leave it disabled by default
> until we test it (need a chip with the Punit enabled first).
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  #define NEEDS_FORCE_WAKE(dev_priv, reg) \
>        (((dev_priv)->info->gen >= 6) && \
>         ((reg) < 0x40000) &&            \
> -        ((reg) != FORCEWAKE))
> +        ((reg) != FORCEWAKE)) && \
> +       (!IS_VALLEYVIEW((dev_priv)->dev))
>

In the spirit of bikeshedding, I think that NEEDS_FORCE_WAKE is becoming a
bit scary this way. But I don't know if it makes sense to move the gen and
dev check into a feature flag, to avoid similar issues with possible future
generations of chips..

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView

[Eugeni Dodonov]

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On Thu, Mar 22, 2012 at 18:38, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> ValleyView and similar hardware (like CedarView) put some display
> related registers like the PLL controls and dividers on a DPIO bus.  Add
> simple indirect register access routines to get to those registers.
>
> v2: move new wait_for macro to intel_drv.h (Ben)
>    fix DPIO_PKT double write (Ben)
>    add debugfs file
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>

(Also answering danvet's question on one of my patches).

Those dpio read/write routines are very similar to the SBI ones for LPT,
but some subtle registers changes make them different enough not to be
directly reused AFAIK. So I think we'll have to stick with a set of DPIO
and SBI ops for now.

So other that the other Ben's and Chris'  comments about this:

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

-- 
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<http://eugeni.dodonov.net/>

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Re: [PATCH 01/26] drm/i915: move NEEDS_FORCE_WAKE to i915_drv.c

[Daniel Vetter]

On Thu, Mar 22, 2012 at 03:20:51PM -0700, Ben Widawsky wrote:
> On Thu, Mar 22, 2012 at 02:38:43PM -0700, Jesse Barnes wrote:
> > It's only used by the main read/write functions, so we can keep it with
> > them.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 02/26] drm/i915: re-order GT IIR bit definitions

[Daniel Vetter]

On Thu, Mar 22, 2012 at 03:25:28PM -0700, Ben Widawsky wrote:
> On Thu, Mar 22, 2012 at 02:38:44PM -0700, Jesse Barnes wrote:
> > They were all over the place, order them by position and add a few.
> > 
> > v2: add gen indications to the new bits (Ben)
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 09/26] drm/i915: split PLL update code out of i9xx_crtc_mode_set

[Daniel Vetter]

On Thu, Mar 22, 2012 at 02:38:51PM -0700, Jesse Barnes wrote:
> Makes it more readable and maintainable.  ValleyView will add its own
> PLL update function in a later patch.
> 
> v2: split LVDS bits out of this patch (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

In-depth review ftw, i.e. two things below. Otherwise this looks good, so
keep everything else exactly as-is (I hate doing these kind of split
things up reviews).
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |  291 ++++++++++++++++++++--------------
>  1 files changed, 172 insertions(+), 119 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f27728c..84480da 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5230,6 +5230,170 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>  	}
>  }
>  
> +static void i9xx_update_pll(struct drm_crtc *crtc,
> +			    struct drm_display_mode *mode,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock, intel_clock_t *reduced_clock,
> +			    int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll;
> +	bool is_sdvo;
> +
> +	is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
> +		intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		dpll |= DPLLB_MODE_LVDS;
> +	else
> +		dpll |= DPLLB_MODE_DAC_SERIAL;
> +	if (is_sdvo) {
> +		int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
> +		if (pixel_multiplier > 1) {
> +			if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> +				dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
> +		}
> +		dpll |= DPLL_DVO_HIGH_SPEED;
> +	}
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		dpll |= DPLL_DVO_HIGH_SPEED;
> +
> +	/* compute bitmask from p1 value */
> +	if (IS_PINEVIEW(dev))
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> +	else {
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +		if (IS_G4X(dev) && reduced_clock)
> +			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> +	}
> +	switch (clock->p2) {
> +	case 5:
> +		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
> +		break;
> +	case 7:
> +		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
> +		break;
> +	case 10:
> +		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
> +		break;
> +	case 14:
> +		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
> +		break;
> +	}
> +	if (INTEL_INFO(dev)->gen >= 4)
> +		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
> +
> +	if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		dpll |= PLL_REF_INPUT_TVCLKINBC;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		/* XXX: just matching BIOS for now */
> +		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> +		dpll |= 3;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> +		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	else
> +		dpll |= PLL_REF_INPUT_DREFCLK;
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> +		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		u32 temp = 0;
> +		if (is_sdvo) {
> +			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> +			if (temp > 1)
> +				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> +			else
> +				temp = 0;
> +		}
> +		I915_WRITE(DPLL_MD(pipe), temp);
> +	} else {
> +		/* The pixel multiplier can only be updated once the
> +		 * DPLL is enabled and the clocks are stable.
> +		 *
> +		 * So write it again.
> +		 */
> +		I915_WRITE(DPLL(pipe), dpll);
> +	}
> +}
> +
> +static void i8xx_update_pll(struct drm_crtc *crtc,
> +			    struct drm_display_mode *adjusted_mode,
> +			    intel_clock_t *clock,
> +			    int num_connectors)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 dpll;
> +
> +	dpll = DPLL_VGA_MODE_DIS;
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
> +		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +	} else {
> +		if (clock->p1 == 2)
> +			dpll |= PLL_P1_DIVIDE_BY_TWO;
> +		else
> +			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> +		if (clock->p2 == 4)
> +			dpll |= PLL_P2_DIVIDE_BY_4;
> +	}
> +
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
> +		/* XXX: just matching BIOS for now */
> +		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> +		dpll |= 3;
> +	else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
> +		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> +		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

Just curious: Does gen2 really have ssc on lvds?

> +	else
> +		dpll |= PLL_REF_INPUT_DREFCLK;
> +
> +	dpll |= DPLL_VCO_ENABLE;
> +	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> +	 * This is an exception to the general rule that mode_set doesn't turn
> +	 * things on.
> +	 */
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		intel_update_lvds(crtc, clock, adjusted_mode);
> +
> +	I915_WRITE(DPLL(pipe), dpll);
> +
> +	/* Wait for the clocks to stabilize. */
> +	POSTING_READ(DPLL(pipe));
> +	udelay(150);
> +
> +	/* The pixel multiplier can only be updated once the
> +	 * DPLL is enabled and the clocks are stable.
> +	 *
> +	 * So write it again.
> +	 */
> +	I915_WRITE(DPLL(pipe), dpll);
> +}
> +
>  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  			      struct drm_display_mode *mode,
>  			      struct drm_display_mode *adjusted_mode,
> @@ -5243,9 +5407,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	int plane = intel_crtc->plane;
>  	int refclk, num_connectors = 0;
>  	intel_clock_t clock, reduced_clock;
> -	u32 dpll, dspcntr, pipeconf, vsyncshift;
> -	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
> -	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
> +	u32 dspcntr, pipeconf, vsyncshift;
> +	bool ok, has_reduced_clock = false, is_sdvo = false;
> +	bool is_lvds = false, is_tv = false;
>  	struct drm_mode_config *mode_config = &dev->mode_config;
>  	struct intel_encoder *encoder;
>  	const intel_limit_t *limit;
> @@ -5267,18 +5431,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  			if (encoder->needs_tv_clock)
>  				is_tv = true;
>  			break;
> -		case INTEL_OUTPUT_DVO:
> -			is_dvo = true;
> -			break;
>  		case INTEL_OUTPUT_TVOUT:
>  			is_tv = true;
>  			break;
> -		case INTEL_OUTPUT_ANALOG:
> -			is_crt = true;
> -			break;
> -		case INTEL_OUTPUT_DISPLAYPORT:
> -			is_dp = true;
> -			break;
>  		}
>  
>  		num_connectors++;
> @@ -5322,71 +5477,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
>  				 &reduced_clock : NULL);
>  
> -	dpll = DPLL_VGA_MODE_DIS;
> -
> -	if (!IS_GEN2(dev)) {
> -		if (is_lvds)
> -			dpll |= DPLLB_MODE_LVDS;
> -		else
> -			dpll |= DPLLB_MODE_DAC_SERIAL;
> -		if (is_sdvo) {
> -			int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
> -			if (pixel_multiplier > 1) {
> -				if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
> -					dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
> -			}
> -			dpll |= DPLL_DVO_HIGH_SPEED;
> -		}
> -		if (is_dp)
> -			dpll |= DPLL_DVO_HIGH_SPEED;
> -
> -		/* compute bitmask from p1 value */
> -		if (IS_PINEVIEW(dev))
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
> -		else {
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -			if (IS_G4X(dev) && has_reduced_clock)
> -				dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
> -		}
> -		switch (clock.p2) {
> -		case 5:
> -			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
> -			break;
> -		case 7:
> -			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
> -			break;
> -		case 10:
> -			dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
> -			break;
> -		case 14:
> -			dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
> -			break;
> -		}
> -		if (INTEL_INFO(dev)->gen >= 4)
> -			dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
> -	} else {
> -		if (is_lvds) {
> -			dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -		} else {
> -			if (clock.p1 == 2)
> -				dpll |= PLL_P1_DIVIDE_BY_TWO;
> -			else
> -				dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
> -			if (clock.p2 == 4)
> -				dpll |= PLL_P2_DIVIDE_BY_4;
> -		}
> -	}
> -
> -	if (is_sdvo && is_tv)
> -		dpll |= PLL_REF_INPUT_TVCLKINBC;
> -	else if (is_tv)
> -		/* XXX: just matching BIOS for now */
> -		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> -		dpll |= 3;
> -	else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
> -		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> +	if (IS_GEN2(dev))
> +		i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
>  	else
> -		dpll |= PLL_REF_INPUT_DREFCLK;
> +		i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
> +				has_reduced_clock ? &reduced_clock : NULL,
> +				num_connectors);
>  
>  	/* setup pipeconf */
>  	pipeconf = I915_READ(PIPECONF(pipe));
> @@ -5415,24 +5511,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  
>  	/* default to 8bpc */
>  	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
> -	if (is_dp) {
> -		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> -			pipeconf |= PIPECONF_BPP_6 |
> -				    PIPECONF_DITHER_EN |
> -				    PIPECONF_DITHER_TYPE_SP;
> -		}
> -	}

This hunk seems to have gotten lost. Why?

> -
> -	dpll |= DPLL_VCO_ENABLE;
>  
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> -	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
> -
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
>  	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
>  	 * This is an exception to the general rule that mode_set doesn't turn
>  	 * things on.
> @@ -5485,35 +5567,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  		I915_WRITE(LVDS, temp);
>  	}
>  
> -	if (is_dp) {
> -		intel_dp_set_m_n(crtc, mode, adjusted_mode);
> -	}
> -
> -	I915_WRITE(DPLL(pipe), dpll);
> -
> -	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(DPLL(pipe));
> -	udelay(150);
> -
> -	if (INTEL_INFO(dev)->gen >= 4) {
> -		temp = 0;
> -		if (is_sdvo) {
> -			temp = intel_mode_get_pixel_multiplier(adjusted_mode);
> -			if (temp > 1)
> -				temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
> -			else
> -				temp = 0;
> -		}
> -		I915_WRITE(DPLL_MD(pipe), temp);
> -	} else {
> -		/* The pixel multiplier can only be updated once the
> -		 * DPLL is enabled and the clocks are stable.
> -		 *
> -		 * So write it again.
> -		 */
> -		I915_WRITE(DPLL(pipe), dpll);
> -	}
> -
>  	if (HAS_PIPE_CXSR(dev)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 10/26] drm/i915: split LVDS update code out of i9xx_crtc_mode_set

[Daniel Vetter]

On Thu, Mar 22, 2012 at 02:38:52PM -0700, Jesse Barnes wrote:
> Just to make things clearer and reduce the size of this monstrosity.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

In-depth review ftw. This time the code looks good, but the call the the
new funtion looks a bit misplaced. See below.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |  117 ++++++++++++++++++----------------
>  1 files changed, 63 insertions(+), 54 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 84480da..adfa19b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5230,6 +5230,62 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
>  	}
>  }
>  
> +static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
> +			      struct drm_display_mode *adjusted_mode)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	int pipe = intel_crtc->pipe;
> +	u32 temp, lvds_sync = 0;
> +
> +	temp = I915_READ(LVDS);
> +	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> +	if (pipe == 1) {
> +		temp |= LVDS_PIPEB_SELECT;
> +	} else {
> +		temp &= ~LVDS_PIPEB_SELECT;
> +	}
> +	/* set the corresponsding LVDS_BORDER bit */
> +	temp |= dev_priv->lvds_border_bits;
> +	/* Set the B0-B3 data pairs corresponding to whether we're going to
> +	 * set the DPLLs for dual-channel mode or not.
> +	 */
> +	if (clock->p2 == 7)
> +		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> +	else
> +		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> +
> +	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> +	 * appropriately here, but we need to look more thoroughly into how
> +	 * panels behave in the two modes.
> +	 */
> +	/* set the dithering flag on LVDS as needed */
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		if (dev_priv->lvds_dither)
> +			temp |= LVDS_ENABLE_DITHER;
> +		else
> +			temp &= ~LVDS_ENABLE_DITHER;
> +	}
> +	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> +		lvds_sync |= LVDS_HSYNC_POLARITY;
> +	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> +		lvds_sync |= LVDS_VSYNC_POLARITY;
> +	if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
> +	    != lvds_sync) {
> +		char flags[2] = "-+";
> +		DRM_INFO("Changing LVDS panel from "
> +			 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
> +			 flags[!(temp & LVDS_HSYNC_POLARITY)],
> +			 flags[!(temp & LVDS_VSYNC_POLARITY)],
> +			 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
> +			 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
> +		temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> +		temp |= lvds_sync;
> +	}
> +	I915_WRITE(LVDS, temp);
> +}
> +
>  static void i9xx_update_pll(struct drm_crtc *crtc,
>  			    struct drm_display_mode *mode,
>  			    struct drm_display_mode *adjusted_mode,
> @@ -5305,6 +5361,13 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>  	POSTING_READ(DPLL(pipe));
>  	udelay(150);
>  
> +	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> +	 * This is an exception to the general rule that mode_set doesn't turn
> +	 * things on.
> +	 */
> +	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> +		intel_update_lvds(crtc, clock, adjusted_mode);
> +

Why is this code now at a different place? Especially since it looks like
this will break my dear old i855gm :(

>  	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>  		intel_dp_set_m_n(crtc, mode, adjusted_mode);
>  
> @@ -5414,8 +5477,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	struct intel_encoder *encoder;
>  	const intel_limit_t *limit;
>  	int ret;
> -	u32 temp;
> -	u32 lvds_sync = 0;
>  
>  	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
>  		if (encoder->base.crtc != crtc)
> @@ -5515,58 +5576,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
>  	drm_mode_debug_printmodeline(mode);
>  
> -	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> -	 * This is an exception to the general rule that mode_set doesn't turn
> -	 * things on.
> -	 */
> -	if (is_lvds) {
> -		temp = I915_READ(LVDS);
> -		temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> -		if (pipe == 1) {
> -			temp |= LVDS_PIPEB_SELECT;
> -		} else {
> -			temp &= ~LVDS_PIPEB_SELECT;
> -		}
> -		/* set the corresponsding LVDS_BORDER bit */
> -		temp |= dev_priv->lvds_border_bits;
> -		/* Set the B0-B3 data pairs corresponding to whether we're going to
> -		 * set the DPLLs for dual-channel mode or not.
> -		 */
> -		if (clock.p2 == 7)
> -			temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> -		else
> -			temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> -
> -		/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> -		 * appropriately here, but we need to look more thoroughly into how
> -		 * panels behave in the two modes.
> -		 */
> -		/* set the dithering flag on LVDS as needed */
> -		if (INTEL_INFO(dev)->gen >= 4) {
> -			if (dev_priv->lvds_dither)
> -				temp |= LVDS_ENABLE_DITHER;
> -			else
> -				temp &= ~LVDS_ENABLE_DITHER;
> -		}
> -		if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> -			lvds_sync |= LVDS_HSYNC_POLARITY;
> -		if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> -			lvds_sync |= LVDS_VSYNC_POLARITY;
> -		if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
> -		    != lvds_sync) {
> -			char flags[2] = "-+";
> -			DRM_INFO("Changing LVDS panel from "
> -				 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
> -				 flags[!(temp & LVDS_HSYNC_POLARITY)],
> -				 flags[!(temp & LVDS_VSYNC_POLARITY)],
> -				 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
> -				 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
> -			temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> -			temp |= lvds_sync;
> -		}
> -		I915_WRITE(LVDS, temp);
> -	}
> -
>  	if (HAS_PIPE_CXSR(dev)) {
>  		if (intel_crtc->lowfreq_avail) {
>  			DRM_DEBUG_KMS("enabling CxSR downclocking\n");
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 04/26] drm/i915: ValleyView watermark support

[Ben Widawsky]

On Fri, 23 Mar 2012 10:51:03 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Thu, Mar 22, 2012 at 08:29:30PM -0700, Ben Widawsky wrote:
> > On Thu, Mar 22, 2012 at 02:38:46PM -0700, Jesse Barnes wrote:
> > > Add support for ValleyView watermark handling.  It's like Cantiga
> > > with a few small differences (big FIFO mode and different WM
> > > limits).
> > > 
> > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h      |    9 +++++
> > >  drivers/gpu/drm/i915/intel_display.c |   65
> > > ++++++++++++++++++++++++++++++++++ 2 files changed, 74
> > > insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h index f3609f2..0540099 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -1043,6 +1043,12 @@
> > >  #define RAMCLK_GATE_D		0x6210		/*
> > > CRL only */ #define DEUC
> > > 0x6214          /* CRL only */ 
> > > +#define FW_BLC_SELF_VLV		0x6500
> > > +#define  FW_CSPWRDWNEN		(1<<15)
> > > +#define MI_ARB_VLV		0x6504
> > > +#define  DISP_TRICKLE_FEED_DIS	(1<<2)
> > > +#define CZCLK_CDCLK_FREQ_RATIO_VLV	0x6508
> > > +
> > >  /*
> > >   * Palette regs
> > >   */
> > 
> > Seems like the bottom 3 of these aren't used anywhere.
> 
> I honestly don't mind a few extra #defines, as long as someone has
> bothered to cross check them with bspec (to avoid another MI_WTF). At
> least if they're sounding somewhat relevant.
> -Daniel

Okay, seriously - fix mutt so it actually responds To: me.

The reason I'm only acking most of the patches thus far is I can't find
the register definitions. Jesse said some exist in some doc, and
others were just told to him by the design team. OTOH, anything with my
r-b has been crossed checked with the bspec.

Also, since we got into the discussion RIGHT BEFORE the vlv patches
about how messy our code is, I was being extra diligent about cutting
out stuff we don't use, since the odds of someone doing it after the
fact are slim to none. Furthermore, these defines are so terribly
named, the odds of someone creating another set of defines for the same
purpose are greater than 0.

~Ben

> 
> > 
> > > @@ -2495,6 +2501,7 @@
> > >  #define I915_FIFO_LINE_SIZE	64
> > >  #define I830_FIFO_LINE_SIZE	32
> > >  
> > > +#define VALLEYVIEW_FIFO_SIZE	255
> > >  #define G4X_FIFO_SIZE		127
> > >  #define I965_FIFO_SIZE		512
> > >  #define I945_FIFO_SIZE		127
> > > @@ -2502,6 +2509,7 @@
> > >  #define I855GM_FIFO_SIZE	127 /* In cachelines */
> > >  #define I830_FIFO_SIZE		95
> > >  
> > > +#define VALLEYVIEW_MAX_WM	0xff
> > >  #define G4X_MAX_WM		0x3f
> > >  #define I915_MAX_WM		0x3f
> > >  
> > > @@ -2516,6 +2524,7 @@
> > >  #define PINEVIEW_CURSOR_DFT_WM	0
> > >  #define PINEVIEW_CURSOR_GUARD_WM	5
> > >  
> > > +#define VALLEYVIEW_CURSOR_MAX_WM 64
> > >  #define I965_CURSOR_FIFO	64
> > >  #define I965_CURSOR_MAX_WM	32
> > >  #define I965_CURSOR_DFT_WM	8
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c index de1ba19..daa8853
> > > 100644 --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3606,6 +3606,20 @@ static const struct intel_watermark_params
> > > g4x_cursor_wm_info = { 2,
> > >  	G4X_FIFO_LINE_SIZE,
> > >  };
> > > +static const struct intel_watermark_params valleyview_wm_info = {
> > > +	VALLEYVIEW_FIFO_SIZE,
> > > +	VALLEYVIEW_MAX_WM,
> > > +	VALLEYVIEW_MAX_WM,
> > > +	2,
> > > +	G4X_FIFO_LINE_SIZE,
> > > +};
> > > +static const struct intel_watermark_params
> > > valleyview_cursor_wm_info = {
> > > +	I965_CURSOR_FIFO,
> > > +	VALLEYVIEW_CURSOR_MAX_WM,
> > > +	I965_CURSOR_DFT_WM,
> > > +	2,
> > > +	G4X_FIFO_LINE_SIZE,
> > > +};
> > >  static const struct intel_watermark_params i965_cursor_wm_info =
> > > { I965_CURSOR_FIFO,
> > >  	I965_CURSOR_MAX_WM,
> > > @@ -4130,6 +4144,55 @@ static bool g4x_compute_srwm(struct
> > > drm_device *dev, 
> > >  #define single_plane_enabled(mask) is_power_of_2(mask)
> > >  
> > > +static void valleyview_update_wm(struct drm_device *dev)
> > > +{
> > > +	static const int sr_latency_ns = 12000;
> > > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > > +	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
> > > +	int plane_sr, cursor_sr;
> > > +	unsigned int enabled = 0;
> > > +
> > > +	if (g4x_compute_wm0(dev, 0,
> > > +			    &valleyview_wm_info, latency_ns,
> > > +			    &valleyview_cursor_wm_info,
> > > latency_ns,
> > > +			    &planea_wm, &cursora_wm))
> > > +		enabled |= 1;
> > > +
> > > +	if (g4x_compute_wm0(dev, 1,
> > > +			    &valleyview_wm_info, latency_ns,
> > > +			    &valleyview_cursor_wm_info,
> > > latency_ns,
> > > +			    &planeb_wm, &cursorb_wm))
> > > +		enabled |= 2;
> > > +
> > > +	plane_sr = cursor_sr = 0;
> > > +	if (single_plane_enabled(enabled) &&
> > > +	    g4x_compute_srwm(dev, ffs(enabled) - 1,
> > > +			     sr_latency_ns,
> > > +			     &valleyview_wm_info,
> > > +			     &valleyview_cursor_wm_info,
> > > +			     &plane_sr, &cursor_sr))
> > > +		I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
> > > +	else
> > > +		I915_WRITE(FW_BLC_SELF_VLV,
> > > +			   I915_READ(FW_BLC_SELF_VLV) &
> > > ~FW_CSPWRDWNEN); +
> > > +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d,
> > > cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> > > +		      planea_wm, cursora_wm,
> > > +		      planeb_wm, cursorb_wm,
> > > +		      plane_sr, cursor_sr);
> > > +
> > > +	I915_WRITE(DSPFW1,
> > > +		   (plane_sr << DSPFW_SR_SHIFT) |
> > > +		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> > > +		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > > +		   planea_wm);
> > > +	I915_WRITE(DSPFW2,
> > > +		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
> > > +		   (cursora_wm << DSPFW_CURSORA_SHIFT));
> > > +	I915_WRITE(DSPFW3,
> > > +		   (I915_READ(DSPFW3) | (cursor_sr <<
> > > DSPFW_CURSOR_SR_SHIFT))); +}
> > > +
> > >  static void g4x_update_wm(struct drm_device *dev)
> > >  {
> > >  	static const int sr_latency_ns = 12000;
> > > @@ -8917,6 +8980,8 @@ static void intel_init_display(struct
> > > drm_device *dev) dev_priv->display.write_eld = ironlake_write_eld;
> > >  		} else
> > >  			dev_priv->display.update_wm = NULL;
> > > +	} else if (IS_VALLEYVIEW(dev)) {
> > > +		dev_priv->display.update_wm =
> > > valleyview_update_wm; } else if (IS_PINEVIEW(dev)) {
> > >  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
> > >  					    dev_priv->is_ddr3,
> > 
> > Aside from the extraneous #defines
> > Acked-by: Ben Widawsky <ben@bwidawsk.net>
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

Re: [PATCH 12/26] drm/i915: program drain latency regs on ValleyView

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:54PM -0700, Jesse Barnes wrote:
> From: Gajanan Bhat <gajanan.bhat@intel.com>
> 
> This patch adds support for programming drain latency registers of Pondicherry
> memory arbiter of Valleyview.
> 
> v2: clarify function names (Daniel)
>     fix summary typo (Daniel)
> 
> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
> Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes@intel.com>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   16 +++++++
>  drivers/gpu/drm/i915/intel_display.c |   76 ++++++++++++++++++++++++++++++++++
>  2 files changed, 92 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index be11d39..57e8980 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2605,6 +2605,22 @@
>  #define   DSPFW_HPLL_CURSOR_MASK	(0x3f<<16)
>  #define   DSPFW_HPLL_SR_MASK		(0x1ff)
>  
> +/* drain latency register values*/
> +#define DRAIN_LATENCY_PRECISION_32	32
> +#define DRAIN_LATENCY_PRECISION_16	16
> +#define VLV_DDL1			0x70050
> +#define DDL_CURSORA_PRECISION_32	(1<<31)
> +#define DDL_CURSORA_PRECISION_16	(0<<31)
> +#define DDL_CURSORA_SHIFT		24
> +#define DDL_PLANEA_PRECISION_32		(1<<7)
> +#define DDL_PLANEA_PRECISION_16		(0<<7)
> +#define VLV_DDL2			0x70054
> +#define DDL_CURSORB_PRECISION_32	(1<<31)
> +#define DDL_CURSORB_PRECISION_16	(0<<31)
> +#define DDL_CURSORB_SHIFT		24
> +#define DDL_PLANEB_PRECISION_32		(1<<7)
> +#define DDL_PLANEB_PRECISION_16		(0<<7)
> +
>  /* FIFO watermark sizes etc */
>  #define G4X_FIFO_LINE_SIZE	64
>  #define I915_FIFO_LINE_SIZE	64
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6bed629..4b5905c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4337,6 +4337,80 @@ static bool g4x_compute_srwm(struct drm_device *dev,
>  			      display, cursor);
>  }
>  
> +static int vlv_compute_drain_latency(struct drm_device *dev,
> +				     int plane,
> +				     int *plane_prec_mult,
> +				     int *plane_dl,
> +				     int *cursor_prec_mult,
> +				     int *cursor_dl)
> +{
> +	struct drm_crtc *crtc;
> +	int clock, pixel_size;
> +	int entries;
> +
> +	crtc = intel_get_crtc_for_plane(dev, plane);
> +	if (crtc->fb == NULL || !crtc->enabled)
> +		return false;


> +
> +	clock = crtc->mode.clock;	/* VESA DOT Clock */
> +	pixel_size = crtc->fb->bits_per_pixel / 8;	/* BPP */
> +
> +	entries = (clock / 1000) * pixel_size;
> +	*plane_prec_mult = (entries > 256) ?
> +		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +	*plane_dl = (64 * *plane_prec_mult * 4) / ((clock / 1000) * pixel_size);
> +
> +	entries = (clock / 1000) * 4;	/* BPP is always 4 for cursor */
> +	*cursor_prec_mult = (entries > 256) ?
> +		DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> +	*cursor_dl = (64 * *cursor_prec_mult * 4) / ((clock / 1000) * 4);

Can we add some parentheses around *cursor_prec_mult here (two places
above)?

> +
> +	return true;
> +}

It doesn't produce a warning for me, but 0, and 1 are more typically
returned when using ints. I'd just change the return type to bool.

> +
> +/*
> + * Update drain latency registers of memory arbiter
> + *
> + * Valleyview SoC has a new memory arbiter and needs drain latency registers
> + * to be programmed. Each plane has a drain latency multiplier and a drain
> + * latency value.
> + */

Better than this comment would have been how the arbiter's drain latency
functions.

> +
> +static void vlv_update_drain_latency(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int planea_prec, planea_dl, planeb_prec, planeb_dl;
> +	int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
> +	int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
> +							either 16 or 32 */
> +
> +	/* For plane A, Cursor A */
> +	if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
> +				      &cursor_prec_mult, &cursora_dl)) {
> +		cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> +		planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> +
> +		I915_WRITE(VLV_DDL1, cursora_prec |
> +				(cursora_dl << DDL_CURSORA_SHIFT) |
> +				planea_prec | planea_dl);
> +	}
> +
> +	/* For plane B, Cursor B */
> +	if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
> +				      &cursor_prec_mult, &cursorb_dl)) {
> +		cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> +		planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> +			DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> +
> +		I915_WRITE(VLV_DDL2, cursorb_prec |
> +				(cursorb_dl << DDL_CURSORB_SHIFT) |
> +				planeb_prec | planeb_dl);
> +	}
> +}
> +
>  #define single_plane_enabled(mask) is_power_of_2(mask)
>  
>  static void valleyview_update_wm(struct drm_device *dev)
> @@ -4347,6 +4421,8 @@ static void valleyview_update_wm(struct drm_device *dev)
>  	int plane_sr, cursor_sr;
>  	unsigned int enabled = 0;
>  
> +	vlv_update_drain_latency(dev);
> +
>  	if (g4x_compute_wm0(dev, 0,
>  			    &valleyview_wm_info, latency_ns,
>  			    &valleyview_cursor_wm_info, latency_ns,


Couldn't find the registers in docs, so only
Acked-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 15/26] agp/intel: map more registers for use by the GTT code

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:57PM -0700, Jesse Barnes wrote:
> We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
> register for doing so is above the range we normally map.  Map the whole
> register space to make sure we can get it.
> 
> v2: only map the larger space on gen7+ (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/char/agp/intel-gtt.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 5cf47ac..269cb02 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
>  static int i9xx_setup(void)
>  {
>  	u32 reg_addr;
> +	int size = KB(512);
>  
>  	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
>  
>  	reg_addr &= 0xfff80000;
>  
> -	intel_private.registers = ioremap(reg_addr, 128 * 4096);
> +	if (INTEL_GTT_GEN >= 7)
> +		size = MB(2);
> +
> +	intel_private.registers = ioremap(reg_addr, size);
>  	if (!intel_private.registers)
>  		return -ENOMEM;
>  

Acked-by: Ben Widawsky <ben@bwidawsk.net>

Does this need to go in -fixes since it seems like a "fix" for IVB?

Also, just looking at the code, is offset still correct? Gen5, and Gen6
have 2MB, Gen4, and default have 512kb.

Re: [PATCH 16/26] agp/intel: add ValleyView AGP driver

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:38:58PM -0700, Jesse Barnes wrote:
> But don't bind the PCI ID yet.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/char/agp/intel-agp.c |    1 +
>  drivers/char/agp/intel-agp.h |    3 +++
>  drivers/char/agp/intel-gtt.c |   23 +++++++++++++++++++++++
>  3 files changed, 27 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
> index 962e75d..74c2d92 100644
> --- a/drivers/char/agp/intel-agp.c
> +++ b/drivers/char/agp/intel-agp.c
> @@ -907,6 +907,7 @@ static struct pci_device_id agp_intel_pci_table[] = {
>  	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
>  	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
>  	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
> +	ID(PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB),
>  	{ }
>  };
>  
> diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
> index 5da67f1..41d9ee1 100644
> --- a/drivers/char/agp/intel-agp.h
> +++ b/drivers/char/agp/intel-agp.h
> @@ -96,6 +96,7 @@
>  #define G4x_GMCH_SIZE_VT_2M	(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
>  
>  #define GFX_FLSH_CNTL		0x2170 /* 915+ */
> +#define GFX_FLSH_CNTL_VLV	0x101008
>  
>  #define I810_DRAM_CTL		0x3000
>  #define I810_DRAM_ROW_0		0x00000001
> @@ -234,6 +235,8 @@
>  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166
>  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */
>  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A
> +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB		0x0F00 /* VLV1 */
> +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG		0x0F30
>  
>  int intel_gmch_probe(struct pci_dev *pdev,
>  			       struct agp_bridge_data *bridge);
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 269cb02..ccc0045 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1179,6 +1179,20 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
>  	writel(addr | pte_flags, intel_private.gtt + entry);
>  }
>  
> +static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
> +				   unsigned int flags)
> +{
> +	u32 pte_flags;
> +
> +	pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
> +
> +	/* gen6 has bit11-4 for physical addr bit39-32 */
The comment about gen6 should probably go.
> +	addr |= (addr >> 28) & 0xff0;
> +	writel(addr | pte_flags, intel_private.gtt + entry);
> +
> +	writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
I think a comment here is very well deserved.

> +}
> +
>  static void gen6_cleanup(void)
>  {
>  }
> @@ -1359,6 +1373,15 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
>  	.check_flags = gen6_check_flags,
>  	.chipset_flush = i9xx_chipset_flush,
>  };
> +static const struct intel_gtt_driver valleyview_gtt_driver = {
> +	.gen = 7,
> +	.setup = i9xx_setup,
> +	.cleanup = gen6_cleanup,
> +	.write_entry = valleyview_write_entry,
> +	.dma_mask_size = 40,
> +	.check_flags = gen6_check_flags,
> +	.chipset_flush = i9xx_chipset_flush,
> +};

I'm pretty torn about whether or not we actually want to use .gen=7
(both here and in the other patch). But if it's what you think is best,
let's do it.

do you really want gen6_check_flags? or i830_check_flags?
FWIW, I have no clue why we even need check_flags()

>  
>  /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
>   * driver and gmch_driver must be non-null, and find_gmch will determine

Assuming you consider the above:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 15/26] agp/intel: map more registers for use by the GTT code

[Daniel Vetter]

On Sun, Mar 25, 2012 at 07:05:40PM -0700, Ben Widawsky wrote:
> On Thu, Mar 22, 2012 at 02:38:57PM -0700, Jesse Barnes wrote:
> > We need to flush the Gunit TLB when we update GTT PTEs on VLV, but the
> > register for doing so is above the range we normally map.  Map the whole
> > register space to make sure we can get it.
> > 
> > v2: only map the larger space on gen7+ (Daniel)
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/char/agp/intel-gtt.c |    6 +++++-
> >  1 files changed, 5 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> > index 5cf47ac..269cb02 100644
> > --- a/drivers/char/agp/intel-gtt.c
> > +++ b/drivers/char/agp/intel-gtt.c
> > @@ -1206,12 +1206,16 @@ static inline int needs_idle_maps(void)
> >  static int i9xx_setup(void)
> >  {
> >  	u32 reg_addr;
> > +	int size = KB(512);
> >  
> >  	pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
> >  
> >  	reg_addr &= 0xfff80000;
> >  
> > -	intel_private.registers = ioremap(reg_addr, 128 * 4096);
> > +	if (INTEL_GTT_GEN >= 7)
> > +		size = MB(2);
> > +
> > +	intel_private.registers = ioremap(reg_addr, size);
> >  	if (!intel_private.registers)
> >  		return -ENOMEM;
> >  
> 
> Acked-by: Ben Widawsky <ben@bwidawsk.net>
> 
> Does this need to go in -fixes since it seems like a "fix" for IVB?

Afaics no, because only on vlv we need to frob one of thes high-up
registers in intel-gtt. In drm/i915 we already map the entire mmio space
(by checking the bar size, iirc).

> Also, just looking at the code, is offset still correct? Gen5, and Gen6
> have 2MB, Gen4, and default have 512kb.

Same reason as why this is not a fix, we don't need more. Imo the right
thing to do is to reap intel-gtt support for gen6+ and move it completely
into drm/i915. This won't break any used abi because we never supported
ums on these in upstream.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 16/26] agp/intel: add ValleyView AGP driver

[Daniel Vetter]

On Sun, Mar 25, 2012 at 07:16:31PM -0700, Ben Widawsky wrote:
> I'm pretty torn about whether or not we actually want to use .gen=7
> (both here and in the other patch). But if it's what you think is best,
> let's do it.

gen here is only used in the intel-gtt code. I expect it's prette
irrelevant (haven't checked though).

> do you really want gen6_check_flags? or i830_check_flags?
> FWIW, I have no clue why we even need check_flags()

Backwards compat for tha fake agp interface. We don't use it and hence
it's totally irrelevant. We really should reap all this crap for gen6+ at
least.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 16/26] agp/intel: add ValleyView AGP driver

[Ben Widawsky]

On Mon, Mar 26, 2012 at 09:08:28AM +0200, Daniel Vetter wrote:
> On Sun, Mar 25, 2012 at 07:16:31PM -0700, Ben Widawsky wrote:
> > I'm pretty torn about whether or not we actually want to use .gen=7
> > (both here and in the other patch). But if it's what you think is best,
> > let's do it.
> 
> gen here is only used in the intel-gtt code. I expect it's prette
> irrelevant (haven't checked though).
> 
> > do you really want gen6_check_flags? or i830_check_flags?
> > FWIW, I have no clue why we even need check_flags()
> 
> Backwards compat for tha fake agp interface. We don't use it and hence
> it's totally irrelevant. We really should reap all this crap for gen6+ at
> least.

It seemed like we gained nothing by doing this, when I looked
beforehand.

> -Daniel

Re: [PATCH 19/26] drm/i915: add ValleyView specific force wake get/put functions

[Ben Widawsky]

On Fri, Mar 23, 2012 at 02:20:09PM -0300, Eugeni Dodonov wrote:
> On Thu, Mar 22, 2012 at 18:39, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:
> 
> > ValleyView handles force wake differently than previous chipsets, so add
> > a couple of new functions for it.  But leave it disabled by default
> > until we test it (need a chip with the Punit enabled first).
> >
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  #define NEEDS_FORCE_WAKE(dev_priv, reg) \
> >        (((dev_priv)->info->gen >= 6) && \
> >         ((reg) < 0x40000) &&            \
> > -        ((reg) != FORCEWAKE))
> > +        ((reg) != FORCEWAKE)) && \
> > +       (!IS_VALLEYVIEW((dev_priv)->dev))
> >
> 
> In the spirit of bikeshedding, I think that NEEDS_FORCE_WAKE is becoming a
> bit scary this way. But I don't know if it makes sense to move the gen and
> dev check into a feature flag, to avoid similar issues with possible future
> generations of chips..

Agreed. I think the better approach is to check if the fwake function
pointers are !NULL also (since it will apply to other chipsets
potentially as well).

> 
> -- 
> Eugeni Dodonov
> <http://eugeni.dodonov.net/>

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 20/26] drm/i915: ValleyView has limited cacheability

[Ben Widawsky]

On Thu, Mar 22, 2012 at 02:39:02PM -0700, Jesse Barnes wrote:
> The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> it does writes, so we can't use the cache bits the same way.

I found this commit message to be confusing. Is it simply saying CPU
writes are snooped by the GT, but GT writes are not snooped bv the CPU?

> 
> So map the status and pipe control pages as uncached on ValleyView, and
> only set the pages to cached if we're on a supported platform.

I'd like to see in the commit message why the pipe control page needs to
be uncached. The only workarounds on the top of my head don't care about
the coherency.

> 
> v2: add clarifying comments and don't use the LLC flag for ioremap vs
>     kmap (Daniel)
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |   45 ++++++++++++++++++++++++++-----
>  1 files changed, 38 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ca3972f..9b26c9d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
>  {
>  	struct pipe_control *pc;
>  	struct drm_i915_gem_object *obj;
> +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> +	struct drm_device *dev;
>  	int ret;
>  
>  	if (ring->private)
> @@ -335,14 +337,24 @@ init_pipe_control(struct intel_ring_buffer *ring)
>  		goto err;
>  	}
>  
> -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> +	i915_gem_object_set_cache_level(obj, cache_level);
>  
>  	ret = i915_gem_object_pin(obj, 4096, true);
>  	if (ret)
>  		goto err_unref;
> -
> +	dev = obj->base.dev;
>  	pc->gtt_offset = obj->gtt_offset;
> -	pc->cpu_page =  kmap(obj->pages[0]);
> +	/*
> +	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
> +	 * not GPU writes followed by CPU reads.  So we need to map status
> +	 * pages as uncached.
> +	 */
> +	if (IS_VALLEYVIEW(dev))
> +		pc->cpu_page = ioremap(dev->agp->base +
> +				       obj->gtt_offset,
> +				       PAGE_SIZE);

Bikeshed: I think ioremap_nocache is a bit better to use. It's more
self-commenting.

> +	else
> +		pc->cpu_page =  kmap(obj->pages[0]);
>  	if (pc->cpu_page == NULL)
>  		goto err_unpin;
>  
> @@ -364,12 +376,17 @@ cleanup_pipe_control(struct intel_ring_buffer *ring)
>  {
>  	struct pipe_control *pc = ring->private;
>  	struct drm_i915_gem_object *obj;
> +	struct drm_device *dev;
>  
>  	if (!ring->private)
>  		return;
>  
>  	obj = pc->obj;
> -	kunmap(obj->pages[0]);
> +	dev = obj->base.dev;
> +	if (IS_VALLEYVIEW(dev))
> +		iounmap(pc->cpu_page);
> +	else
> +		kunmap(obj->pages[0]);
>  	i915_gem_object_unpin(obj);
>  	drm_gem_object_unreference(&obj->base);
>  
> @@ -929,7 +946,10 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
>  	if (obj == NULL)
>  		return;
>  
> -	kunmap(obj->pages[0]);
> +	if (IS_VALLEYVIEW(dev_priv->dev))
> +		iounmap(ring->status_page.page_addr);
> +	else
> +		kunmap(obj->pages[0]);
>  	i915_gem_object_unpin(obj);
>  	drm_gem_object_unreference(&obj->base);
>  	ring->status_page.obj = NULL;
> @@ -942,6 +962,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  	struct drm_device *dev = ring->dev;
>  	drm_i915_private_t *dev_priv = dev->dev_private;
>  	struct drm_i915_gem_object *obj;
> +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
>  	int ret;
>  
>  	obj = i915_gem_alloc_object(dev, 4096);
> @@ -951,7 +972,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  		goto err;
>  	}
>  
> -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> +	i915_gem_object_set_cache_level(obj, cache_level);
>  
>  	ret = i915_gem_object_pin(obj, 4096, true);
>  	if (ret != 0) {
> @@ -959,7 +980,17 @@ static int init_status_page(struct intel_ring_buffer *ring)
>  	}
>  
>  	ring->status_page.gfx_addr = obj->gtt_offset;
> -	ring->status_page.page_addr = kmap(obj->pages[0]);
> +	/*
> +	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
> +	 * not GPU writes followed by CPU reads.  So we need to map status
> +	 * pages as uncached.
> +	 */
> +	if (IS_VALLEYVIEW(dev))
> +		ring->status_page.page_addr = ioremap(dev->agp->base +
> +						      obj->gtt_offset,
> +						      PAGE_SIZE);

Same bikeshed as above.

> +	else
> +		ring->status_page.page_addr = kmap(obj->pages[0]);
>  	if (ring->status_page.page_addr == NULL) {
>  		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
>  		goto err_unpin;

Re: [PATCH 20/26] drm/i915: ValleyView has limited cacheability

[Daniel Vetter]

On Mon, Mar 26, 2012 at 11:34:21AM -0700, Ben Widawsky wrote:
> On Thu, Mar 22, 2012 at 02:39:02PM -0700, Jesse Barnes wrote:
> > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> > it does writes, so we can't use the cache bits the same way.
> 
> I found this commit message to be confusing. Is it simply saying CPU
> writes are snooped by the GT, but GT writes are not snooped bv the CPU?
> 
> > 
> > So map the status and pipe control pages as uncached on ValleyView, and
> > only set the pages to cached if we're on a supported platform.
> 
> I'd like to see in the commit message why the pipe control page needs to
> be uncached. The only workarounds on the top of my head don't care about
> the coherency.

Afaik we've cleared this up in our mtg yesterday:
- Full coherent gtt mappings work, they simply moved the bit around (we
  need to set bit2 instead of bit1 like on snb/ivb).
- It sounds like all the gpu functions can handle coherent memory, like
  on snb/ivb. But because there's no shared cache between the gpu and the
  cpu you don't gain anything, but only lose due to the required snoop
  traffic.
- Because there's no last level cache it also means that when the gpu does
  a write and snoops the cpu cache, it essentially means the cpu
  completely drops it's cacheline and has to go back to main memory
  (instead of l3 like it does on llc platforms). Gpu reads snoop the cpu
  cache corectly.

I hope this clears up the confusion around coherency on vlv. Let Jesse
only needs to check with a real piece of silicon whether that's true ;-)
-Daniel

> 
> > 
> > v2: add clarifying comments and don't use the LLC flag for ioremap vs
> >     kmap (Daniel)
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c |   45 ++++++++++++++++++++++++++-----
> >  1 files changed, 38 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index ca3972f..9b26c9d 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -319,6 +319,8 @@ init_pipe_control(struct intel_ring_buffer *ring)
> >  {
> >  	struct pipe_control *pc;
> >  	struct drm_i915_gem_object *obj;
> > +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> > +	struct drm_device *dev;
> >  	int ret;
> >  
> >  	if (ring->private)
> > @@ -335,14 +337,24 @@ init_pipe_control(struct intel_ring_buffer *ring)
> >  		goto err;
> >  	}
> >  
> > -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> > +	i915_gem_object_set_cache_level(obj, cache_level);
> >  
> >  	ret = i915_gem_object_pin(obj, 4096, true);
> >  	if (ret)
> >  		goto err_unref;
> > -
> > +	dev = obj->base.dev;
> >  	pc->gtt_offset = obj->gtt_offset;
> > -	pc->cpu_page =  kmap(obj->pages[0]);
> > +	/*
> > +	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
> > +	 * not GPU writes followed by CPU reads.  So we need to map status
> > +	 * pages as uncached.
> > +	 */
> > +	if (IS_VALLEYVIEW(dev))
> > +		pc->cpu_page = ioremap(dev->agp->base +
> > +				       obj->gtt_offset,
> > +				       PAGE_SIZE);
> 
> Bikeshed: I think ioremap_nocache is a bit better to use. It's more
> self-commenting.
> 
> > +	else
> > +		pc->cpu_page =  kmap(obj->pages[0]);
> >  	if (pc->cpu_page == NULL)
> >  		goto err_unpin;
> >  
> > @@ -364,12 +376,17 @@ cleanup_pipe_control(struct intel_ring_buffer *ring)
> >  {
> >  	struct pipe_control *pc = ring->private;
> >  	struct drm_i915_gem_object *obj;
> > +	struct drm_device *dev;
> >  
> >  	if (!ring->private)
> >  		return;
> >  
> >  	obj = pc->obj;
> > -	kunmap(obj->pages[0]);
> > +	dev = obj->base.dev;
> > +	if (IS_VALLEYVIEW(dev))
> > +		iounmap(pc->cpu_page);
> > +	else
> > +		kunmap(obj->pages[0]);
> >  	i915_gem_object_unpin(obj);
> >  	drm_gem_object_unreference(&obj->base);
> >  
> > @@ -929,7 +946,10 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
> >  	if (obj == NULL)
> >  		return;
> >  
> > -	kunmap(obj->pages[0]);
> > +	if (IS_VALLEYVIEW(dev_priv->dev))
> > +		iounmap(ring->status_page.page_addr);
> > +	else
> > +		kunmap(obj->pages[0]);
> >  	i915_gem_object_unpin(obj);
> >  	drm_gem_object_unreference(&obj->base);
> >  	ring->status_page.obj = NULL;
> > @@ -942,6 +962,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
> >  	struct drm_device *dev = ring->dev;
> >  	drm_i915_private_t *dev_priv = dev->dev_private;
> >  	struct drm_i915_gem_object *obj;
> > +	int cache_level = HAS_LLC(ring->dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
> >  	int ret;
> >  
> >  	obj = i915_gem_alloc_object(dev, 4096);
> > @@ -951,7 +972,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
> >  		goto err;
> >  	}
> >  
> > -	i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
> > +	i915_gem_object_set_cache_level(obj, cache_level);
> >  
> >  	ret = i915_gem_object_pin(obj, 4096, true);
> >  	if (ret != 0) {
> > @@ -959,7 +980,17 @@ static int init_status_page(struct intel_ring_buffer *ring)
> >  	}
> >  
> >  	ring->status_page.gfx_addr = obj->gtt_offset;
> > -	ring->status_page.page_addr = kmap(obj->pages[0]);
> > +	/*
> > +	 * On ValleyView, only CPU writes followed by GPU reads are snooped,
> > +	 * not GPU writes followed by CPU reads.  So we need to map status
> > +	 * pages as uncached.
> > +	 */
> > +	if (IS_VALLEYVIEW(dev))
> > +		ring->status_page.page_addr = ioremap(dev->agp->base +
> > +						      obj->gtt_offset,
> > +						      PAGE_SIZE);
> 
> Same bikeshed as above.
> 
> > +	else
> > +		ring->status_page.page_addr = kmap(obj->pages[0]);
> >  	if (ring->status_page.page_addr == NULL) {
> >  		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
> >  		goto err_unpin;
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 20/26] drm/i915: ValleyView has limited cacheability

[Jesse Barnes]

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On Mon, 26 Mar 2012 20:49:45 +0200
Daniel Vetter <daniel@ffwll.ch> wrote:

> On Mon, Mar 26, 2012 at 11:34:21AM -0700, Ben Widawsky wrote:
> > On Thu, Mar 22, 2012 at 02:39:02PM -0700, Jesse Barnes wrote:
> > > The GT can snoop CPU writes, but doesn't snoop into the CPU cache when
> > > it does writes, so we can't use the cache bits the same way.
> > 
> > I found this commit message to be confusing. Is it simply saying CPU
> > writes are snooped by the GT, but GT writes are not snooped bv the CPU?
> > 
> > > 
> > > So map the status and pipe control pages as uncached on ValleyView, and
> > > only set the pages to cached if we're on a supported platform.
> > 
> > I'd like to see in the commit message why the pipe control page needs to
> > be uncached. The only workarounds on the top of my head don't care about
> > the coherency.
> 
> Afaik we've cleared this up in our mtg yesterday:
> - Full coherent gtt mappings work, they simply moved the bit around (we
>   need to set bit2 instead of bit1 like on snb/ivb).
> - It sounds like all the gpu functions can handle coherent memory, like
>   on snb/ivb. But because there's no shared cache between the gpu and the
>   cpu you don't gain anything, but only lose due to the required snoop
>   traffic.
> - Because there's no last level cache it also means that when the gpu does
>   a write and snoops the cpu cache, it essentially means the cpu
>   completely drops it's cacheline and has to go back to main memory
>   (instead of l3 like it does on llc platforms). Gpu reads snoop the cpu
>   cache corectly.
> 
> I hope this clears up the confusion around coherency on vlv. Let Jesse
> only needs to check with a real piece of silicon whether that's true ;-)
> -Daniel

Right, this patch is bogus; VLV should be just as capable here, so we
can drop this one and I'll verify the cache bits.

-- 
Jesse Barnes, Intel Open Source Technology Center

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