[PATCH 0/3] Detect UDIV/SDIV support from ISAR0

[PATCH 0/3] Detect UDIV/SDIV support from ISAR0

[Stephen Boyd]

While attempting to upstream a patch to add the IDIV hwcap for
Krait processors, Will suggested we move the code to read the
ISAR0 register. This patchset does that and also works around
the early Krait CPU designs that don't follow the latest ARM ARM
for the ISAR0 register.

Stephen Boyd (3):
  ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
  ARM: Detect support for SDIV/UDIV from ISAR0 register
  ARM: Work around faulty ISAR0 register in some Krait CPUs

 arch/arm/kernel/setup.c | 30 +++++++++++++++++++++++++++++-
 arch/arm/mm/proc-v7.S   |  4 ++--
 2 files changed, 31 insertions(+), 3 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 0/3] Detect UDIV/SDIV support from ISAR0

[Stephen Boyd]

While attempting to upstream a patch to add the IDIV hwcap for
Krait processors, Will suggested we move the code to read the
ISAR0 register. This patchset does that and also works around
the early Krait CPU designs that don't follow the latest ARM ARM
for the ISAR0 register.

Stephen Boyd (3):
  ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n
  ARM: Detect support for SDIV/UDIV from ISAR0 register
  ARM: Work around faulty ISAR0 register in some Krait CPUs

 arch/arm/kernel/setup.c | 30 +++++++++++++++++++++++++++++-
 arch/arm/mm/proc-v7.S   |  4 ++--
 2 files changed, 31 insertions(+), 3 deletions(-)

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n

[Stephen Boyd]

Don't advertise support for the SDIV/UDIV thumb instructions if
the kernel is not compiled with support for thumb userspace. This
is in line with how we remove the THUMB hwcap in these
configurations.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2..e2c8bbf 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -484,7 +484,7 @@ static void __init setup_processor(void)
 		 list->elf_name, ENDIANNESS);
 	elf_hwcap = list->elf_hwcap;
 #ifndef CONFIG_ARM_THUMB
-	elf_hwcap &= ~HWCAP_THUMB;
+	elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
 
 	feat_v6_fixup();
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n

[Stephen Boyd]

Don't advertise support for the SDIV/UDIV thumb instructions if
the kernel is not compiled with support for thumb userspace. This
is in line with how we remove the THUMB hwcap in these
configurations.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2..e2c8bbf 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -484,7 +484,7 @@ static void __init setup_processor(void)
 		 list->elf_name, ENDIANNESS);
 	elf_hwcap = list->elf_hwcap;
 #ifndef CONFIG_ARM_THUMB
-	elf_hwcap &= ~HWCAP_THUMB;
+	elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
 
 	feat_v6_fixup();
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n

[Stephen Boyd]

Don't advertise support for the SDIV/UDIV thumb instructions if
the kernel is not compiled with support for thumb userspace. This
is in line with how we remove the THUMB hwcap in these
configurations.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3f6cbb2..e2c8bbf 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -484,7 +484,7 @@ static void __init setup_processor(void)
 		 list->elf_name, ENDIANNESS);
 	elf_hwcap = list->elf_hwcap;
 #ifndef CONFIG_ARM_THUMB
-	elf_hwcap &= ~HWCAP_THUMB;
+	elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
 
 	feat_v6_fixup();
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Stephen Boyd]

The ISAR0 register indicates support for the SDIV and UDIV
instructions in both the Thumb and ARM instruction set. Read the
register to detect the supported instructions and update the
elf_hwcap mask as appropriate. This is better than adding more
and more cpuid checks in proc-v7.S for each new cpu variant that
supports these instructions.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
 arch/arm/mm/proc-v7.S   |  4 ++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index e2c8bbf..bd27a70 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
 	printk("%s", buf);
 }
 
+static void __init idiv_setup(void)
+{
+	unsigned int divide_instrs;
+
+	if (cpu_architecture() < CPU_ARCH_ARMv7)
+		return;
+
+	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
+
+	switch (divide_instrs) {
+	case 2:
+		elf_hwcap |= HWCAP_IDIVA;
+	case 1:
+		elf_hwcap |= HWCAP_IDIVT;
+	}
+}
+
 static void __init feat_v6_fixup(void)
 {
 	int id = read_cpuid_id();
@@ -483,6 +500,9 @@ static void __init setup_processor(void)
 	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
 		 list->elf_name, ENDIANNESS);
 	elf_hwcap = list->elf_hwcap;
+
+	idiv_setup();
+
 #ifndef CONFIG_ARM_THUMB
 	elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015..bcd3d48 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
 __v7_ca7mp_proc_info:
 	.long	0x410fc070
 	.long	0xff0ffff0
-	__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
+	__v7_proc __v7_ca7mp_setup
 	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
 	/*
@@ -430,7 +430,7 @@ __v7_ca7mp_proc_info:
 __v7_ca15mp_proc_info:
 	.long	0x410fc0f0
 	.long	0xff0ffff0
-	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
+	__v7_proc __v7_ca15mp_setup
 	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
 	/*
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Stephen Boyd]

The ISAR0 register indicates support for the SDIV and UDIV
instructions in both the Thumb and ARM instruction set. Read the
register to detect the supported instructions and update the
elf_hwcap mask as appropriate. This is better than adding more
and more cpuid checks in proc-v7.S for each new cpu variant that
supports these instructions.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
 arch/arm/mm/proc-v7.S   |  4 ++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index e2c8bbf..bd27a70 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
 	printk("%s", buf);
 }
 
+static void __init idiv_setup(void)
+{
+	unsigned int divide_instrs;
+
+	if (cpu_architecture() < CPU_ARCH_ARMv7)
+		return;
+
+	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
+
+	switch (divide_instrs) {
+	case 2:
+		elf_hwcap |= HWCAP_IDIVA;
+	case 1:
+		elf_hwcap |= HWCAP_IDIVT;
+	}
+}
+
 static void __init feat_v6_fixup(void)
 {
 	int id = read_cpuid_id();
@@ -483,6 +500,9 @@ static void __init setup_processor(void)
 	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
 		 list->elf_name, ENDIANNESS);
 	elf_hwcap = list->elf_hwcap;
+
+	idiv_setup();
+
 #ifndef CONFIG_ARM_THUMB
 	elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 3a3c015..bcd3d48 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
 __v7_ca7mp_proc_info:
 	.long	0x410fc070
 	.long	0xff0ffff0
-	__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
+	__v7_proc __v7_ca7mp_setup
 	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
 	/*
@@ -430,7 +430,7 @@ __v7_ca7mp_proc_info:
 __v7_ca15mp_proc_info:
 	.long	0x410fc0f0
 	.long	0xff0ffff0
-	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
+	__v7_proc __v7_ca15mp_setup
 	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 
 	/*
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Stephen Boyd]

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the detection code
to indicate support in both modes.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bd27a70..34ec24e 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -362,6 +362,14 @@ static void __init idiv_setup(void)
 
 	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
 
+	/*
+	 * Some Krait processors don't indicate support for SDIV and UDIV
+	 * instructions in the ARM instruction set, even though they actually
+	 * do support them.
+	 */
+	if ((read_cpuid_id() & 0xff0ffc00) == 0x510f0400)
+		divide_instrs = 2;
+
 	switch (divide_instrs) {
 	case 2:
 		elf_hwcap |= HWCAP_IDIVA;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Stephen Boyd]

Some early versions of the Krait CPU design incorrectly indicate
that they only support the UDIV and SDIV instructions in Thumb
mode when they actually support them in ARM and Thumb mode. It
seems that these CPUs follow the DDI0406B ARM ARM which has two
possible values for the divide instructions field, instead of the
DDI0406C document which has three possible values.

Work around this problem by checking the MIDR against Krait CPUs
with this faulty ISAR0 register and force the detection code
to indicate support in both modes.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 arch/arm/kernel/setup.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bd27a70..34ec24e 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -362,6 +362,14 @@ static void __init idiv_setup(void)
 
 	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
 
+	/*
+	 * Some Krait processors don't indicate support for SDIV and UDIV
+	 * instructions in the ARM instruction set, even though they actually
+	 * do support them.
+	 */
+	if ((read_cpuid_id() & 0xff0ffc00) == 0x510f0400)
+		divide_instrs = 2;
+
 	switch (divide_instrs) {
 	case 2:
 		elf_hwcap |= HWCAP_IDIVA;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation

Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
> Some early versions of the Krait CPU design incorrectly indicate
> that they only support the UDIV and SDIV instructions in Thumb
> mode when they actually support them in ARM and Thumb mode. It
> seems that these CPUs follow the DDI0406B ARM ARM which has two
> possible values for the divide instructions field, instead of the
> DDI0406C document which has three possible values.
> 
> Work around this problem by checking the MIDR against Krait CPUs
> with this faulty ISAR0 register and force the detection code
> to indicate support in both modes.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/kernel/setup.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

After all this, you might as well just pass the relevant HWCAPs for your
krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
code.

Thanks for adding the detection code though -- we can use that for A7/A15.

Will

Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
> Some early versions of the Krait CPU design incorrectly indicate
> that they only support the UDIV and SDIV instructions in Thumb
> mode when they actually support them in ARM and Thumb mode. It
> seems that these CPUs follow the DDI0406B ARM ARM which has two
> possible values for the divide instructions field, instead of the
> DDI0406C document which has three possible values.
> 
> Work around this problem by checking the MIDR against Krait CPUs
> with this faulty ISAR0 register and force the detection code
> to indicate support in both modes.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/kernel/setup.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

After all this, you might as well just pass the relevant HWCAPs for your
krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
code.

Thanks for adding the detection code though -- we can use that for A7/A15.

Will

[PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
> Some early versions of the Krait CPU design incorrectly indicate
> that they only support the UDIV and SDIV instructions in Thumb
> mode when they actually support them in ARM and Thumb mode. It
> seems that these CPUs follow the DDI0406B ARM ARM which has two
> possible values for the divide instructions field, instead of the
> DDI0406C document which has three possible values.
> 
> Work around this problem by checking the MIDR against Krait CPUs
> with this faulty ISAR0 register and force the detection code
> to indicate support in both modes.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/kernel/setup.c | 8 ++++++++
>  1 file changed, 8 insertions(+)

After all this, you might as well just pass the relevant HWCAPs for your
krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
code.

Thanks for adding the detection code though -- we can use that for A7/A15.

Will

Re: [PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n

[Will Deacon]

On Wed, Mar 13, 2013 at 01:31:59AM +0000, Stephen Boyd wrote:
> Don't advertise support for the SDIV/UDIV thumb instructions if
> the kernel is not compiled with support for thumb userspace. This
> is in line with how we remove the THUMB hwcap in these
> configurations.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Will Deacon <will.deacon@arm.com>

Will

Re: [PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n

[Will Deacon]

On Wed, Mar 13, 2013 at 01:31:59AM +0000, Stephen Boyd wrote:
> Don't advertise support for the SDIV/UDIV thumb instructions if
> the kernel is not compiled with support for thumb userspace. This
> is in line with how we remove the THUMB hwcap in these
> configurations.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Will Deacon <will.deacon@arm.com>

Will

[PATCH 1/3] ARM: Clear IDIVT hwcap if CONFIG_ARM_THUMB=n

[Will Deacon]

On Wed, Mar 13, 2013 at 01:31:59AM +0000, Stephen Boyd wrote:
> Don't advertise support for the SDIV/UDIV thumb instructions if
> the kernel is not compiled with support for thumb userspace. This
> is in line with how we remove the THUMB hwcap in these
> configurations.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Acked-by: Will Deacon <will.deacon@arm.com>

Will

Re: [PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Will Deacon]

On Wed, Mar 13, 2013 at 01:32:00AM +0000, Stephen Boyd wrote:
> The ISAR0 register indicates support for the SDIV and UDIV
> instructions in both the Thumb and ARM instruction set. Read the
> register to detect the supported instructions and update the
> elf_hwcap mask as appropriate. This is better than adding more
> and more cpuid checks in proc-v7.S for each new cpu variant that
> supports these instructions.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>  arch/arm/mm/proc-v7.S   |  4 ++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index e2c8bbf..bd27a70 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>  	printk("%s", buf);
>  }
>  
> +static void __init idiv_setup(void)
> +{
> +	unsigned int divide_instrs;
> +
> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
> +		return;
> +
> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
> +
> +	switch (divide_instrs) {
> +	case 2:
> +		elf_hwcap |= HWCAP_IDIVA;
> +	case 1:
> +		elf_hwcap |= HWCAP_IDIVT;
> +	}
> +}
> +
>  static void __init feat_v6_fixup(void)
>  {
>  	int id = read_cpuid_id();
> @@ -483,6 +500,9 @@ static void __init setup_processor(void)
>  	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
>  		 list->elf_name, ENDIANNESS);
>  	elf_hwcap = list->elf_hwcap;
> +
> +	idiv_setup();

Perhaps give this a more generic name (cpuid_init_hwcaps) so we can add more
probing later on (we could probe swp, for example).

With that minor change:

  Acked-by: Will Deacon <will.deacon@arm.com>

Will

Re: [PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Will Deacon]

On Wed, Mar 13, 2013 at 01:32:00AM +0000, Stephen Boyd wrote:
> The ISAR0 register indicates support for the SDIV and UDIV
> instructions in both the Thumb and ARM instruction set. Read the
> register to detect the supported instructions and update the
> elf_hwcap mask as appropriate. This is better than adding more
> and more cpuid checks in proc-v7.S for each new cpu variant that
> supports these instructions.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>  arch/arm/mm/proc-v7.S   |  4 ++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index e2c8bbf..bd27a70 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>  	printk("%s", buf);
>  }
>  
> +static void __init idiv_setup(void)
> +{
> +	unsigned int divide_instrs;
> +
> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
> +		return;
> +
> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
> +
> +	switch (divide_instrs) {
> +	case 2:
> +		elf_hwcap |= HWCAP_IDIVA;
> +	case 1:
> +		elf_hwcap |= HWCAP_IDIVT;
> +	}
> +}
> +
>  static void __init feat_v6_fixup(void)
>  {
>  	int id = read_cpuid_id();
> @@ -483,6 +500,9 @@ static void __init setup_processor(void)
>  	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
>  		 list->elf_name, ENDIANNESS);
>  	elf_hwcap = list->elf_hwcap;
> +
> +	idiv_setup();

Perhaps give this a more generic name (cpuid_init_hwcaps) so we can add more
probing later on (we could probe swp, for example).

With that minor change:

  Acked-by: Will Deacon <will.deacon@arm.com>

Will

[PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Will Deacon]

On Wed, Mar 13, 2013 at 01:32:00AM +0000, Stephen Boyd wrote:
> The ISAR0 register indicates support for the SDIV and UDIV
> instructions in both the Thumb and ARM instruction set. Read the
> register to detect the supported instructions and update the
> elf_hwcap mask as appropriate. This is better than adding more
> and more cpuid checks in proc-v7.S for each new cpu variant that
> supports these instructions.
> 
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>  arch/arm/mm/proc-v7.S   |  4 ++--
>  2 files changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index e2c8bbf..bd27a70 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>  	printk("%s", buf);
>  }
>  
> +static void __init idiv_setup(void)
> +{
> +	unsigned int divide_instrs;
> +
> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
> +		return;
> +
> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
> +
> +	switch (divide_instrs) {
> +	case 2:
> +		elf_hwcap |= HWCAP_IDIVA;
> +	case 1:
> +		elf_hwcap |= HWCAP_IDIVT;
> +	}
> +}
> +
>  static void __init feat_v6_fixup(void)
>  {
>  	int id = read_cpuid_id();
> @@ -483,6 +500,9 @@ static void __init setup_processor(void)
>  	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
>  		 list->elf_name, ENDIANNESS);
>  	elf_hwcap = list->elf_hwcap;
> +
> +	idiv_setup();

Perhaps give this a more generic name (cpuid_init_hwcaps) so we can add more
probing later on (we could probe swp, for example).

With that minor change:

  Acked-by: Will Deacon <will.deacon@arm.com>

Will

Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Stephen Boyd]

On 03/17/13 07:28, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>>
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the detection code
>> to indicate support in both modes.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
> After all this, you might as well just pass the relevant HWCAPs for your
> krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> code.

Ok. Care to ack the previous patch I sent then?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Stephen Boyd]

On 03/17/13 07:28, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>>
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the detection code
>> to indicate support in both modes.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
> After all this, you might as well just pass the relevant HWCAPs for your
> krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> code.

Ok. Care to ack the previous patch I sent then?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Stephen Boyd]

On 03/17/13 07:28, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
>> Some early versions of the Krait CPU design incorrectly indicate
>> that they only support the UDIV and SDIV instructions in Thumb
>> mode when they actually support them in ARM and Thumb mode. It
>> seems that these CPUs follow the DDI0406B ARM ARM which has two
>> possible values for the divide instructions field, instead of the
>> DDI0406C document which has three possible values.
>>
>> Work around this problem by checking the MIDR against Krait CPUs
>> with this faulty ISAR0 register and force the detection code
>> to indicate support in both modes.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
> After all this, you might as well just pass the relevant HWCAPs for your
> krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> code.

Ok. Care to ack the previous patch I sent then?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

Re: [PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Stephen Boyd]

On 03/17/13 07:36, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:00AM +0000, Stephen Boyd wrote:
>> The ISAR0 register indicates support for the SDIV and UDIV
>> instructions in both the Thumb and ARM instruction set. Read the
>> register to detect the supported instructions and update the
>> elf_hwcap mask as appropriate. This is better than adding more
>> and more cpuid checks in proc-v7.S for each new cpu variant that
>> supports these instructions.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>>  arch/arm/mm/proc-v7.S   |  4 ++--
>>  2 files changed, 22 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>> index e2c8bbf..bd27a70 100644
>> --- a/arch/arm/kernel/setup.c
>> +++ b/arch/arm/kernel/setup.c
>> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>>  	printk("%s", buf);
>>  }
>>  
>> +static void __init idiv_setup(void)
>> +{
>> +	unsigned int divide_instrs;
>> +
>> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
>> +		return;
>> +
>> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
>> +
>> +	switch (divide_instrs) {
>> +	case 2:
>> +		elf_hwcap |= HWCAP_IDIVA;
>> +	case 1:
>> +		elf_hwcap |= HWCAP_IDIVT;
>> +	}
>> +}
>> +
>>  static void __init feat_v6_fixup(void)
>>  {
>>  	int id = read_cpuid_id();
>> @@ -483,6 +500,9 @@ static void __init setup_processor(void)
>>  	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
>>  		 list->elf_name, ENDIANNESS);
>>  	elf_hwcap = list->elf_hwcap;
>> +
>> +	idiv_setup();
> Perhaps give this a more generic name (cpuid_init_hwcaps) so we can add more
> probing later on (we could probe swp, for example).

No problem. Thanks for the review.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

Re: [PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Stephen Boyd]

On 03/17/13 07:36, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:00AM +0000, Stephen Boyd wrote:
>> The ISAR0 register indicates support for the SDIV and UDIV
>> instructions in both the Thumb and ARM instruction set. Read the
>> register to detect the supported instructions and update the
>> elf_hwcap mask as appropriate. This is better than adding more
>> and more cpuid checks in proc-v7.S for each new cpu variant that
>> supports these instructions.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>>  arch/arm/mm/proc-v7.S   |  4 ++--
>>  2 files changed, 22 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>> index e2c8bbf..bd27a70 100644
>> --- a/arch/arm/kernel/setup.c
>> +++ b/arch/arm/kernel/setup.c
>> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>>  	printk("%s", buf);
>>  }
>>  
>> +static void __init idiv_setup(void)
>> +{
>> +	unsigned int divide_instrs;
>> +
>> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
>> +		return;
>> +
>> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
>> +
>> +	switch (divide_instrs) {
>> +	case 2:
>> +		elf_hwcap |= HWCAP_IDIVA;
>> +	case 1:
>> +		elf_hwcap |= HWCAP_IDIVT;
>> +	}
>> +}
>> +
>>  static void __init feat_v6_fixup(void)
>>  {
>>  	int id = read_cpuid_id();
>> @@ -483,6 +500,9 @@ static void __init setup_processor(void)
>>  	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
>>  		 list->elf_name, ENDIANNESS);
>>  	elf_hwcap = list->elf_hwcap;
>> +
>> +	idiv_setup();
> Perhaps give this a more generic name (cpuid_init_hwcaps) so we can add more
> probing later on (we could probe swp, for example).

No problem. Thanks for the review.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

[PATCH 2/3] ARM: Detect support for SDIV/UDIV from ISAR0 register

[Stephen Boyd]

On 03/17/13 07:36, Will Deacon wrote:
> On Wed, Mar 13, 2013 at 01:32:00AM +0000, Stephen Boyd wrote:
>> The ISAR0 register indicates support for the SDIV and UDIV
>> instructions in both the Thumb and ARM instruction set. Read the
>> register to detect the supported instructions and update the
>> elf_hwcap mask as appropriate. This is better than adding more
>> and more cpuid checks in proc-v7.S for each new cpu variant that
>> supports these instructions.
>>
>> Cc: Will Deacon <will.deacon@arm.com>
>> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  arch/arm/kernel/setup.c | 20 ++++++++++++++++++++
>>  arch/arm/mm/proc-v7.S   |  4 ++--
>>  2 files changed, 22 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
>> index e2c8bbf..bd27a70 100644
>> --- a/arch/arm/kernel/setup.c
>> +++ b/arch/arm/kernel/setup.c
>> @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
>>  	printk("%s", buf);
>>  }
>>  
>> +static void __init idiv_setup(void)
>> +{
>> +	unsigned int divide_instrs;
>> +
>> +	if (cpu_architecture() < CPU_ARCH_ARMv7)
>> +		return;
>> +
>> +	divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
>> +
>> +	switch (divide_instrs) {
>> +	case 2:
>> +		elf_hwcap |= HWCAP_IDIVA;
>> +	case 1:
>> +		elf_hwcap |= HWCAP_IDIVT;
>> +	}
>> +}
>> +
>>  static void __init feat_v6_fixup(void)
>>  {
>>  	int id = read_cpuid_id();
>> @@ -483,6 +500,9 @@ static void __init setup_processor(void)
>>  	snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
>>  		 list->elf_name, ENDIANNESS);
>>  	elf_hwcap = list->elf_hwcap;
>> +
>> +	idiv_setup();
> Perhaps give this a more generic name (cpuid_init_hwcaps) so we can add more
> probing later on (we could probe swp, for example).

No problem. Thanks for the review.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation

Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Mon, Mar 18, 2013 at 05:03:49PM +0000, Stephen Boyd wrote:
> On 03/17/13 07:28, Will Deacon wrote:
> > On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
> >> Some early versions of the Krait CPU design incorrectly indicate
> >> that they only support the UDIV and SDIV instructions in Thumb
> >> mode when they actually support them in ARM and Thumb mode. It
> >> seems that these CPUs follow the DDI0406B ARM ARM which has two
> >> possible values for the divide instructions field, instead of the
> >> DDI0406C document which has three possible values.
> >>
> >> Work around this problem by checking the MIDR against Krait CPUs
> >> with this faulty ISAR0 register and force the detection code
> >> to indicate support in both modes.
> >>
> >> Cc: Will Deacon <will.deacon@arm.com>
> >> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> >> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> >> ---
> >>  arch/arm/kernel/setup.c | 8 ++++++++
> >>  1 file changed, 8 insertions(+)
> > After all this, you might as well just pass the relevant HWCAPs for your
> > krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> > code.
> 
> Ok. Care to ack the previous patch I sent then?

Gah, I can't find the original one. If you resend the series with the
changes I suggested in the other mail, I'll add the necessary acks there.

Will

Re: [PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Mon, Mar 18, 2013 at 05:03:49PM +0000, Stephen Boyd wrote:
> On 03/17/13 07:28, Will Deacon wrote:
> > On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
> >> Some early versions of the Krait CPU design incorrectly indicate
> >> that they only support the UDIV and SDIV instructions in Thumb
> >> mode when they actually support them in ARM and Thumb mode. It
> >> seems that these CPUs follow the DDI0406B ARM ARM which has two
> >> possible values for the divide instructions field, instead of the
> >> DDI0406C document which has three possible values.
> >>
> >> Work around this problem by checking the MIDR against Krait CPUs
> >> with this faulty ISAR0 register and force the detection code
> >> to indicate support in both modes.
> >>
> >> Cc: Will Deacon <will.deacon@arm.com>
> >> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> >> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> >> ---
> >>  arch/arm/kernel/setup.c | 8 ++++++++
> >>  1 file changed, 8 insertions(+)
> > After all this, you might as well just pass the relevant HWCAPs for your
> > krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> > code.
> 
> Ok. Care to ack the previous patch I sent then?

Gah, I can't find the original one. If you resend the series with the
changes I suggested in the other mail, I'll add the necessary acks there.

Will

[PATCH 3/3] ARM: Work around faulty ISAR0 register in some Krait CPUs

[Will Deacon]

On Mon, Mar 18, 2013 at 05:03:49PM +0000, Stephen Boyd wrote:
> On 03/17/13 07:28, Will Deacon wrote:
> > On Wed, Mar 13, 2013 at 01:32:01AM +0000, Stephen Boyd wrote:
> >> Some early versions of the Krait CPU design incorrectly indicate
> >> that they only support the UDIV and SDIV instructions in Thumb
> >> mode when they actually support them in ARM and Thumb mode. It
> >> seems that these CPUs follow the DDI0406B ARM ARM which has two
> >> possible values for the divide instructions field, instead of the
> >> DDI0406C document which has three possible values.
> >>
> >> Work around this problem by checking the MIDR against Krait CPUs
> >> with this faulty ISAR0 register and force the detection code
> >> to indicate support in both modes.
> >>
> >> Cc: Will Deacon <will.deacon@arm.com>
> >> Cc: Stepan Moskovchenko <stepanm@codeaurora.org>
> >> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> >> ---
> >>  arch/arm/kernel/setup.c | 8 ++++++++
> >>  1 file changed, 8 insertions(+)
> > After all this, you might as well just pass the relevant HWCAPs for your
> > krait entry in proc-v7.S rather than have an exception in the CPU-agnostic
> > code.
> 
> Ok. Care to ack the previous patch I sent then?

Gah, I can't find the original one. If you resend the series with the
changes I suggested in the other mail, I'll add the necessary acks there.

Will