* [PATCH 01/18] drm/i915: Comments for semaphore clarification
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 13:54 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
` (19 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
Semaphores are tied very closely to the rings in the GPU. Trivial patch
adds comments to the existing code so that when we add new rings we can
include comments there as well. It also helps distinguish the ring to
semaphore mailbox interactions by using the ringname in the semaphore
data structures.
This patch should have no functional impact.
A subset of this patch was:
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d66898..767aa32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -267,12 +267,12 @@
#define MI_SEMAPHORE_UPDATE (1<<21)
#define MI_SEMAPHORE_COMPARE (1<<20)
#define MI_SEMAPHORE_REGISTER (1<<18)
-#define MI_SEMAPHORE_SYNC_RV (2<<16)
-#define MI_SEMAPHORE_SYNC_RB (0<<16)
-#define MI_SEMAPHORE_SYNC_VR (0<<16)
-#define MI_SEMAPHORE_SYNC_VB (2<<16)
-#define MI_SEMAPHORE_SYNC_BR (2<<16)
-#define MI_SEMAPHORE_SYNC_BV (0<<16)
+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
/*
* 3D instructions used by the kernel
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1d5d613..38751a7 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1666,9 +1666,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
ring->signal_mbox[0] = GEN6_VRSYNC;
ring->signal_mbox[1] = GEN6_BRSYNC;
} else if (IS_GEN5(dev)) {
@@ -1825,9 +1825,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
ring->signal_mbox[0] = GEN6_RVSYNC;
ring->signal_mbox[1] = GEN6_BVSYNC;
} else {
@@ -1871,9 +1871,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->signal_mbox[0] = GEN6_RBSYNC;
ring->signal_mbox[1] = GEN6_VBSYNC;
ring->init = init_ring_common;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d66208c..785df13 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -102,7 +102,7 @@ struct intel_ring_buffer {
struct intel_ring_buffer *to,
u32 seqno);
- u32 semaphore_register[3]; /*our mbox written by others */
+ u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
u32 signal_mbox[2]; /* mboxes this ring signals to */
/**
* List of objects currently involved in rendering from the
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 01/18] drm/i915: Comments for semaphore clarification
2013-04-28 0:59 ` [PATCH 01/18] drm/i915: Comments for semaphore clarification Ben Widawsky
@ 2013-05-07 13:54 ` Damien Lespiau
2013-05-07 16:51 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-07 13:54 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:12PM -0700, Ben Widawsky wrote:
> Semaphores are tied very closely to the rings in the GPU. Trivial patch
> adds comments to the existing code so that when we add new rings we can
> include comments there as well. It also helps distinguish the ring to
> semaphore mailbox interactions by using the ringname in the semaphore
> data structures.
>
> This patch should have no functional impact.
>
> A subset of this patch was:
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 3 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4d66898..767aa32 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -267,12 +267,12 @@
> #define MI_SEMAPHORE_UPDATE (1<<21)
> #define MI_SEMAPHORE_COMPARE (1<<20)
> #define MI_SEMAPHORE_REGISTER (1<<18)
> -#define MI_SEMAPHORE_SYNC_RV (2<<16)
> -#define MI_SEMAPHORE_SYNC_RB (0<<16)
> -#define MI_SEMAPHORE_SYNC_VR (0<<16)
> -#define MI_SEMAPHORE_SYNC_VB (2<<16)
> -#define MI_SEMAPHORE_SYNC_BR (2<<16)
> -#define MI_SEMAPHORE_SYNC_BV (0<<16)
> +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
Huum aren't the register names inverted in the comment? RCS waiting for
BCS would be RBSYNC? (Register read by RCS, written by BCS)
--
Damien
> #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
> /*
> * 3D instructions used by the kernel
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1d5d613..38751a7 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1666,9 +1666,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> ring->sync_to = gen6_ring_sync;
> - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
> - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
> - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
> + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> ring->signal_mbox[0] = GEN6_VRSYNC;
> ring->signal_mbox[1] = GEN6_BRSYNC;
> } else if (IS_GEN5(dev)) {
> @@ -1825,9 +1825,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> ring->sync_to = gen6_ring_sync;
> - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
> - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
> - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
> + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> ring->signal_mbox[0] = GEN6_RVSYNC;
> ring->signal_mbox[1] = GEN6_BVSYNC;
> } else {
> @@ -1871,9 +1871,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> ring->sync_to = gen6_ring_sync;
> - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
> - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
> - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->signal_mbox[0] = GEN6_RBSYNC;
> ring->signal_mbox[1] = GEN6_VBSYNC;
> ring->init = init_ring_common;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index d66208c..785df13 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -102,7 +102,7 @@ struct intel_ring_buffer {
> struct intel_ring_buffer *to,
> u32 seqno);
>
> - u32 semaphore_register[3]; /*our mbox written by others */
> + u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
> u32 signal_mbox[2]; /* mboxes this ring signals to */
> /**
> * List of objects currently involved in rendering from the
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 01/18] drm/i915: Comments for semaphore clarification
2013-05-07 13:54 ` Damien Lespiau
@ 2013-05-07 16:51 ` Ben Widawsky
2013-05-07 17:00 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-07 16:51 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 07, 2013 at 02:54:06PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:12PM -0700, Ben Widawsky wrote:
> > Semaphores are tied very closely to the rings in the GPU. Trivial patch
> > adds comments to the existing code so that when we add new rings we can
> > include comments there as well. It also helps distinguish the ring to
> > semaphore mailbox interactions by using the ringname in the semaphore
> > data structures.
> >
> > This patch should have no functional impact.
> >
> > A subset of this patch was:
> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> > 3 files changed, 16 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4d66898..767aa32 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -267,12 +267,12 @@
> > #define MI_SEMAPHORE_UPDATE (1<<21)
> > #define MI_SEMAPHORE_COMPARE (1<<20)
> > #define MI_SEMAPHORE_REGISTER (1<<18)
> > -#define MI_SEMAPHORE_SYNC_RV (2<<16)
> > -#define MI_SEMAPHORE_SYNC_RB (0<<16)
> > -#define MI_SEMAPHORE_SYNC_VR (0<<16)
> > -#define MI_SEMAPHORE_SYNC_VB (2<<16)
> > -#define MI_SEMAPHORE_SYNC_BR (2<<16)
> > -#define MI_SEMAPHORE_SYNC_BV (0<<16)
> > +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> > +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> > +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> > +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> > +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> > +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
>
> Huum aren't the register names inverted in the comment? RCS waiting for
> BCS would be RBSYNC? (Register read by RCS, written by BCS)
>
> --
> Damien
Admittedly this code is quite confusing. So I won't go past, I *think*
The current comments are correct.
Using the example of the render waiting on the blitter:
gen6_ring_sync(render, blitter, seqno)
iender emits a wait on:
blitter->semaphore_register[RCS] (MI_SEMAPHORE_SYNC_BR)
gen6_add_request(blitter)
update_mboxes(GEN6_RBSYNC)
update_mboxes(GEN6_VBSYNC)
So in this case:
MI_SEMAPHORE_SYNC_BR <==> GEN6_RBSYNC
>
> > #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
> > /*
> > * 3D instructions used by the kernel
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 1d5d613..38751a7 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1666,9 +1666,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> > ring->get_seqno = gen6_ring_get_seqno;
> > ring->set_seqno = ring_set_seqno;
> > ring->sync_to = gen6_ring_sync;
> > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
> > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
> > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
> > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> > ring->signal_mbox[0] = GEN6_VRSYNC;
> > ring->signal_mbox[1] = GEN6_BRSYNC;
> > } else if (IS_GEN5(dev)) {
> > @@ -1825,9 +1825,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > ring->irq_put = gen6_ring_put_irq;
> > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> > ring->sync_to = gen6_ring_sync;
> > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
> > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
> > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
> > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> > ring->signal_mbox[0] = GEN6_RVSYNC;
> > ring->signal_mbox[1] = GEN6_BVSYNC;
> > } else {
> > @@ -1871,9 +1871,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> > ring->irq_put = gen6_ring_put_irq;
> > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> > ring->sync_to = gen6_ring_sync;
> > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
> > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
> > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
> > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> > ring->signal_mbox[0] = GEN6_RBSYNC;
> > ring->signal_mbox[1] = GEN6_VBSYNC;
> > ring->init = init_ring_common;
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index d66208c..785df13 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -102,7 +102,7 @@ struct intel_ring_buffer {
> > struct intel_ring_buffer *to,
> > u32 seqno);
> >
> > - u32 semaphore_register[3]; /*our mbox written by others */
> > + u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
> > u32 signal_mbox[2]; /* mboxes this ring signals to */
> > /**
> > * List of objects currently involved in rendering from the
> > --
> > 1.8.2.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 01/18] drm/i915: Comments for semaphore clarification
2013-05-07 16:51 ` Ben Widawsky
@ 2013-05-07 17:00 ` Ben Widawsky
0 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-07 17:00 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 07, 2013 at 09:51:16AM -0700, Ben Widawsky wrote:
> On Tue, May 07, 2013 at 02:54:06PM +0100, Damien Lespiau wrote:
> > On Sat, Apr 27, 2013 at 05:59:12PM -0700, Ben Widawsky wrote:
> > > Semaphores are tied very closely to the rings in the GPU. Trivial patch
> > > adds comments to the existing code so that when we add new rings we can
> > > include comments there as well. It also helps distinguish the ring to
> > > semaphore mailbox interactions by using the ringname in the semaphore
> > > data structures.
> > >
> > > This patch should have no functional impact.
> > >
> > > A subset of this patch was:
> > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
> > > drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
> > > drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> > > 3 files changed, 16 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4d66898..767aa32 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -267,12 +267,12 @@
> > > #define MI_SEMAPHORE_UPDATE (1<<21)
> > > #define MI_SEMAPHORE_COMPARE (1<<20)
> > > #define MI_SEMAPHORE_REGISTER (1<<18)
> > > -#define MI_SEMAPHORE_SYNC_RV (2<<16)
> > > -#define MI_SEMAPHORE_SYNC_RB (0<<16)
> > > -#define MI_SEMAPHORE_SYNC_VR (0<<16)
> > > -#define MI_SEMAPHORE_SYNC_VB (2<<16)
> > > -#define MI_SEMAPHORE_SYNC_BR (2<<16)
> > > -#define MI_SEMAPHORE_SYNC_BV (0<<16)
> > > +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> > > +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> > > +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> > > +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> > > +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> > > +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
> >
> > Huum aren't the register names inverted in the comment? RCS waiting for
> > BCS would be RBSYNC? (Register read by RCS, written by BCS)
> >
> > --
> > Damien
>
> Admittedly this code is quite confusing. So I won't go past, I *think*
> The current comments are correct.
>
> Using the example of the render waiting on the blitter:
>
> gen6_ring_sync(render, blitter, seqno)
> iender emits a wait on:
> blitter->semaphore_register[RCS] (MI_SEMAPHORE_SYNC_BR)
>
> gen6_add_request(blitter)
> update_mboxes(GEN6_RBSYNC)
> update_mboxes(GEN6_VBSYNC)
>
> So in this case:
> MI_SEMAPHORE_SYNC_BR <==> GEN6_RBSYNC
>
Okay, I've fixed this locally. Thanks for catching this.
To embarrass myself less, I got confused is the names are actually
correct, the string <FOO> wait for <BAR> is the part that's incorrect.
>
>
> >
> > > #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
> > > /*
> > > * 3D instructions used by the kernel
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > index 1d5d613..38751a7 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > > @@ -1666,9 +1666,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> > > ring->get_seqno = gen6_ring_get_seqno;
> > > ring->set_seqno = ring_set_seqno;
> > > ring->sync_to = gen6_ring_sync;
> > > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
> > > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
> > > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
> > > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> > > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> > > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> > > ring->signal_mbox[0] = GEN6_VRSYNC;
> > > ring->signal_mbox[1] = GEN6_BRSYNC;
> > > } else if (IS_GEN5(dev)) {
> > > @@ -1825,9 +1825,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > > ring->irq_put = gen6_ring_put_irq;
> > > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> > > ring->sync_to = gen6_ring_sync;
> > > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
> > > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
> > > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
> > > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> > > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> > > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> > > ring->signal_mbox[0] = GEN6_RVSYNC;
> > > ring->signal_mbox[1] = GEN6_BVSYNC;
> > > } else {
> > > @@ -1871,9 +1871,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> > > ring->irq_put = gen6_ring_put_irq;
> > > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> > > ring->sync_to = gen6_ring_sync;
> > > - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
> > > - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
> > > - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
> > > + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> > > + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> > > + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> > > ring->signal_mbox[0] = GEN6_RBSYNC;
> > > ring->signal_mbox[1] = GEN6_VBSYNC;
> > > ring->init = init_ring_common;
> > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > index d66208c..785df13 100644
> > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > > @@ -102,7 +102,7 @@ struct intel_ring_buffer {
> > > struct intel_ring_buffer *to,
> > > u32 seqno);
> > >
> > > - u32 semaphore_register[3]; /*our mbox written by others */
> > > + u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
> > > u32 signal_mbox[2]; /* mboxes this ring signals to */
> > > /**
> > > * List of objects currently involved in rendering from the
> > > --
> > > 1.8.2.1
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ben Widawsky, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 02/18] drm/i915: Semaphore MBOX update generalization
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
2013-04-28 0:59 ` [PATCH 01/18] drm/i915: Comments for semaphore clarification Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 15:34 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
` (18 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
This replaces the existing MBOX update code with a more generalized
calculation for emitting mbox updates. We also create a sentinel for
doing the updates so we can more abstractly deal with the rings.
When doing MBOX updates the code must be aware of the /other/ rings.
Until now the platforms which supported semaphores had a fixed number of
rings and so it made sense for the code to be very specialized
(hardcoded).
The patch does contain a functional change, but should have no
behavioral changes.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 38 +++++++++++++++++++++------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
3 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 767aa32..5be4a75 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -568,6 +568,7 @@
#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_NOSYNC 0
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 38751a7..0f97547 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -578,9 +578,11 @@ static void
update_mboxes(struct intel_ring_buffer *ring,
u32 mmio_offset)
{
+#define MBOX_UPDATE_DWORDS 4
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit(ring, mmio_offset);
intel_ring_emit(ring, ring->outstanding_lazy_request);
+ intel_ring_emit(ring, MI_NOOP);
}
/**
@@ -595,19 +597,24 @@ update_mboxes(struct intel_ring_buffer *ring,
static int
gen6_add_request(struct intel_ring_buffer *ring)
{
- u32 mbox1_reg;
- u32 mbox2_reg;
- int ret;
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *useless;
+ int i, ret;
- ret = intel_ring_begin(ring, 10);
+ ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
+ MBOX_UPDATE_DWORDS) +
+ 4);
if (ret)
return ret;
+#undef MBOX_UPDATE_DWORDS
- mbox1_reg = ring->signal_mbox[0];
- mbox2_reg = ring->signal_mbox[1];
+ for_each_ring(useless, dev_priv, i) {
+ u32 mbox_reg = ring->signal_mbox[i];
+ if (mbox_reg != GEN6_NOSYNC)
+ update_mboxes(ring, mbox_reg);
+ }
- update_mboxes(ring, mbox1_reg);
- update_mboxes(ring, mbox2_reg);
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, ring->outstanding_lazy_request);
@@ -1669,8 +1676,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
- ring->signal_mbox[0] = GEN6_VRSYNC;
- ring->signal_mbox[1] = GEN6_BRSYNC;
+ ring->signal_mbox[RCS] = GEN6_NOSYNC;
+ ring->signal_mbox[VCS] = GEN6_VRSYNC;
+ ring->signal_mbox[BCS] = GEN6_BRSYNC;
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->flush = gen4_render_ring_flush;
@@ -1828,8 +1836,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
- ring->signal_mbox[0] = GEN6_RVSYNC;
- ring->signal_mbox[1] = GEN6_BVSYNC;
+ ring->signal_mbox[RCS] = GEN6_RVSYNC;
+ ring->signal_mbox[VCS] = GEN6_NOSYNC;
+ ring->signal_mbox[BCS] = GEN6_BVSYNC;
} else {
ring->mmio_base = BSD_RING_BASE;
ring->flush = bsd_ring_flush;
@@ -1874,8 +1883,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
- ring->signal_mbox[0] = GEN6_RBSYNC;
- ring->signal_mbox[1] = GEN6_VBSYNC;
+ ring->signal_mbox[RCS] = GEN6_RBSYNC;
+ ring->signal_mbox[VCS] = GEN6_VBSYNC;
+ ring->signal_mbox[BCS] = GEN6_NOSYNC;
ring->init = init_ring_common;
return intel_init_ring_buffer(dev, ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 785df13..f1aef0d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -103,7 +103,7 @@ struct intel_ring_buffer {
u32 seqno);
u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
- u32 signal_mbox[2]; /* mboxes this ring signals to */
+ u32 signal_mbox[I915_NUM_RINGS]; /* mboxes this ring signals to + sentinel */
/**
* List of objects currently involved in rendering from the
* ringbuffer.
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 02/18] drm/i915: Semaphore MBOX update generalization
2013-04-28 0:59 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
@ 2013-05-07 15:34 ` Damien Lespiau
2013-05-08 5:17 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-07 15:34 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:13PM -0700, Ben Widawsky wrote:
> This replaces the existing MBOX update code with a more generalized
> calculation for emitting mbox updates. We also create a sentinel for
> doing the updates so we can more abstractly deal with the rings.
>
> When doing MBOX updates the code must be aware of the /other/ rings.
> Until now the platforms which supported semaphores had a fixed number of
> rings and so it made sense for the code to be very specialized
> (hardcoded).
>
> The patch does contain a functional change, but should have no
> behavioral changes.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 38 +++++++++++++++++++++------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 3 files changed, 26 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 767aa32..5be4a75 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -568,6 +568,7 @@
> #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> +#define GEN6_NOSYNC 0
> #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> #define RING_MAX_IDLE(base) ((base)+0x54)
> #define RING_HWS_PGA(base) ((base)+0x80)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 38751a7..0f97547 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -578,9 +578,11 @@ static void
> update_mboxes(struct intel_ring_buffer *ring,
> u32 mmio_offset)
> {
> +#define MBOX_UPDATE_DWORDS 4
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit(ring, mmio_offset);
> intel_ring_emit(ring, ring->outstanding_lazy_request);
> + intel_ring_emit(ring, MI_NOOP);
Not sure why you are adding a MI_NOOP here, mind documenting this?
> }
>
> /**
> @@ -595,19 +597,24 @@ update_mboxes(struct intel_ring_buffer *ring,
> static int
> gen6_add_request(struct intel_ring_buffer *ring)
> {
> - u32 mbox1_reg;
> - u32 mbox2_reg;
> - int ret;
> + struct drm_device *dev = ring->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ring_buffer *useless;
> + int i, ret;
>
> - ret = intel_ring_begin(ring, 10);
> + ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
> + MBOX_UPDATE_DWORDS) +
> + 4);
> if (ret)
> return ret;
> +#undef MBOX_UPDATE_DWORDS
>
> - mbox1_reg = ring->signal_mbox[0];
> - mbox2_reg = ring->signal_mbox[1];
> + for_each_ring(useless, dev_priv, i) {
> + u32 mbox_reg = ring->signal_mbox[i];
> + if (mbox_reg != GEN6_NOSYNC)
> + update_mboxes(ring, mbox_reg);
> + }
>
> - update_mboxes(ring, mbox1_reg);
> - update_mboxes(ring, mbox2_reg);
> intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> intel_ring_emit(ring, ring->outstanding_lazy_request);
> @@ -1669,8 +1676,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> - ring->signal_mbox[0] = GEN6_VRSYNC;
> - ring->signal_mbox[1] = GEN6_BRSYNC;
> + ring->signal_mbox[RCS] = GEN6_NOSYNC;
> + ring->signal_mbox[VCS] = GEN6_VRSYNC;
> + ring->signal_mbox[BCS] = GEN6_BRSYNC;
> } else if (IS_GEN5(dev)) {
> ring->add_request = pc_render_add_request;
> ring->flush = gen4_render_ring_flush;
> @@ -1828,8 +1836,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> - ring->signal_mbox[0] = GEN6_RVSYNC;
> - ring->signal_mbox[1] = GEN6_BVSYNC;
> + ring->signal_mbox[RCS] = GEN6_RVSYNC;
> + ring->signal_mbox[VCS] = GEN6_NOSYNC;
> + ring->signal_mbox[BCS] = GEN6_BVSYNC;
> } else {
> ring->mmio_base = BSD_RING_BASE;
> ring->flush = bsd_ring_flush;
> @@ -1874,8 +1883,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> - ring->signal_mbox[0] = GEN6_RBSYNC;
> - ring->signal_mbox[1] = GEN6_VBSYNC;
> + ring->signal_mbox[RCS] = GEN6_RBSYNC;
> + ring->signal_mbox[VCS] = GEN6_VBSYNC;
> + ring->signal_mbox[BCS] = GEN6_NOSYNC;
> ring->init = init_ring_common;
>
> return intel_init_ring_buffer(dev, ring);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 785df13..f1aef0d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -103,7 +103,7 @@ struct intel_ring_buffer {
> u32 seqno);
>
> u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
> - u32 signal_mbox[2]; /* mboxes this ring signals to */
> + u32 signal_mbox[I915_NUM_RINGS]; /* mboxes this ring signals to + sentinel */
> /**
> * List of objects currently involved in rendering from the
> * ringbuffer.
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 02/18] drm/i915: Semaphore MBOX update generalization
2013-05-07 15:34 ` Damien Lespiau
@ 2013-05-08 5:17 ` Ben Widawsky
0 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-08 5:17 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 07, 2013 at 04:34:46PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:13PM -0700, Ben Widawsky wrote:
> > This replaces the existing MBOX update code with a more generalized
> > calculation for emitting mbox updates. We also create a sentinel for
> > doing the updates so we can more abstractly deal with the rings.
> >
> > When doing MBOX updates the code must be aware of the /other/ rings.
> > Until now the platforms which supported semaphores had a fixed number of
> > rings and so it made sense for the code to be very specialized
> > (hardcoded).
> >
> > The patch does contain a functional change, but should have no
> > behavioral changes.
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 38 +++++++++++++++++++++------------
> > drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> > 3 files changed, 26 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 767aa32..5be4a75 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -568,6 +568,7 @@
> > #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> > #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> > #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> > +#define GEN6_NOSYNC 0
> > #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> > #define RING_MAX_IDLE(base) ((base)+0x54)
> > #define RING_HWS_PGA(base) ((base)+0x80)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 38751a7..0f97547 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -578,9 +578,11 @@ static void
> > update_mboxes(struct intel_ring_buffer *ring,
> > u32 mmio_offset)
> > {
> > +#define MBOX_UPDATE_DWORDS 4
> > intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> > intel_ring_emit(ring, mmio_offset);
> > intel_ring_emit(ring, ring->outstanding_lazy_request);
> > + intel_ring_emit(ring, MI_NOOP);
>
> Not sure why you are adding a MI_NOOP here, mind documenting this?
>
Sure. The key is that we move to for_each_ring and the number of rings
we must update move from even to odd...
How's this:
/* In order to be able to do semaphore MBOX updates for varying number
* of rings, it's easiest if we round up each individual update to a
* multiple of 2 (since ring updates must always be a multiple of 2)
* even though the actual update only requires 3 dwords.
*/
> > }
> >
> > /**
> > @@ -595,19 +597,24 @@ update_mboxes(struct intel_ring_buffer *ring,
> > static int
> > gen6_add_request(struct intel_ring_buffer *ring)
> > {
> > - u32 mbox1_reg;
> > - u32 mbox2_reg;
> > - int ret;
> > + struct drm_device *dev = ring->dev;
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct intel_ring_buffer *useless;
> > + int i, ret;
> >
> > - ret = intel_ring_begin(ring, 10);
> > + ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
> > + MBOX_UPDATE_DWORDS) +
> > + 4);
> > if (ret)
> > return ret;
> > +#undef MBOX_UPDATE_DWORDS
> >
> > - mbox1_reg = ring->signal_mbox[0];
> > - mbox2_reg = ring->signal_mbox[1];
> > + for_each_ring(useless, dev_priv, i) {
> > + u32 mbox_reg = ring->signal_mbox[i];
> > + if (mbox_reg != GEN6_NOSYNC)
> > + update_mboxes(ring, mbox_reg);
> > + }
> >
> > - update_mboxes(ring, mbox1_reg);
> > - update_mboxes(ring, mbox2_reg);
> > intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
> > intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> > intel_ring_emit(ring, ring->outstanding_lazy_request);
> > @@ -1669,8 +1676,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> > ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> > ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> > ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> > - ring->signal_mbox[0] = GEN6_VRSYNC;
> > - ring->signal_mbox[1] = GEN6_BRSYNC;
> > + ring->signal_mbox[RCS] = GEN6_NOSYNC;
> > + ring->signal_mbox[VCS] = GEN6_VRSYNC;
> > + ring->signal_mbox[BCS] = GEN6_BRSYNC;
> > } else if (IS_GEN5(dev)) {
> > ring->add_request = pc_render_add_request;
> > ring->flush = gen4_render_ring_flush;
> > @@ -1828,8 +1836,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> > ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> > ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> > - ring->signal_mbox[0] = GEN6_RVSYNC;
> > - ring->signal_mbox[1] = GEN6_BVSYNC;
> > + ring->signal_mbox[RCS] = GEN6_RVSYNC;
> > + ring->signal_mbox[VCS] = GEN6_NOSYNC;
> > + ring->signal_mbox[BCS] = GEN6_BVSYNC;
> > } else {
> > ring->mmio_base = BSD_RING_BASE;
> > ring->flush = bsd_ring_flush;
> > @@ -1874,8 +1883,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> > ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> > ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> > ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> > - ring->signal_mbox[0] = GEN6_RBSYNC;
> > - ring->signal_mbox[1] = GEN6_VBSYNC;
> > + ring->signal_mbox[RCS] = GEN6_RBSYNC;
> > + ring->signal_mbox[VCS] = GEN6_VBSYNC;
> > + ring->signal_mbox[BCS] = GEN6_NOSYNC;
> > ring->init = init_ring_common;
> >
> > return intel_init_ring_buffer(dev, ring);
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index 785df13..f1aef0d 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -103,7 +103,7 @@ struct intel_ring_buffer {
> > u32 seqno);
> >
> > u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
> > - u32 signal_mbox[2]; /* mboxes this ring signals to */
> > + u32 signal_mbox[I915_NUM_RINGS]; /* mboxes this ring signals to + sentinel */
> > /**
> > * List of objects currently involved in rendering from the
> > * ringbuffer.
> > --
> > 1.8.2.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
2013-04-28 0:59 ` [PATCH 01/18] drm/i915: Comments for semaphore clarification Ben Widawsky
2013-04-28 0:59 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 15:35 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 04/18] drm/i915: Add VECS semaphore bits Ben Widawsky
` (17 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
The video enhancement command streamer is a new ring on HSW which does
what it sounds like it does. This patch provides the most minimal
inception of the ring.
In order to support a new ring, we need to bump the number. The patch
may look trivial to the untrained eye, but bumping the number of rings
is a bit scary. As such the patch is not terribly useful by itself, but
a pretty nice place to find issues during a bisection.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0f97547..555f8b8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -906,6 +906,8 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
case VCS:
mmio = BSD_HWS_PGA_GEN7;
break;
+ case VECS:
+ BUG();
}
} else if (IS_GEN6(ring->dev)) {
mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f1aef0d..9afca1a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -43,8 +43,9 @@ struct intel_ring_buffer {
RCS = 0x0,
VCS,
BCS,
+ VECS,
} id;
-#define I915_NUM_RINGS 3
+#define I915_NUM_RINGS 4
u32 mmio_base;
void __iomem *virtual_start;
struct drm_device *dev;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring
2013-04-28 0:59 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
@ 2013-05-07 15:35 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-07 15:35 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:14PM -0700, Ben Widawsky wrote:
> The video enhancement command streamer is a new ring on HSW which does
> what it sounds like it does. This patch provides the most minimal
> inception of the ring.
>
> In order to support a new ring, we need to bump the number. The patch
> may look trivial to the untrained eye, but bumping the number of rings
> is a bit scary. As such the patch is not terribly useful by itself, but
> a pretty nice place to find issues during a bisection.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 04/18] drm/i915: Add VECS semaphore bits
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (2 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 14:49 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 05/18] drm/i915: Rename ring flush functions Ben Widawsky
` (16 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
Like the other rings, the VECS supports semaphores. The semaphore stuff
is a bit wonky so this patch on it's own should be nice for review.
This patch should have no functional impact.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++---
2 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5be4a75..3899f71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -267,13 +267,19 @@
#define MI_SEMAPHORE_UPDATE (1<<21)
#define MI_SEMAPHORE_COMPARE (1<<20)
#define MI_SEMAPHORE_REGISTER (1<<18)
-#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
-#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
-#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
-#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
-#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
-#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
-#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
+#define MI_SEMAPHORE_SYNC_VER (1<<16) /* VECS wait for RCS (RVESYNC) */
+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
+#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VECS wait for VCS (VVESYNC) */
+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
+#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* VECS wait for BCS (BVESYNC) */
+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
+#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* BCS wait for VECS (VEBSYNC) */
+#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VCS wait for VECS (VEVSYNC) */
+#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* RCS wait for VECS (VERSYNC) */
+#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
/*
* 3D instructions used by the kernel
*/
@@ -556,6 +562,7 @@
#define RENDER_RING_BASE 0x02000
#define BSD_RING_BASE 0x04000
#define GEN6_BSD_RING_BASE 0x12000
+#define VEBOX_RING_BASE 0x1a000
#define BLT_RING_BASE 0x22000
#define RING_TAIL(base) ((base)+0x30)
#define RING_HEAD(base) ((base)+0x34)
@@ -563,13 +570,20 @@
#define RING_CTL(base) ((base)+0x3c)
#define RING_SYNC_0(base) ((base)+0x40)
#define RING_SYNC_1(base) ((base)+0x44)
-#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
-#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
-#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
-#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
-#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define RING_SYNC_2(base) ((base)+0x48)
+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
+#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
+#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
+#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
#define GEN6_NOSYNC 0
-#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 555f8b8..b597d1e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -654,9 +654,6 @@ gen6_ring_sync(struct intel_ring_buffer *waiter,
*/
seqno -= 1;
- WARN_ON(signaller->semaphore_register[waiter->id] ==
- MI_SEMAPHORE_SYNC_INVALID);
-
ret = intel_ring_begin(waiter, 4);
if (ret)
return ret;
@@ -1678,9 +1675,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
ring->signal_mbox[RCS] = GEN6_NOSYNC;
ring->signal_mbox[VCS] = GEN6_VRSYNC;
ring->signal_mbox[BCS] = GEN6_BRSYNC;
+ ring->signal_mbox[VECS] = GEN6_VERSYNC;
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->flush = gen4_render_ring_flush;
@@ -1838,9 +1837,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VEV;
ring->signal_mbox[RCS] = GEN6_RVSYNC;
ring->signal_mbox[VCS] = GEN6_NOSYNC;
ring->signal_mbox[BCS] = GEN6_BVSYNC;
+ ring->signal_mbox[VECS] = GEN6_VEVSYNC;
} else {
ring->mmio_base = BSD_RING_BASE;
ring->flush = bsd_ring_flush;
@@ -1885,9 +1886,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
ring->signal_mbox[RCS] = GEN6_RBSYNC;
ring->signal_mbox[VCS] = GEN6_VBSYNC;
ring->signal_mbox[BCS] = GEN6_NOSYNC;
+ ring->signal_mbox[VECS] = GEN6_VEBSYNC;
ring->init = init_ring_common;
return intel_init_ring_buffer(dev, ring);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 04/18] drm/i915: Add VECS semaphore bits
2013-04-28 0:59 ` [PATCH 04/18] drm/i915: Add VECS semaphore bits Ben Widawsky
@ 2013-05-07 14:49 ` Damien Lespiau
2013-05-08 5:59 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-07 14:49 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:15PM -0700, Ben Widawsky wrote:
> Like the other rings, the VECS supports semaphores. The semaphore stuff
> is a bit wonky so this patch on it's own should be nice for review.
>
> This patch should have no functional impact.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++-----------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++---
> 2 files changed, 33 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5be4a75..3899f71 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -267,13 +267,19 @@
> #define MI_SEMAPHORE_UPDATE (1<<21)
> #define MI_SEMAPHORE_COMPARE (1<<20)
> #define MI_SEMAPHORE_REGISTER (1<<18)
> -#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> -#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> -#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> -#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> -#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> -#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
> -#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
> +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> +#define MI_SEMAPHORE_SYNC_VER (1<<16) /* VECS wait for RCS (RVESYNC) */
> +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
> +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> +#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VECS wait for VCS (VVESYNC) */
> +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> +#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* VECS wait for BCS (BVESYNC) */
> +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> +#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* BCS wait for VECS (VEBSYNC) */
> +#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VCS wait for VECS (VEVSYNC) */
> +#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* RCS wait for VECS (VERSYNC) */
> +#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
Same thing as in patch 1, I think the registers are the other way
around.
> /*
> * 3D instructions used by the kernel
> */
> @@ -556,6 +562,7 @@
> #define RENDER_RING_BASE 0x02000
> #define BSD_RING_BASE 0x04000
> #define GEN6_BSD_RING_BASE 0x12000
> +#define VEBOX_RING_BASE 0x1a000
> #define BLT_RING_BASE 0x22000
> #define RING_TAIL(base) ((base)+0x30)
> #define RING_HEAD(base) ((base)+0x34)
> @@ -563,13 +570,20 @@
> #define RING_CTL(base) ((base)+0x3c)
> #define RING_SYNC_0(base) ((base)+0x40)
> #define RING_SYNC_1(base) ((base)+0x44)
> -#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
> -#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
> -#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> -#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> -#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> +#define RING_SYNC_2(base) ((base)+0x48)
> +#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
> +#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
> +#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
> +#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> +#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> +#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
> +#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> +#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> +#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
> +#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
> +#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
> +#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
> #define GEN6_NOSYNC 0
> -#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> #define RING_MAX_IDLE(base) ((base)+0x54)
> #define RING_HWS_PGA(base) ((base)+0x80)
> #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 555f8b8..b597d1e 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -654,9 +654,6 @@ gen6_ring_sync(struct intel_ring_buffer *waiter,
> */
> seqno -= 1;
>
> - WARN_ON(signaller->semaphore_register[waiter->id] ==
> - MI_SEMAPHORE_SYNC_INVALID);
> -
Hum, this WARN_ON() is still valid isn't it?
> ret = intel_ring_begin(waiter, 4);
> if (ret)
> return ret;
> @@ -1678,9 +1675,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> + ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
> ring->signal_mbox[RCS] = GEN6_NOSYNC;
> ring->signal_mbox[VCS] = GEN6_VRSYNC;
> ring->signal_mbox[BCS] = GEN6_BRSYNC;
> + ring->signal_mbox[VECS] = GEN6_VERSYNC;
> } else if (IS_GEN5(dev)) {
> ring->add_request = pc_render_add_request;
> ring->flush = gen4_render_ring_flush;
> @@ -1838,9 +1837,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> + ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VEV;
MI_SEMAPHORE_SYNC_VVE here?
> ring->signal_mbox[RCS] = GEN6_RVSYNC;
> ring->signal_mbox[VCS] = GEN6_NOSYNC;
> ring->signal_mbox[BCS] = GEN6_BVSYNC;
> + ring->signal_mbox[VECS] = GEN6_VEVSYNC;
> } else {
> ring->mmio_base = BSD_RING_BASE;
> ring->flush = bsd_ring_flush;
> @@ -1885,9 +1886,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
> ring->signal_mbox[RCS] = GEN6_RBSYNC;
> ring->signal_mbox[VCS] = GEN6_VBSYNC;
> ring->signal_mbox[BCS] = GEN6_NOSYNC;
> + ring->signal_mbox[VECS] = GEN6_VEBSYNC;
> ring->init = init_ring_common;
>
> return intel_init_ring_buffer(dev, ring);
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 04/18] drm/i915: Add VECS semaphore bits
2013-05-07 14:49 ` Damien Lespiau
@ 2013-05-08 5:59 ` Ben Widawsky
0 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-08 5:59 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 07, 2013 at 03:49:18PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:15PM -0700, Ben Widawsky wrote:
> > Like the other rings, the VECS supports semaphores. The semaphore stuff
> > is a bit wonky so this patch on it's own should be nice for review.
> >
> > This patch should have no functional impact.
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++-----------
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 9 +++++---
> > 2 files changed, 33 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5be4a75..3899f71 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -267,13 +267,19 @@
> > #define MI_SEMAPHORE_UPDATE (1<<21)
> > #define MI_SEMAPHORE_COMPARE (1<<20)
> > #define MI_SEMAPHORE_REGISTER (1<<18)
> > -#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> > -#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> > -#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> > -#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> > -#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> > -#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
> > -#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
> > +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* VCS wait for RCS (RVSYNC) */
> > +#define MI_SEMAPHORE_SYNC_VER (1<<16) /* VECS wait for RCS (RVESYNC) */
> > +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* BCS wait for RCS (RBSYNC) */
> > +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* BCS wait for VCS (VBSYNC) */
> > +#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VECS wait for VCS (VVESYNC) */
> > +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* RCS wait for VCS (VRSYNC) */
> > +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* RCS wait for BCS (BRSYNC) */
> > +#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* VECS wait for BCS (BVESYNC) */
> > +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* VCS wait for BCS (BVSYNC) */
> > +#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* BCS wait for VECS (VEBSYNC) */
> > +#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VCS wait for VECS (VEVSYNC) */
> > +#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* RCS wait for VECS (VERSYNC) */
> > +#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
>
> Same thing as in patch 1, I think the registers are the other way
> around.
Yep, fixed.
>
> > /*
> > * 3D instructions used by the kernel
> > */
> > @@ -556,6 +562,7 @@
> > #define RENDER_RING_BASE 0x02000
> > #define BSD_RING_BASE 0x04000
> > #define GEN6_BSD_RING_BASE 0x12000
> > +#define VEBOX_RING_BASE 0x1a000
> > #define BLT_RING_BASE 0x22000
> > #define RING_TAIL(base) ((base)+0x30)
> > #define RING_HEAD(base) ((base)+0x34)
> > @@ -563,13 +570,20 @@
> > #define RING_CTL(base) ((base)+0x3c)
> > #define RING_SYNC_0(base) ((base)+0x40)
> > #define RING_SYNC_1(base) ((base)+0x44)
> > -#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
> > -#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
> > -#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> > -#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> > -#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> > +#define RING_SYNC_2(base) ((base)+0x48)
> > +#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
> > +#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
> > +#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
> > +#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> > +#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> > +#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
> > +#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> > +#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> > +#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
> > +#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
> > +#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
> > +#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
> > #define GEN6_NOSYNC 0
> > -#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> > #define RING_MAX_IDLE(base) ((base)+0x54)
> > #define RING_HWS_PGA(base) ((base)+0x80)
> > #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 555f8b8..b597d1e 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -654,9 +654,6 @@ gen6_ring_sync(struct intel_ring_buffer *waiter,
> > */
> > seqno -= 1;
> >
> > - WARN_ON(signaller->semaphore_register[waiter->id] ==
> > - MI_SEMAPHORE_SYNC_INVALID);
> > -
>
> Hum, this WARN_ON() is still valid isn't it?
I must have killed this by accident while rebasing. It is indeed valid. Nice catch.
>
> > ret = intel_ring_begin(waiter, 4);
> > if (ret)
> > return ret;
> > @@ -1678,9 +1675,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> > ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> > ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> > ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> > + ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
> > ring->signal_mbox[RCS] = GEN6_NOSYNC;
> > ring->signal_mbox[VCS] = GEN6_VRSYNC;
> > ring->signal_mbox[BCS] = GEN6_BRSYNC;
> > + ring->signal_mbox[VECS] = GEN6_VERSYNC;
> > } else if (IS_GEN5(dev)) {
> > ring->add_request = pc_render_add_request;
> > ring->flush = gen4_render_ring_flush;
> > @@ -1838,9 +1837,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> > ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> > ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> > + ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VEV;
>
> MI_SEMAPHORE_SYNC_VVE here?
Weird. I remember Haihao had caught this typo earlier, and I fixed it
earlier. I'm beginning to fear I may have rebased the wrong branch...
Anyway, thanks for finding it again.
Got all the fixes locally. Will send when I'm done with the other
changes.
>
> > ring->signal_mbox[RCS] = GEN6_RVSYNC;
> > ring->signal_mbox[VCS] = GEN6_NOSYNC;
> > ring->signal_mbox[BCS] = GEN6_BVSYNC;
> > + ring->signal_mbox[VECS] = GEN6_VEVSYNC;
> > } else {
> > ring->mmio_base = BSD_RING_BASE;
> > ring->flush = bsd_ring_flush;
> > @@ -1885,9 +1886,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> > ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> > ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> > ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> > + ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
> > ring->signal_mbox[RCS] = GEN6_RBSYNC;
> > ring->signal_mbox[VCS] = GEN6_VBSYNC;
> > ring->signal_mbox[BCS] = GEN6_NOSYNC;
> > + ring->signal_mbox[VECS] = GEN6_VEBSYNC;
> > ring->init = init_ring_common;
> >
> > return intel_init_ring_buffer(dev, ring);
> > --
> > 1.8.2.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 05/18] drm/i915: Rename ring flush functions
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (3 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 04/18] drm/i915: Add VECS semaphore bits Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 17:28 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 06/18] drm/i915: add HAS_VEBOX Ben Widawsky
` (15 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
Historically we considered the render ring to have special flush
semantics and everything else to fall under a more general umbrella.
Probably by coincidence more than anything we decided to make the bsd
ring have the default *other* flush. As the new vebox ring exposes, the
bsd ring is actually the weird one. Doing this allows us to call
gen6_ring_flush for the vebox because calling blt_ring_flush would be
weird...
This patch should have no functional change.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b597d1e..21d004c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1552,8 +1552,8 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
}
-static int gen6_ring_flush(struct intel_ring_buffer *ring,
- u32 invalidate, u32 flush)
+static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
+ u32 invalidate, u32 flush)
{
uint32_t cmd;
int ret;
@@ -1624,8 +1624,8 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
/* Blitter support (SandyBridge+) */
-static int blt_ring_flush(struct intel_ring_buffer *ring,
- u32 invalidate, u32 flush)
+static int gen6_ring_flush(struct intel_ring_buffer *ring,
+ u32 invalidate, u32 flush)
{
uint32_t cmd;
int ret;
@@ -1825,7 +1825,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
/* gen6 bsd needs a special wa for tail updates */
if (IS_GEN6(dev))
ring->write_tail = gen6_bsd_ring_write_tail;
- ring->flush = gen6_ring_flush;
+ ring->flush = gen6_bsd_ring_flush;
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
@@ -1874,7 +1874,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->mmio_base = BLT_RING_BASE;
ring->write_tail = ring_write_tail;
- ring->flush = blt_ring_flush;
+ ring->flush = gen6_ring_flush;
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 05/18] drm/i915: Rename ring flush functions
2013-04-28 0:59 ` [PATCH 05/18] drm/i915: Rename ring flush functions Ben Widawsky
@ 2013-05-07 17:28 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-07 17:28 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:16PM -0700, Ben Widawsky wrote:
> Historically we considered the render ring to have special flush
> semantics and everything else to fall under a more general umbrella.
> Probably by coincidence more than anything we decided to make the bsd
> ring have the default *other* flush. As the new vebox ring exposes, the
> bsd ring is actually the weird one. Doing this allows us to call
> gen6_ring_flush for the vebox because calling blt_ring_flush would be
> weird...
>
> This patch should have no functional change.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 06/18] drm/i915: add HAS_VEBOX
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (4 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 05/18] drm/i915: Rename ring flush functions Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 14:59 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 07/18] drm/i915: Vebox ringbuffer init Ben Widawsky
` (14 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
The flag will be useful to help share code between IVB, and HSW as the
programming is similar in many places with this as one of the major
differences.
v2 (Ben): used the new dev info macros
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Commit message + small fix by]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 624cdfc..be8602f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -308,6 +308,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
static const struct intel_device_info intel_haswell_d_info = {
GEN7_FEATURES,
.is_haswell = 1,
+ .has_vebox_ring = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
};
@@ -316,6 +317,7 @@ static const struct intel_device_info intel_haswell_m_info = {
GEN7_FEATURES,
.is_haswell = 1,
.is_mobile = 1,
+ .has_vebox_ring = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 14156f2..bd51b6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -357,6 +357,7 @@ struct drm_i915_gt_funcs {
func(supports_tv) sep \
func(has_bsd_ring) sep \
func(has_blt_ring) sep \
+ func(has_vebox_ring) sep \
func(has_llc) sep \
func(has_ddi) sep \
func(has_fpga_dbg)
@@ -1338,6 +1339,7 @@ struct drm_i915_file_private {
#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
+#define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 06/18] drm/i915: add HAS_VEBOX
2013-04-28 0:59 ` [PATCH 06/18] drm/i915: add HAS_VEBOX Ben Widawsky
@ 2013-05-07 14:59 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-07 14:59 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:17PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao" <haihao.xiang@intel.com>
>
> The flag will be useful to help share code between IVB, and HSW as the
> programming is similar in many places with this as one of the major
> differences.
>
> v2 (Ben): used the new dev info macros
>
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> [Commit message + small fix by]
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 07/18] drm/i915: Vebox ringbuffer init
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (5 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 06/18] drm/i915: add HAS_VEBOX Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-07 17:16 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
` (13 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
v2: Add set_seqno which didn't exist before rebase (Haihao)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 11 ++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 ++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6be940e..855ce3b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3982,12 +3982,21 @@ static int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_bsd_ring;
}
+ if (HAS_VEBOX(dev)) {
+ ret = intel_init_vebox_ring_buffer(dev);
+ if (ret)
+ goto cleanup_blt_ring;
+ }
+
+
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
- goto cleanup_blt_ring;
+ goto cleanup_vebox_ring;
return 0;
+cleanup_vebox_ring:
+ intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
cleanup_blt_ring:
intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3899f71..5dae1d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -595,6 +595,7 @@
#define DONE_REG 0x40b0
#define BSD_HWS_PGA_GEN7 (0x04180)
#define BLT_HWS_PGA_GEN7 (0x04280)
+#define VEBOX_HWS_PGA_GEN7 (0x04380)
#define RING_ACTHD(base) ((base)+0x74)
#define RING_NOPID(base) ((base)+0x94)
#define RING_IMR(base) ((base)+0xa8)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 21d004c..01937f3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -904,7 +904,8 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
mmio = BSD_HWS_PGA_GEN7;
break;
case VECS:
- BUG();
+ mmio = VEBOX_HWS_PGA_GEN7;
+ break;
}
} else if (IS_GEN6(ring->dev)) {
mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
@@ -1896,6 +1897,38 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
return intel_init_ring_buffer(dev, ring);
}
+int intel_init_vebox_ring_buffer(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
+
+ ring->name = "video enhancement ring";
+ ring->id = VECS;
+
+ ring->mmio_base = VEBOX_RING_BASE;
+ ring->write_tail = ring_write_tail;
+ ring->flush = gen6_ring_flush;
+ ring->add_request = gen6_add_request;
+ ring->get_seqno = gen6_ring_get_seqno;
+ ring->set_seqno = ring_set_seqno;
+ ring->irq_enable_mask = 0;
+ ring->irq_get = NULL;
+ ring->irq_put = NULL;
+ ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+ ring->sync_to = gen6_ring_sync;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->signal_mbox[RCS] = GEN6_RVESYNC;
+ ring->signal_mbox[VCS] = GEN6_VVESYNC;
+ ring->signal_mbox[BCS] = GEN6_BVESYNC;
+ ring->signal_mbox[VECS] = GEN6_NOSYNC;
+ ring->init = init_ring_common;
+
+ return intel_init_ring_buffer(dev, ring);
+}
+
int
intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
{
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 9afca1a..cb70f37 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -225,6 +225,7 @@ int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
+int intel_init_vebox_ring_buffer(struct drm_device *dev);
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (6 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 07/18] drm/i915: Vebox ringbuffer init Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 13:00 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
` (12 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
HSW has some special requirements for the VEBOX. Splitting out the
interrupt handler will make the code a bit nicer and less error prone
when we begin to handle those.
The slight functional change in this patch (queueing work while holding
the spinlock) is intentional as it makes a subsequent patch a bit nicer.
The change should also only effect HSW platforms.
Based on patches from:
CC: Haihao Xiang <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 125b45a..98af4fe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -843,6 +843,7 @@ static void snb_gt_irq_handler(struct drm_device *dev,
ivybridge_handle_parity_error(dev);
}
+/* Legacy way of handling PM interrupts */
static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
u32 pm_iir)
{
@@ -922,6 +923,31 @@ static void dp_aux_irq_handler(struct drm_device *dev)
wake_up_all(&dev_priv->gmbus_wait_queue);
}
+/* Unlike gen6_queue_rps_work() from which this function is originally derived,
+ * we must be able to deal with other PM interrupts. This is complicated because
+ * of the way in which we use the masks to defer the RPS work (which for
+ * posterity is necessary because of forcewake).
+ */
+static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
+ u32 pm_iir)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->rps.lock, flags);
+ dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
+ if (dev_priv->rps.pm_iir) {
+ I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
+ /* We never want to mask useful interrupts. (also posting read) */
+ WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
+ /* TODO: if queue_work is slow, move it out of the spinlock */
+ queue_work(dev_priv->wq, &dev_priv->rps.work);
+ }
+ spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+
+ if (pm_iir & ~GEN6_PM_DEFERRED_EVENTS)
+ DRM_ERROR("Unexpected PM interrupted\n");
+}
+
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *) arg;
@@ -1232,7 +1258,9 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
pm_iir = I915_READ(GEN6_PMIIR);
if (pm_iir) {
- if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ if (IS_HASWELL(dev))
+ hsw_pm_irq_handler(dev_priv, pm_iir);
+ else if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
ret = IRQ_HANDLED;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+
2013-04-28 0:59 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
@ 2013-05-28 13:00 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 13:00 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:19PM -0700, Ben Widawsky wrote:
> HSW has some special requirements for the VEBOX. Splitting out the
> interrupt handler will make the code a bit nicer and less error prone
> when we begin to handle those.
>
> The slight functional change in this patch (queueing work while holding
> the spinlock) is intentional as it makes a subsequent patch a bit nicer.
> The change should also only effect HSW platforms.
>
> Based on patches from:
> CC: Haihao Xiang <haihao.xiang@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (7 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 13:30 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
` (11 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
PM interrupts have an expanded role on HSW. It helps route the EBOX
interrupts. This patch is necessary to make the existing code which
touches the mask, and enable registers more friendly to other code paths
that also will need these registers.
To be more explicit:
At preinstall all interrupts are masked and disabled. This implies that
preinstall should always happen before any enabling/disabling of RPS or
other interrupts.
The PMIMR is touched by the workqueue, so enable/disable touch IER and
IIR. Similarly, the code currently expects IMR has no use outside of the
RPS related interrupts so they unconditionally set 0, or ~0. We could
use IER in the workqueue, and IMR elsewhere, but since the workqueue
use-case is more transient the existing usage makes sense.
Disable RPS events:
IER := IER & ~GEN6_PM_RPS_EVENTS // Disable RPS related interrupts
IIR := GEN6_PM_RPS_EVENTS // Disable any outstanding interrupts
Enable RPS events:
IER := IER | GEN6_PM_RPS_EVENTS // Enable the RPS related interrupts
IIR := GEN6_PM_RPS_EVENTS // Make sure there were no leftover events
(really shouldn't happen)
v2: Shouldn't destroy PMIIR or PMIMR VEBOX interrupt state in
enable/disable rps functions (Haihao)
v3: Bug found by Chris where we were clearing the wrong bits at rps
disable.
expanded commit message
v4: v3 was based off the wrong branch
v5: Updated for VLV
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 17 +++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
3 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98af4fe..13ea6c2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -701,10 +701,11 @@ static void gen6_pm_rps_work(struct work_struct *work)
pm_iir = dev_priv->rps.pm_iir;
dev_priv->rps.pm_iir = 0;
pm_imr = I915_READ(GEN6_PMIMR);
- I915_WRITE(GEN6_PMIMR, 0);
+ /* Make sure not to corrupt PMIMR state used by ringbuffer code */
+ I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
spin_unlock_irq(&dev_priv->rps.lock);
- if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
+ if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
return;
mutex_lock(&dev_priv->rps.hw_lock);
@@ -934,17 +935,17 @@ static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
unsigned long flags;
spin_lock_irqsave(&dev_priv->rps.lock, flags);
- dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
+ dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
if (dev_priv->rps.pm_iir) {
I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
/* We never want to mask useful interrupts. (also posting read) */
- WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
+ WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
/* TODO: if queue_work is slow, move it out of the spinlock */
queue_work(dev_priv->wq, &dev_priv->rps.work);
}
spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
- if (pm_iir & ~GEN6_PM_DEFERRED_EVENTS)
+ if (pm_iir & ~GEN6_PM_RPS_EVENTS)
DRM_ERROR("Unexpected PM interrupted\n");
}
@@ -1019,7 +1020,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
gmbus_irq_handler(dev);
- if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ if (pm_iir & GEN6_PM_RPS_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GTIIR, gt_iir);
@@ -1260,7 +1261,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
if (pm_iir) {
if (IS_HASWELL(dev))
hsw_pm_irq_handler(dev_priv, pm_iir);
- else if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ else if (pm_iir & GEN6_PM_RPS_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
ret = IRQ_HANDLED;
@@ -1375,7 +1376,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
ironlake_handle_rps_change(dev);
- if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GTIIR, gt_iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5dae1d9..4485dfa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4518,7 +4518,7 @@
#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
-#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
+#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
GEN6_PM_RP_DOWN_THRESHOLD | \
GEN6_PM_RP_DOWN_TIMEOUT)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3534a71..d3dd043 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2534,7 +2534,7 @@ static void gen6_disable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
- I915_WRITE(GEN6_PMIER, 0);
+ I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
/* Complete PM interrupt masking here doesn't race with the rps work
* item again unmasking PM interrupts because that is using a different
* register (PMIMR) to mask PM interrupts. The only risk is in leaving
@@ -2563,7 +2563,7 @@ static void valleyview_disable_rps(struct drm_device *dev)
dev_priv->rps.pm_iir = 0;
spin_unlock_irq(&dev_priv->rps.lock);
- I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+ I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
}
int intel_enable_rc6(const struct drm_device *dev)
@@ -2720,12 +2720,12 @@ static void gen6_enable_rps(struct drm_device *dev)
gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
/* requires MSI enabled */
- I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
spin_lock_irq(&dev_priv->rps.lock);
WARN_ON(dev_priv->rps.pm_iir != 0);
- I915_WRITE(GEN6_PMIMR, 0);
+ I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
spin_unlock_irq(&dev_priv->rps.lock);
- /* enable all PM interrupts */
+ /* unmask all PM interrupts */
I915_WRITE(GEN6_PMINTRMSK, 0);
rc6vids = 0;
@@ -2937,7 +2937,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
valleyview_set_rps(dev_priv->dev, rpe);
/* requires MSI enabled */
- I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
spin_lock_irq(&dev_priv->rps.lock);
WARN_ON(dev_priv->rps.pm_iir != 0);
I915_WRITE(GEN6_PMIMR, 0);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive
2013-04-28 0:59 ` [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
@ 2013-05-28 13:30 ` Damien Lespiau
2013-05-28 18:02 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 13:30 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:20PM -0700, Ben Widawsky wrote:
> @@ -2720,12 +2720,12 @@ static void gen6_enable_rps(struct drm_device *dev)
> gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
>
> /* requires MSI enabled */
> - I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
> + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
> spin_lock_irq(&dev_priv->rps.lock);
> WARN_ON(dev_priv->rps.pm_iir != 0);
> - I915_WRITE(GEN6_PMIMR, 0);
> + I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
You're not unmasking the RPS interrupts in PMIMR here now. I'm missing
how they are enabled now.
> spin_unlock_irq(&dev_priv->rps.lock);
> - /* enable all PM interrupts */
> + /* unmask all PM interrupts */
> I915_WRITE(GEN6_PMINTRMSK, 0);
>
> rc6vids = 0;
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive
2013-05-28 13:30 ` Damien Lespiau
@ 2013-05-28 18:02 ` Ben Widawsky
0 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-28 18:02 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 28, 2013 at 02:30:56PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:20PM -0700, Ben Widawsky wrote:
> > @@ -2720,12 +2720,12 @@ static void gen6_enable_rps(struct drm_device *dev)
> > gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
> >
> > /* requires MSI enabled */
> > - I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
> > + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
> > spin_lock_irq(&dev_priv->rps.lock);
> > WARN_ON(dev_priv->rps.pm_iir != 0);
> > - I915_WRITE(GEN6_PMIMR, 0);
> > + I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
>
> You're not unmasking the RPS interrupts in PMIMR here now. I'm missing
> how they are enabled now.
You are right. It's fixed in a later patch IFF we have VEBOX, but would
regress on IVB and HSW. Both this patch, and that are easily fixed. BRB.
>
> > spin_unlock_irq(&dev_priv->rps.lock); - /* enable all PM
> > interrupts */ + /* unmask all PM interrupts */
> > I915_WRITE(GEN6_PMINTRMSK, 0);
> >
> > rc6vids = 0;
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (8 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 13:37 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 11/18] drm/i915: Add PM regs to pre install Ben Widawsky
` (10 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 13ea6c2..21b09cd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2502,6 +2502,31 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
POSTING_READ(SDEIER);
}
+static void ivybridge_irq_preinstall(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ atomic_set(&dev_priv->irq_received, 0);
+
+ I915_WRITE(HWSTAM, 0xeffe);
+
+ /* XXX hotplug from PCH */
+
+ I915_WRITE(DEIMR, 0xffffffff);
+ I915_WRITE(DEIER, 0x0);
+ POSTING_READ(DEIER);
+
+ /* and GT */
+ I915_WRITE(GTIMR, 0xffffffff);
+ I915_WRITE(GTIER, 0x0);
+ POSTING_READ(GTIER);
+
+ /* south display irq */
+ I915_WRITE(SDEIMR, 0xffffffff);
+ I915_WRITE(SDEIER, 0x0);
+ POSTING_READ(SDEIER);
+}
+
static void valleyview_irq_preinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -3500,7 +3525,7 @@ void intel_irq_init(struct drm_device *dev)
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
/* Share pre & uninstall handlers with ILK/SNB */
dev->driver->irq_handler = ivybridge_irq_handler;
- dev->driver->irq_preinstall = ironlake_irq_preinstall;
+ dev->driver->irq_preinstall = ivybridge_irq_preinstall;
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
dev->driver->enable_vblank = ivybridge_enable_vblank;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall
2013-04-28 0:59 ` [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
@ 2013-05-28 13:37 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 13:37 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:21PM -0700, Ben Widawsky wrote:
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 13ea6c2..21b09cd 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2502,6 +2502,31 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
> POSTING_READ(SDEIER);
> }
>
> +static void ivybridge_irq_preinstall(struct drm_device *dev)
> +{
> + drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> +
> + atomic_set(&dev_priv->irq_received, 0);
> +
> + I915_WRITE(HWSTAM, 0xeffe);
> +
> + /* XXX hotplug from PCH */
> +
> + I915_WRITE(DEIMR, 0xffffffff);
> + I915_WRITE(DEIER, 0x0);
> + POSTING_READ(DEIER);
> +
> + /* and GT */
> + I915_WRITE(GTIMR, 0xffffffff);
> + I915_WRITE(GTIER, 0x0);
> + POSTING_READ(GTIER);
you're missing a:
if (HAS_PCH_NOP(dev))
return;
that you've added in the ironlake path since that patch.
> +
> + /* south display irq */
> + I915_WRITE(SDEIMR, 0xffffffff);
> + I915_WRITE(SDEIER, 0x0);
> + POSTING_READ(SDEIER);
> +}
SDEIER is set to 0xffffffff now with a big comment explaining why.
> static void valleyview_irq_preinstall(struct drm_device *dev)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> @@ -3500,7 +3525,7 @@ void intel_irq_init(struct drm_device *dev)
> } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> /* Share pre & uninstall handlers with ILK/SNB */
> dev->driver->irq_handler = ivybridge_irq_handler;
> - dev->driver->irq_preinstall = ironlake_irq_preinstall;
> + dev->driver->irq_preinstall = ivybridge_irq_preinstall;
> dev->driver->irq_postinstall = ivybridge_irq_postinstall;
> dev->driver->irq_uninstall = ironlake_irq_uninstall;
> dev->driver->enable_vblank = ivybridge_enable_vblank;
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 11/18] drm/i915: Add PM regs to pre install
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (9 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 13:38 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 12/18] drm/i915: Convert irq_refounct to struct Ben Widawsky
` (9 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 21b09cd..4a1b7f5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2525,6 +2525,11 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
I915_WRITE(SDEIMR, 0xffffffff);
I915_WRITE(SDEIER, 0x0);
POSTING_READ(SDEIER);
+
+ /* Power management */
+ I915_WRITE(GEN6_PMIMR, 0xffffffff);
+ I915_WRITE(GEN6_PMIER, 0x0);
+ POSTING_READ(GEN6_PMIER);
}
static void valleyview_irq_preinstall(struct drm_device *dev)
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 11/18] drm/i915: Add PM regs to pre install
2013-04-28 0:59 ` [PATCH 11/18] drm/i915: Add PM regs to pre install Ben Widawsky
@ 2013-05-28 13:38 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 13:38 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:22PM -0700, Ben Widawsky wrote:
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 21b09cd..4a1b7f5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2525,6 +2525,11 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
> I915_WRITE(SDEIMR, 0xffffffff);
> I915_WRITE(SDEIER, 0x0);
> POSTING_READ(SDEIER);
> +
> + /* Power management */
> + I915_WRITE(GEN6_PMIMR, 0xffffffff);
> + I915_WRITE(GEN6_PMIER, 0x0);
> + POSTING_READ(GEN6_PMIER);
> }
With the comments on the previous patch, I guess this shoulde be put
before the if (HAS_PCH_NOP) return; block and thus before the DE
init.
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 12/18] drm/i915: Convert irq_refounct to struct
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (10 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 11/18] drm/i915: Add PM regs to pre install Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 13:40 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 13/18] drm/i915: consolidate interrupt naming scheme Ben Widawsky
` (8 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
It's overkill on older gens, but it's useful for newer gens.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++--------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +++-
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 01937f3..a737c66 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -783,7 +783,7 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
@@ -801,7 +801,7 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
dev_priv->gt_irq_mask |= ring->irq_enable_mask;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
@@ -820,7 +820,7 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
dev_priv->irq_mask &= ~ring->irq_enable_mask;
I915_WRITE(IMR, dev_priv->irq_mask);
POSTING_READ(IMR);
@@ -838,7 +838,7 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
dev_priv->irq_mask |= ring->irq_enable_mask;
I915_WRITE(IMR, dev_priv->irq_mask);
POSTING_READ(IMR);
@@ -857,7 +857,7 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
dev_priv->irq_mask &= ~ring->irq_enable_mask;
I915_WRITE16(IMR, dev_priv->irq_mask);
POSTING_READ16(IMR);
@@ -875,7 +875,7 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
dev_priv->irq_mask |= ring->irq_enable_mask;
I915_WRITE16(IMR, dev_priv->irq_mask);
POSTING_READ16(IMR);
@@ -968,7 +968,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
gen6_gt_force_wake_get(dev_priv);
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
GEN6_RENDER_L3_PARITY_ERROR));
@@ -991,7 +991,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
else
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index cb70f37..24b4413 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -68,7 +68,9 @@ struct intel_ring_buffer {
*/
u32 last_retired_head;
- u32 irq_refcount; /* protected by dev_priv->irq_lock */
+ struct {
+ u32 gt;
+ } irq_refcount; /* protected by dev_priv->irq_lock */
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
u32 trace_irq_seqno;
u32 sync_seqno[I915_NUM_RINGS-1];
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 13/18] drm/i915: consolidate interrupt naming scheme
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (11 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 12/18] drm/i915: Convert irq_refounct to struct Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 14:01 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 14/18] drm/i915: vebox interrupt get/put Ben Widawsky
` (7 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
The motivation here is we're going to add some new interrupt definitions
and handling outside of the GT interrupts which is all we've managed so
far (with some RPS exceptions). By consolidating the names in the future
we can make thing a bit cleaner as we don't need to define register
names twice, and we can leverage pretty decent overlap in HW registers
since ILK.
To explain briefly what is in the comments: there are two sets of
interrupt masking/enabling registers. At least so far, the definitions
of the two sets overlap. The old code setup distinct names for
interrupts in each set, ie. one for global, and one for ring. This made
things confusing when using the wrong defines in the wrong places.
rebase: Modified VLV bits
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 101 ++++++++++++++------------------
drivers/gpu/drm/i915/intel_ringbuffer.c | 17 +++---
3 files changed, 79 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4a1b7f5..06e254a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -781,7 +781,7 @@ static void ivybridge_parity_work(struct work_struct *work)
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@@ -813,7 +813,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev)
return;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@@ -825,22 +825,21 @@ static void snb_gt_irq_handler(struct drm_device *dev,
u32 gt_iir)
{
- if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
- GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
+ if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
notify_ring(dev, &dev_priv->ring[RCS]);
- if (gt_iir & GEN6_BSD_USER_INTERRUPT)
+ if (gt_iir & GT_BSD_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[VCS]);
- if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
+ if (gt_iir & GT_BLT_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[BCS]);
- if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
- GT_GEN6_BSD_CS_ERROR_INTERRUPT |
- GT_RENDER_CS_ERROR_INTERRUPT)) {
+ if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
+ GT_BSD_CS_ERROR_INTERRUPT |
+ GT_RENDER_MASTER_ERROR_INTERRUPT)) {
DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
i915_handle_error(dev, false);
}
- if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
+ if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
ivybridge_handle_parity_error(dev);
}
@@ -1284,9 +1283,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
struct drm_i915_private *dev_priv,
u32 gt_iir)
{
- if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+ if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
notify_ring(dev, &dev_priv->ring[RCS]);
- if (gt_iir & GT_BSD_USER_INTERRUPT)
+ if (gt_iir & ILK_BSD_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[VCS]);
}
@@ -2629,7 +2628,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
- u32 render_irqs;
+ u32 gt_irqs;
dev_priv->irq_mask = ~display_mask;
@@ -2644,17 +2643,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+ gt_irqs = GT_RENDER_USER_INTERRUPT;
+
if (IS_GEN6(dev))
- render_irqs =
- GT_USER_INTERRUPT |
- GEN6_BSD_USER_INTERRUPT |
- GEN6_BLITTER_USER_INTERRUPT;
+ gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
else
- render_irqs =
- GT_USER_INTERRUPT |
- GT_PIPE_NOTIFY |
- GT_BSD_USER_INTERRUPT;
- I915_WRITE(GTIER, render_irqs);
+ gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | ILK_BSD_USER_INTERRUPT;
+
+ I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
ibx_irq_postinstall(dev);
@@ -2680,7 +2676,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
DE_PLANEA_FLIP_DONE_IVB |
DE_AUX_CHANNEL_A_IVB |
DE_ERR_INT_IVB;
- u32 render_irqs;
+ u32 gt_irqs;
dev_priv->irq_mask = ~display_mask;
@@ -2695,14 +2691,14 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
DE_PIPEA_VBLANK_IVB);
POSTING_READ(DEIER);
- dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
- render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
- GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
- I915_WRITE(GTIER, render_irqs);
+ gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
+ GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+ I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
ibx_irq_postinstall(dev);
@@ -2713,9 +2709,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
static int valleyview_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ u32 gt_irqs;
u32 enable_mask;
u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
- u32 render_irqs;
u16 msid;
enable_mask = I915_DISPLAY_PORT_INTERRUPT;
@@ -2759,9 +2755,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
- render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
- GEN6_BLITTER_USER_INTERRUPT;
- I915_WRITE(GTIER, render_irqs);
+ gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
+ GT_BLT_USER_INTERRUPT;
+ I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
/* ack & enable invalid PTE error interrupts */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4485dfa..399d041 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -716,24 +716,6 @@
#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
-#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
-#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
-#define I915_HWB_OOM_INTERRUPT (1<<13)
-#define I915_SYNC_STATUS_INTERRUPT (1<<12)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
-#define I915_DEBUG_INTERRUPT (1<<2)
-#define I915_USER_INTERRUPT (1<<1)
-#define I915_ASLE_INTERRUPT (1<<0)
-#define I915_BSD_USER_INTERRUPT (1<<25)
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
#define EIR 0x020b0
#define EMR 0x020b4
@@ -845,28 +827,6 @@
#define CACHE_MODE_1 0x7004 /* IVB+ */
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
-/* GEN6 interrupt control
- * Note that the per-ring interrupt bits do alias with the global interrupt bits
- * in GTIMR. */
-#define GEN6_RENDER_HWSTAM 0x2098
-#define GEN6_RENDER_IMR 0x20a8
-#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
-#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
-#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
-#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
-#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
-#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
-#define GEN6_RENDER_SYNC_STATUS (1 << 2)
-#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
-#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
-
-#define GEN6_BLITTER_HWSTAM 0x22098
-#define GEN6_BLITTER_IMR 0x220a8
-#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
-#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
-#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
-#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
-
#define GEN6_BLITTER_ECOSKPD 0x221d0
#define GEN6_BLITTER_LOCK_SHIFT 16
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
@@ -877,9 +837,49 @@
#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
#define GEN6_BSD_GO_INDICATOR (1 << 4)
-#define GEN6_BSD_HWSTAM 0x12098
-#define GEN6_BSD_IMR 0x120a8
-#define GEN6_BSD_USER_INTERRUPT (1 << 12)
+/* On modern GEN architectures interrupt control consists of two sets
+ * of registers. The first set pertains to the ring generating the
+ * interrupt. The second control is for the functional block generating the
+ * interrupt. These are PM, GT, DE, etc.
+ *
+ * Luckily *knocks on wood* all the ring interrupt bits match up with the
+ * GT interrupt bits, so we don't need to duplicate the defines.
+ *
+ * These defines should cover us well from SNB->HSW with minor exceptions
+ * it can also work on ILK.
+ */
+#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
+#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
+#define GT_BLT_USER_INTERRUPT (1 << 22)
+#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
+#define GT_BSD_USER_INTERRUPT (1 << 12)
+#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
+#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
+#define GT_RENDER_MASTER_ERROR_INTERRUPT (1 << 3)
+#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
+#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
+#define GT_RENDER_USER_INTERRUPT (1 << 0)
+
+/* These are all the "old" interrupts */
+#define ILK_BSD_USER_INTERRUPT (1<<5)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
+#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
+#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
+#define I915_HWB_OOM_INTERRUPT (1<<13)
+#define I915_SYNC_STATUS_INTERRUPT (1<<12)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
+#define I915_DEBUG_INTERRUPT (1<<2)
+#define I915_USER_INTERRUPT (1<<1)
+#define I915_ASLE_INTERRUPT (1<<0)
+#define I915_BSD_USER_INTERRUPT (1 << 25)
#define GEN6_BSD_RNCID 0x12198
@@ -3665,21 +3665,6 @@
#define DEIIR 0x44008
#define DEIER 0x4400c
-/* GT interrupt.
- * Note that for gen6+ the ring-specific interrupt bits do alias with the
- * corresponding bits in the per-ring interrupt control registers. */
-#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
-#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
-#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
-#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
-#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
-#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
-#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
-#define GT_PIPE_NOTIFY (1 << 4)
-#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
-#define GT_SYNC_STATUS (1 << 2)
-#define GT_USER_INTERRUPT (1 << 0)
-
#define GTISR 0x44010
#define GTIMR 0x44014
#define GTIIR 0x44018
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a737c66..ccfa1f9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -556,7 +556,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
if (HAS_L3_GPU_CACHE(dev))
- I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+ I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
return ret;
}
@@ -971,7 +971,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
if (ring->irq_refcount.gt++ == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
- GEN6_RENDER_L3_PARITY_ERROR));
+ GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
else
I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
@@ -993,7 +993,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--ring->irq_refcount.gt == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
- I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+ I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
else
I915_WRITE_IMR(ring, ~0);
dev_priv->gt_irq_mask |= ring->irq_enable_mask;
@@ -1669,7 +1669,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->flush = gen6_render_ring_flush;
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
- ring->irq_enable_mask = GT_USER_INTERRUPT;
+ ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->sync_to = gen6_ring_sync;
@@ -1688,7 +1688,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->set_seqno = pc_render_set_seqno;
ring->irq_get = gen5_ring_get_irq;
ring->irq_put = gen5_ring_put_irq;
- ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
+ ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
+ GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
ring->add_request = i9xx_add_request;
if (INTEL_INFO(dev)->gen < 4)
@@ -1830,7 +1831,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
+ ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
@@ -1850,7 +1851,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->get_seqno = ring_get_seqno;
ring->set_seqno = ring_set_seqno;
if (IS_GEN5(dev)) {
- ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+ ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
ring->irq_get = gen5_ring_get_irq;
ring->irq_put = gen5_ring_put_irq;
} else {
@@ -1879,7 +1880,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
+ ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 13/18] drm/i915: consolidate interrupt naming scheme
2013-04-28 0:59 ` [PATCH 13/18] drm/i915: consolidate interrupt naming scheme Ben Widawsky
@ 2013-05-28 14:01 ` Damien Lespiau
2013-05-28 18:50 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 14:01 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:24PM -0700, Ben Widawsky wrote:
> The motivation here is we're going to add some new interrupt definitions
> and handling outside of the GT interrupts which is all we've managed so
> far (with some RPS exceptions). By consolidating the names in the future
> we can make thing a bit cleaner as we don't need to define register
> names twice, and we can leverage pretty decent overlap in HW registers
> since ILK.
>
> To explain briefly what is in the comments: there are two sets of
> interrupt masking/enabling registers. At least so far, the definitions
> of the two sets overlap. The old code setup distinct names for
> interrupts in each set, ie. one for global, and one for ring. This made
> things confusing when using the wrong defines in the wrong places.
>
> rebase: Modified VLV bits
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
With or without the naming biskeshed below:
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++---------
> drivers/gpu/drm/i915/i915_reg.h | 101 ++++++++++++++------------------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 17 +++---
> 3 files changed, 79 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4a1b7f5..06e254a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -781,7 +781,7 @@ static void ivybridge_parity_work(struct work_struct *work)
> I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> - dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> + dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
>
> @@ -813,7 +813,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev)
> return;
>
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> - dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> + dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
>
> @@ -825,22 +825,21 @@ static void snb_gt_irq_handler(struct drm_device *dev,
> u32 gt_iir)
> {
>
> - if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
> - GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
> + if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
> notify_ring(dev, &dev_priv->ring[RCS]);
> - if (gt_iir & GEN6_BSD_USER_INTERRUPT)
> + if (gt_iir & GT_BSD_USER_INTERRUPT)
> notify_ring(dev, &dev_priv->ring[VCS]);
> - if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
> + if (gt_iir & GT_BLT_USER_INTERRUPT)
> notify_ring(dev, &dev_priv->ring[BCS]);
>
> - if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
> - GT_GEN6_BSD_CS_ERROR_INTERRUPT |
> - GT_RENDER_CS_ERROR_INTERRUPT)) {
> + if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
> + GT_BSD_CS_ERROR_INTERRUPT |
> + GT_RENDER_MASTER_ERROR_INTERRUPT)) {
If we ware in the naming domain here, not sure why the CS master error
for render would have a different name than the others,
GT_RENDER_CS_ERROR_INTERRUPT looked good to me.
> DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
> i915_handle_error(dev, false);
> }
>
> - if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
> + if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
> ivybridge_handle_parity_error(dev);
> }
>
> @@ -1284,9 +1283,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
> struct drm_i915_private *dev_priv,
> u32 gt_iir)
> {
> - if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
> + if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
> notify_ring(dev, &dev_priv->ring[RCS]);
> - if (gt_iir & GT_BSD_USER_INTERRUPT)
> + if (gt_iir & ILK_BSD_USER_INTERRUPT)
> notify_ring(dev, &dev_priv->ring[VCS]);
> }
>
> @@ -2629,7 +2628,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
> DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
> DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
> - u32 render_irqs;
> + u32 gt_irqs;
>
> dev_priv->irq_mask = ~display_mask;
>
> @@ -2644,17 +2643,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> I915_WRITE(GTIIR, I915_READ(GTIIR));
> I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
>
> + gt_irqs = GT_RENDER_USER_INTERRUPT;
> +
> if (IS_GEN6(dev))
> - render_irqs =
> - GT_USER_INTERRUPT |
> - GEN6_BSD_USER_INTERRUPT |
> - GEN6_BLITTER_USER_INTERRUPT;
> + gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> else
> - render_irqs =
> - GT_USER_INTERRUPT |
> - GT_PIPE_NOTIFY |
> - GT_BSD_USER_INTERRUPT;
> - I915_WRITE(GTIER, render_irqs);
> + gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | ILK_BSD_USER_INTERRUPT;
> +
> + I915_WRITE(GTIER, gt_irqs);
> POSTING_READ(GTIER);
>
> ibx_irq_postinstall(dev);
> @@ -2680,7 +2676,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> DE_PLANEA_FLIP_DONE_IVB |
> DE_AUX_CHANNEL_A_IVB |
> DE_ERR_INT_IVB;
> - u32 render_irqs;
> + u32 gt_irqs;
>
> dev_priv->irq_mask = ~display_mask;
>
> @@ -2695,14 +2691,14 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> DE_PIPEA_VBLANK_IVB);
> POSTING_READ(DEIER);
>
> - dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> + dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
>
> I915_WRITE(GTIIR, I915_READ(GTIIR));
> I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
>
> - render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
> - GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> - I915_WRITE(GTIER, render_irqs);
> + gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
> + GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> + I915_WRITE(GTIER, gt_irqs);
> POSTING_READ(GTIER);
>
> ibx_irq_postinstall(dev);
> @@ -2713,9 +2709,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> static int valleyview_irq_postinstall(struct drm_device *dev)
> {
> drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> + u32 gt_irqs;
> u32 enable_mask;
> u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> - u32 render_irqs;
> u16 msid;
>
> enable_mask = I915_DISPLAY_PORT_INTERRUPT;
> @@ -2759,9 +2755,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
> I915_WRITE(GTIIR, I915_READ(GTIIR));
> I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
>
> - render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
> - GEN6_BLITTER_USER_INTERRUPT;
> - I915_WRITE(GTIER, render_irqs);
> + gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
> + GT_BLT_USER_INTERRUPT;
> + I915_WRITE(GTIER, gt_irqs);
> POSTING_READ(GTIER);
>
> /* ack & enable invalid PTE error interrupts */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4485dfa..399d041 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -716,24 +716,6 @@
> #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
> #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
> #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
> -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
> -#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
> -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
> -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
> -#define I915_HWB_OOM_INTERRUPT (1<<13)
> -#define I915_SYNC_STATUS_INTERRUPT (1<<12)
> -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
> -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
> -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
> -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
> -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
> -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
> -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
> -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
> -#define I915_DEBUG_INTERRUPT (1<<2)
> -#define I915_USER_INTERRUPT (1<<1)
> -#define I915_ASLE_INTERRUPT (1<<0)
> -#define I915_BSD_USER_INTERRUPT (1<<25)
> #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
> #define EIR 0x020b0
> #define EMR 0x020b4
> @@ -845,28 +827,6 @@
> #define CACHE_MODE_1 0x7004 /* IVB+ */
> #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
>
> -/* GEN6 interrupt control
> - * Note that the per-ring interrupt bits do alias with the global interrupt bits
> - * in GTIMR. */
> -#define GEN6_RENDER_HWSTAM 0x2098
> -#define GEN6_RENDER_IMR 0x20a8
> -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
> -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
> -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
> -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
> -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
> -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
> -#define GEN6_RENDER_SYNC_STATUS (1 << 2)
> -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
> -#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
> -
> -#define GEN6_BLITTER_HWSTAM 0x22098
> -#define GEN6_BLITTER_IMR 0x220a8
> -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
> -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
> -#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
> -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
> -
> #define GEN6_BLITTER_ECOSKPD 0x221d0
> #define GEN6_BLITTER_LOCK_SHIFT 16
> #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
> @@ -877,9 +837,49 @@
> #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
> #define GEN6_BSD_GO_INDICATOR (1 << 4)
>
> -#define GEN6_BSD_HWSTAM 0x12098
> -#define GEN6_BSD_IMR 0x120a8
> -#define GEN6_BSD_USER_INTERRUPT (1 << 12)
> +/* On modern GEN architectures interrupt control consists of two sets
> + * of registers. The first set pertains to the ring generating the
> + * interrupt. The second control is for the functional block generating the
> + * interrupt. These are PM, GT, DE, etc.
> + *
> + * Luckily *knocks on wood* all the ring interrupt bits match up with the
> + * GT interrupt bits, so we don't need to duplicate the defines.
> + *
> + * These defines should cover us well from SNB->HSW with minor exceptions
> + * it can also work on ILK.
> + */
> +#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
> +#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
> +#define GT_BLT_USER_INTERRUPT (1 << 22)
> +#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
> +#define GT_BSD_USER_INTERRUPT (1 << 12)
> +#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
> +#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
> +#define GT_RENDER_MASTER_ERROR_INTERRUPT (1 << 3)
> +#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
> +#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
> +#define GT_RENDER_USER_INTERRUPT (1 << 0)
> +
> +/* These are all the "old" interrupts */
> +#define ILK_BSD_USER_INTERRUPT (1<<5)
> +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
> +#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
> +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
> +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
> +#define I915_HWB_OOM_INTERRUPT (1<<13)
> +#define I915_SYNC_STATUS_INTERRUPT (1<<12)
> +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
> +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
> +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
> +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
> +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
> +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
> +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
> +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
> +#define I915_DEBUG_INTERRUPT (1<<2)
> +#define I915_USER_INTERRUPT (1<<1)
> +#define I915_ASLE_INTERRUPT (1<<0)
> +#define I915_BSD_USER_INTERRUPT (1 << 25)
>
> #define GEN6_BSD_RNCID 0x12198
>
> @@ -3665,21 +3665,6 @@
> #define DEIIR 0x44008
> #define DEIER 0x4400c
>
> -/* GT interrupt.
> - * Note that for gen6+ the ring-specific interrupt bits do alias with the
> - * corresponding bits in the per-ring interrupt control registers. */
> -#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
> -#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
> -#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
> -#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
> -#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
> -#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
> -#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
> -#define GT_PIPE_NOTIFY (1 << 4)
> -#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
> -#define GT_SYNC_STATUS (1 << 2)
> -#define GT_USER_INTERRUPT (1 << 0)
> -
> #define GTISR 0x44010
> #define GTIMR 0x44014
> #define GTIIR 0x44018
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a737c66..ccfa1f9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -556,7 +556,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> if (HAS_L3_GPU_CACHE(dev))
> - I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
> + I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
>
> return ret;
> }
> @@ -971,7 +971,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
> if (ring->irq_refcount.gt++ == 0) {
> if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
> I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
> - GEN6_RENDER_L3_PARITY_ERROR));
> + GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
> else
> I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
> dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
> @@ -993,7 +993,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
> spin_lock_irqsave(&dev_priv->irq_lock, flags);
> if (--ring->irq_refcount.gt == 0) {
> if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
> - I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
> + I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
> else
> I915_WRITE_IMR(ring, ~0);
> dev_priv->gt_irq_mask |= ring->irq_enable_mask;
> @@ -1669,7 +1669,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->flush = gen6_render_ring_flush;
> ring->irq_get = gen6_ring_get_irq;
> ring->irq_put = gen6_ring_put_irq;
> - ring->irq_enable_mask = GT_USER_INTERRUPT;
> + ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> ring->sync_to = gen6_ring_sync;
> @@ -1688,7 +1688,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->set_seqno = pc_render_set_seqno;
> ring->irq_get = gen5_ring_get_irq;
> ring->irq_put = gen5_ring_put_irq;
> - ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
> + ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
> + GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> } else {
> ring->add_request = i9xx_add_request;
> if (INTEL_INFO(dev)->gen < 4)
> @@ -1830,7 +1831,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->add_request = gen6_add_request;
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> - ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
> + ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> ring->irq_get = gen6_ring_get_irq;
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> @@ -1850,7 +1851,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->get_seqno = ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> if (IS_GEN5(dev)) {
> - ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> + ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> ring->irq_get = gen5_ring_get_irq;
> ring->irq_put = gen5_ring_put_irq;
> } else {
> @@ -1879,7 +1880,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->add_request = gen6_add_request;
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> - ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
> + ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
> ring->irq_get = gen6_ring_get_irq;
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 13/18] drm/i915: consolidate interrupt naming scheme
2013-05-28 14:01 ` Damien Lespiau
@ 2013-05-28 18:50 ` Ben Widawsky
2013-05-29 15:51 ` Damien Lespiau
0 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-28 18:50 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 28, 2013 at 03:01:54PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:24PM -0700, Ben Widawsky wrote:
> > The motivation here is we're going to add some new interrupt definitions
> > and handling outside of the GT interrupts which is all we've managed so
> > far (with some RPS exceptions). By consolidating the names in the future
> > we can make thing a bit cleaner as we don't need to define register
> > names twice, and we can leverage pretty decent overlap in HW registers
> > since ILK.
> >
> > To explain briefly what is in the comments: there are two sets of
> > interrupt masking/enabling registers. At least so far, the definitions
> > of the two sets overlap. The old code setup distinct names for
> > interrupts in each set, ie. one for global, and one for ring. This made
> > things confusing when using the wrong defines in the wrong places.
> >
> > rebase: Modified VLV bits
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>
>
> With or without the naming biskeshed below:
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>
> --
> Damien
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++---------
> > drivers/gpu/drm/i915/i915_reg.h | 101 ++++++++++++++------------------
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 17 +++---
> > 3 files changed, 79 insertions(+), 97 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 4a1b7f5..06e254a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -781,7 +781,7 @@ static void ivybridge_parity_work(struct work_struct *work)
> > I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> >
> > spin_lock_irqsave(&dev_priv->irq_lock, flags);
> > - dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> > + dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> > I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> > spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> >
> > @@ -813,7 +813,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev)
> > return;
> >
> > spin_lock_irqsave(&dev_priv->irq_lock, flags);
> > - dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> > + dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> > I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> > spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
> >
> > @@ -825,22 +825,21 @@ static void snb_gt_irq_handler(struct drm_device *dev,
> > u32 gt_iir)
> > {
> >
> > - if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
> > - GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
> > + if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
> > notify_ring(dev, &dev_priv->ring[RCS]);
> > - if (gt_iir & GEN6_BSD_USER_INTERRUPT)
> > + if (gt_iir & GT_BSD_USER_INTERRUPT)
> > notify_ring(dev, &dev_priv->ring[VCS]);
> > - if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
> > + if (gt_iir & GT_BLT_USER_INTERRUPT)
> > notify_ring(dev, &dev_priv->ring[BCS]);
> >
> > - if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
> > - GT_GEN6_BSD_CS_ERROR_INTERRUPT |
> > - GT_RENDER_CS_ERROR_INTERRUPT)) {
> > + if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
> > + GT_BSD_CS_ERROR_INTERRUPT |
> > + GT_RENDER_MASTER_ERROR_INTERRUPT)) {
>
> If we ware in the naming domain here, not sure why the CS master error
> for render would have a different name than the others,
> GT_RENDER_CS_ERROR_INTERRUPT looked good to me.
I was just copying the docs. I presume on earlier gens, maybe it meant
something else? It seems I accidently dropped the "CS" part though. I've
added that back, and left the MASTER.
"Render Command Parser Master Error"
>
> > DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
> > i915_handle_error(dev, false);
> > }
> >
> > - if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
> > + if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
> > ivybridge_handle_parity_error(dev);
> > }
> >
> > @@ -1284,9 +1283,9 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
> > struct drm_i915_private *dev_priv,
> > u32 gt_iir)
> > {
> > - if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
> > + if (gt_iir & (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
> > notify_ring(dev, &dev_priv->ring[RCS]);
> > - if (gt_iir & GT_BSD_USER_INTERRUPT)
> > + if (gt_iir & ILK_BSD_USER_INTERRUPT)
> > notify_ring(dev, &dev_priv->ring[VCS]);
> > }
> >
> > @@ -2629,7 +2628,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> > DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
> > DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
> > DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
> > - u32 render_irqs;
> > + u32 gt_irqs;
> >
> > dev_priv->irq_mask = ~display_mask;
> >
> > @@ -2644,17 +2643,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> > I915_WRITE(GTIIR, I915_READ(GTIIR));
> > I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> >
> > + gt_irqs = GT_RENDER_USER_INTERRUPT;
> > +
> > if (IS_GEN6(dev))
> > - render_irqs =
> > - GT_USER_INTERRUPT |
> > - GEN6_BSD_USER_INTERRUPT |
> > - GEN6_BLITTER_USER_INTERRUPT;
> > + gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> > else
> > - render_irqs =
> > - GT_USER_INTERRUPT |
> > - GT_PIPE_NOTIFY |
> > - GT_BSD_USER_INTERRUPT;
> > - I915_WRITE(GTIER, render_irqs);
> > + gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | ILK_BSD_USER_INTERRUPT;
> > +
> > + I915_WRITE(GTIER, gt_irqs);
> > POSTING_READ(GTIER);
> >
> > ibx_irq_postinstall(dev);
> > @@ -2680,7 +2676,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> > DE_PLANEA_FLIP_DONE_IVB |
> > DE_AUX_CHANNEL_A_IVB |
> > DE_ERR_INT_IVB;
> > - u32 render_irqs;
> > + u32 gt_irqs;
> >
> > dev_priv->irq_mask = ~display_mask;
> >
> > @@ -2695,14 +2691,14 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> > DE_PIPEA_VBLANK_IVB);
> > POSTING_READ(DEIER);
> >
> > - dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> > + dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> >
> > I915_WRITE(GTIIR, I915_READ(GTIIR));
> > I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> >
> > - render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
> > - GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
> > - I915_WRITE(GTIER, render_irqs);
> > + gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
> > + GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
> > + I915_WRITE(GTIER, gt_irqs);
> > POSTING_READ(GTIER);
> >
> > ibx_irq_postinstall(dev);
> > @@ -2713,9 +2709,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> > static int valleyview_irq_postinstall(struct drm_device *dev)
> > {
> > drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
> > + u32 gt_irqs;
> > u32 enable_mask;
> > u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
> > - u32 render_irqs;
> > u16 msid;
> >
> > enable_mask = I915_DISPLAY_PORT_INTERRUPT;
> > @@ -2759,9 +2755,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
> > I915_WRITE(GTIIR, I915_READ(GTIIR));
> > I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
> >
> > - render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
> > - GEN6_BLITTER_USER_INTERRUPT;
> > - I915_WRITE(GTIER, render_irqs);
> > + gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
> > + GT_BLT_USER_INTERRUPT;
> > + I915_WRITE(GTIER, gt_irqs);
> > POSTING_READ(GTIER);
> >
> > /* ack & enable invalid PTE error interrupts */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4485dfa..399d041 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -716,24 +716,6 @@
> > #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
> > #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
> > #define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
> > -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
> > -#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
> > -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
> > -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
> > -#define I915_HWB_OOM_INTERRUPT (1<<13)
> > -#define I915_SYNC_STATUS_INTERRUPT (1<<12)
> > -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
> > -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
> > -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
> > -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
> > -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
> > -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
> > -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
> > -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
> > -#define I915_DEBUG_INTERRUPT (1<<2)
> > -#define I915_USER_INTERRUPT (1<<1)
> > -#define I915_ASLE_INTERRUPT (1<<0)
> > -#define I915_BSD_USER_INTERRUPT (1<<25)
> > #define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
> > #define EIR 0x020b0
> > #define EMR 0x020b4
> > @@ -845,28 +827,6 @@
> > #define CACHE_MODE_1 0x7004 /* IVB+ */
> > #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
> >
> > -/* GEN6 interrupt control
> > - * Note that the per-ring interrupt bits do alias with the global interrupt bits
> > - * in GTIMR. */
> > -#define GEN6_RENDER_HWSTAM 0x2098
> > -#define GEN6_RENDER_IMR 0x20a8
> > -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
> > -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
> > -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
> > -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
> > -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
> > -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
> > -#define GEN6_RENDER_SYNC_STATUS (1 << 2)
> > -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
> > -#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
> > -
> > -#define GEN6_BLITTER_HWSTAM 0x22098
> > -#define GEN6_BLITTER_IMR 0x220a8
> > -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
> > -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
> > -#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
> > -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
> > -
> > #define GEN6_BLITTER_ECOSKPD 0x221d0
> > #define GEN6_BLITTER_LOCK_SHIFT 16
> > #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
> > @@ -877,9 +837,49 @@
> > #define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
> > #define GEN6_BSD_GO_INDICATOR (1 << 4)
> >
> > -#define GEN6_BSD_HWSTAM 0x12098
> > -#define GEN6_BSD_IMR 0x120a8
> > -#define GEN6_BSD_USER_INTERRUPT (1 << 12)
> > +/* On modern GEN architectures interrupt control consists of two sets
> > + * of registers. The first set pertains to the ring generating the
> > + * interrupt. The second control is for the functional block generating the
> > + * interrupt. These are PM, GT, DE, etc.
> > + *
> > + * Luckily *knocks on wood* all the ring interrupt bits match up with the
> > + * GT interrupt bits, so we don't need to duplicate the defines.
> > + *
> > + * These defines should cover us well from SNB->HSW with minor exceptions
> > + * it can also work on ILK.
> > + */
> > +#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
> > +#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
> > +#define GT_BLT_USER_INTERRUPT (1 << 22)
> > +#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
> > +#define GT_BSD_USER_INTERRUPT (1 << 12)
> > +#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
> > +#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
> > +#define GT_RENDER_MASTER_ERROR_INTERRUPT (1 << 3)
> > +#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
> > +#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
> > +#define GT_RENDER_USER_INTERRUPT (1 << 0)
> > +
> > +/* These are all the "old" interrupts */
> > +#define ILK_BSD_USER_INTERRUPT (1<<5)
> > +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
> > +#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
> > +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
> > +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
> > +#define I915_HWB_OOM_INTERRUPT (1<<13)
> > +#define I915_SYNC_STATUS_INTERRUPT (1<<12)
> > +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
> > +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
> > +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
> > +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
> > +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
> > +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
> > +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
> > +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
> > +#define I915_DEBUG_INTERRUPT (1<<2)
> > +#define I915_USER_INTERRUPT (1<<1)
> > +#define I915_ASLE_INTERRUPT (1<<0)
> > +#define I915_BSD_USER_INTERRUPT (1 << 25)
> >
> > #define GEN6_BSD_RNCID 0x12198
> >
> > @@ -3665,21 +3665,6 @@
> > #define DEIIR 0x44008
> > #define DEIER 0x4400c
> >
> > -/* GT interrupt.
> > - * Note that for gen6+ the ring-specific interrupt bits do alias with the
> > - * corresponding bits in the per-ring interrupt control registers. */
> > -#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
> > -#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
> > -#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
> > -#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
> > -#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
> > -#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
> > -#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
> > -#define GT_PIPE_NOTIFY (1 << 4)
> > -#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
> > -#define GT_SYNC_STATUS (1 << 2)
> > -#define GT_USER_INTERRUPT (1 << 0)
> > -
> > #define GTISR 0x44010
> > #define GTIMR 0x44014
> > #define GTIIR 0x44018
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index a737c66..ccfa1f9 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -556,7 +556,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
> >
> > if (HAS_L3_GPU_CACHE(dev))
> > - I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
> > + I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
> >
> > return ret;
> > }
> > @@ -971,7 +971,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
> > if (ring->irq_refcount.gt++ == 0) {
> > if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
> > I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
> > - GEN6_RENDER_L3_PARITY_ERROR));
> > + GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
> > else
> > I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
> > dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
> > @@ -993,7 +993,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
> > spin_lock_irqsave(&dev_priv->irq_lock, flags);
> > if (--ring->irq_refcount.gt == 0) {
> > if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
> > - I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
> > + I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
> > else
> > I915_WRITE_IMR(ring, ~0);
> > dev_priv->gt_irq_mask |= ring->irq_enable_mask;
> > @@ -1669,7 +1669,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> > ring->flush = gen6_render_ring_flush;
> > ring->irq_get = gen6_ring_get_irq;
> > ring->irq_put = gen6_ring_put_irq;
> > - ring->irq_enable_mask = GT_USER_INTERRUPT;
> > + ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> > ring->get_seqno = gen6_ring_get_seqno;
> > ring->set_seqno = ring_set_seqno;
> > ring->sync_to = gen6_ring_sync;
> > @@ -1688,7 +1688,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> > ring->set_seqno = pc_render_set_seqno;
> > ring->irq_get = gen5_ring_get_irq;
> > ring->irq_put = gen5_ring_put_irq;
> > - ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
> > + ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
> > + GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> > } else {
> > ring->add_request = i9xx_add_request;
> > if (INTEL_INFO(dev)->gen < 4)
> > @@ -1830,7 +1831,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > ring->add_request = gen6_add_request;
> > ring->get_seqno = gen6_ring_get_seqno;
> > ring->set_seqno = ring_set_seqno;
> > - ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
> > + ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> > ring->irq_get = gen6_ring_get_irq;
> > ring->irq_put = gen6_ring_put_irq;
> > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> > @@ -1850,7 +1851,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> > ring->get_seqno = ring_get_seqno;
> > ring->set_seqno = ring_set_seqno;
> > if (IS_GEN5(dev)) {
> > - ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
> > + ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
> > ring->irq_get = gen5_ring_get_irq;
> > ring->irq_put = gen5_ring_put_irq;
> > } else {
> > @@ -1879,7 +1880,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> > ring->add_request = gen6_add_request;
> > ring->get_seqno = gen6_ring_get_seqno;
> > ring->set_seqno = ring_set_seqno;
> > - ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
> > + ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
> > ring->irq_get = gen6_ring_get_irq;
> > ring->irq_put = gen6_ring_put_irq;
> > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> > --
> > 1.8.2.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 13/18] drm/i915: consolidate interrupt naming scheme
2013-05-28 18:50 ` Ben Widawsky
@ 2013-05-29 15:51 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 15:51 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Tue, May 28, 2013 at 11:50:46AM -0700, Ben Widawsky wrote:
> > > - if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
> > > - GT_GEN6_BSD_CS_ERROR_INTERRUPT |
> > > - GT_RENDER_CS_ERROR_INTERRUPT)) {
> > > + if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
> > > + GT_BSD_CS_ERROR_INTERRUPT |
> > > + GT_RENDER_MASTER_ERROR_INTERRUPT)) {
> >
> > If we ware in the naming domain here, not sure why the CS master error
> > for render would have a different name than the others,
> > GT_RENDER_CS_ERROR_INTERRUPT looked good to me.
>
> I was just copying the docs. I presume on earlier gens, maybe it meant
> something else? It seems I accidently dropped the "CS" part though. I've
> added that back, and left the MASTER.
>
> "Render Command Parser Master Error"
They are all called $engine Command Parser Master Error, my point was
they should look alike (and I'd just drop the master, I think it's just
because it means an aggregate of the possible CS errors (2 at most as
far as I can see, privilege error and bad command).
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 14/18] drm/i915: vebox interrupt get/put
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (12 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 13/18] drm/i915: consolidate interrupt naming scheme Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 14:38 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 15/18] drm/i915: Enable vebox interrupts Ben Widawsky
` (6 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
v2: Use the correct lock to protect PM interrupt regs, this was
accidentally lost from earlier (Haihao)
Fix return types (Ben)
CC: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 46 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++--
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ccfa1f9..93a3128 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1005,6 +1005,48 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
gen6_gt_force_wake_put(dev_priv);
}
+static bool
+hsw_vebox_get_irq(struct intel_ring_buffer *ring)
+{
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ if (!dev->irq_enabled)
+ return false;
+
+ spin_lock_irqsave(&dev_priv->rps.lock, flags);
+ if (ring->irq_refcount.pm++ == 0) {
+ u32 pm_imr = I915_READ(GEN6_PMIMR);
+ I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
+ I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
+ POSTING_READ(GEN6_PMIMR);
+ }
+ spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+
+ return true;
+}
+
+static void
+hsw_vebox_put_irq(struct intel_ring_buffer *ring)
+{
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ if (!dev->irq_enabled)
+ return;
+
+ spin_lock_irqsave(&dev_priv->rps.lock, flags);
+ if (--ring->irq_refcount.pm == 0) {
+ u32 pm_imr = I915_READ(GEN6_PMIMR);
+ I915_WRITE_IMR(ring, ~0);
+ I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
+ POSTING_READ(GEN6_PMIMR);
+ }
+ spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+}
+
static int
i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 length,
@@ -1913,8 +1955,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->irq_enable_mask = 0;
- ring->irq_get = NULL;
- ring->irq_put = NULL;
+ ring->irq_get = hsw_vebox_get_irq;
+ ring->irq_put = hsw_vebox_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 24b4413..d040dae 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -69,8 +69,9 @@ struct intel_ring_buffer {
u32 last_retired_head;
struct {
- u32 gt;
- } irq_refcount; /* protected by dev_priv->irq_lock */
+ u32 gt; /* protected by dev_priv->irq_lock */
+ u32 pm; /* protected by dev_priv->rps.lock (sucks) */
+ } irq_refcount;
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
u32 trace_irq_seqno;
u32 sync_seqno[I915_NUM_RINGS-1];
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 14/18] drm/i915: vebox interrupt get/put
2013-04-28 0:59 ` [PATCH 14/18] drm/i915: vebox interrupt get/put Ben Widawsky
@ 2013-05-28 14:38 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 14:38 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:25PM -0700, Ben Widawsky wrote:
> v2: Use the correct lock to protect PM interrupt regs, this was
> accidentally lost from earlier (Haihao)
> Fix return types (Ben)
>
> CC: Xiang, Haihao <haihao.xiang@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> drivers/gpu/drm/i915/intel_ringbuffer.c | 46 +++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++--
> 2 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ccfa1f9..93a3128 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1005,6 +1005,48 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
> gen6_gt_force_wake_put(dev_priv);
> }
>
> +static bool
> +hsw_vebox_get_irq(struct intel_ring_buffer *ring)
> +{
> + struct drm_device *dev = ring->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + if (!dev->irq_enabled)
> + return false;
> +
> + spin_lock_irqsave(&dev_priv->rps.lock, flags);
> + if (ring->irq_refcount.pm++ == 0) {
> + u32 pm_imr = I915_READ(GEN6_PMIMR);
> + I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
> + I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
> + POSTING_READ(GEN6_PMIMR);
> + }
> + spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
> +
> + return true;
> +}
> +
> +static void
> +hsw_vebox_put_irq(struct intel_ring_buffer *ring)
> +{
> + struct drm_device *dev = ring->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + if (!dev->irq_enabled)
> + return;
> +
> + spin_lock_irqsave(&dev_priv->rps.lock, flags);
> + if (--ring->irq_refcount.pm == 0) {
> + u32 pm_imr = I915_READ(GEN6_PMIMR);
> + I915_WRITE_IMR(ring, ~0);
> + I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
> + POSTING_READ(GEN6_PMIMR);
> + }
> + spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
> +}
> +
> static int
> i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
> u32 offset, u32 length,
> @@ -1913,8 +1955,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> ring->irq_enable_mask = 0;
> - ring->irq_get = NULL;
> - ring->irq_put = NULL;
> + ring->irq_get = hsw_vebox_get_irq;
> + ring->irq_put = hsw_vebox_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> ring->sync_to = gen6_ring_sync;
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 24b4413..d040dae 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -69,8 +69,9 @@ struct intel_ring_buffer {
> u32 last_retired_head;
>
> struct {
> - u32 gt;
> - } irq_refcount; /* protected by dev_priv->irq_lock */
> + u32 gt; /* protected by dev_priv->irq_lock */
> + u32 pm; /* protected by dev_priv->rps.lock (sucks) */
> + } irq_refcount;
> u32 irq_enable_mask; /* bitmask to enable ring interrupt */
> u32 trace_irq_seqno;
> u32 sync_seqno[I915_NUM_RINGS-1];
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 15/18] drm/i915: Enable vebox interrupts
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (13 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 14/18] drm/i915: vebox interrupt get/put Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 14:52 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 16/18] drm/i915: add VEBOX into debugfs Ben Widawsky
` (5 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
Similar to a patch originally written by:
v2: Reversed the meanings of masked and enabled (Haihao)
Made non-destructive writes in case enable/disabler rps runs first
(Haihao)
CC: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 26 ++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 06e254a..ae2ee9d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -944,8 +944,15 @@ static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
}
spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
- if (pm_iir & ~GEN6_PM_RPS_EVENTS)
- DRM_ERROR("Unexpected PM interrupted\n");
+ if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
+ if (pm_iir & PM_VEBOX_USER_INTERRUPT)
+ notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
+
+ if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
+ DRM_ERROR("PM error interrupt 0x%08x\n", pm_iir);
+ i915_handle_error(dev_priv->dev, false);
+ }
+ }
}
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
@@ -2701,6 +2708,21 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
+ I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+ if (HAS_VEBOX(dev)) {
+ u32 pm_irqs, pmier, pmimr;
+ pm_irqs = PM_VEBOX_USER_INTERRUPT | PM_VEBOX_CS_ERROR_INTERRUPT;
+
+ /* Our enable/disable rps functions may touch these registers so
+ * make sure to set a known state for only the non-RPS bits. */
+ pmier = (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs;
+ pmimr = (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs;
+ I915_WRITE(GEN6_PMIMR, pmimr);
+ I915_WRITE(GEN6_PMIER, pmier);
+ }
+
+ POSTING_READ(GEN6_PMIER);
+
ibx_irq_postinstall(dev);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 399d041..9e8b8b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -860,6 +860,9 @@
#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
#define GT_RENDER_USER_INTERRUPT (1 << 0)
+#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
+#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
+
/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT (1<<5)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 93a3128..30f22e1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1954,7 +1954,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- ring->irq_enable_mask = 0;
+ ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT | PM_VEBOX_CS_ERROR_INTERRUPT;
ring->irq_get = hsw_vebox_get_irq;
ring->irq_put = hsw_vebox_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 15/18] drm/i915: Enable vebox interrupts
2013-04-28 0:59 ` [PATCH 15/18] drm/i915: Enable vebox interrupts Ben Widawsky
@ 2013-05-28 14:52 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 14:52 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:26PM -0700, Ben Widawsky wrote:
> Similar to a patch originally written by:
>
> v2: Reversed the meanings of masked and enabled (Haihao)
> Made non-destructive writes in case enable/disabler rps runs first
> (Haihao)
>
> CC: Xiang, Haihao <haihao.xiang@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
With or without the bikeshed below:
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_irq.c | 26 ++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> 3 files changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 06e254a..ae2ee9d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -944,8 +944,15 @@ static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
> }
> spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
>
> - if (pm_iir & ~GEN6_PM_RPS_EVENTS)
> - DRM_ERROR("Unexpected PM interrupted\n");
> + if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
> + if (pm_iir & PM_VEBOX_USER_INTERRUPT)
> + notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
> +
> + if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
> + DRM_ERROR("PM error interrupt 0x%08x\n", pm_iir);
Maybe we could even be a bit more explicit here, saying it's a command
stream/parser error.
> + i915_handle_error(dev_priv->dev, false);
> + }
> + }
> }
>
> static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> @@ -2701,6 +2708,21 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> I915_WRITE(GTIER, gt_irqs);
> POSTING_READ(GTIER);
>
> + I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
> + if (HAS_VEBOX(dev)) {
> + u32 pm_irqs, pmier, pmimr;
> + pm_irqs = PM_VEBOX_USER_INTERRUPT | PM_VEBOX_CS_ERROR_INTERRUPT;
> +
> + /* Our enable/disable rps functions may touch these registers so
> + * make sure to set a known state for only the non-RPS bits. */
> + pmier = (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs;
> + pmimr = (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs;
> + I915_WRITE(GEN6_PMIMR, pmimr);
> + I915_WRITE(GEN6_PMIER, pmier);
> + }
> +
> + POSTING_READ(GEN6_PMIER);
> +
> ibx_irq_postinstall(dev);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 399d041..9e8b8b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -860,6 +860,9 @@
> #define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
> #define GT_RENDER_USER_INTERRUPT (1 << 0)
>
> +#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
> +#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
> +
> /* These are all the "old" interrupts */
> #define ILK_BSD_USER_INTERRUPT (1<<5)
> #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 93a3128..30f22e1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1954,7 +1954,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->add_request = gen6_add_request;
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> - ring->irq_enable_mask = 0;
> + ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT | PM_VEBOX_CS_ERROR_INTERRUPT;
> ring->irq_get = hsw_vebox_get_irq;
> ring->irq_put = hsw_vebox_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 16/18] drm/i915: add VEBOX into debugfs
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (14 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 15/18] drm/i915: Enable vebox interrupts Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 15:06 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer() Ben Widawsky
` (4 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
v2 (Ben): s/hsw/hws
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Order changed, and modified by]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a55630a..71fb7aa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -379,6 +379,17 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
}
count++;
}
+ if (!list_empty(&dev_priv->ring[VECS].request_list)) {
+ seq_printf(m, "VEBOX requests:\n");
+ list_for_each_entry(gem_request,
+ &dev_priv->ring[VECS].request_list,
+ list) {
+ seq_printf(m, " %d @ %d\n",
+ gem_request->seqno,
+ (int) (jiffies - gem_request->emitted_jiffies));
+ }
+ count++;
+ }
mutex_unlock(&dev->struct_mutex);
if (count == 0)
@@ -570,6 +581,7 @@ static const char *ring_str(int ring)
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
+ case VECS: return "vebox";
default: return "";
}
}
@@ -2099,6 +2111,7 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
+ {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
{"i915_rstdby_delays", i915_rstdby_delays, 0},
{"i915_cur_delayinfo", i915_cur_delayinfo, 0},
{"i915_delayfreq_table", i915_delayfreq_table, 0},
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 16/18] drm/i915: add VEBOX into debugfs
2013-04-28 0:59 ` [PATCH 16/18] drm/i915: add VEBOX into debugfs Ben Widawsky
@ 2013-05-28 15:06 ` Damien Lespiau
2013-05-28 18:44 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 15:06 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:27PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao" <haihao.xiang@intel.com>
>
> v2 (Ben): s/hsw/hws
>
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> [Order changed, and modified by]
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a55630a..71fb7aa 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -379,6 +379,17 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
> }
> count++;
> }
> + if (!list_empty(&dev_priv->ring[VECS].request_list)) {
> + seq_printf(m, "VEBOX requests:\n");
> + list_for_each_entry(gem_request,
> + &dev_priv->ring[VECS].request_list,
> + list) {
> + seq_printf(m, " %d @ %d\n",
> + gem_request->seqno,
> + (int) (jiffies - gem_request->emitted_jiffies));
> + }
> + count++;
> + }
> mutex_unlock(&dev->struct_mutex);
That block doesn't seem necessary as the code above this chuck cycles
over all the rings?
>
> if (count == 0)
> @@ -570,6 +581,7 @@ static const char *ring_str(int ring)
> case RCS: return "render";
> case VCS: return "bsd";
> case BCS: return "blt";
> + case VECS: return "vebox";
> default: return "";
> }
> }
> @@ -2099,6 +2111,7 @@ static struct drm_info_list i915_debugfs_list[] = {
> {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
> {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
> {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
> + {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
> {"i915_rstdby_delays", i915_rstdby_delays, 0},
> {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
> {"i915_delayfreq_table", i915_delayfreq_table, 0},
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 16/18] drm/i915: add VEBOX into debugfs
2013-05-28 15:06 ` Damien Lespiau
@ 2013-05-28 18:44 ` Ben Widawsky
0 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-28 18:44 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel-GFX
On Tue, May 28, 2013 at 04:06:07PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:27PM -0700, Ben Widawsky wrote:
> > From: "Xiang, Haihao" <haihao.xiang@intel.com>
> >
> > v2 (Ben): s/hsw/hws
> >
> > Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> > [Order changed, and modified by]
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index a55630a..71fb7aa 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -379,6 +379,17 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
> > }
> > count++;
> > }
> > + if (!list_empty(&dev_priv->ring[VECS].request_list)) {
> > + seq_printf(m, "VEBOX requests:\n");
> > + list_for_each_entry(gem_request,
> > + &dev_priv->ring[VECS].request_list,
> > + list) {
> > + seq_printf(m, " %d @ %d\n",
> > + gem_request->seqno,
> > + (int) (jiffies - gem_request->emitted_jiffies));
> > + }
> > + count++;
> > + }
> > mutex_unlock(&dev->struct_mutex);
>
> That block doesn't seem necessary as the code above this chuck cycles
> over all the rings?
Indeed. This is a rebase relic. This hunk is removed.
>
> >
> > if (count == 0)
> > @@ -570,6 +581,7 @@ static const char *ring_str(int ring)
> > case RCS: return "render";
> > case VCS: return "bsd";
> > case BCS: return "blt";
> > + case VECS: return "vebox";
> > default: return "";
> > }
> > }
> > @@ -2099,6 +2111,7 @@ static struct drm_info_list i915_debugfs_list[] = {
> > {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
> > {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
> > {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
> > + {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
> > {"i915_rstdby_delays", i915_rstdby_delays, 0},
> > {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
> > {"i915_delayfreq_table", i915_delayfreq_table, 0},
> > --
> > 1.8.2.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer()
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (15 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 16/18] drm/i915: add VEBOX into debugfs Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 15:08 ` Damien Lespiau
2013-04-28 0:59 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
` (3 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
A user can run batchbuffer via VEBOX ring.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Order changed by]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +++++++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 117ce38..a8bb62c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -885,6 +885,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
return -EPERM;
}
break;
+ case I915_EXEC_VEBOX:
+ ring = &dev_priv->ring[VECS];
+ if (ctx_id != 0) {
+ DRM_DEBUG("Ring %s doesn't support contexts\n",
+ ring->name);
+ return -EPERM;
+ }
+ break;
+
default:
DRM_DEBUG("execbuf with unknown ring: %d\n",
(int)(args->flags & I915_EXEC_RING_MASK));
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 07d5941..81b9981 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -660,6 +660,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_VEBOX (4<<0)
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
* Gen6+ only supports relative addressing to dynamic state (default) and
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer()
2013-04-28 0:59 ` [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer() Ben Widawsky
@ 2013-05-28 15:08 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 15:08 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:28PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao" <haihao.xiang@intel.com>
>
> A user can run batchbuffer via VEBOX ring.
>
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> [Order changed by]
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +++++++++
> include/uapi/drm/i915_drm.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 117ce38..a8bb62c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -885,6 +885,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
> return -EPERM;
> }
> break;
> + case I915_EXEC_VEBOX:
> + ring = &dev_priv->ring[VECS];
> + if (ctx_id != 0) {
> + DRM_DEBUG("Ring %s doesn't support contexts\n",
> + ring->name);
> + return -EPERM;
> + }
> + break;
> +
> default:
> DRM_DEBUG("execbuf with unknown ring: %d\n",
> (int)(args->flags & I915_EXEC_RING_MASK));
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 07d5941..81b9981 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -660,6 +660,7 @@ struct drm_i915_gem_execbuffer2 {
> #define I915_EXEC_RENDER (1<<0)
> #define I915_EXEC_BSD (2<<0)
> #define I915_EXEC_BLT (3<<0)
> +#define I915_EXEC_VEBOX (4<<0)
>
> /* Used for switching the constants addressing mode on gen4+ RENDER ring.
> * Gen6+ only supports relative addressing to dynamic state (default) and
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (16 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer() Ben Widawsky
@ 2013-04-28 0:59 ` Ben Widawsky
2013-05-28 15:10 ` Damien Lespiau
2013-04-30 21:25 ` [PATCH 00/18] Introduce the Haswell VECS Jesse Barnes
` (2 subsequent siblings)
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-04-28 0:59 UTC (permalink / raw)
To: Intel-GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
This will let userland only try to use the new ring
when the appropriate kernel is present
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Order changed, and merge conflict resolved by]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
include/uapi/drm/i915_drm.h | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a1648eb..66a1e39 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -956,6 +956,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_BLT:
value = intel_ring_initialized(&dev_priv->ring[BCS]);
break;
+ case I915_PARAM_HAS_VEBOX:
+ value = intel_ring_initialized(&dev_priv->ring[VECS]);
+ break;
case I915_PARAM_HAS_RELAXED_FENCING:
value = 1;
break;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 81b9981..923ed7f 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -305,7 +305,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
#define I915_PARAM_HAS_SEMAPHORES 20
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
-#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
+#define I915_PARAM_HAS_VEBOX 22
#define I915_PARAM_HAS_SECURE_BATCHES 23
#define I915_PARAM_HAS_PINNED_BATCHES 24
#define I915_PARAM_HAS_EXEC_NO_RELOC 25
--
1.8.2.1
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
2013-04-28 0:59 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
@ 2013-05-28 15:10 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-28 15:10 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, Apr 27, 2013 at 05:59:29PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao" <haihao.xiang@intel.com>
>
> This will let userland only try to use the new ring
> when the appropriate kernel is present
>
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> [Order changed, and merge conflict resolved by]
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_dma.c | 3 +++
> include/uapi/drm/i915_drm.h | 2 +-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index a1648eb..66a1e39 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -956,6 +956,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
> case I915_PARAM_HAS_BLT:
> value = intel_ring_initialized(&dev_priv->ring[BCS]);
> break;
> + case I915_PARAM_HAS_VEBOX:
> + value = intel_ring_initialized(&dev_priv->ring[VECS]);
> + break;
> case I915_PARAM_HAS_RELAXED_FENCING:
> value = 1;
> break;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 81b9981..923ed7f 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -305,7 +305,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_HAS_WAIT_TIMEOUT 19
> #define I915_PARAM_HAS_SEMAPHORES 20
> #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
> -#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
> +#define I915_PARAM_HAS_VEBOX 22
> #define I915_PARAM_HAS_SECURE_BATCHES 23
> #define I915_PARAM_HAS_PINNED_BATCHES 24
> #define I915_PARAM_HAS_EXEC_NO_RELOC 25
> --
> 1.8.2.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH 00/18] Introduce the Haswell VECS
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (17 preceding siblings ...)
2013-04-28 0:59 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
@ 2013-04-30 21:25 ` Jesse Barnes
2013-05-08 6:13 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
20 siblings, 0 replies; 84+ messages in thread
From: Jesse Barnes @ 2013-04-30 21:25 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel-GFX
On Sat, 27 Apr 2013 17:59:11 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:
> Here is the original post with the RFC for these patches.
> http://lists.freedesktop.org/archives/intel-gfx/2012-November/022330.html
So where are we with these? They're almost old enough to drink now...
I think the media team already has tests for them?
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 00/18] Introduce the Haswell VECS
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (18 preceding siblings ...)
2013-04-30 21:25 ` [PATCH 00/18] Introduce the Haswell VECS Jesse Barnes
@ 2013-05-08 6:13 ` Ben Widawsky
2013-05-09 9:07 ` Li, Zhong
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
20 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-08 6:13 UTC (permalink / raw)
To: Intel-GFX, Damien Lespiau; +Cc: Jocelyn Li
I've pushed a branch with everything I got from Damien's review so far.
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=vecs-rebase
Since it appears Damien hasn't finished yet, I won't send the updated
patches in case someone else comes along with more comments on those
patches.
Also, since Damien found a pretty significant functional bug with the
semaphore registers, it would be good if we could get some more testing
on the branch. Jocelyn, would it be possible to have someone from your
team run a test with libva. If I recall correctly, Haihao found the same
bug previously, but we seemed to have missed it this time around when I
rebased on the wrong branch.
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 00/18] Introduce the Haswell VECS
2013-05-08 6:13 ` Ben Widawsky
@ 2013-05-09 9:07 ` Li, Zhong
0 siblings, 0 replies; 84+ messages in thread
From: Li, Zhong @ 2013-05-09 9:07 UTC (permalink / raw)
To: Ben Widawsky, Intel-GFX, Lespiau, Damien; +Cc: Li, Jocelyn
I have run some video process test cases calling libva based on vesc-rebase kernel, output videos of video processing are ok by a little mild test cases (include de-interlacing, denoise, color space conversion and scaling).
Then I used upstream kernel which not support vesc, output of vpp was wrong. This means vecs-rebase kernel can work indeed.
-----Original Message-----
From: Ben Widawsky [mailto:ben@bwidawsk.net]
Sent: Wednesday, May 08, 2013 2:14 PM
To: Intel-GFX; Lespiau, Damien
Cc: Xiang, Haihao; Li, Zhong; Li, Jocelyn
Subject: Re: [PATCH 00/18] Introduce the Haswell VECS
I've pushed a branch with everything I got from Damien's review so far.
http://cgit.freedesktop.org/~bwidawsk/drm-intel/log/?h=vecs-rebase
Since it appears Damien hasn't finished yet, I won't send the updated patches in case someone else comes along with more comments on those patches.
Also, since Damien found a pretty significant functional bug with the semaphore registers, it would be good if we could get some more testing on the branch. Jocelyn, would it be possible to have someone from your team run a test with libva. If I recall correctly, Haihao found the same bug previously, but we seemed to have missed it this time around when I rebased on the wrong branch.
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 00/18] Introduce the Haswell VECS v2
2013-04-28 0:59 [PATCH 00/18] Introduce the Haswell VECS Ben Widawsky
` (19 preceding siblings ...)
2013-05-08 6:13 ` Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification Ben Widawsky
` (17 more replies)
20 siblings, 18 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
The primary change in this series is I introduce the
ivybridge_preinstall and "Add PM regs to pre/post install"
before make "PM interrupt writes non-destructive". This helps address
the issue Damien caught where the PMIMR is never cleared midway through
the series. On that note, I fixed a bug introduced on the previous
rebase where the PMIMR wasn't getting cleared without VEBOX. That fix is
addressed in v2 of "vebox interrupt get/put"
I've also rebased this series on the latest -nightly, and tried to fix
all comments Damien made in the series.
Thanks again to Damien for the review this far.
v1 with more background:
http://lists.freedesktop.org/archives/intel-gfx/2013-April/027308.html
Ben Widawsky (14):
drm/i915: Comments for semaphore clarification
drm/i915: Semaphore MBOX update generalization
drm/i915: Introduce VECS: the 4th ring
drm/i915: Add VECS semaphore bits
drm/i915: Rename ring flush functions
drm/i915: Vebox ringbuffer init
drm/i915: Create a more generic pm handler for hsw+
drm/i915: Create an ivybridge_irq_preinstall
drm/i915: Add PM regs to pre/post install
drm/i915: make PM interrupt writes non-destructive
drm/i915: Convert irq_refounct to struct
drm/i915: consolidate interrupt naming scheme
drm/i915: vebox interrupt get/put
drm/i915: Enable vebox interrupts
Xiang, Haihao (4):
drm/i915: add HAS_VEBOX
drm/i915: add VEBOX into debugfs
drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer()
drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
drivers/gpu/drm/i915/i915_debugfs.c | 2 +
drivers/gpu/drm/i915/i915_dma.c | 3 +
drivers/gpu/drm/i915/i915_drv.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 11 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 ++
drivers/gpu/drm/i915/i915_irq.c | 162 ++++++++++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 148 +++++++++++-----------
drivers/gpu/drm/i915/intel_pm.c | 15 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 194 ++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_ringbuffer.h | 16 ++-
include/uapi/drm/i915_drm.h | 3 +-
12 files changed, 399 insertions(+), 168 deletions(-)
--
1.8.3
^ permalink raw reply [flat|nested] 84+ messages in thread* [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 16:02 ` Damien Lespiau
2013-05-29 2:22 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
` (16 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
Semaphores are tied very closely to the rings in the GPU. Trivial patch
adds comments to the existing code so that when we add new rings we can
include comments there as well. It also helps distinguish the ring to
semaphore mailbox interactions by using the ringname in the semaphore
data structures.
This patch should have no functional impact.
v2: The English parts (as opposed to register names) of the comments
were reversed. (Damien)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
3 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dbd9de5..6579d0c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -265,12 +265,12 @@
#define MI_SEMAPHORE_UPDATE (1<<21)
#define MI_SEMAPHORE_COMPARE (1<<20)
#define MI_SEMAPHORE_REGISTER (1<<18)
-#define MI_SEMAPHORE_SYNC_RV (2<<16)
-#define MI_SEMAPHORE_SYNC_RB (0<<16)
-#define MI_SEMAPHORE_SYNC_VR (0<<16)
-#define MI_SEMAPHORE_SYNC_VB (2<<16)
-#define MI_SEMAPHORE_SYNC_BR (2<<16)
-#define MI_SEMAPHORE_SYNC_BV (0<<16)
+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
/*
* 3D instructions used by the kernel
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9b97cf6..2d2a362 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1671,9 +1671,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
ring->signal_mbox[0] = GEN6_VRSYNC;
ring->signal_mbox[1] = GEN6_BRSYNC;
} else if (IS_GEN5(dev)) {
@@ -1830,9 +1830,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
ring->signal_mbox[0] = GEN6_RVSYNC;
ring->signal_mbox[1] = GEN6_BVSYNC;
} else {
@@ -1876,9 +1876,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
- ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
- ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
- ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->signal_mbox[0] = GEN6_RBSYNC;
ring->signal_mbox[1] = GEN6_VBSYNC;
ring->init = init_ring_common;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index ef374a8..24268fb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -105,8 +105,8 @@ struct intel_ring_buffer {
int (*sync_to)(struct intel_ring_buffer *ring,
struct intel_ring_buffer *to,
u32 seqno);
-
- u32 semaphore_register[3]; /*our mbox written by others */
+ /* our mbox written by others */
+ u32 semaphore_register[I915_NUM_RINGS];
u32 signal_mbox[2]; /* mboxes this ring signals to */
/**
* List of objects currently involved in rendering from the
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification
2013-05-29 2:22 ` [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification Ben Widawsky
@ 2013-05-29 16:02 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 16:02 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:17PM -0700, Ben Widawsky wrote:
> Semaphores are tied very closely to the rings in the GPU. Trivial patch
> adds comments to the existing code so that when we add new rings we can
> include comments there as well. It also helps distinguish the ring to
> semaphore mailbox interactions by using the ringname in the semaphore
> data structures.
>
> This patch should have no functional impact.
>
> v2: The English parts (as opposed to register names) of the comments
> were reversed. (Damien)
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++--
> 3 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dbd9de5..6579d0c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -265,12 +265,12 @@
> #define MI_SEMAPHORE_UPDATE (1<<21)
> #define MI_SEMAPHORE_COMPARE (1<<20)
> #define MI_SEMAPHORE_REGISTER (1<<18)
> -#define MI_SEMAPHORE_SYNC_RV (2<<16)
> -#define MI_SEMAPHORE_SYNC_RB (0<<16)
> -#define MI_SEMAPHORE_SYNC_VR (0<<16)
> -#define MI_SEMAPHORE_SYNC_VB (2<<16)
> -#define MI_SEMAPHORE_SYNC_BR (2<<16)
> -#define MI_SEMAPHORE_SYNC_BV (0<<16)
> +#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
> +#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
> +#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
> +#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
> +#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
> +#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
> #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
> /*
> * 3D instructions used by the kernel
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9b97cf6..2d2a362 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1671,9 +1671,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> ring->sync_to = gen6_ring_sync;
> - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
> - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
> - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
> + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> ring->signal_mbox[0] = GEN6_VRSYNC;
> ring->signal_mbox[1] = GEN6_BRSYNC;
> } else if (IS_GEN5(dev)) {
> @@ -1830,9 +1830,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> ring->sync_to = gen6_ring_sync;
> - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
> - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
> - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
> + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> ring->signal_mbox[0] = GEN6_RVSYNC;
> ring->signal_mbox[1] = GEN6_BVSYNC;
> } else {
> @@ -1876,9 +1876,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> ring->sync_to = gen6_ring_sync;
> - ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
> - ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
> - ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
> + ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> + ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> + ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->signal_mbox[0] = GEN6_RBSYNC;
> ring->signal_mbox[1] = GEN6_VBSYNC;
> ring->init = init_ring_common;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index ef374a8..24268fb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -105,8 +105,8 @@ struct intel_ring_buffer {
> int (*sync_to)(struct intel_ring_buffer *ring,
> struct intel_ring_buffer *to,
> u32 seqno);
> -
> - u32 semaphore_register[3]; /*our mbox written by others */
> + /* our mbox written by others */
> + u32 semaphore_register[I915_NUM_RINGS];
> u32 signal_mbox[2]; /* mboxes this ring signals to */
> /**
> * List of objects currently involved in rendering from the
> --
> 1.8.3
>
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 02/18] drm/i915: Semaphore MBOX update generalization
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
2013-05-29 2:22 ` [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 16:05 ` Damien Lespiau
2013-05-29 2:22 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
` (15 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
This replaces the existing MBOX update code with a more generalized
calculation for emitting mbox updates. We also create a sentinel for
doing the updates so we can more abstractly deal with the rings.
When doing MBOX updates the code must be aware of the /other/ rings.
Until now the platforms which supported semaphores had a fixed number of
rings and so it made sense for the code to be very specialized
(hardcoded).
The patch does contain a functional change, but should have no
behavioral changes.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 43 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++-
3 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6579d0c..19f8e51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -593,6 +593,7 @@
#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_NOSYNC 0
#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2d2a362..5df1791 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -582,9 +582,16 @@ static void
update_mboxes(struct intel_ring_buffer *ring,
u32 mmio_offset)
{
+/* NB: In order to be able to do semaphore MBOX updates for varying number
+ * of rings, it's easiest if we round up each individual update to a
+ * multiple of 2 (since ring updates must always be a multiple of 2)
+ * even though the actual update only requires 3 dwords.
+ */
+#define MBOX_UPDATE_DWORDS 4
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit(ring, mmio_offset);
intel_ring_emit(ring, ring->outstanding_lazy_request);
+ intel_ring_emit(ring, MI_NOOP);
}
/**
@@ -599,19 +606,24 @@ update_mboxes(struct intel_ring_buffer *ring,
static int
gen6_add_request(struct intel_ring_buffer *ring)
{
- u32 mbox1_reg;
- u32 mbox2_reg;
- int ret;
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *useless;
+ int i, ret;
- ret = intel_ring_begin(ring, 10);
+ ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
+ MBOX_UPDATE_DWORDS) +
+ 4);
if (ret)
return ret;
+#undef MBOX_UPDATE_DWORDS
- mbox1_reg = ring->signal_mbox[0];
- mbox2_reg = ring->signal_mbox[1];
+ for_each_ring(useless, dev_priv, i) {
+ u32 mbox_reg = ring->signal_mbox[i];
+ if (mbox_reg != GEN6_NOSYNC)
+ update_mboxes(ring, mbox_reg);
+ }
- update_mboxes(ring, mbox1_reg);
- update_mboxes(ring, mbox2_reg);
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, ring->outstanding_lazy_request);
@@ -1674,8 +1686,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
- ring->signal_mbox[0] = GEN6_VRSYNC;
- ring->signal_mbox[1] = GEN6_BRSYNC;
+ ring->signal_mbox[RCS] = GEN6_NOSYNC;
+ ring->signal_mbox[VCS] = GEN6_VRSYNC;
+ ring->signal_mbox[BCS] = GEN6_BRSYNC;
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->flush = gen4_render_ring_flush;
@@ -1833,8 +1846,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
- ring->signal_mbox[0] = GEN6_RVSYNC;
- ring->signal_mbox[1] = GEN6_BVSYNC;
+ ring->signal_mbox[RCS] = GEN6_RVSYNC;
+ ring->signal_mbox[VCS] = GEN6_NOSYNC;
+ ring->signal_mbox[BCS] = GEN6_BVSYNC;
} else {
ring->mmio_base = BSD_RING_BASE;
ring->flush = bsd_ring_flush;
@@ -1879,8 +1893,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
- ring->signal_mbox[0] = GEN6_RBSYNC;
- ring->signal_mbox[1] = GEN6_VBSYNC;
+ ring->signal_mbox[RCS] = GEN6_RBSYNC;
+ ring->signal_mbox[VCS] = GEN6_VBSYNC;
+ ring->signal_mbox[BCS] = GEN6_NOSYNC;
ring->init = init_ring_common;
return intel_init_ring_buffer(dev, ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 24268fb..f55d92e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -105,9 +105,12 @@ struct intel_ring_buffer {
int (*sync_to)(struct intel_ring_buffer *ring,
struct intel_ring_buffer *to,
u32 seqno);
+
/* our mbox written by others */
u32 semaphore_register[I915_NUM_RINGS];
- u32 signal_mbox[2]; /* mboxes this ring signals to */
+ /* mboxes this ring signals to */
+ u32 signal_mbox[I915_NUM_RINGS];
+
/**
* List of objects currently involved in rendering from the
* ringbuffer.
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 02/18] drm/i915: Semaphore MBOX update generalization
2013-05-29 2:22 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
@ 2013-05-29 16:05 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 16:05 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:18PM -0700, Ben Widawsky wrote:
> This replaces the existing MBOX update code with a more generalized
> calculation for emitting mbox updates. We also create a sentinel for
> doing the updates so we can more abstractly deal with the rings.
>
> When doing MBOX updates the code must be aware of the /other/ rings.
> Until now the platforms which supported semaphores had a fixed number of
> rings and so it made sense for the code to be very specialized
> (hardcoded).
>
> The patch does contain a functional change, but should have no
> behavioral changes.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
2013-05-29 2:22 ` [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification Ben Widawsky
2013-05-29 2:22 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 19:10 ` Daniel Vetter
2013-05-29 2:22 ` [PATCH 04/18] [v2] drm/i915: Add VECS semaphore bits Ben Widawsky
` (14 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
The video enhancement command streamer is a new ring on HSW which does
what it sounds like it does. This patch provides the most minimal
inception of the ring.
In order to support a new ring, we need to bump the number. The patch
may look trivial to the untrained eye, but bumping the number of rings
is a bit scary. As such the patch is not terribly useful by itself, but
a pretty nice place to find issues during a bisection.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5df1791..ead979a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -915,6 +915,8 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
case VCS:
mmio = BSD_HWS_PGA_GEN7;
break;
+ case VECS:
+ BUG();
}
} else if (IS_GEN6(ring->dev)) {
mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f55d92e..73619cb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -47,8 +47,9 @@ struct intel_ring_buffer {
RCS = 0x0,
VCS,
BCS,
+ VECS,
} id;
-#define I915_NUM_RINGS 3
+#define I915_NUM_RINGS 4
u32 mmio_base;
void __iomem *virtual_start;
struct drm_device *dev;
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring
2013-05-29 2:22 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
@ 2013-05-29 19:10 ` Daniel Vetter
0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-05-29 19:10 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:19PM -0700, Ben Widawsky wrote:
> The video enhancement command streamer is a new ring on HSW which does
> what it sounds like it does. This patch provides the most minimal
> inception of the ring.
>
> In order to support a new ring, we need to bump the number. The patch
> may look trivial to the untrained eye, but bumping the number of rings
> is a bit scary. As such the patch is not terribly useful by itself, but
> a pretty nice place to find issues during a bisection.
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 5df1791..ead979a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -915,6 +915,8 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
> case VCS:
> mmio = BSD_HWS_PGA_GEN7;
> break;
> + case VECS:
> + BUG();
My maintainer script freaked out a bit since you're adding a BUG here
without any particular reason that it's strictly better than a WARN. But
since it'll disappear in a follow-up patch I'll let it slide.
Yes, I've hit one of my own stupid BUG_ONs just recently, so I'm now
doubleplusgrumpy about this henceforth ;-)
Cheers, Daniel
> }
> } else if (IS_GEN6(ring->dev)) {
> mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index f55d92e..73619cb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -47,8 +47,9 @@ struct intel_ring_buffer {
> RCS = 0x0,
> VCS,
> BCS,
> + VECS,
> } id;
> -#define I915_NUM_RINGS 3
> +#define I915_NUM_RINGS 4
> u32 mmio_base;
> void __iomem *virtual_start;
> struct drm_device *dev;
> --
> 1.8.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 04/18] [v2] drm/i915: Add VECS semaphore bits
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (2 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 16:06 ` Damien Lespiau
2013-05-29 2:22 ` [PATCH 05/18] drm/i915: Rename ring flush functions Ben Widawsky
` (13 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
Like the other rings, the VECS supports semaphores. The semaphore stuff
is a bit wonky so this patch on it's own should be nice for review.
This patch should have no functional impact.
v2: Fix the English parts of clarification (again, register names were
right, text was reversed) (Damien)
Restore the still valid invariant. (Damien)
The bsd semaphore register should be MI_SEMAPHORE_SYNC_VVE (Damien)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++
2 files changed, 33 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 19f8e51..41c5d45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -265,13 +265,19 @@
#define MI_SEMAPHORE_UPDATE (1<<21)
#define MI_SEMAPHORE_COMPARE (1<<20)
#define MI_SEMAPHORE_REGISTER (1<<18)
-#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
-#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
-#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
-#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
-#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
-#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
-#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
+#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
+#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
+#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
+#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
+#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
+#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
+#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
+#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
+#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
+#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
+#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
+#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
+#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
/*
* 3D instructions used by the kernel
*/
@@ -581,6 +587,7 @@
#define RENDER_RING_BASE 0x02000
#define BSD_RING_BASE 0x04000
#define GEN6_BSD_RING_BASE 0x12000
+#define VEBOX_RING_BASE 0x1a000
#define BLT_RING_BASE 0x22000
#define RING_TAIL(base) ((base)+0x30)
#define RING_HEAD(base) ((base)+0x34)
@@ -588,13 +595,20 @@
#define RING_CTL(base) ((base)+0x3c)
#define RING_SYNC_0(base) ((base)+0x40)
#define RING_SYNC_1(base) ((base)+0x44)
-#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
-#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
-#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
-#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
-#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define RING_SYNC_2(base) ((base)+0x48)
+#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
+#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
+#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
+#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
+#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
+#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
+#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
+#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
+#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
+#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
+#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
#define GEN6_NOSYNC 0
-#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ead979a..93ccd1e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1688,9 +1688,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
ring->signal_mbox[RCS] = GEN6_NOSYNC;
ring->signal_mbox[VCS] = GEN6_VRSYNC;
ring->signal_mbox[BCS] = GEN6_BRSYNC;
+ ring->signal_mbox[VECS] = GEN6_VERSYNC;
} else if (IS_GEN5(dev)) {
ring->add_request = pc_render_add_request;
ring->flush = gen4_render_ring_flush;
@@ -1848,9 +1850,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
ring->signal_mbox[RCS] = GEN6_RVSYNC;
ring->signal_mbox[VCS] = GEN6_NOSYNC;
ring->signal_mbox[BCS] = GEN6_BVSYNC;
+ ring->signal_mbox[VECS] = GEN6_VEVSYNC;
} else {
ring->mmio_base = BSD_RING_BASE;
ring->flush = bsd_ring_flush;
@@ -1895,9 +1899,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
ring->signal_mbox[RCS] = GEN6_RBSYNC;
ring->signal_mbox[VCS] = GEN6_VBSYNC;
ring->signal_mbox[BCS] = GEN6_NOSYNC;
+ ring->signal_mbox[VECS] = GEN6_VEBSYNC;
ring->init = init_ring_common;
return intel_init_ring_buffer(dev, ring);
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 04/18] [v2] drm/i915: Add VECS semaphore bits
2013-05-29 2:22 ` [PATCH 04/18] [v2] drm/i915: Add VECS semaphore bits Ben Widawsky
@ 2013-05-29 16:06 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 16:06 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:20PM -0700, Ben Widawsky wrote:
> Like the other rings, the VECS supports semaphores. The semaphore stuff
> is a bit wonky so this patch on it's own should be nice for review.
>
> This patch should have no functional impact.
>
> v2: Fix the English parts of clarification (again, register names were
> right, text was reversed) (Damien)
> Restore the still valid invariant. (Damien)
> The bsd semaphore register should be MI_SEMAPHORE_SYNC_VVE (Damien)
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 05/18] drm/i915: Rename ring flush functions
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (3 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 04/18] [v2] drm/i915: Add VECS semaphore bits Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 06/18] drm/i915: add HAS_VEBOX Ben Widawsky
` (12 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
Historically we considered the render ring to have special flush
semantics and everything else to fall under a more general umbrella.
Probably by coincidence more than anything we decided to make the bsd
ring have the default *other* flush. As the new vebox ring exposes, the
bsd ring is actually the weird one. Doing this allows us to call
gen6_ring_flush for the vebox because calling blt_ring_flush would be
weird...
This patch should have no functional change.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 93ccd1e..3022e15 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1565,8 +1565,8 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
_MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
}
-static int gen6_ring_flush(struct intel_ring_buffer *ring,
- u32 invalidate, u32 flush)
+static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
+ u32 invalidate, u32 flush)
{
uint32_t cmd;
int ret;
@@ -1637,8 +1637,8 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
/* Blitter support (SandyBridge+) */
-static int blt_ring_flush(struct intel_ring_buffer *ring,
- u32 invalidate, u32 flush)
+static int gen6_ring_flush(struct intel_ring_buffer *ring,
+ u32 invalidate, u32 flush)
{
uint32_t cmd;
int ret;
@@ -1838,7 +1838,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
/* gen6 bsd needs a special wa for tail updates */
if (IS_GEN6(dev))
ring->write_tail = gen6_bsd_ring_write_tail;
- ring->flush = gen6_ring_flush;
+ ring->flush = gen6_bsd_ring_flush;
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
@@ -1887,7 +1887,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->mmio_base = BLT_RING_BASE;
ring->write_tail = ring_write_tail;
- ring->flush = blt_ring_flush;
+ ring->flush = gen6_ring_flush;
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 06/18] drm/i915: add HAS_VEBOX
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (4 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 05/18] drm/i915: Rename ring flush functions Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 07/18] [v2] drm/i915: Vebox ringbuffer init Ben Widawsky
` (11 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
The flag will be useful to help share code between IVB, and HSW as the
programming is similar in many places with this as one of the major
differences.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Commit message + small fix by]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b7c3b98..078d284 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -311,6 +311,7 @@ static const struct intel_device_info intel_haswell_d_info = {
.is_haswell = 1,
.has_ddi = 1,
.has_fpga_dbg = 1,
+ .has_vebox_ring = 1,
};
static const struct intel_device_info intel_haswell_m_info = {
@@ -320,6 +321,7 @@ static const struct intel_device_info intel_haswell_m_info = {
.has_ddi = 1,
.has_fpga_dbg = 1,
.has_fbc = 1,
+ .has_vebox_ring = 1,
};
static const struct pci_device_id pciidlist[] = { /* aka */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0bbe9a..b6f2968 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -374,6 +374,7 @@ struct drm_i915_gt_funcs {
func(supports_tv) sep \
func(has_bsd_ring) sep \
func(has_blt_ring) sep \
+ func(has_vebox_ring) sep \
func(has_llc) sep \
func(has_ddi) sep \
func(has_fpga_dbg)
@@ -1373,6 +1374,7 @@ struct drm_i915_file_private {
#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
+#define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 07/18] [v2] drm/i915: Vebox ringbuffer init
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (5 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 06/18] drm/i915: add HAS_VEBOX Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
` (10 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
v2: Add set_seqno which didn't exist before rebase (Haihao)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 11 ++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 ++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index adb1c18..e5b6a92 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4010,12 +4010,21 @@ static int i915_gem_init_rings(struct drm_device *dev)
goto cleanup_bsd_ring;
}
+ if (HAS_VEBOX(dev)) {
+ ret = intel_init_vebox_ring_buffer(dev);
+ if (ret)
+ goto cleanup_blt_ring;
+ }
+
+
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
- goto cleanup_blt_ring;
+ goto cleanup_vebox_ring;
return 0;
+cleanup_vebox_ring:
+ intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
cleanup_blt_ring:
intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
cleanup_bsd_ring:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41c5d45..a5717f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -620,6 +620,7 @@
#define DONE_REG 0x40b0
#define BSD_HWS_PGA_GEN7 (0x04180)
#define BLT_HWS_PGA_GEN7 (0x04280)
+#define VEBOX_HWS_PGA_GEN7 (0x04380)
#define RING_ACTHD(base) ((base)+0x74)
#define RING_NOPID(base) ((base)+0x94)
#define RING_IMR(base) ((base)+0xa8)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 3022e15..89dfc63 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -916,7 +916,8 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
mmio = BSD_HWS_PGA_GEN7;
break;
case VECS:
- BUG();
+ mmio = VEBOX_HWS_PGA_GEN7;
+ break;
}
} else if (IS_GEN6(ring->dev)) {
mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
@@ -1909,6 +1910,38 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
return intel_init_ring_buffer(dev, ring);
}
+int intel_init_vebox_ring_buffer(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
+
+ ring->name = "video enhancement ring";
+ ring->id = VECS;
+
+ ring->mmio_base = VEBOX_RING_BASE;
+ ring->write_tail = ring_write_tail;
+ ring->flush = gen6_ring_flush;
+ ring->add_request = gen6_add_request;
+ ring->get_seqno = gen6_ring_get_seqno;
+ ring->set_seqno = ring_set_seqno;
+ ring->irq_enable_mask = 0;
+ ring->irq_get = NULL;
+ ring->irq_put = NULL;
+ ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
+ ring->sync_to = gen6_ring_sync;
+ ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
+ ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
+ ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
+ ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
+ ring->signal_mbox[RCS] = GEN6_RVESYNC;
+ ring->signal_mbox[VCS] = GEN6_VVESYNC;
+ ring->signal_mbox[BCS] = GEN6_BVESYNC;
+ ring->signal_mbox[VECS] = GEN6_NOSYNC;
+ ring->init = init_ring_common;
+
+ return intel_init_ring_buffer(dev, ring);
+}
+
int
intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
{
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 73619cb..1c79520 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -234,6 +234,7 @@ int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
int intel_init_render_ring_buffer(struct drm_device *dev);
int intel_init_bsd_ring_buffer(struct drm_device *dev);
int intel_init_blt_ring_buffer(struct drm_device *dev);
+int intel_init_vebox_ring_buffer(struct drm_device *dev);
u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (6 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 07/18] [v2] drm/i915: Vebox ringbuffer init Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 19:19 ` Daniel Vetter
2013-05-29 2:22 ` [PATCH 09/18] [v2] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
` (9 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
HSW has some special requirements for the VEBOX. Splitting out the
interrupt handler will make the code a bit nicer and less error prone
when we begin to handle those.
The slight functional change in this patch (queueing work while holding
the spinlock) is intentional as it makes a subsequent patch a bit nicer.
The change should also only effect HSW platforms.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 557acd3..c7b51c2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -842,6 +842,7 @@ static void snb_gt_irq_handler(struct drm_device *dev,
ivybridge_handle_parity_error(dev);
}
+/* Legacy way of handling PM interrupts */
static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
u32 pm_iir)
{
@@ -921,6 +922,31 @@ static void dp_aux_irq_handler(struct drm_device *dev)
wake_up_all(&dev_priv->gmbus_wait_queue);
}
+/* Unlike gen6_queue_rps_work() from which this function is originally derived,
+ * we must be able to deal with other PM interrupts. This is complicated because
+ * of the way in which we use the masks to defer the RPS work (which for
+ * posterity is necessary because of forcewake).
+ */
+static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
+ u32 pm_iir)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->rps.lock, flags);
+ dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
+ if (dev_priv->rps.pm_iir) {
+ I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
+ /* never want to mask useful interrupts. (also posting read) */
+ WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
+ /* TODO: if queue_work is slow, move it out of the spinlock */
+ queue_work(dev_priv->wq, &dev_priv->rps.work);
+ }
+ spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+
+ if (pm_iir & ~GEN6_PM_DEFERRED_EVENTS)
+ DRM_ERROR("Unexpected PM interrupted\n");
+}
+
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *) arg;
@@ -1231,7 +1257,9 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
pm_iir = I915_READ(GEN6_PMIIR);
if (pm_iir) {
- if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ if (IS_HASWELL(dev))
+ hsw_pm_irq_handler(dev_priv, pm_iir);
+ else if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
ret = IRQ_HANDLED;
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+
2013-05-29 2:22 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
@ 2013-05-29 19:19 ` Daniel Vetter
2013-05-31 18:25 ` Daniel Vetter
0 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-05-29 19:19 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:24PM -0700, Ben Widawsky wrote:
> HSW has some special requirements for the VEBOX. Splitting out the
> interrupt handler will make the code a bit nicer and less error prone
> when we begin to handle those.
>
> The slight functional change in this patch (queueing work while holding
> the spinlock) is intentional as it makes a subsequent patch a bit nicer.
> The change should also only effect HSW platforms.
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++++++++++++++++-
> 1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 557acd3..c7b51c2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -842,6 +842,7 @@ static void snb_gt_irq_handler(struct drm_device *dev,
> ivybridge_handle_parity_error(dev);
> }
>
> +/* Legacy way of handling PM interrupts */
> static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
> u32 pm_iir)
> {
> @@ -921,6 +922,31 @@ static void dp_aux_irq_handler(struct drm_device *dev)
> wake_up_all(&dev_priv->gmbus_wait_queue);
> }
>
> +/* Unlike gen6_queue_rps_work() from which this function is originally derived,
> + * we must be able to deal with other PM interrupts. This is complicated because
> + * of the way in which we use the masks to defer the RPS work (which for
> + * posterity is necessary because of forcewake).
> + */
> +static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
> + u32 pm_iir)
> +{
> + unsigned long flags;
> +
> + spin_lock_irqsave(&dev_priv->rps.lock, flags);
> + dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
> + if (dev_priv->rps.pm_iir) {
> + I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
> + /* never want to mask useful interrupts. (also posting read) */
> + WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
> + /* TODO: if queue_work is slow, move it out of the spinlock */
> + queue_work(dev_priv->wq, &dev_priv->rps.work);
Not happy how hsw and gen6 rps queueing now differs ever so slightly. It's
rather completely irrelevant where we actually queue the work since:
- interrupt handlers are non-reentrant
- queue_work is irq safe anyway.
So smells like cargo-culting too me.
So I've killed your TODO and moved it out. If there's indeed a good reason
later on we can reconsider.
-Daniel
> + }
> + spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
> +
> + if (pm_iir & ~GEN6_PM_DEFERRED_EVENTS)
> + DRM_ERROR("Unexpected PM interrupted\n");
> +}
> +
> static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> {
> struct drm_device *dev = (struct drm_device *) arg;
> @@ -1231,7 +1257,9 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
>
> pm_iir = I915_READ(GEN6_PMIIR);
> if (pm_iir) {
> - if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
> + if (IS_HASWELL(dev))
> + hsw_pm_irq_handler(dev_priv, pm_iir);
> + else if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
> gen6_queue_rps_work(dev_priv, pm_iir);
> I915_WRITE(GEN6_PMIIR, pm_iir);
> ret = IRQ_HANDLED;
> --
> 1.8.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+
2013-05-29 19:19 ` Daniel Vetter
@ 2013-05-31 18:25 ` Daniel Vetter
0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-05-31 18:25 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Wed, May 29, 2013 at 09:19:25PM +0200, Daniel Vetter wrote:
> On Tue, May 28, 2013 at 07:22:24PM -0700, Ben Widawsky wrote:
> > HSW has some special requirements for the VEBOX. Splitting out the
> > interrupt handler will make the code a bit nicer and less error prone
> > when we begin to handle those.
> >
> > The slight functional change in this patch (queueing work while holding
> > the spinlock) is intentional as it makes a subsequent patch a bit nicer.
> > The change should also only effect HSW platforms.
> >
> > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 30 +++++++++++++++++++++++++++++-
> > 1 file changed, 29 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 557acd3..c7b51c2 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -842,6 +842,7 @@ static void snb_gt_irq_handler(struct drm_device *dev,
> > ivybridge_handle_parity_error(dev);
> > }
> >
> > +/* Legacy way of handling PM interrupts */
> > static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
> > u32 pm_iir)
> > {
> > @@ -921,6 +922,31 @@ static void dp_aux_irq_handler(struct drm_device *dev)
> > wake_up_all(&dev_priv->gmbus_wait_queue);
> > }
> >
> > +/* Unlike gen6_queue_rps_work() from which this function is originally derived,
> > + * we must be able to deal with other PM interrupts. This is complicated because
> > + * of the way in which we use the masks to defer the RPS work (which for
> > + * posterity is necessary because of forcewake).
> > + */
> > +static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
> > + u32 pm_iir)
> > +{
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&dev_priv->rps.lock, flags);
> > + dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
> > + if (dev_priv->rps.pm_iir) {
> > + I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
> > + /* never want to mask useful interrupts. (also posting read) */
> > + WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
> > + /* TODO: if queue_work is slow, move it out of the spinlock */
> > + queue_work(dev_priv->wq, &dev_priv->rps.work);
>
> Not happy how hsw and gen6 rps queueing now differs ever so slightly. It's
> rather completely irrelevant where we actually queue the work since:
> - interrupt handlers are non-reentrant
> - queue_work is irq safe anyway.
> So smells like cargo-culting too me.
>
> So I've killed your TODO and moved it out. If there's indeed a good reason
> later on we can reconsider.
Dropped this change again since it affects correctness later on.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 09/18] [v2] drm/i915: Create an ivybridge_irq_preinstall
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (7 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 16:23 ` Damien Lespiau
2013-05-29 2:22 ` [PATCH 10/18] [v2] drm/i915: Add PM regs to pre/post install Ben Widawsky
` (8 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
v2: Add new PCH_NOP check (Damien)
Add SDEIMR comment (Damien)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c7b51c2..9143452 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2491,6 +2491,37 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
I915_WRITE(GTIER, 0x0);
POSTING_READ(GTIER);
+ /* south display irq */
+ I915_WRITE(SDEIMR, 0xffffffff);
+ /*
+ * SDEIER is also touched by the interrupt handler to work around missed
+ * PCH interrupts. Hence we can't update it after the interrupt handler
+ * is enabled - instead we unconditionally enable all PCH interrupt
+ * sources here, but then only unmask them as needed with SDEIMR.
+ */
+ I915_WRITE(SDEIER, 0xffffffff);
+ POSTING_READ(SDEIER);
+}
+
+static void ivybridge_irq_preinstall(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ atomic_set(&dev_priv->irq_received, 0);
+
+ I915_WRITE(HWSTAM, 0xeffe);
+
+ /* XXX hotplug from PCH */
+
+ I915_WRITE(DEIMR, 0xffffffff);
+ I915_WRITE(DEIER, 0x0);
+ POSTING_READ(DEIER);
+
+ /* and GT */
+ I915_WRITE(GTIMR, 0xffffffff);
+ I915_WRITE(GTIER, 0x0);
+ POSTING_READ(GTIER);
+
if (HAS_PCH_NOP(dev))
return;
@@ -3496,7 +3527,7 @@ void intel_irq_init(struct drm_device *dev)
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
/* Share pre & uninstall handlers with ILK/SNB */
dev->driver->irq_handler = ivybridge_irq_handler;
- dev->driver->irq_preinstall = ironlake_irq_preinstall;
+ dev->driver->irq_preinstall = ivybridge_irq_preinstall;
dev->driver->irq_postinstall = ivybridge_irq_postinstall;
dev->driver->irq_uninstall = ironlake_irq_uninstall;
dev->driver->enable_vblank = ivybridge_enable_vblank;
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 09/18] [v2] drm/i915: Create an ivybridge_irq_preinstall
2013-05-29 2:22 ` [PATCH 09/18] [v2] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
@ 2013-05-29 16:23 ` Damien Lespiau
2013-05-29 19:48 ` Daniel Vetter
0 siblings, 1 reply; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 16:23 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:25PM -0700, Ben Widawsky wrote:
> v2: Add new PCH_NOP check (Damien)
> Add SDEIMR comment (Damien)
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH 09/18] [v2] drm/i915: Create an ivybridge_irq_preinstall
2013-05-29 16:23 ` Damien Lespiau
@ 2013-05-29 19:48 ` Daniel Vetter
0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-05-29 19:48 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Ben Widawsky, Intel GFX
On Wed, May 29, 2013 at 05:23:46PM +0100, Damien Lespiau wrote:
> On Tue, May 28, 2013 at 07:22:25PM -0700, Ben Widawsky wrote:
> > v2: Add new PCH_NOP check (Damien)
> > Add SDEIMR comment (Damien)
> >
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Merged thus far, I need to sleep a bit over the interrupt changes. Oh how
I hate the tricky depencies we have in there, all without any runtime
asserts or anything like that to check it's still correct ...
Anyway, thanks for patches and review thus far.
Cheers, Daniel
>
> --
> Damien
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 10/18] [v2] drm/i915: Add PM regs to pre/post install
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (8 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 09/18] [v2] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 17:04 ` Damien Lespiau
2013-05-29 2:22 ` [PATCH 11/18] [v5] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
` (7 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
At the moment, these values are wiped out anyway by the rps
enable/disable. That will be changed in the next patch though.
v2: Add post install setup to address issue found by Damien in the next
patch.
replaced
WARN_ON(dev_priv->rps.pm_iir != 0);
with rps.pm_iir = 0;
With the v2 of this patch and the deferred pm enabling (which changed
since the original patches) we're now able to get PM interrupts before
we've brought up enabled rps. At this point in boot, we don't want to do
anything about it, so we simply ignore it. Since writing the original
assertion, the code has changed quite a bit, and I believe removing this
assertion is perfectly safe.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 10 ++++++++++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9143452..9c66fcf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2522,6 +2522,11 @@ static void ivybridge_irq_preinstall(struct drm_device *dev)
I915_WRITE(GTIER, 0x0);
POSTING_READ(GTIER);
+ /* Power management */
+ I915_WRITE(GEN6_PMIMR, 0xffffffff);
+ I915_WRITE(GEN6_PMIER, 0x0);
+ POSTING_READ(GEN6_PMIER);
+
if (HAS_PCH_NOP(dev))
return;
@@ -2710,6 +2715,11 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIER, render_irqs);
POSTING_READ(GTIER);
+ /* Power management */
+ I915_WRITE(GEN6_PMIMR, ~GEN6_PM_DEFERRED_EVENTS);
+ I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ POSTING_READ(GEN6_PMIMR);
+
ibx_irq_postinstall(dev);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9328ed9..66750fe 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2818,7 +2818,7 @@ static void gen6_enable_rps(struct drm_device *dev)
/* requires MSI enabled */
I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
spin_lock_irq(&dev_priv->rps.lock);
- WARN_ON(dev_priv->rps.pm_iir != 0);
+ dev_priv->rps.pm_iir = 0;
I915_WRITE(GEN6_PMIMR, 0);
spin_unlock_irq(&dev_priv->rps.lock);
/* enable all PM interrupts */
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 10/18] [v2] drm/i915: Add PM regs to pre/post install
2013-05-29 2:22 ` [PATCH 10/18] [v2] drm/i915: Add PM regs to pre/post install Ben Widawsky
@ 2013-05-29 17:04 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 17:04 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:26PM -0700, Ben Widawsky wrote:
> At the moment, these values are wiped out anyway by the rps
> enable/disable. That will be changed in the next patch though.
>
> v2: Add post install setup to address issue found by Damien in the next
> patch.
> replaced
> WARN_ON(dev_priv->rps.pm_iir != 0);
> with rps.pm_iir = 0;
>
> With the v2 of this patch and the deferred pm enabling (which changed
> since the original patches) we're now able to get PM interrupts before
> we've brought up enabled rps. At this point in boot, we don't want to do
> anything about it, so we simply ignore it. Since writing the original
> assertion, the code has changed quite a bit, and I believe removing this
> assertion is perfectly safe.
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 11/18] [v5] drm/i915: make PM interrupt writes non-destructive
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (9 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 10/18] [v2] drm/i915: Add PM regs to pre/post install Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 17:02 ` Damien Lespiau
2013-05-29 2:22 ` [PATCH 12/18] drm/i915: Convert irq_refounct to struct Ben Widawsky
` (6 subsequent siblings)
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
PM interrupts have an expanded role on HSW. It helps route the EBOX
interrupts. This patch is necessary to make the existing code which
touches the mask, and enable registers more friendly to other code paths
that also will need these registers.
To be more explicit:
At preinstall all interrupts are masked and disabled. This implies that
preinstall should always happen before any enabling/disabling of RPS or
other interrupts.
The PMIMR is touched by the workqueue, so enable/disable touch IER and
IIR. Similarly, the code currently expects IMR has no use outside of the
RPS related interrupts so they unconditionally set 0, or ~0. We could
use IER in the workqueue, and IMR elsewhere, but since the workqueue
use-case is more transient the existing usage makes sense.
Disable RPS events:
IER := IER & ~GEN6_PM_RPS_EVENTS // Disable RPS related interrupts
IIR := GEN6_PM_RPS_EVENTS // Disable any outstanding interrupts
Enable RPS events:
IER := IER | GEN6_PM_RPS_EVENTS // Enable the RPS related interrupts
IIR := GEN6_PM_RPS_EVENTS // Make sure there were no leftover events
(really shouldn't happen)
v2: Shouldn't destroy PMIIR or PMIMR VEBOX interrupt state in
enable/disable rps functions (Haihao)
v3: Bug found by Chris where we were clearing the wrong bits at rps
disable.
expanded commit message
v4: v3 was based off the wrong branch
v5: Added the setting of PMIMR because of previous patch update
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 21 +++++++++++----------
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++------
3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9c66fcf..8da936d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -700,10 +700,11 @@ static void gen6_pm_rps_work(struct work_struct *work)
pm_iir = dev_priv->rps.pm_iir;
dev_priv->rps.pm_iir = 0;
pm_imr = I915_READ(GEN6_PMIMR);
- I915_WRITE(GEN6_PMIMR, 0);
+ /* Make sure not to corrupt PMIMR state used by ringbuffer code */
+ I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
spin_unlock_irq(&dev_priv->rps.lock);
- if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
+ if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
return;
mutex_lock(&dev_priv->rps.hw_lock);
@@ -933,17 +934,17 @@ static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
unsigned long flags;
spin_lock_irqsave(&dev_priv->rps.lock, flags);
- dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
+ dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
if (dev_priv->rps.pm_iir) {
I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
/* never want to mask useful interrupts. (also posting read) */
- WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
+ WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
/* TODO: if queue_work is slow, move it out of the spinlock */
queue_work(dev_priv->wq, &dev_priv->rps.work);
}
spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
- if (pm_iir & ~GEN6_PM_DEFERRED_EVENTS)
+ if (pm_iir & ~GEN6_PM_RPS_EVENTS)
DRM_ERROR("Unexpected PM interrupted\n");
}
@@ -1018,7 +1019,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
gmbus_irq_handler(dev);
- if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ if (pm_iir & GEN6_PM_RPS_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GTIIR, gt_iir);
@@ -1259,7 +1260,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
if (pm_iir) {
if (IS_HASWELL(dev))
hsw_pm_irq_handler(dev_priv, pm_iir);
- else if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ else if (pm_iir & GEN6_PM_RPS_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GEN6_PMIIR, pm_iir);
ret = IRQ_HANDLED;
@@ -1374,7 +1375,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
ironlake_handle_rps_change(dev);
- if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
+ if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
gen6_queue_rps_work(dev_priv, pm_iir);
I915_WRITE(GTIIR, gt_iir);
@@ -2716,8 +2717,8 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
POSTING_READ(GTIER);
/* Power management */
- I915_WRITE(GEN6_PMIMR, ~GEN6_PM_DEFERRED_EVENTS);
- I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ I915_WRITE(GEN6_PMIMR, ~GEN6_PM_RPS_EVENTS);
+ I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
POSTING_READ(GEN6_PMIMR);
ibx_irq_postinstall(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a5717f1..3a29f99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4562,7 +4562,7 @@
#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
-#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
+#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
GEN6_PM_RP_DOWN_THRESHOLD | \
GEN6_PM_RP_DOWN_TIMEOUT)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 66750fe..09a2f90 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2625,7 +2625,7 @@ static void gen6_disable_rps(struct drm_device *dev)
I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
- I915_WRITE(GEN6_PMIER, 0);
+ I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
/* Complete PM interrupt masking here doesn't race with the rps work
* item again unmasking PM interrupts because that is using a different
* register (PMIMR) to mask PM interrupts. The only risk is in leaving
@@ -2635,7 +2635,7 @@ static void gen6_disable_rps(struct drm_device *dev)
dev_priv->rps.pm_iir = 0;
spin_unlock_irq(&dev_priv->rps.lock);
- I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+ I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
}
static void valleyview_disable_rps(struct drm_device *dev)
@@ -2816,12 +2816,13 @@ static void gen6_enable_rps(struct drm_device *dev)
gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
/* requires MSI enabled */
- I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
spin_lock_irq(&dev_priv->rps.lock);
dev_priv->rps.pm_iir = 0;
- I915_WRITE(GEN6_PMIMR, 0);
+ I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
+ I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
spin_unlock_irq(&dev_priv->rps.lock);
- /* enable all PM interrupts */
+ /* unmask all PM interrupts */
I915_WRITE(GEN6_PMINTRMSK, 0);
rc6vids = 0;
@@ -3084,7 +3085,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
valleyview_set_rps(dev_priv->dev, rpe);
/* requires MSI enabled */
- I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+ I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
spin_lock_irq(&dev_priv->rps.lock);
WARN_ON(dev_priv->rps.pm_iir != 0);
I915_WRITE(GEN6_PMIMR, 0);
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 11/18] [v5] drm/i915: make PM interrupt writes non-destructive
2013-05-29 2:22 ` [PATCH 11/18] [v5] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
@ 2013-05-29 17:02 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 17:02 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:27PM -0700, Ben Widawsky wrote:
> PM interrupts have an expanded role on HSW. It helps route the EBOX
> interrupts. This patch is necessary to make the existing code which
> touches the mask, and enable registers more friendly to other code paths
> that also will need these registers.
>
> To be more explicit:
> At preinstall all interrupts are masked and disabled. This implies that
> preinstall should always happen before any enabling/disabling of RPS or
> other interrupts.
>
> The PMIMR is touched by the workqueue, so enable/disable touch IER and
> IIR. Similarly, the code currently expects IMR has no use outside of the
> RPS related interrupts so they unconditionally set 0, or ~0. We could
> use IER in the workqueue, and IMR elsewhere, but since the workqueue
> use-case is more transient the existing usage makes sense.
>
> Disable RPS events:
> IER := IER & ~GEN6_PM_RPS_EVENTS // Disable RPS related interrupts
> IIR := GEN6_PM_RPS_EVENTS // Disable any outstanding interrupts
>
> Enable RPS events:
> IER := IER | GEN6_PM_RPS_EVENTS // Enable the RPS related interrupts
> IIR := GEN6_PM_RPS_EVENTS // Make sure there were no leftover events
> (really shouldn't happen)
>
> v2: Shouldn't destroy PMIIR or PMIMR VEBOX interrupt state in
> enable/disable rps functions (Haihao)
>
> v3: Bug found by Chris where we were clearing the wrong bits at rps
> disable.
> expanded commit message
>
> v4: v3 was based off the wrong branch
>
> v5: Added the setting of PMIMR because of previous patch update
>
> CC: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> drivers/gpu/drm/i915/i915_irq.c | 21 +++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 13 +++++++------
> 3 files changed, 19 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 9c66fcf..8da936d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -700,10 +700,11 @@ static void gen6_pm_rps_work(struct work_struct *work)
> pm_iir = dev_priv->rps.pm_iir;
> dev_priv->rps.pm_iir = 0;
> pm_imr = I915_READ(GEN6_PMIMR);
> - I915_WRITE(GEN6_PMIMR, 0);
> + /* Make sure not to corrupt PMIMR state used by ringbuffer code */
> + I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
> spin_unlock_irq(&dev_priv->rps.lock);
>
> - if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
> + if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
> return;
>
> mutex_lock(&dev_priv->rps.hw_lock);
> @@ -933,17 +934,17 @@ static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
> unsigned long flags;
>
> spin_lock_irqsave(&dev_priv->rps.lock, flags);
> - dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_DEFERRED_EVENTS;
> + dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
> if (dev_priv->rps.pm_iir) {
> I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
> /* never want to mask useful interrupts. (also posting read) */
> - WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_DEFERRED_EVENTS);
> + WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
> /* TODO: if queue_work is slow, move it out of the spinlock */
> queue_work(dev_priv->wq, &dev_priv->rps.work);
> }
> spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
>
> - if (pm_iir & ~GEN6_PM_DEFERRED_EVENTS)
> + if (pm_iir & ~GEN6_PM_RPS_EVENTS)
> DRM_ERROR("Unexpected PM interrupted\n");
> }
>
> @@ -1018,7 +1019,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
> gmbus_irq_handler(dev);
>
> - if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
> + if (pm_iir & GEN6_PM_RPS_EVENTS)
> gen6_queue_rps_work(dev_priv, pm_iir);
>
> I915_WRITE(GTIIR, gt_iir);
> @@ -1259,7 +1260,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
> if (pm_iir) {
> if (IS_HASWELL(dev))
> hsw_pm_irq_handler(dev_priv, pm_iir);
> - else if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
> + else if (pm_iir & GEN6_PM_RPS_EVENTS)
> gen6_queue_rps_work(dev_priv, pm_iir);
> I915_WRITE(GEN6_PMIIR, pm_iir);
> ret = IRQ_HANDLED;
> @@ -1374,7 +1375,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
> if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
> ironlake_handle_rps_change(dev);
>
> - if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
> + if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
> gen6_queue_rps_work(dev_priv, pm_iir);
>
> I915_WRITE(GTIIR, gt_iir);
> @@ -2716,8 +2717,8 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
> POSTING_READ(GTIER);
>
> /* Power management */
> - I915_WRITE(GEN6_PMIMR, ~GEN6_PM_DEFERRED_EVENTS);
> - I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
> + I915_WRITE(GEN6_PMIMR, ~GEN6_PM_RPS_EVENTS);
> + I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
> POSTING_READ(GEN6_PMIMR);
>
> ibx_irq_postinstall(dev);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a5717f1..3a29f99 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4562,7 +4562,7 @@
> #define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
> #define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
> #define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
> -#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
> +#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
> GEN6_PM_RP_DOWN_THRESHOLD | \
> GEN6_PM_RP_DOWN_TIMEOUT)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 66750fe..09a2f90 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2625,7 +2625,7 @@ static void gen6_disable_rps(struct drm_device *dev)
> I915_WRITE(GEN6_RC_CONTROL, 0);
> I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
> I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
> - I915_WRITE(GEN6_PMIER, 0);
> + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
> /* Complete PM interrupt masking here doesn't race with the rps work
> * item again unmasking PM interrupts because that is using a different
> * register (PMIMR) to mask PM interrupts. The only risk is in leaving
> @@ -2635,7 +2635,7 @@ static void gen6_disable_rps(struct drm_device *dev)
> dev_priv->rps.pm_iir = 0;
> spin_unlock_irq(&dev_priv->rps.lock);
>
> - I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
> + I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
> }
>
> static void valleyview_disable_rps(struct drm_device *dev)
> @@ -2816,12 +2816,13 @@ static void gen6_enable_rps(struct drm_device *dev)
> gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
>
> /* requires MSI enabled */
> - I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
> + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
> spin_lock_irq(&dev_priv->rps.lock);
> dev_priv->rps.pm_iir = 0;
> - I915_WRITE(GEN6_PMIMR, 0);
> + I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
> + I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
> spin_unlock_irq(&dev_priv->rps.lock);
> - /* enable all PM interrupts */
> + /* unmask all PM interrupts */
> I915_WRITE(GEN6_PMINTRMSK, 0);
>
> rc6vids = 0;
> @@ -3084,7 +3085,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
> valleyview_set_rps(dev_priv->dev, rpe);
>
> /* requires MSI enabled */
> - I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
> + I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
> spin_lock_irq(&dev_priv->rps.lock);
> WARN_ON(dev_priv->rps.pm_iir != 0);
> I915_WRITE(GEN6_PMIMR, 0);
> --
> 1.8.3
>
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 12/18] drm/i915: Convert irq_refounct to struct
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (10 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 11/18] [v5] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 13/18] [v2] drm/i915: consolidate interrupt naming scheme Ben Widawsky
` (5 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
It's overkill on older gens, but it's useful for newer gens.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++--------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +++-
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 89dfc63..c7a89bb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -795,7 +795,7 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
@@ -813,7 +813,7 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
dev_priv->gt_irq_mask |= ring->irq_enable_mask;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
POSTING_READ(GTIMR);
@@ -832,7 +832,7 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
dev_priv->irq_mask &= ~ring->irq_enable_mask;
I915_WRITE(IMR, dev_priv->irq_mask);
POSTING_READ(IMR);
@@ -850,7 +850,7 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
dev_priv->irq_mask |= ring->irq_enable_mask;
I915_WRITE(IMR, dev_priv->irq_mask);
POSTING_READ(IMR);
@@ -869,7 +869,7 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring)
return false;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
dev_priv->irq_mask &= ~ring->irq_enable_mask;
I915_WRITE16(IMR, dev_priv->irq_mask);
POSTING_READ16(IMR);
@@ -887,7 +887,7 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
dev_priv->irq_mask |= ring->irq_enable_mask;
I915_WRITE16(IMR, dev_priv->irq_mask);
POSTING_READ16(IMR);
@@ -980,7 +980,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
gen6_gt_force_wake_get(dev_priv);
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (ring->irq_refcount++ == 0) {
+ if (ring->irq_refcount.gt++ == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
GEN6_RENDER_L3_PARITY_ERROR));
@@ -1003,7 +1003,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- if (--ring->irq_refcount == 0) {
+ if (--ring->irq_refcount.gt == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
else
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1c79520..153b87f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -72,7 +72,9 @@ struct intel_ring_buffer {
*/
u32 last_retired_head;
- u32 irq_refcount; /* protected by dev_priv->irq_lock */
+ struct {
+ u32 gt;
+ } irq_refcount; /* protected by dev_priv->irq_lock */
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
u32 trace_irq_seqno;
u32 sync_seqno[I915_NUM_RINGS-1];
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 13/18] [v2] drm/i915: consolidate interrupt naming scheme
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (11 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 12/18] drm/i915: Convert irq_refounct to struct Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 14/18] [v2] drm/i915: vebox interrupt get/put Ben Widawsky
` (4 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
The motivation here is we're going to add some new interrupt definitions
and handling outside of the GT interrupts which is all we've managed so
far (with some RPS exceptions). By consolidating the names in the future
we can make thing a bit cleaner as we don't need to define register
names twice, and we can leverage pretty decent overlap in HW registers
since ILK.
To explain briefly what is in the comments: there are two sets of
interrupt masking/enabling registers. At least so far, the definitions
of the two sets overlap. The old code setup distinct names for
interrupts in each set, ie. one for global, and one for ring. This made
things confusing when using the wrong defines in the wrong places.
rebase: Modified VLV bits
v2: Renamed GT_RENDER_MASTER to GT_RENDER_CS_MASTER (Damien)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 61 ++++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 101 ++++++++++++++------------------
drivers/gpu/drm/i915/intel_ringbuffer.c | 21 ++++---
3 files changed, 85 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8da936d..4f7a12f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -780,7 +780,7 @@ static void ivybridge_parity_work(struct work_struct *work)
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@@ -812,7 +812,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev)
return;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
- dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
@@ -824,22 +824,22 @@ static void snb_gt_irq_handler(struct drm_device *dev,
u32 gt_iir)
{
- if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
- GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
+ if (gt_iir &
+ (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
notify_ring(dev, &dev_priv->ring[RCS]);
- if (gt_iir & GEN6_BSD_USER_INTERRUPT)
+ if (gt_iir & GT_BSD_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[VCS]);
- if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
+ if (gt_iir & GT_BLT_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[BCS]);
- if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
- GT_GEN6_BSD_CS_ERROR_INTERRUPT |
- GT_RENDER_CS_ERROR_INTERRUPT)) {
+ if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
+ GT_BSD_CS_ERROR_INTERRUPT |
+ GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
i915_handle_error(dev, false);
}
- if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
+ if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
ivybridge_handle_parity_error(dev);
}
@@ -1283,9 +1283,10 @@ static void ilk_gt_irq_handler(struct drm_device *dev,
struct drm_i915_private *dev_priv,
u32 gt_iir)
{
- if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+ if (gt_iir &
+ (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
notify_ring(dev, &dev_priv->ring[RCS]);
- if (gt_iir & GT_BSD_USER_INTERRUPT)
+ if (gt_iir & ILK_BSD_USER_INTERRUPT)
notify_ring(dev, &dev_priv->ring[VCS]);
}
@@ -2640,7 +2641,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
- u32 render_irqs;
+ u32 gt_irqs;
dev_priv->irq_mask = ~display_mask;
@@ -2655,17 +2656,15 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+ gt_irqs = GT_RENDER_USER_INTERRUPT;
+
if (IS_GEN6(dev))
- render_irqs =
- GT_USER_INTERRUPT |
- GEN6_BSD_USER_INTERRUPT |
- GEN6_BLITTER_USER_INTERRUPT;
+ gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
else
- render_irqs =
- GT_USER_INTERRUPT |
- GT_PIPE_NOTIFY |
- GT_BSD_USER_INTERRUPT;
- I915_WRITE(GTIER, render_irqs);
+ gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
+ ILK_BSD_USER_INTERRUPT;
+
+ I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
ibx_irq_postinstall(dev);
@@ -2691,7 +2690,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
DE_PLANEA_FLIP_DONE_IVB |
DE_AUX_CHANNEL_A_IVB |
DE_ERR_INT_IVB;
- u32 render_irqs;
+ u32 gt_irqs;
dev_priv->irq_mask = ~display_mask;
@@ -2706,14 +2705,14 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
DE_PIPEA_VBLANK_IVB);
POSTING_READ(DEIER);
- dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
+ dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
- render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
- GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
- I915_WRITE(GTIER, render_irqs);
+ gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
+ GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
+ I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
/* Power management */
@@ -2729,9 +2728,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
static int valleyview_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ u32 gt_irqs;
u32 enable_mask;
u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
- u32 render_irqs;
enable_mask = I915_DISPLAY_PORT_INTERRUPT;
enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -2767,9 +2766,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIIR, I915_READ(GTIIR));
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
- render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
- GEN6_BLITTER_USER_INTERRUPT;
- I915_WRITE(GTIER, render_irqs);
+ gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
+ GT_BLT_USER_INTERRUPT;
+ I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
/* ack & enable invalid PTE error interrupts */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3a29f99..b740f0d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -742,24 +742,6 @@
#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
-#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
-#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
-#define I915_HWB_OOM_INTERRUPT (1<<13)
-#define I915_SYNC_STATUS_INTERRUPT (1<<12)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
-#define I915_DEBUG_INTERRUPT (1<<2)
-#define I915_USER_INTERRUPT (1<<1)
-#define I915_ASLE_INTERRUPT (1<<0)
-#define I915_BSD_USER_INTERRUPT (1<<25)
#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
#define EIR 0x020b0
#define EMR 0x020b4
@@ -871,28 +853,6 @@
#define CACHE_MODE_1 0x7004 /* IVB+ */
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
-/* GEN6 interrupt control
- * Note that the per-ring interrupt bits do alias with the global interrupt bits
- * in GTIMR. */
-#define GEN6_RENDER_HWSTAM 0x2098
-#define GEN6_RENDER_IMR 0x20a8
-#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
-#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
-#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
-#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
-#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
-#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
-#define GEN6_RENDER_SYNC_STATUS (1 << 2)
-#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
-#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
-
-#define GEN6_BLITTER_HWSTAM 0x22098
-#define GEN6_BLITTER_IMR 0x220a8
-#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
-#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
-#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
-#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
-
#define GEN6_BLITTER_ECOSKPD 0x221d0
#define GEN6_BLITTER_LOCK_SHIFT 16
#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
@@ -903,9 +863,49 @@
#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
#define GEN6_BSD_GO_INDICATOR (1 << 4)
-#define GEN6_BSD_HWSTAM 0x12098
-#define GEN6_BSD_IMR 0x120a8
-#define GEN6_BSD_USER_INTERRUPT (1 << 12)
+/* On modern GEN architectures interrupt control consists of two sets
+ * of registers. The first set pertains to the ring generating the
+ * interrupt. The second control is for the functional block generating the
+ * interrupt. These are PM, GT, DE, etc.
+ *
+ * Luckily *knocks on wood* all the ring interrupt bits match up with the
+ * GT interrupt bits, so we don't need to duplicate the defines.
+ *
+ * These defines should cover us well from SNB->HSW with minor exceptions
+ * it can also work on ILK.
+ */
+#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
+#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
+#define GT_BLT_USER_INTERRUPT (1 << 22)
+#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
+#define GT_BSD_USER_INTERRUPT (1 << 12)
+#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
+#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
+#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
+#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
+#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
+#define GT_RENDER_USER_INTERRUPT (1 << 0)
+
+/* These are all the "old" interrupts */
+#define ILK_BSD_USER_INTERRUPT (1<<5)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
+#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
+#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
+#define I915_HWB_OOM_INTERRUPT (1<<13)
+#define I915_SYNC_STATUS_INTERRUPT (1<<12)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
+#define I915_DEBUG_INTERRUPT (1<<2)
+#define I915_USER_INTERRUPT (1<<1)
+#define I915_ASLE_INTERRUPT (1<<0)
+#define I915_BSD_USER_INTERRUPT (1 << 25)
#define GEN6_BSD_RNCID 0x12198
@@ -3710,21 +3710,6 @@
#define DEIIR 0x44008
#define DEIER 0x4400c
-/* GT interrupt.
- * Note that for gen6+ the ring-specific interrupt bits do alias with the
- * corresponding bits in the per-ring interrupt control registers. */
-#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
-#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25)
-#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22)
-#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15)
-#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
-#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */
-#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5)
-#define GT_PIPE_NOTIFY (1 << 4)
-#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3)
-#define GT_SYNC_STATUS (1 << 2)
-#define GT_USER_INTERRUPT (1 << 0)
-
#define GTISR 0x44010
#define GTIMR 0x44014
#define GTIIR 0x44018
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c7a89bb..5ab8cc2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -560,7 +560,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
if (HAS_L3_GPU_CACHE(dev))
- I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+ I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
return ret;
}
@@ -982,8 +982,9 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (ring->irq_refcount.gt++ == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
- I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
- GEN6_RENDER_L3_PARITY_ERROR));
+ I915_WRITE_IMR(ring,
+ ~(ring->irq_enable_mask |
+ GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
else
I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
@@ -1005,7 +1006,8 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--ring->irq_refcount.gt == 0) {
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
- I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
+ I915_WRITE_IMR(ring,
+ ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
else
I915_WRITE_IMR(ring, ~0);
dev_priv->gt_irq_mask |= ring->irq_enable_mask;
@@ -1682,7 +1684,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->flush = gen6_render_ring_flush;
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
- ring->irq_enable_mask = GT_USER_INTERRUPT;
+ ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->sync_to = gen6_ring_sync;
@@ -1701,7 +1703,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->set_seqno = pc_render_set_seqno;
ring->irq_get = gen5_ring_get_irq;
ring->irq_put = gen5_ring_put_irq;
- ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
+ ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
+ GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
} else {
ring->add_request = i9xx_add_request;
if (INTEL_INFO(dev)->gen < 4)
@@ -1843,7 +1846,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
+ ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
@@ -1863,7 +1866,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->get_seqno = ring_get_seqno;
ring->set_seqno = ring_set_seqno;
if (IS_GEN5(dev)) {
- ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
+ ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
ring->irq_get = gen5_ring_get_irq;
ring->irq_put = gen5_ring_put_irq;
} else {
@@ -1892,7 +1895,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
+ ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 14/18] [v2] drm/i915: vebox interrupt get/put
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (12 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 13/18] [v2] drm/i915: consolidate interrupt naming scheme Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 15/18] [v3] drm/i915: Enable vebox interrupts Ben Widawsky
` (3 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
v2: Use the correct lock to protect PM interrupt regs, this was
accidentally lost from earlier (Haihao)
Fix return types (Ben)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 46 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++--
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 5ab8cc2..8a6a0ee 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1019,6 +1019,48 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
gen6_gt_force_wake_put(dev_priv);
}
+static bool
+hsw_vebox_get_irq(struct intel_ring_buffer *ring)
+{
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ if (!dev->irq_enabled)
+ return false;
+
+ spin_lock_irqsave(&dev_priv->rps.lock, flags);
+ if (ring->irq_refcount.pm++ == 0) {
+ u32 pm_imr = I915_READ(GEN6_PMIMR);
+ I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
+ I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
+ POSTING_READ(GEN6_PMIMR);
+ }
+ spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+
+ return true;
+}
+
+static void
+hsw_vebox_put_irq(struct intel_ring_buffer *ring)
+{
+ struct drm_device *dev = ring->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ if (!dev->irq_enabled)
+ return;
+
+ spin_lock_irqsave(&dev_priv->rps.lock, flags);
+ if (--ring->irq_refcount.pm == 0) {
+ u32 pm_imr = I915_READ(GEN6_PMIMR);
+ I915_WRITE_IMR(ring, ~0);
+ I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
+ POSTING_READ(GEN6_PMIMR);
+ }
+ spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
+}
+
static int
i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
u32 offset, u32 length,
@@ -1928,8 +1970,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
ring->irq_enable_mask = 0;
- ring->irq_get = NULL;
- ring->irq_put = NULL;
+ ring->irq_get = hsw_vebox_get_irq;
+ ring->irq_put = hsw_vebox_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
ring->sync_to = gen6_ring_sync;
ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 153b87f..022d07e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -73,8 +73,9 @@ struct intel_ring_buffer {
u32 last_retired_head;
struct {
- u32 gt;
- } irq_refcount; /* protected by dev_priv->irq_lock */
+ u32 gt; /* protected by dev_priv->irq_lock */
+ u32 pm; /* protected by dev_priv->rps.lock (sucks) */
+ } irq_refcount;
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
u32 trace_irq_seqno;
u32 sync_seqno[I915_NUM_RINGS-1];
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 15/18] [v3] drm/i915: Enable vebox interrupts
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (13 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 14/18] [v2] drm/i915: vebox interrupt get/put Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 16/18] [v2] drm/i915: add VEBOX into debugfs Ben Widawsky
` (2 subsequent siblings)
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
Similar to a patch originally written by:
v2: Reversed the meanings of masked and enabled (Haihao)
Made non-destructive writes in case enable/disabler rps runs first
(Haihao)
v3: Reword error message (Damien)
Modify postinstall to do the right thing based on previous fixup. (Ben)
CC: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++++++++++------
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
3 files changed, 30 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4f7a12f..560465d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -944,8 +944,15 @@ static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
}
spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
- if (pm_iir & ~GEN6_PM_RPS_EVENTS)
- DRM_ERROR("Unexpected PM interrupted\n");
+ if (pm_iir & ~GEN6_PM_RPS_EVENTS) {
+ if (pm_iir & PM_VEBOX_USER_INTERRUPT)
+ notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
+
+ if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
+ DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
+ i915_handle_error(dev_priv->dev, false);
+ }
+ }
}
static irqreturn_t valleyview_irq_handler(int irq, void *arg)
@@ -2690,6 +2697,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
DE_PLANEA_FLIP_DONE_IVB |
DE_AUX_CHANNEL_A_IVB |
DE_ERR_INT_IVB;
+ u32 pm_irqs = GEN6_PM_RPS_EVENTS;
u32 gt_irqs;
dev_priv->irq_mask = ~display_mask;
@@ -2715,10 +2723,21 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
I915_WRITE(GTIER, gt_irqs);
POSTING_READ(GTIER);
- /* Power management */
- I915_WRITE(GEN6_PMIMR, ~GEN6_PM_RPS_EVENTS);
- I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
- POSTING_READ(GEN6_PMIMR);
+ I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
+ if (HAS_VEBOX(dev))
+ pm_irqs |= PM_VEBOX_USER_INTERRUPT |
+ PM_VEBOX_CS_ERROR_INTERRUPT;
+
+ /* Our enable/disable rps functions may touch these registers so
+ * make sure to set a known state for only the non-RPS bits.
+ * The RMW is extra paranoia since this should be called after being set
+ * to a known state in preinstall.
+ * */
+ I915_WRITE(GEN6_PMIMR,
+ (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
+ I915_WRITE(GEN6_PMIER,
+ (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
+ POSTING_READ(GEN6_PMIER);
ibx_irq_postinstall(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b740f0d..73348ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -886,6 +886,9 @@
#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
#define GT_RENDER_USER_INTERRUPT (1 << 0)
+#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
+#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
+
/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT (1<<5)
#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8a6a0ee..0e72da6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1969,7 +1969,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->add_request = gen6_add_request;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- ring->irq_enable_mask = 0;
+ ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
+ PM_VEBOX_CS_ERROR_INTERRUPT;
ring->irq_get = hsw_vebox_get_irq;
ring->irq_put = hsw_vebox_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 16/18] [v2] drm/i915: add VEBOX into debugfs
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (14 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 15/18] [v3] drm/i915: Enable vebox interrupts Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 16:22 ` [PATCH 16/18] [v3] " Ben Widawsky
2013-05-29 2:22 ` [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer() Ben Widawsky
2013-05-29 2:22 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
v2: Removed rebase relic VECS ring from i915_gem_request_info (Damien)
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Order changed, and modified by]
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2eb572a..5bbfc10 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -570,6 +570,7 @@ static const char *ring_str(int ring)
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
+ case VECS: return "vebox";
default: return "";
}
}
@@ -2222,6 +2223,7 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
+ {"i915_gem_hsw_vebox", i915_hws_info, 0, (void *)VECS},
{"i915_rstdby_delays", i915_rstdby_delays, 0},
{"i915_cur_delayinfo", i915_cur_delayinfo, 0},
{"i915_delayfreq_table", i915_delayfreq_table, 0},
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 16/18] [v3] drm/i915: add VEBOX into debugfs
2013-05-29 2:22 ` [PATCH 16/18] [v2] drm/i915: add VEBOX into debugfs Ben Widawsky
@ 2013-05-29 16:22 ` Ben Widawsky
2013-05-29 16:44 ` Damien Lespiau
0 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 16:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
v2: Removed rebase relic VECS ring from i915_gem_request_info (Damien)
v3: s/hsw/hws in debugfs which I introduced in v2 (Jon)
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Order changed, and modified by]
CC: "Bloomfield, Jon" <jon.bloomfield@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2eb572a..2b4a6fa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -570,6 +570,7 @@ static const char *ring_str(int ring)
case RCS: return "render";
case VCS: return "bsd";
case BCS: return "blt";
+ case VECS: return "vebox";
default: return "";
}
}
@@ -2222,6 +2223,7 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
+ {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
{"i915_rstdby_delays", i915_rstdby_delays, 0},
{"i915_cur_delayinfo", i915_cur_delayinfo, 0},
{"i915_delayfreq_table", i915_delayfreq_table, 0},
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 16/18] [v3] drm/i915: add VEBOX into debugfs
2013-05-29 16:22 ` [PATCH 16/18] [v3] " Ben Widawsky
@ 2013-05-29 16:44 ` Damien Lespiau
0 siblings, 0 replies; 84+ messages in thread
From: Damien Lespiau @ 2013-05-29 16:44 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Wed, May 29, 2013 at 09:22:36AM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao" <haihao.xiang@intel.com>
>
> v2: Removed rebase relic VECS ring from i915_gem_request_info (Damien)
>
> v3: s/hsw/hws in debugfs which I introduced in v2 (Jon)
>
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> [Order changed, and modified by]
> CC: "Bloomfield, Jon" <jon.bloomfield@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 84+ messages in thread
* [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer()
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (15 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 16/18] [v2] drm/i915: add VEBOX into debugfs Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-29 2:22 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
17 siblings, 0 replies; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
A user can run batchbuffer via VEBOX ring.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 9 +++++++++
include/uapi/drm/i915_drm.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 117ce38..a8bb62c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -885,6 +885,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
return -EPERM;
}
break;
+ case I915_EXEC_VEBOX:
+ ring = &dev_priv->ring[VECS];
+ if (ctx_id != 0) {
+ DRM_DEBUG("Ring %s doesn't support contexts\n",
+ ring->name);
+ return -EPERM;
+ }
+ break;
+
default:
DRM_DEBUG("execbuf with unknown ring: %d\n",
(int)(args->flags & I915_EXEC_RING_MASK));
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 07d5941..81b9981 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -660,6 +660,7 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_VEBOX (4<<0)
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
* Gen6+ only supports relative addressing to dynamic state (default) and
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
2013-05-29 2:22 ` [PATCH 00/18] Introduce the Haswell VECS v2 Ben Widawsky
` (16 preceding siblings ...)
2013-05-29 2:22 ` [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer() Ben Widawsky
@ 2013-05-29 2:22 ` Ben Widawsky
2013-05-31 18:52 ` Daniel Vetter
17 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-29 2:22 UTC (permalink / raw)
To: Intel GFX; +Cc: Ben Widawsky
From: "Xiang, Haihao" <haihao.xiang@intel.com>
This will let userland only try to use the new ring
when the appropriate kernel is present
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
include/uapi/drm/i915_drm.h | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 3cd2b60..03ee193 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -956,6 +956,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_BLT:
value = intel_ring_initialized(&dev_priv->ring[BCS]);
break;
+ case I915_PARAM_HAS_VEBOX:
+ value = intel_ring_initialized(&dev_priv->ring[VECS]);
+ break;
case I915_PARAM_HAS_RELAXED_FENCING:
value = 1;
break;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 81b9981..923ed7f 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -305,7 +305,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
#define I915_PARAM_HAS_SEMAPHORES 20
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
-#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
+#define I915_PARAM_HAS_VEBOX 22
#define I915_PARAM_HAS_SECURE_BATCHES 23
#define I915_PARAM_HAS_PINNED_BATCHES 24
#define I915_PARAM_HAS_EXEC_NO_RELOC 25
--
1.8.3
^ permalink raw reply related [flat|nested] 84+ messages in thread* Re: [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
2013-05-29 2:22 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
@ 2013-05-31 18:52 ` Daniel Vetter
2013-05-31 19:52 ` Ben Widawsky
0 siblings, 1 reply; 84+ messages in thread
From: Daniel Vetter @ 2013-05-31 18:52 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Tue, May 28, 2013 at 07:22:34PM -0700, Ben Widawsky wrote:
> From: "Xiang, Haihao" <haihao.xiang@intel.com>
>
> This will let userland only try to use the new ring
> when the appropriate kernel is present
>
> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
So originally I wanted to take a closer look at the interrupt handling
changes before merging them. But somehow my brain was notoriously not up
to the task of reviewing tricky interrupt stuff. Anyway here's my list of
things I've spotted while applying patches:
- Unrelated, but spotted while checking interrupt code:
ironlake_enable_display_irq is not called with the irq_lock held
everywhere, and some are outside of the irq setup/teradown (so real
races). Specifically
commit 8664281b64c457705db72fc60143d03827e75ca9
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Fri Apr 12 17:57:57 2013 -0300
drm/i915: report Gen5+ CPU and PCH FIFO underruns
broke stuff. But I guess a full review of the interrupt handling code
should be in order ... At least we should sprinkle assert_spin_locked
harder.
Now the real stuff:
- rmw register access isn't paranoid, but imo fragile. Either we don't
need it, and then it just obfuscates the code (especially with scary
comments around). Or there's indeed a race somewhere, and then rmw is
_really_ good at papering over it. Until it blows up randomly and no one
has a clue why.
So I'm not a fan, and I've pretty much exlcusive just killed them. These
patches add _lots_ of them instead.
- rps.lock could just be killed and existing users switched over to
irq_lock. Would simplify a lot in the interrupt handling. E.g. the
special ring->irqrefcount could just be dropped.
- rps setup is async now (yeah, that's newer than these patches, still). I
think I've seen a few races around that ...
- There's no inconsistencies in the PM rps interrupt setup on snb vs
ivb/hsw. Such inconsistency tend to be fragile (but I haven't spotted
something which would blow up on snb).
- CS_MASTER interrupt handling: None of the other rings seem to enable
this on gen5+. Not sure whether it actually works correctly, I suspect
at least i915_report_and_clear_eir needs some more code ...
- Calling queue_work from the spin_lock protection smells a bit like
cargo-culting (I've reinstated that one since later patches would have
been broken).
- hsw_pm_irq_handler has no need to unconditionally take the spinlock.
Patches are merged for now, but I'm not happy by far.
Cheers, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 84+ messages in thread* Re: [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
2013-05-31 18:52 ` Daniel Vetter
@ 2013-05-31 19:52 ` Ben Widawsky
2013-05-31 20:08 ` Daniel Vetter
0 siblings, 1 reply; 84+ messages in thread
From: Ben Widawsky @ 2013-05-31 19:52 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Intel GFX
On Fri, May 31, 2013 at 08:52:29PM +0200, Daniel Vetter wrote:
> On Tue, May 28, 2013 at 07:22:34PM -0700, Ben Widawsky wrote:
> > From: "Xiang, Haihao" <haihao.xiang@intel.com>
> >
> > This will let userland only try to use the new ring
> > when the appropriate kernel is present
> >
> > Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>
> So originally I wanted to take a closer look at the interrupt handling
> changes before merging them. But somehow my brain was notoriously not up
> to the task of reviewing tricky interrupt stuff. Anyway here's my list of
> things I've spotted while applying patches:
>
> - Unrelated, but spotted while checking interrupt code:
> ironlake_enable_display_irq is not called with the irq_lock held
> everywhere, and some are outside of the irq setup/teradown (so real
> races). Specifically
>
> commit 8664281b64c457705db72fc60143d03827e75ca9
> Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Date: Fri Apr 12 17:57:57 2013 -0300
>
> drm/i915: report Gen5+ CPU and PCH FIFO underruns
>
> broke stuff. But I guess a full review of the interrupt handling code
> should be in order ... At least we should sprinkle assert_spin_locked
> harder.
>
> Now the real stuff:
>
> - rmw register access isn't paranoid, but imo fragile. Either we don't
> need it, and then it just obfuscates the code (especially with scary
> comments around). Or there's indeed a race somewhere, and then rmw is
> _really_ good at papering over it. Until it blows up randomly and no one
> has a clue why.
>
> So I'm not a fan, and I've pretty much exlcusive just killed them. These
> patches add _lots_ of them instead.
>
> - rps.lock could just be killed and existing users switched over to
> irq_lock. Would simplify a lot in the interrupt handling. E.g. the
> special ring->irqrefcount could just be dropped.
>
> - rps setup is async now (yeah, that's newer than these patches, still). I
> think I've seen a few races around that ...
>
> - There's no inconsistencies in the PM rps interrupt setup on snb vs
> ivb/hsw. Such inconsistency tend to be fragile (but I haven't spotted
> something which would blow up on snb).
>
> - CS_MASTER interrupt handling: None of the other rings seem to enable
> this on gen5+. Not sure whether it actually works correctly, I suspect
> at least i915_report_and_clear_eir needs some more code ...
>
> - Calling queue_work from the spin_lock protection smells a bit like
> cargo-culting (I've reinstated that one since later patches would have
> been broken).
>
> - hsw_pm_irq_handler has no need to unconditionally take the spinlock.
>
> Patches are merged for now, but I'm not happy by far.
>
> Cheers, Daniel
Of these, which have you changed/fixed? That way if someone wants to
start addressing the issues, they know where to start.
--
Ben Widawsky, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 84+ messages in thread
* Re: [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam
2013-05-31 19:52 ` Ben Widawsky
@ 2013-05-31 20:08 ` Daniel Vetter
0 siblings, 0 replies; 84+ messages in thread
From: Daniel Vetter @ 2013-05-31 20:08 UTC (permalink / raw)
To: Ben Widawsky; +Cc: Intel GFX
On Fri, May 31, 2013 at 12:52:03PM -0700, Ben Widawsky wrote:
> On Fri, May 31, 2013 at 08:52:29PM +0200, Daniel Vetter wrote:
> > On Tue, May 28, 2013 at 07:22:34PM -0700, Ben Widawsky wrote:
> > > From: "Xiang, Haihao" <haihao.xiang@intel.com>
> > >
> > > This will let userland only try to use the new ring
> > > when the appropriate kernel is present
> > >
> > > Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> > > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> >
> > So originally I wanted to take a closer look at the interrupt handling
> > changes before merging them. But somehow my brain was notoriously not up
> > to the task of reviewing tricky interrupt stuff. Anyway here's my list of
> > things I've spotted while applying patches:
> >
> > - Unrelated, but spotted while checking interrupt code:
> > ironlake_enable_display_irq is not called with the irq_lock held
> > everywhere, and some are outside of the irq setup/teradown (so real
> > races). Specifically
> >
> > commit 8664281b64c457705db72fc60143d03827e75ca9
> > Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Date: Fri Apr 12 17:57:57 2013 -0300
> >
> > drm/i915: report Gen5+ CPU and PCH FIFO underruns
> >
> > broke stuff. But I guess a full review of the interrupt handling code
> > should be in order ... At least we should sprinkle assert_spin_locked
> > harder.
> >
> > Now the real stuff:
> >
> > - rmw register access isn't paranoid, but imo fragile. Either we don't
> > need it, and then it just obfuscates the code (especially with scary
> > comments around). Or there's indeed a race somewhere, and then rmw is
> > _really_ good at papering over it. Until it blows up randomly and no one
> > has a clue why.
> >
> > So I'm not a fan, and I've pretty much exlcusive just killed them. These
> > patches add _lots_ of them instead.
> >
> > - rps.lock could just be killed and existing users switched over to
> > irq_lock. Would simplify a lot in the interrupt handling. E.g. the
> > special ring->irqrefcount could just be dropped.
> >
> > - rps setup is async now (yeah, that's newer than these patches, still). I
> > think I've seen a few races around that ...
> >
> > - There's no inconsistencies in the PM rps interrupt setup on snb vs
*now*
> > ivb/hsw. Such inconsistency tend to be fragile (but I haven't spotted
> > something which would blow up on snb).
> >
> > - CS_MASTER interrupt handling: None of the other rings seem to enable
> > this on gen5+. Not sure whether it actually works correctly, I suspect
> > at least i915_report_and_clear_eir needs some more code ...
> >
> > - Calling queue_work from the spin_lock protection smells a bit like
> > cargo-culting (I've reinstated that one since later patches would have
> > been broken).
> >
> > - hsw_pm_irq_handler has no need to unconditionally take the spinlock.
> >
> > Patches are merged for now, but I'm not happy by far.
> >
> > Cheers, Daniel
>
> Of these, which have you changed/fixed? That way if someone wants to
> start addressing the issues, they know where to start.
I've added a FIXME comment for the dropped WARN (which isn't in this list,
oops). Otherwise I've dropped all my changes since it grew unwiedly, fast.
But anyway that list above is only a rough guideline of things that had a
funny smell while reading. Like I've said my brain wasn't on top of things
to do a full irq handling review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 84+ messages in thread