From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Russell King <linux@arm.linux.org.uk>, Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 7/9] ARM: dove: add PCIe controllers to SoC DT Date: Mon, 12 Aug 2013 20:46:53 +0200 [thread overview] Message-ID: <1376333215-12885-8-git-send-email-sebastian.hesselbarth@gmail.com> (raw) In-Reply-To: <1376333215-12885-1-git-send-email-sebastian.hesselbarth@gmail.com> This adds a node for the pcie controllers found on Dove SoCs to the SoC DT include. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- Cc: Russell King <linux@arm.linux.org.uk> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/dove.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index d42b323..499abad 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -44,6 +44,60 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ + pcie: pcie-controller { + compatible = "marvell,dove-pcie"; + status = "disabled"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&intc>; + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 + 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 + 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ + 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ + 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ + 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ + + pcie-port@0 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + clocks = <&gate_clk 4>; + marvell,pcie-port = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 16>; + }; + + pcie-port@1 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + clocks = <&gate_clk 5>; + marvell,pcie-port = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 18>; + }; + }; + internal-regs { compatible = "simple-bus"; #address-cells = <1>; -- 1.7.10.4
WARNING: multiple messages have this Message-ID (diff)
From: sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 7/9] ARM: dove: add PCIe controllers to SoC DT Date: Mon, 12 Aug 2013 20:46:53 +0200 [thread overview] Message-ID: <1376333215-12885-8-git-send-email-sebastian.hesselbarth@gmail.com> (raw) In-Reply-To: <1376333215-12885-1-git-send-email-sebastian.hesselbarth@gmail.com> This adds a node for the pcie controllers found on Dove SoCs to the SoC DT include. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- Cc: Russell King <linux@arm.linux.org.uk> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-kernel at vger.kernel.org Cc: linux-arm-kernel at lists.infradead.org --- arch/arm/boot/dts/dove.dtsi | 54 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index d42b323..499abad 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -44,6 +44,60 @@ MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */ MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */ + pcie: pcie-controller { + compatible = "marvell,dove-pcie"; + status = "disabled"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&intc>; + bus-range = <0x00 0xff>; + + ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000 + 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000 + 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */ + 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */ + 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */ + 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */ + + pcie-port at 0 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + clocks = <&gate_clk 4>; + marvell,pcie-port = <0>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 16>; + }; + + pcie-port at 1 { + device_type = "pci"; + status = "disabled"; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + clocks = <&gate_clk 5>; + marvell,pcie-port = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc 18>; + }; + }; + internal-regs { compatible = "simple-bus"; #address-cells = <1>; -- 1.7.10.4
next prev parent reply other threads:[~2013-08-12 18:47 UTC|newest] Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top 2013-08-12 18:46 [PATCH 0/9] ARM: dove: DT PCIe support Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-12 18:46 ` [PATCH 1/9] PCI: mvebu: move clock enable before register access Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-13 7:11 ` Thomas Petazzoni 2013-08-13 7:11 ` Thomas Petazzoni 2013-08-13 9:22 ` Sebastian Hesselbarth 2013-08-13 9:22 ` Sebastian Hesselbarth 2013-08-13 7:58 ` Thierry Reding 2013-08-13 7:58 ` Thierry Reding 2013-08-12 18:46 ` [PATCH 2/9] PCI: mvebu: increment nports only for registered ports Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-13 7:15 ` Thomas Petazzoni 2013-08-13 7:15 ` Thomas Petazzoni 2013-08-13 9:23 ` Sebastian Hesselbarth 2013-08-13 9:23 ` Sebastian Hesselbarth 2013-08-12 18:46 ` [PATCH 3/9] PCI: mvebu: remove subsys_initcall Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-13 7:19 ` Thomas Petazzoni 2013-08-13 7:19 ` Thomas Petazzoni 2013-08-13 8:06 ` Thierry Reding 2013-08-13 8:06 ` Thierry Reding 2013-08-13 9:25 ` Sebastian Hesselbarth 2013-08-13 9:25 ` Sebastian Hesselbarth 2013-08-12 18:46 ` [PATCH 4/9] PCI: mvebu: add support for reset on GPIO Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-13 0:56 ` Kumar Gala 2013-08-13 0:56 ` Kumar Gala 2013-08-13 9:19 ` Sebastian Hesselbarth 2013-08-13 9:19 ` Sebastian Hesselbarth 2013-08-13 8:09 ` Thierry Reding 2013-08-13 8:09 ` Thierry Reding 2013-08-13 8:30 ` Thomas Petazzoni 2013-08-13 8:30 ` Thomas Petazzoni 2013-08-13 9:59 ` Sascha Hauer 2013-08-13 9:59 ` Sascha Hauer 2013-08-13 10:03 ` Thierry Reding 2013-08-13 10:03 ` Thierry Reding 2013-08-13 10:40 ` Sebastian Hesselbarth 2013-08-13 10:40 ` Sebastian Hesselbarth 2013-08-13 10:59 ` Philipp Zabel 2013-08-13 10:59 ` Philipp Zabel 2013-08-12 18:46 ` [PATCH 5/9] PCI: mvebu: add support for Marvell Dove SoCs Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-12 18:46 ` [PATCH 6/9] ARM: dove: update dove_defconfig with SI5351, PCI, and xHCI Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-12 20:00 ` Jason Cooper 2013-08-12 20:00 ` Jason Cooper 2013-08-12 18:46 ` Sebastian Hesselbarth [this message] 2013-08-12 18:46 ` [PATCH 7/9] ARM: dove: add PCIe controllers to SoC DT Sebastian Hesselbarth 2013-08-12 20:04 ` Jason Cooper 2013-08-12 20:04 ` Jason Cooper 2013-08-13 11:28 ` Sebastian Hesselbarth 2013-08-13 11:28 ` Sebastian Hesselbarth 2013-08-13 13:21 ` Jason Cooper 2013-08-13 13:21 ` Jason Cooper 2013-08-13 13:48 ` Jason Cooper 2013-08-13 13:48 ` Jason Cooper 2013-08-12 18:46 ` [PATCH 8/9] ARM: dove: add initial DT file for Globalscale D3Plug Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-12 18:46 ` [PATCH 9/9] ARM: dove: remove legacy pcie and clock init Sebastian Hesselbarth 2013-08-12 18:46 ` Sebastian Hesselbarth 2013-08-12 20:54 ` [PATCH 0/9] ARM: dove: DT PCIe support Bjorn Helgaas 2013-08-12 20:54 ` Bjorn Helgaas
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