[PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

The patch series aims to add memory mapped support for TI qspi
contoller and also add support for the same in serial flash driver(m25p80).

These feature was added as a part of the series[1]:
The series[1] add support for quad and memory mapped feature in spi and
flash driver. Based on Brian Norris suggestion on splitting the quad and 
memory mapped feature, I had sent a seperate series for quad support which 
has beed accepted by Brian.

The $subject patch series takes care of the memory mapped part.  

Overview of memory mapped support in qspi:
 TI qspi controller supports memory mapped read support, switching to which
 requires  register modifications(qspi registers, control module register for
 DRA, qspi register for am43x). Once switched, the flash data can be available
 at a soc specific memory mapped address. For operations in normal mode, we need 
 to keep memory mapped disable.

 Flow of the patch is to keep the memory mapped enable by default in the driver.
 Whenever Normal spi mode operations are desired, we switch to configuration mode
 and at the end of it memory mapped is again enabled. There are few function pointers
 added to fecilitate easy communication between the flash and spi controllers.

Major changes in the $subject patch based on discussion in [1]:

- Feature has been broken down into small meaningfl patches.
- memcpy is done in flash driver and spi framework is bypassed.
- configuration of memory mapped spi controller regsiters is done
  through function calls from flash side.

[1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html

v1->v2:
 Mentioned on individual patches.
Overall change is the squashing of few patches.


v1:
https://patchwork.kernel.org/patch/3237091/

Tested on DRA7 board with spansion S25FL256S flash along with some
internal irq crossbar patches.
Tested on AM437x epos evm with macronix MX66l51235l flash.

Testing done:
-Erase the whole flash.
-write to the flash
-read back the flash
- compare the data


Sourav Poddar (10):
  spi/spi.h: Add get_buf/put_buf support in spi master..
  spi/qspi: parse register by name.
  spi/qspi: Add support to switc to memory mapped operation.
  spi/qspi: configure set up register for memory map..
  spi/qspi: Add api for get_buf/put_buf.
  drivers: mtd: m25p80: Add api to configure master register.
  drivers: mtd: m25p80: Adapt driver to support memory mapped read.
  Documentation: bindings: ti-qspi: update binding information.
  arm: dts: dra7: Add qspi device.
  arm: dts: am43x-epos: Add qspi device.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    8 +-
 arch/arm/boot/dts/am4372.dtsi                     |   12 ++
 arch/arm/boot/dts/am43x-epos-evm.dts              |   28 +++++
 arch/arm/boot/dts/dra7-evm.dts                    |   32 +++++
 arch/arm/boot/dts/dra7.dtsi                       |   13 ++
 drivers/mtd/devices/m25p80.c                      |   38 ++++++
 drivers/spi/spi-ti-qspi.c                         |  130 ++++++++++++++++++++-
 include/linux/spi/spi.h                           |   22 ++++
 8 files changed, 280 insertions(+), 3 deletions(-)

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[PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

The patch series aims to add memory mapped support for TI qspi
contoller and also add support for the same in serial flash driver(m25p80).

These feature was added as a part of the series[1]:
The series[1] add support for quad and memory mapped feature in spi and
flash driver. Based on Brian Norris suggestion on splitting the quad and 
memory mapped feature, I had sent a seperate series for quad support which 
has beed accepted by Brian.

The $subject patch series takes care of the memory mapped part.  

Overview of memory mapped support in qspi:
 TI qspi controller supports memory mapped read support, switching to which
 requires  register modifications(qspi registers, control module register for
 DRA, qspi register for am43x). Once switched, the flash data can be available
 at a soc specific memory mapped address. For operations in normal mode, we need 
 to keep memory mapped disable.

 Flow of the patch is to keep the memory mapped enable by default in the driver.
 Whenever Normal spi mode operations are desired, we switch to configuration mode
 and at the end of it memory mapped is again enabled. There are few function pointers
 added to fecilitate easy communication between the flash and spi controllers.

Major changes in the $subject patch based on discussion in [1]:

- Feature has been broken down into small meaningfl patches.
- memcpy is done in flash driver and spi framework is bypassed.
- configuration of memory mapped spi controller regsiters is done
  through function calls from flash side.

[1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html

v1->v2:
 Mentioned on individual patches.
Overall change is the squashing of few patches.


v1:
https://patchwork.kernel.org/patch/3237091/

Tested on DRA7 board with spansion S25FL256S flash along with some
internal irq crossbar patches.
Tested on AM437x epos evm with macronix MX66l51235l flash.

Testing done:
-Erase the whole flash.
-write to the flash
-read back the flash
- compare the data


Sourav Poddar (10):
  spi/spi.h: Add get_buf/put_buf support in spi master..
  spi/qspi: parse register by name.
  spi/qspi: Add support to switc to memory mapped operation.
  spi/qspi: configure set up register for memory map..
  spi/qspi: Add api for get_buf/put_buf.
  drivers: mtd: m25p80: Add api to configure master register.
  drivers: mtd: m25p80: Adapt driver to support memory mapped read.
  Documentation: bindings: ti-qspi: update binding information.
  arm: dts: dra7: Add qspi device.
  arm: dts: am43x-epos: Add qspi device.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    8 +-
 arch/arm/boot/dts/am4372.dtsi                     |   12 ++
 arch/arm/boot/dts/am43x-epos-evm.dts              |   28 +++++
 arch/arm/boot/dts/dra7-evm.dts                    |   32 +++++
 arch/arm/boot/dts/dra7.dtsi                       |   13 ++
 drivers/mtd/devices/m25p80.c                      |   38 ++++++
 drivers/spi/spi-ti-qspi.c                         |  130 ++++++++++++++++++++-
 include/linux/spi/spi.h                           |   22 ++++
 8 files changed, 280 insertions(+), 3 deletions(-)

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To unsubscribe from this list: send the line "unsubscribe linux-spi" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

The patch series aims to add memory mapped support for TI qspi
contoller and also add support for the same in serial flash driver(m25p80).

These feature was added as a part of the series[1]:
The series[1] add support for quad and memory mapped feature in spi and
flash driver. Based on Brian Norris suggestion on splitting the quad and 
memory mapped feature, I had sent a seperate series for quad support which 
has beed accepted by Brian.

The $subject patch series takes care of the memory mapped part.  

Overview of memory mapped support in qspi:
 TI qspi controller supports memory mapped read support, switching to which
 requires  register modifications(qspi registers, control module register for
 DRA, qspi register for am43x). Once switched, the flash data can be available
 at a soc specific memory mapped address. For operations in normal mode, we need 
 to keep memory mapped disable.

 Flow of the patch is to keep the memory mapped enable by default in the driver.
 Whenever Normal spi mode operations are desired, we switch to configuration mode
 and at the end of it memory mapped is again enabled. There are few function pointers
 added to fecilitate easy communication between the flash and spi controllers.

Major changes in the $subject patch based on discussion in [1]:

- Feature has been broken down into small meaningfl patches.
- memcpy is done in flash driver and spi framework is bypassed.
- configuration of memory mapped spi controller regsiters is done
  through function calls from flash side.

[1]: http://lists.infradead.org/pipermail/linux-mtd/2013-October/049058.html

v1->v2:
 Mentioned on individual patches.
Overall change is the squashing of few patches.


v1:
https://patchwork.kernel.org/patch/3237091/

Tested on DRA7 board with spansion S25FL256S flash along with some
internal irq crossbar patches.
Tested on AM437x epos evm with macronix MX66l51235l flash.

Testing done:
-Erase the whole flash.
-write to the flash
-read back the flash
- compare the data


Sourav Poddar (10):
  spi/spi.h: Add get_buf/put_buf support in spi master..
  spi/qspi: parse register by name.
  spi/qspi: Add support to switc to memory mapped operation.
  spi/qspi: configure set up register for memory map..
  spi/qspi: Add api for get_buf/put_buf.
  drivers: mtd: m25p80: Add api to configure master register.
  drivers: mtd: m25p80: Adapt driver to support memory mapped read.
  Documentation: bindings: ti-qspi: update binding information.
  arm: dts: dra7: Add qspi device.
  arm: dts: am43x-epos: Add qspi device.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    8 +-
 arch/arm/boot/dts/am4372.dtsi                     |   12 ++
 arch/arm/boot/dts/am43x-epos-evm.dts              |   28 +++++
 arch/arm/boot/dts/dra7-evm.dts                    |   32 +++++
 arch/arm/boot/dts/dra7.dtsi                       |   13 ++
 drivers/mtd/devices/m25p80.c                      |   38 ++++++
 drivers/spi/spi-ti-qspi.c                         |  130 ++++++++++++++++++++-
 include/linux/spi/spi.h                           |   22 ++++
 8 files changed, 280 insertions(+), 3 deletions(-)

[PATCHv2 01/10] spi/spi.h: Add get_buf/put_buf support in spi master.

[Sourav Poddar]

Add get_buf, put_buf api support in spi master.
This can be used in a scenario where spi controller
supports memory mapped operations(typically with flash devices).
So, the memcpy needs top be done in slave devices which need the
required memory mapped address. These api can be used to get that
master address.

These can also be used to turm the master controller clock, as usually
the clocks get turned in spi core. But, in memory mapped case, we will
bypass the spi core and hence needa way out to turn on the controller clock.

Add configure from slave api, which can be used to configure the master
controller with slave specific information.

Add slave info struct, that can be filled with slave  properties required by
master controller for its register configuration.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
- Added a slave info structure.
- Merge all other header related patches into this.
 include/linux/spi/spi.h |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba7..c91d883 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -31,6 +31,14 @@
  */
 extern struct bus_type spi_bus_type;
 
+/* For SPI flash */
+struct slave_info {
+	u8 read_opcode;
+	u8 program_opcode;
+	u8 addr_width;
+	u8 dummy_cycles;
+};
+
 /**
  * struct spi_device - Master side proxy for an SPI slave device
  * @dev: Driver model representation of the device.
@@ -73,6 +81,7 @@ extern struct bus_type spi_bus_type;
 struct spi_device {
 	struct device		dev;
 	struct spi_master	*master;
+	struct slave_info	info;		/* flash devices */
 	u32			max_speed_hz;
 	u8			chip_select;
 	u16			mode;
@@ -291,6 +300,14 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *	number. Any individual value may be -ENOENT for CS lines that
  *	are not GPIOs (driven by the SPI controller itself).
  *
+ * @get_buf: used for memory mapped cases, when the slave device wants to
+ *       know the address to be used for memcopy.
+ * @put_buf: Used for memory mapped cases after get_buf, after the memcpy
+ *       has finished.
+ * @configure_from_slave: Used when SPI controller has registers which need
+ *      to be configured from slave specifics information(typical use case for
+ *      SPI flash device).
+ * @mmap: Used to show that controller supports memory mapped operation.
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -421,8 +438,13 @@ struct spi_master {
 	int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
 			    struct spi_transfer *transfer);
 
+	int	__iomem *(*get_buf)(struct spi_master *master);
+	void	(*put_buf)(struct spi_master *master);
+	void	(*configure_from_slave)(struct spi_device *spi);
+
 	/* gpio chip select */
 	int			*cs_gpios;
+	bool	mmap;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.1

[PATCHv2 01/10] spi/spi.h: Add get_buf/put_buf support in spi master.

[Sourav Poddar]

Add get_buf, put_buf api support in spi master.
This can be used in a scenario where spi controller
supports memory mapped operations(typically with flash devices).
So, the memcpy needs top be done in slave devices which need the
required memory mapped address. These api can be used to get that
master address.

These can also be used to turm the master controller clock, as usually
the clocks get turned in spi core. But, in memory mapped case, we will
bypass the spi core and hence needa way out to turn on the controller clock.

Add configure from slave api, which can be used to configure the master
controller with slave specific information.

Add slave info struct, that can be filled with slave  properties required by
master controller for its register configuration.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
- Added a slave info structure.
- Merge all other header related patches into this.
 include/linux/spi/spi.h |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba7..c91d883 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -31,6 +31,14 @@
  */
 extern struct bus_type spi_bus_type;
 
+/* For SPI flash */
+struct slave_info {
+	u8 read_opcode;
+	u8 program_opcode;
+	u8 addr_width;
+	u8 dummy_cycles;
+};
+
 /**
  * struct spi_device - Master side proxy for an SPI slave device
  * @dev: Driver model representation of the device.
@@ -73,6 +81,7 @@ extern struct bus_type spi_bus_type;
 struct spi_device {
 	struct device		dev;
 	struct spi_master	*master;
+	struct slave_info	info;		/* flash devices */
 	u32			max_speed_hz;
 	u8			chip_select;
 	u16			mode;
@@ -291,6 +300,14 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *	number. Any individual value may be -ENOENT for CS lines that
  *	are not GPIOs (driven by the SPI controller itself).
  *
+ * @get_buf: used for memory mapped cases, when the slave device wants to
+ *       know the address to be used for memcopy.
+ * @put_buf: Used for memory mapped cases after get_buf, after the memcpy
+ *       has finished.
+ * @configure_from_slave: Used when SPI controller has registers which need
+ *      to be configured from slave specifics information(typical use case for
+ *      SPI flash device).
+ * @mmap: Used to show that controller supports memory mapped operation.
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -421,8 +438,13 @@ struct spi_master {
 	int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
 			    struct spi_transfer *transfer);
 
+	int	__iomem *(*get_buf)(struct spi_master *master);
+	void	(*put_buf)(struct spi_master *master);
+	void	(*configure_from_slave)(struct spi_device *spi);
+
 	/* gpio chip select */
 	int			*cs_gpios;
+	bool	mmap;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.1

[PATCHv2 01/10] spi/spi.h: Add get_buf/put_buf support in spi master.

[Sourav Poddar]

Add get_buf, put_buf api support in spi master.
This can be used in a scenario where spi controller
supports memory mapped operations(typically with flash devices).
So, the memcpy needs top be done in slave devices which need the
required memory mapped address. These api can be used to get that
master address.

These can also be used to turm the master controller clock, as usually
the clocks get turned in spi core. But, in memory mapped case, we will
bypass the spi core and hence needa way out to turn on the controller clock.

Add configure from slave api, which can be used to configure the master
controller with slave specific information.

Add slave info struct, that can be filled with slave  properties required by
master controller for its register configuration.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
- Added a slave info structure.
- Merge all other header related patches into this.
 include/linux/spi/spi.h |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 8c62ba7..c91d883 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -31,6 +31,14 @@
  */
 extern struct bus_type spi_bus_type;
 
+/* For SPI flash */
+struct slave_info {
+	u8 read_opcode;
+	u8 program_opcode;
+	u8 addr_width;
+	u8 dummy_cycles;
+};
+
 /**
  * struct spi_device - Master side proxy for an SPI slave device
  * @dev: Driver model representation of the device.
@@ -73,6 +81,7 @@ extern struct bus_type spi_bus_type;
 struct spi_device {
 	struct device		dev;
 	struct spi_master	*master;
+	struct slave_info	info;		/* flash devices */
 	u32			max_speed_hz;
 	u8			chip_select;
 	u16			mode;
@@ -291,6 +300,14 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  *	number. Any individual value may be -ENOENT for CS lines that
  *	are not GPIOs (driven by the SPI controller itself).
  *
+ * @get_buf: used for memory mapped cases, when the slave device wants to
+ *       know the address to be used for memcopy.
+ * @put_buf: Used for memory mapped cases after get_buf, after the memcpy
+ *       has finished.
+ * @configure_from_slave: Used when SPI controller has registers which need
+ *      to be configured from slave specifics information(typical use case for
+ *      SPI flash device).
+ * @mmap: Used to show that controller supports memory mapped operation.
  * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
@@ -421,8 +438,13 @@ struct spi_master {
 	int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
 			    struct spi_transfer *transfer);
 
+	int	__iomem *(*get_buf)(struct spi_master *master);
+	void	(*put_buf)(struct spi_master *master);
+	void	(*configure_from_slave)(struct spi_device *spi);
+
 	/* gpio chip select */
 	int			*cs_gpios;
+	bool	mmap;
 };
 
 static inline void *spi_master_get_devdata(struct spi_master *master)
-- 
1.7.1

[PATCHv2 02/10] spi/qspi: parse register by name.

[Sourav Poddar]

Modify the qspi driver to parse reg information by name.
If "reg names" is not found, then revert back to normal
get resource.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
- if __byname variant is not found, go for standard 
  api. If both are not found, then the resource is considered
  to be optional and is not required for the given SOC.
 drivers/spi/spi-ti-qspi.c |   53 +++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 51 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 033ef8d..a0cee08 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -46,6 +46,8 @@ struct ti_qspi {
 
 	struct spi_master	*master;
 	void __iomem            *base;
+	void __iomem            *ctrl_base;
+	void __iomem            *mmap_base;
 	struct clk		*fclk;
 	struct device           *dev;
 
@@ -54,6 +56,8 @@ struct ti_qspi {
 	u32 spi_max_frequency;
 	u32 cmd;
 	u32 dc;
+
+	bool ctrl_mod;
 };
 
 #define QSPI_PID			(0x0)
@@ -437,7 +441,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 {
 	struct  ti_qspi *qspi;
 	struct spi_master *master;
-	struct resource         *r;
+	struct resource         *r, *res_ctrl, *res_mmap;
 	struct device_node *np = pdev->dev.of_node;
 	u32 max_freq;
 	int ret = 0, num_cs, irq;
@@ -465,7 +469,35 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	qspi->master = master;
 	qspi->dev = &pdev->dev;
 
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
+	if (r == NULL) {
+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (r == NULL) {
+			dev_err(&pdev->dev, "missing platform data\n");
+			return -ENODEV;
+		}
+	}
+
+	res_mmap = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_mmap");
+	if (res_mmap == NULL) {
+		res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (res_mmap == NULL) {
+			dev_err(&pdev->dev,
+				"memory mapped resource not required\n");
+			return -ENODEV;
+		}
+	}
+
+	res_ctrl = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_ctrlmod");
+	if (res_ctrl == NULL) {
+		res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+		if (res_ctrl == NULL) {
+			dev_dbg(&pdev->dev,
+				"control module resources not required\n");
+		}
+	}
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
@@ -481,6 +513,23 @@ static int ti_qspi_probe(struct platform_device *pdev)
 		goto free_master;
 	}
 
+	if (res_ctrl) {
+		qspi->ctrl_mod = true;
+		qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
+		if (IS_ERR(qspi->ctrl_base)) {
+			ret = PTR_ERR(qspi->ctrl_base);
+			goto free_master;
+		}
+	}
+
+	if (res_mmap) {
+		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
+		if (IS_ERR(qspi->mmap_base)) {
+			ret = PTR_ERR(qspi->mmap_base);
+			goto free_master;
+		}
+	}
+
 	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
 			dev_name(&pdev->dev), qspi);
 	if (ret < 0) {
-- 
1.7.1


______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCHv2 02/10] spi/qspi: parse register by name.

[Sourav Poddar]

Modify the qspi driver to parse reg information by name.
If "reg names" is not found, then revert back to normal
get resource.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
- if __byname variant is not found, go for standard 
  api. If both are not found, then the resource is considered
  to be optional and is not required for the given SOC.
 drivers/spi/spi-ti-qspi.c |   53 +++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 51 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 033ef8d..a0cee08 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -46,6 +46,8 @@ struct ti_qspi {
 
 	struct spi_master	*master;
 	void __iomem            *base;
+	void __iomem            *ctrl_base;
+	void __iomem            *mmap_base;
 	struct clk		*fclk;
 	struct device           *dev;
 
@@ -54,6 +56,8 @@ struct ti_qspi {
 	u32 spi_max_frequency;
 	u32 cmd;
 	u32 dc;
+
+	bool ctrl_mod;
 };
 
 #define QSPI_PID			(0x0)
@@ -437,7 +441,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 {
 	struct  ti_qspi *qspi;
 	struct spi_master *master;
-	struct resource         *r;
+	struct resource         *r, *res_ctrl, *res_mmap;
 	struct device_node *np = pdev->dev.of_node;
 	u32 max_freq;
 	int ret = 0, num_cs, irq;
@@ -465,7 +469,35 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	qspi->master = master;
 	qspi->dev = &pdev->dev;
 
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
+	if (r == NULL) {
+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (r == NULL) {
+			dev_err(&pdev->dev, "missing platform data\n");
+			return -ENODEV;
+		}
+	}
+
+	res_mmap = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_mmap");
+	if (res_mmap == NULL) {
+		res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (res_mmap == NULL) {
+			dev_err(&pdev->dev,
+				"memory mapped resource not required\n");
+			return -ENODEV;
+		}
+	}
+
+	res_ctrl = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_ctrlmod");
+	if (res_ctrl == NULL) {
+		res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+		if (res_ctrl == NULL) {
+			dev_dbg(&pdev->dev,
+				"control module resources not required\n");
+		}
+	}
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
@@ -481,6 +513,23 @@ static int ti_qspi_probe(struct platform_device *pdev)
 		goto free_master;
 	}
 
+	if (res_ctrl) {
+		qspi->ctrl_mod = true;
+		qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
+		if (IS_ERR(qspi->ctrl_base)) {
+			ret = PTR_ERR(qspi->ctrl_base);
+			goto free_master;
+		}
+	}
+
+	if (res_mmap) {
+		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
+		if (IS_ERR(qspi->mmap_base)) {
+			ret = PTR_ERR(qspi->mmap_base);
+			goto free_master;
+		}
+	}
+
 	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
 			dev_name(&pdev->dev), qspi);
 	if (ret < 0) {
-- 
1.7.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCHv2 02/10] spi/qspi: parse register by name.

[Sourav Poddar]

Modify the qspi driver to parse reg information by name.
If "reg names" is not found, then revert back to normal
get resource.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
- if __byname variant is not found, go for standard 
  api. If both are not found, then the resource is considered
  to be optional and is not required for the given SOC.
 drivers/spi/spi-ti-qspi.c |   53 +++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 51 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 033ef8d..a0cee08 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -46,6 +46,8 @@ struct ti_qspi {
 
 	struct spi_master	*master;
 	void __iomem            *base;
+	void __iomem            *ctrl_base;
+	void __iomem            *mmap_base;
 	struct clk		*fclk;
 	struct device           *dev;
 
@@ -54,6 +56,8 @@ struct ti_qspi {
 	u32 spi_max_frequency;
 	u32 cmd;
 	u32 dc;
+
+	bool ctrl_mod;
 };
 
 #define QSPI_PID			(0x0)
@@ -437,7 +441,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 {
 	struct  ti_qspi *qspi;
 	struct spi_master *master;
-	struct resource         *r;
+	struct resource         *r, *res_ctrl, *res_mmap;
 	struct device_node *np = pdev->dev.of_node;
 	u32 max_freq;
 	int ret = 0, num_cs, irq;
@@ -465,7 +469,35 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	qspi->master = master;
 	qspi->dev = &pdev->dev;
 
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
+	if (r == NULL) {
+		r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+		if (r == NULL) {
+			dev_err(&pdev->dev, "missing platform data\n");
+			return -ENODEV;
+		}
+	}
+
+	res_mmap = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_mmap");
+	if (res_mmap == NULL) {
+		res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		if (res_mmap == NULL) {
+			dev_err(&pdev->dev,
+				"memory mapped resource not required\n");
+			return -ENODEV;
+		}
+	}
+
+	res_ctrl = platform_get_resource_byname(pdev,
+			IORESOURCE_MEM, "qspi_ctrlmod");
+	if (res_ctrl == NULL) {
+		res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+		if (res_ctrl == NULL) {
+			dev_dbg(&pdev->dev,
+				"control module resources not required\n");
+		}
+	}
 
 	irq = platform_get_irq(pdev, 0);
 	if (irq < 0) {
@@ -481,6 +513,23 @@ static int ti_qspi_probe(struct platform_device *pdev)
 		goto free_master;
 	}
 
+	if (res_ctrl) {
+		qspi->ctrl_mod = true;
+		qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
+		if (IS_ERR(qspi->ctrl_base)) {
+			ret = PTR_ERR(qspi->ctrl_base);
+			goto free_master;
+		}
+	}
+
+	if (res_mmap) {
+		qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
+		if (IS_ERR(qspi->mmap_base)) {
+			ret = PTR_ERR(qspi->mmap_base);
+			goto free_master;
+		}
+	}
+
 	ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
 			dev_name(&pdev->dev), qspi);
 	if (ret < 0) {
-- 
1.7.1

[PATCHv2 03/10] spi/qspi: Add support to switc to memory mapped operation.

[Sourav Poddar]

These add apis that can be used to switch to memory mapped operatons
by configuring control module and qspi registers.
It also add "master->mmap" property to show that qspi
supports memory mapped operation.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 Squash a patch to add mater->mmap here itself.
 drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index a0cee08..48294d1 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -113,6 +113,10 @@ struct ti_qspi {
 #define QSPI_CSPOL(n)			(1 << (1 + n * 8))
 #define QSPI_CKPOL(n)			(1 << (n * 8))
 
+#define MM_SWITCH	(1 << 0)
+#define MEM_CS		(1 << 8)
+#define MEM_CS_DIS	(0 << 8)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
 	writel(val, qspi->base + reg);
 }
 
+static void enable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val |= MEM_CS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
+static void disable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val &= MEM_CS_DIS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
 static int ti_qspi_setup(struct spi_device *spi)
 {
 	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
@@ -459,6 +487,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->transfer_one_message = ti_qspi_start_transfer_one;
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+	master->mmap = true;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 03/10] spi/qspi: Add support to switc to memory mapped operation.

[Sourav Poddar]

These add apis that can be used to switch to memory mapped operatons
by configuring control module and qspi registers.
It also add "master->mmap" property to show that qspi
supports memory mapped operation.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 Squash a patch to add mater->mmap here itself.
 drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index a0cee08..48294d1 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -113,6 +113,10 @@ struct ti_qspi {
 #define QSPI_CSPOL(n)			(1 << (1 + n * 8))
 #define QSPI_CKPOL(n)			(1 << (n * 8))
 
+#define MM_SWITCH	(1 << 0)
+#define MEM_CS		(1 << 8)
+#define MEM_CS_DIS	(0 << 8)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
 	writel(val, qspi->base + reg);
 }
 
+static void enable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val |= MEM_CS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
+static void disable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val &= MEM_CS_DIS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
 static int ti_qspi_setup(struct spi_device *spi)
 {
 	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
@@ -459,6 +487,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->transfer_one_message = ti_qspi_start_transfer_one;
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+	master->mmap = true;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 03/10] spi/qspi: Add support to switc to memory mapped operation.

[Sourav Poddar]

These add apis that can be used to switch to memory mapped operatons
by configuring control module and qspi registers.
It also add "master->mmap" property to show that qspi
supports memory mapped operation.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 Squash a patch to add mater->mmap here itself.
 drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index a0cee08..48294d1 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -113,6 +113,10 @@ struct ti_qspi {
 #define QSPI_CSPOL(n)			(1 << (1 + n * 8))
 #define QSPI_CKPOL(n)			(1 << (n * 8))
 
+#define MM_SWITCH	(1 << 0)
+#define MEM_CS		(1 << 8)
+#define MEM_CS_DIS	(0 << 8)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
 	writel(val, qspi->base + reg);
 }
 
+static void enable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val |= MEM_CS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
+static void disable_qspi_memory_mapped(struct ti_qspi *qspi)
+{
+	u32 val;
+
+	ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
+	if (qspi->ctrl_mod) {
+		val = readl(qspi->ctrl_base);
+		val &= MEM_CS_DIS;
+		writel(val, qspi->ctrl_base);
+	}
+}
+
 static int ti_qspi_setup(struct spi_device *spi)
 {
 	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
@@ -459,6 +487,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->transfer_one_message = ti_qspi_start_transfer_one;
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
+	master->mmap = true;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Sourav Poddar]

These add api to configure set up registers which will be used
for memory mapped operations.

These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 48294d1..e4a8afc 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -117,6 +117,10 @@ struct ti_qspi {
 #define MEM_CS		(1 << 8)
 #define MEM_CS_DIS	(0 << 8)
 
+#define QSPI_SETUP0_RD_NORMAL   (0x0 << 12)
+#define QSPI_SETUP0_RD_DUAL     (0x1 << 12)
+#define QSPI_SETUP0_RD_QUAD     (0x3 << 12)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
 	return 0;
 }
 
+static void ti_qspi_configure_from_slave(struct spi_device *spi)
+{
+	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
+	struct slave_info info = spi->info;
+	u32 memval, mode;
+
+	mode = spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD);
+	memval =  (info.read_opcode << 0) | (info.program_opcode << 16) |
+		((info.addr_width - 1) << 8) | (info.dummy_cycles << 10);
+
+	switch (mode) {
+	case SPI_RX_DUAL:
+		memval |= QSPI_SETUP0_RD_DUAL;
+		break;
+	case SPI_RX_QUAD:
+		memval |= QSPI_SETUP0_RD_QUAD;
+		break;
+	default:
+		memval |= QSPI_SETUP0_RD_NORMAL;
+		break;
+	}
+	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->mmap = true;
+	master->configure_from_slave = ti_qspi_configure_from_slave;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Sourav Poddar]

These add api to configure set up registers which will be used
for memory mapped operations.

These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 48294d1..e4a8afc 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -117,6 +117,10 @@ struct ti_qspi {
 #define MEM_CS		(1 << 8)
 #define MEM_CS_DIS	(0 << 8)
 
+#define QSPI_SETUP0_RD_NORMAL   (0x0 << 12)
+#define QSPI_SETUP0_RD_DUAL     (0x1 << 12)
+#define QSPI_SETUP0_RD_QUAD     (0x3 << 12)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
 	return 0;
 }
 
+static void ti_qspi_configure_from_slave(struct spi_device *spi)
+{
+	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
+	struct slave_info info = spi->info;
+	u32 memval, mode;
+
+	mode = spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD);
+	memval =  (info.read_opcode << 0) | (info.program_opcode << 16) |
+		((info.addr_width - 1) << 8) | (info.dummy_cycles << 10);
+
+	switch (mode) {
+	case SPI_RX_DUAL:
+		memval |= QSPI_SETUP0_RD_DUAL;
+		break;
+	case SPI_RX_QUAD:
+		memval |= QSPI_SETUP0_RD_QUAD;
+		break;
+	default:
+		memval |= QSPI_SETUP0_RD_NORMAL;
+		break;
+	}
+	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->mmap = true;
+	master->configure_from_slave = ti_qspi_configure_from_slave;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Sourav Poddar]

These add api to configure set up registers which will be used
for memory mapped operations.

These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 48294d1..e4a8afc 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -117,6 +117,10 @@ struct ti_qspi {
 #define MEM_CS		(1 << 8)
 #define MEM_CS_DIS	(0 << 8)
 
+#define QSPI_SETUP0_RD_NORMAL   (0x0 << 12)
+#define QSPI_SETUP0_RD_DUAL     (0x1 << 12)
+#define QSPI_SETUP0_RD_QUAD     (0x3 << 12)
+
 #define	QSPI_FRAME			4096
 
 #define QSPI_AUTOSUSPEND_TIMEOUT         2000
@@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
 	return 0;
 }
 
+static void ti_qspi_configure_from_slave(struct spi_device *spi)
+{
+	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
+	struct slave_info info = spi->info;
+	u32 memval, mode;
+
+	mode = spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD);
+	memval =  (info.read_opcode << 0) | (info.program_opcode << 16) |
+		((info.addr_width - 1) << 8) | (info.dummy_cycles << 10);
+
+	switch (mode) {
+	case SPI_RX_DUAL:
+		memval |= QSPI_SETUP0_RD_DUAL;
+		break;
+	case SPI_RX_QUAD:
+		memval |= QSPI_SETUP0_RD_QUAD;
+		break;
+	default:
+		memval |= QSPI_SETUP0_RD_NORMAL;
+		break;
+	}
+	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->dev.of_node = pdev->dev.of_node;
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->mmap = true;
+	master->configure_from_slave = ti_qspi_configure_from_slave;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
v1->v2:
 enable/disable memory mapped only when get_buf/put_buf is
 called (basicaaly only when memory mapped read operation is
 desired).
 drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index e4a8afc..b83583c 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct spi_device *spi)
 	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
 }
 
+static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	pm_runtime_get_sync(qspi->dev);
+	enable_qspi_memory_mapped(qspi);
+	return qspi->mmap_base;
+}
+
+static void ti_qspi_put_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	disable_qspi_memory_mapped(qspi);
+	pm_runtime_put(qspi->dev);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->mmap = true;
 	master->configure_from_slave = ti_qspi_configure_from_slave;
+	master->get_buf = ti_qspi_get_mem_buf;
+	master->put_buf = ti_qspi_put_mem_buf;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

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[PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
v1->v2:
 enable/disable memory mapped only when get_buf/put_buf is
 called (basicaaly only when memory mapped read operation is
 desired).
 drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index e4a8afc..b83583c 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct spi_device *spi)
 	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
 }
 
+static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	pm_runtime_get_sync(qspi->dev);
+	enable_qspi_memory_mapped(qspi);
+	return qspi->mmap_base;
+}
+
+static void ti_qspi_put_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	disable_qspi_memory_mapped(qspi);
+	pm_runtime_put(qspi->dev);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->mmap = true;
 	master->configure_from_slave = ti_qspi_configure_from_slave;
+	master->get_buf = ti_qspi_get_mem_buf;
+	master->put_buf = ti_qspi_put_mem_buf;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

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[PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 enable/disable memory mapped only when get_buf/put_buf is
 called (basicaaly only when memory mapped read operation is
 desired).
 drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index e4a8afc..b83583c 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct spi_device *spi)
 	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
 }
 
+static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	pm_runtime_get_sync(qspi->dev);
+	enable_qspi_memory_mapped(qspi);
+	return qspi->mmap_base;
+}
+
+static void ti_qspi_put_mem_buf(struct spi_master *master)
+{
+	struct ti_qspi *qspi = spi_master_get_devdata(master);
+
+	disable_qspi_memory_mapped(qspi);
+	pm_runtime_put(qspi->dev);
+}
+
 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
 {
 	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
@@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
 	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
 	master->mmap = true;
 	master->configure_from_slave = ti_qspi_configure_from_slave;
+	master->get_buf = ti_qspi_get_mem_buf;
+	master->put_buf = ti_qspi_put_mem_buf;
 
 	if (!of_property_read_u32(np, "num-cs", &num_cs))
 		master->num_chipselect = num_cs;
-- 
1.7.1

[PATCHv2 06/10] drivers: mtd: m25p80: Add api to configure master register.

[Sourav Poddar]

These can be used to fill information needed to configure
master controller registers.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 instead of a u8 *val, use a struct (slave_info)  already defined 
 in the first patch of the series. This will allow us to add more
 parameters into the struct.

 drivers/mtd/devices/m25p80.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 7dc2c14..b90c7e5 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -490,6 +490,24 @@ static inline int m25p80_dummy_cycles_read(struct m25p *flash)
 }
 
 /*
+ * This API can be used to transfer flash information to
+ * SPI controller which needs some of its registers to get
+ * configured on flash information.
+ */
+static void m25p80_fill_flash_information(struct m25p *flash)
+{
+	struct spi_device *spi = flash->spi;
+	struct spi_master *master = spi->master;
+
+	spi->info.read_opcode = flash->read_opcode;
+	spi->info.program_opcode = flash->program_opcode;
+	spi->info.addr_width = flash->addr_width;
+	spi->info.dummy_cycles = m25p80_dummy_cycles_read(flash);
+
+	master->configure_from_slave(flash->spi);
+}
+
+/*
  * Read an address range from the flash chip.  The address range
  * may be any size provided it is within the physical boundaries.
  */
-- 
1.7.1

[PATCHv2 06/10] drivers: mtd: m25p80: Add api to configure master register.

[Sourav Poddar]

These can be used to fill information needed to configure
master controller registers.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 instead of a u8 *val, use a struct (slave_info)  already defined 
 in the first patch of the series. This will allow us to add more
 parameters into the struct.

 drivers/mtd/devices/m25p80.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 7dc2c14..b90c7e5 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -490,6 +490,24 @@ static inline int m25p80_dummy_cycles_read(struct m25p *flash)
 }
 
 /*
+ * This API can be used to transfer flash information to
+ * SPI controller which needs some of its registers to get
+ * configured on flash information.
+ */
+static void m25p80_fill_flash_information(struct m25p *flash)
+{
+	struct spi_device *spi = flash->spi;
+	struct spi_master *master = spi->master;
+
+	spi->info.read_opcode = flash->read_opcode;
+	spi->info.program_opcode = flash->program_opcode;
+	spi->info.addr_width = flash->addr_width;
+	spi->info.dummy_cycles = m25p80_dummy_cycles_read(flash);
+
+	master->configure_from_slave(flash->spi);
+}
+
+/*
  * Read an address range from the flash chip.  The address range
  * may be any size provided it is within the physical boundaries.
  */
-- 
1.7.1

[PATCHv2 06/10] drivers: mtd: m25p80: Add api to configure master register.

[Sourav Poddar]

These can be used to fill information needed to configure
master controller registers.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 instead of a u8 *val, use a struct (slave_info)  already defined 
 in the first patch of the series. This will allow us to add more
 parameters into the struct.

 drivers/mtd/devices/m25p80.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 7dc2c14..b90c7e5 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -490,6 +490,24 @@ static inline int m25p80_dummy_cycles_read(struct m25p *flash)
 }
 
 /*
+ * This API can be used to transfer flash information to
+ * SPI controller which needs some of its registers to get
+ * configured on flash information.
+ */
+static void m25p80_fill_flash_information(struct m25p *flash)
+{
+	struct spi_device *spi = flash->spi;
+	struct spi_master *master = spi->master;
+
+	spi->info.read_opcode = flash->read_opcode;
+	spi->info.program_opcode = flash->program_opcode;
+	spi->info.addr_width = flash->addr_width;
+	spi->info.dummy_cycles = m25p80_dummy_cycles_read(flash);
+
+	master->configure_from_slave(flash->spi);
+}
+
+/*
  * Read an address range from the flash chip.  The address range
  * may be any size provided it is within the physical boundaries.
  */
-- 
1.7.1

[PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

Adapt driver to do a memory mapped read.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
v1->v2:
 - Add a check to Wait for the previous erase/write to
   finish.
 - Ensure proper locking
 drivers/mtd/devices/m25p80.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index b90c7e5..eb75d84 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -109,6 +109,7 @@ struct m25p {
 	u8			program_opcode;
 	u8			*command;
 	enum read_type		flash_read;
+	void __iomem *mem_addr;
 };
 
 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	size_t *retlen, u_char *buf)
 {
 	struct m25p *flash = mtd_to_m25p(mtd);
+	struct spi_master *master = flash->spi->master;
 	struct spi_transfer t[2];
 	struct spi_message m;
 	uint8_t opcode;
@@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
 			__func__, (u32)from, len);
 
+	if (master->mmap) {
+		mutex_lock(&flash->lock);
+		/* Wait till previous write/erase is done. */
+		if (wait_till_ready(flash)) {
+			mutex_unlock(&flash->lock);
+			return 1;
+		}
+		flash->mem_addr = master->get_buf(master);
+		memcpy(buf, flash->mem_addr + from, len);
+		master->put_buf(master);
+		*retlen = len;
+		goto out;
+	}
+
 	spi_message_init(&m);
 	memset(t, 0, (sizeof t));
 
@@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 
 	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
 
+out:
 	mutex_unlock(&flash->lock);
 
 	return 0;
@@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
 		flash->addr_width = 3;
 	}
 
+	if (spi->master->configure_from_slave)
+		m25p80_fill_flash_information(flash);
+
 	dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
 			(long long)flash->mtd.size >> 10);
 
-- 
1.7.1

--
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[PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

Adapt driver to do a memory mapped read.

Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
---
v1->v2:
 - Add a check to Wait for the previous erase/write to
   finish.
 - Ensure proper locking
 drivers/mtd/devices/m25p80.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index b90c7e5..eb75d84 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -109,6 +109,7 @@ struct m25p {
 	u8			program_opcode;
 	u8			*command;
 	enum read_type		flash_read;
+	void __iomem *mem_addr;
 };
 
 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	size_t *retlen, u_char *buf)
 {
 	struct m25p *flash = mtd_to_m25p(mtd);
+	struct spi_master *master = flash->spi->master;
 	struct spi_transfer t[2];
 	struct spi_message m;
 	uint8_t opcode;
@@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
 			__func__, (u32)from, len);
 
+	if (master->mmap) {
+		mutex_lock(&flash->lock);
+		/* Wait till previous write/erase is done. */
+		if (wait_till_ready(flash)) {
+			mutex_unlock(&flash->lock);
+			return 1;
+		}
+		flash->mem_addr = master->get_buf(master);
+		memcpy(buf, flash->mem_addr + from, len);
+		master->put_buf(master);
+		*retlen = len;
+		goto out;
+	}
+
 	spi_message_init(&m);
 	memset(t, 0, (sizeof t));
 
@@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 
 	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
 
+out:
 	mutex_unlock(&flash->lock);
 
 	return 0;
@@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
 		flash->addr_width = 3;
 	}
 
+	if (spi->master->configure_from_slave)
+		m25p80_fill_flash_information(flash);
+
 	dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
 			(long long)flash->mtd.size >> 10);
 
-- 
1.7.1

--
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[PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

Adapt driver to do a memory mapped read.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 - Add a check to Wait for the previous erase/write to
   finish.
 - Ensure proper locking
 drivers/mtd/devices/m25p80.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index b90c7e5..eb75d84 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -109,6 +109,7 @@ struct m25p {
 	u8			program_opcode;
 	u8			*command;
 	enum read_type		flash_read;
+	void __iomem *mem_addr;
 };
 
 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	size_t *retlen, u_char *buf)
 {
 	struct m25p *flash = mtd_to_m25p(mtd);
+	struct spi_master *master = flash->spi->master;
 	struct spi_transfer t[2];
 	struct spi_message m;
 	uint8_t opcode;
@@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
 			__func__, (u32)from, len);
 
+	if (master->mmap) {
+		mutex_lock(&flash->lock);
+		/* Wait till previous write/erase is done. */
+		if (wait_till_ready(flash)) {
+			mutex_unlock(&flash->lock);
+			return 1;
+		}
+		flash->mem_addr = master->get_buf(master);
+		memcpy(buf, flash->mem_addr + from, len);
+		master->put_buf(master);
+		*retlen = len;
+		goto out;
+	}
+
 	spi_message_init(&m);
 	memset(t, 0, (sizeof t));
 
@@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 
 	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
 
+out:
 	mutex_unlock(&flash->lock);
 
 	return 0;
@@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
 		flash->addr_width = 3;
 	}
 
+	if (spi->master->configure_from_slave)
+		m25p80_fill_flash_information(flash);
+
 	dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
 			(long long)flash->mtd.size >> 10);
 
-- 
1.7.1

[PATCHv2 08/10] Documentation: bindings: ti-qspi: update binding information.

[Sourav Poddar]

These update binding information for ti qspi controller.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 Add 'reg-names' variables used in dts files.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 1f9641a..601a360 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -3,6 +3,11 @@ TI QSPI controller.
 Required properties:
 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
 - reg: Should contain QSPI registers location and length.
+- reg-names: Should contain the resource reg names.
+	- qspi_base: Qspi configuration register Address space
+	- qspi_mmap: Memory mapped Address space
+	- (optional) qspi_ctrlmod: Control module Address space
+- interrupts: should contain the qspi interrupt number.
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 - ti,hwmods: Name of the hwmod associated to the QSPI
 
@@ -14,7 +19,8 @@ Example:
 
 qspi: qspi@4b300000 {
 	compatible = "ti,dra7xxx-qspi";
-	reg = <0x4b300000 0x100>;
+	reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+	reg-names = "qspi_base", "qspi_mmap";
 	#address-cells = <1>;
 	#size-cells = <0>;
 	spi-max-frequency = <25000000>;
-- 
1.7.1

[PATCHv2 08/10] Documentation: bindings: ti-qspi: update binding information.

[Sourav Poddar]

These update binding information for ti qspi controller.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 Add 'reg-names' variables used in dts files.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 1f9641a..601a360 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -3,6 +3,11 @@ TI QSPI controller.
 Required properties:
 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
 - reg: Should contain QSPI registers location and length.
+- reg-names: Should contain the resource reg names.
+	- qspi_base: Qspi configuration register Address space
+	- qspi_mmap: Memory mapped Address space
+	- (optional) qspi_ctrlmod: Control module Address space
+- interrupts: should contain the qspi interrupt number.
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 - ti,hwmods: Name of the hwmod associated to the QSPI
 
@@ -14,7 +19,8 @@ Example:
 
 qspi: qspi@4b300000 {
 	compatible = "ti,dra7xxx-qspi";
-	reg = <0x4b300000 0x100>;
+	reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+	reg-names = "qspi_base", "qspi_mmap";
 	#address-cells = <1>;
 	#size-cells = <0>;
 	spi-max-frequency = <25000000>;
-- 
1.7.1

[PATCHv2 08/10] Documentation: bindings: ti-qspi: update binding information.

[Sourav Poddar]

These update binding information for ti qspi controller.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
 Add 'reg-names' variables used in dts files.

 Documentation/devicetree/bindings/spi/ti_qspi.txt |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
index 1f9641a..601a360 100644
--- a/Documentation/devicetree/bindings/spi/ti_qspi.txt
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -3,6 +3,11 @@ TI QSPI controller.
 Required properties:
 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
 - reg: Should contain QSPI registers location and length.
+- reg-names: Should contain the resource reg names.
+	- qspi_base: Qspi configuration register Address space
+	- qspi_mmap: Memory mapped Address space
+	- (optional) qspi_ctrlmod: Control module Address space
+- interrupts: should contain the qspi interrupt number.
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 - ti,hwmods: Name of the hwmod associated to the QSPI
 
@@ -14,7 +19,8 @@ Example:
 
 qspi: qspi@4b300000 {
 	compatible = "ti,dra7xxx-qspi";
-	reg = <0x4b300000 0x100>;
+	reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+	reg-names = "qspi_base", "qspi_mmap";
 	#address-cells = <1>;
 	#size-cells = <0>;
 	spi-max-frequency = <25000000>;
-- 
1.7.1

[PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on dra7.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
use "MUX_MODE1" instead of numeric value
 arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	qspi1_pins: pinmux_qspi1_pins {
+		pinctrl-single,pins = <
+			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
+			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
+			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
+			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
+			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
+			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
+			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
+			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
+			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -273,3 +288,20 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_pins>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "s25fl256s1";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		qspi: qspi@4b300000 {
+			compatible = "ti,dra7xxx-qspi";
+			reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
+					<0x5c000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			num-cs = <4>;
+			interrupts = <0 124 0x4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
-- 
1.7.1

[PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on dra7.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
use "MUX_MODE1" instead of numeric value
 arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	qspi1_pins: pinmux_qspi1_pins {
+		pinctrl-single,pins = <
+			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
+			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
+			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
+			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
+			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
+			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
+			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
+			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
+			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -273,3 +288,20 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_pins>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "s25fl256s1";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		qspi: qspi@4b300000 {
+			compatible = "ti,dra7xxx-qspi";
+			reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
+					<0x5c000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			num-cs = <4>;
+			interrupts = <0 124 0x4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
-- 
1.7.1

[PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on dra7.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
v1->v2:
use "MUX_MODE1" instead of numeric value
 arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0..4a57fdf 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -93,6 +93,21 @@
 			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 		>;
 	};
+
+	qspi1_pins: pinmux_qspi1_pins {
+		pinctrl-single,pins = <
+			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
+			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
+			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
+			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
+			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
+			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
+			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
+			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
+			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
+		>;
+	};
 };
 
 &i2c1 {
@@ -273,3 +288,20 @@
 &cpu0 {
 	cpu0-supply = <&smps123_reg>;
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_pins>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "s25fl256s1";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 67275c8..b06d899 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -582,6 +582,19 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		qspi: qspi@4b300000 {
+			compatible = "ti,dra7xxx-qspi";
+			reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
+					<0x5c000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			num-cs = <4>;
+			interrupts = <0 124 0x4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
-- 
1.7.1

[PATCHv2 10/10] arm: dts: am43x-epos: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on am43x-epos-evm.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi        |   12 ++++++++++++
 arch/arm/boot/dts/am43x-epos-evm.dts |   28 ++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index f1dd131..5d029de 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -663,6 +663,18 @@
 			       <&edma 11>;
 			dma-names = "tx", "rx";
 		};
+
+		qspi: qspi@47900000 {
+			compatible = "ti,am4372-qspi";
+			reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			interrupts = <0 138 0x4>;
+			num-cs = <4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..a037a92 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,17 @@
 				0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
+
+		qspi1_default: qspi1_default {
+			pinctrl-single,pins = <
+				0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+				0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+			>;
+		};
 	};
 
 	matrix_keypad: matrix_keypad@0 {
@@ -184,3 +195,20 @@
 &gpio3 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_default>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+	};
+};
-- 
1.7.1

[PATCHv2 10/10] arm: dts: am43x-epos: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on am43x-epos-evm.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi        |   12 ++++++++++++
 arch/arm/boot/dts/am43x-epos-evm.dts |   28 ++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index f1dd131..5d029de 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -663,6 +663,18 @@
 			       <&edma 11>;
 			dma-names = "tx", "rx";
 		};
+
+		qspi: qspi@47900000 {
+			compatible = "ti,am4372-qspi";
+			reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			interrupts = <0 138 0x4>;
+			num-cs = <4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..a037a92 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,17 @@
 				0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
+
+		qspi1_default: qspi1_default {
+			pinctrl-single,pins = <
+				0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+				0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+			>;
+		};
 	};
 
 	matrix_keypad: matrix_keypad@0 {
@@ -184,3 +195,20 @@
 &gpio3 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_default>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+	};
+};
-- 
1.7.1

[PATCHv2 10/10] arm: dts: am43x-epos: Add qspi device.

[Sourav Poddar]

These add device tree entry for qspi controller driver on am43x-epos-evm.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
---
 arch/arm/boot/dts/am4372.dtsi        |   12 ++++++++++++
 arch/arm/boot/dts/am43x-epos-evm.dts |   28 ++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index f1dd131..5d029de 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -663,6 +663,18 @@
 			       <&edma 11>;
 			dma-names = "tx", "rx";
 		};
+
+		qspi: qspi@47900000 {
+			compatible = "ti,am4372-qspi";
+			reg = <0x47900000 0x100>, <0x30000000 0x3ffffff>;
+			reg-names = "qspi_base", "qspi_mmap";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ti,hwmods = "qspi";
+			interrupts = <0 138 0x4>;
+			num-cs = <4>;
+			status = "disabled";
+		};
 	};
 
 	clocks {
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index fbf9c4c..a037a92 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -79,6 +79,17 @@
 				0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
 			>;
 		};
+
+		qspi1_default: qspi1_default {
+			pinctrl-single,pins = <
+				0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+				0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+				0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+			>;
+		};
 	};
 
 	matrix_keypad: matrix_keypad@0 {
@@ -184,3 +195,20 @@
 &gpio3 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_default>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+	};
+};
-- 
1.7.1

Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Tony Lindgren]

* Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org> [131206 06:29]:
> These add device tree entry for qspi controller driver on dra7.

FYI these .dts changes need to be queued separately by Benoit and
should be posted as a seprate series in general to avoid confusion.

Regards,

Tony
 
> Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
> ---
> v1->v2:
> use "MUX_MODE1" instead of numeric value
>  arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
>  2 files changed, 45 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 5babba0..4a57fdf 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -93,6 +93,21 @@
>  			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>  		>;
>  	};
> +
> +	qspi1_pins: pinmux_qspi1_pins {
> +		pinctrl-single,pins = <
> +			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
> +			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
> +			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
> +			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
> +			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
> +			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
> +			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
> +			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
> +			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
> +			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
> +		>;
> +	};
>  };
>  
>  &i2c1 {
> @@ -273,3 +288,20 @@
>  &cpu0 {
>  	cpu0-supply = <&smps123_reg>;
>  };
> +
> +&qspi {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&qspi1_pins>;
> +
> +	spi-max-frequency = <48000000>;
> +	m25p80@0 {
> +		compatible = "s25fl256s1";
> +		spi-max-frequency = <48000000>;
> +		reg = <0>;
> +		spi-tx-bus-width = <1>;
> +		spi-rx-bus-width = <4>;
> +		spi-cpol;
> +		spi-cpha;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 67275c8..b06d899 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -582,6 +582,19 @@
>  			dma-names = "tx0", "rx0";
>  			status = "disabled";
>  		};
> +
> +		qspi: qspi@4b300000 {
> +			compatible = "ti,dra7xxx-qspi";
> +			reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
> +					<0x5c000000 0x3ffffff>;
> +			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			ti,hwmods = "qspi";
> +			num-cs = <4>;
> +			interrupts = <0 124 0x4>;
> +			status = "disabled";
> +		};
>  	};
>  
>  	clocks {
> -- 
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Tony Lindgren]

* Sourav Poddar <sourav.poddar@ti.com> [131206 06:29]:
> These add device tree entry for qspi controller driver on dra7.

FYI these .dts changes need to be queued separately by Benoit and
should be posted as a seprate series in general to avoid confusion.

Regards,

Tony
 
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> v1->v2:
> use "MUX_MODE1" instead of numeric value
>  arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
>  2 files changed, 45 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index 5babba0..4a57fdf 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -93,6 +93,21 @@
>  			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>  		>;
>  	};
> +
> +	qspi1_pins: pinmux_qspi1_pins {
> +		pinctrl-single,pins = <
> +			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
> +			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
> +			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
> +			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
> +			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
> +			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
> +			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
> +			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
> +			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
> +			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
> +		>;
> +	};
>  };
>  
>  &i2c1 {
> @@ -273,3 +288,20 @@
>  &cpu0 {
>  	cpu0-supply = <&smps123_reg>;
>  };
> +
> +&qspi {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&qspi1_pins>;
> +
> +	spi-max-frequency = <48000000>;
> +	m25p80@0 {
> +		compatible = "s25fl256s1";
> +		spi-max-frequency = <48000000>;
> +		reg = <0>;
> +		spi-tx-bus-width = <1>;
> +		spi-rx-bus-width = <4>;
> +		spi-cpol;
> +		spi-cpha;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 67275c8..b06d899 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -582,6 +582,19 @@
>  			dma-names = "tx0", "rx0";
>  			status = "disabled";
>  		};
> +
> +		qspi: qspi@4b300000 {
> +			compatible = "ti,dra7xxx-qspi";
> +			reg = <0x4b300000 0x100>, <0x4a002558 0x4>,
> +					<0x5c000000 0x3ffffff>;
> +			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			ti,hwmods = "qspi";
> +			num-cs = <4>;
> +			interrupts = <0 124 0x4>;
> +			status = "disabled";
> +		};
>  	};
>  
>  	clocks {
> -- 
> 1.7.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

On Monday 09 December 2013 11:12 PM, Tony Lindgren wrote:
> * Sourav Poddar<sourav.poddar-l0cyMroinI0@public.gmane.org>  [131206 06:29]:
>> These add device tree entry for qspi controller driver on dra7.
> FYI these .dts changes need to be queued separately by Benoit and
> should be posted as a seprate series in general to avoid confusion.
>
Ok, thanks!
I posted this for review along with other code changes.

I will post them seperately to Benoit.
> Regards,
>
> Tony
>
>> Signed-off-by: Sourav Poddar<sourav.poddar-l0cyMroinI0@public.gmane.org>
>> ---
>> v1->v2:
>> use "MUX_MODE1" instead of numeric value
>>   arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
>>   arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
>>   2 files changed, 45 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> index 5babba0..4a57fdf 100644
>> --- a/arch/arm/boot/dts/dra7-evm.dts
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -93,6 +93,21 @@
>>   			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>>   		>;
>>   	};
>> +
>> +	qspi1_pins: pinmux_qspi1_pins {
>> +		pinctrl-single,pins =<
>> +			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
>> +			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
>> +			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
>> +			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
>> +			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
>> +			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
>> +			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
>> +			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
>> +			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
>> +			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
>> +		>;
>> +	};
>>   };
>>
>>   &i2c1 {
>> @@ -273,3 +288,20 @@
>>   &cpu0 {
>>   	cpu0-supply =<&smps123_reg>;
>>   };
>> +
>> +&qspi {
>> +	status = "okay";
>> +	pinctrl-names = "default";
>> +	pinctrl-0 =<&qspi1_pins>;
>> +
>> +	spi-max-frequency =<48000000>;
>> +	m25p80@0 {
>> +		compatible = "s25fl256s1";
>> +		spi-max-frequency =<48000000>;
>> +		reg =<0>;
>> +		spi-tx-bus-width =<1>;
>> +		spi-rx-bus-width =<4>;
>> +		spi-cpol;
>> +		spi-cpha;
>> +	};
>> +};
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 67275c8..b06d899 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -582,6 +582,19 @@
>>   			dma-names = "tx0", "rx0";
>>   			status = "disabled";
>>   		};
>> +
>> +		qspi: qspi@4b300000 {
>> +			compatible = "ti,dra7xxx-qspi";
>> +			reg =<0x4b300000 0x100>,<0x4a002558 0x4>,
>> +					<0x5c000000 0x3ffffff>;
>> +			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
>> +			#address-cells =<1>;
>> +			#size-cells =<0>;
>> +			ti,hwmods = "qspi";
>> +			num-cs =<4>;
>> +			interrupts =<0 124 0x4>;
>> +			status = "disabled";
>> +		};
>>   	};
>>
>>   	clocks {
>> -- 
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

On Monday 09 December 2013 11:12 PM, Tony Lindgren wrote:
> * Sourav Poddar<sourav.poddar-l0cyMroinI0@public.gmane.org>  [131206 06:29]:
>> These add device tree entry for qspi controller driver on dra7.
> FYI these .dts changes need to be queued separately by Benoit and
> should be posted as a seprate series in general to avoid confusion.
>
Ok, thanks!
I posted this for review along with other code changes.

I will post them seperately to Benoit.
> Regards,
>
> Tony
>
>> Signed-off-by: Sourav Poddar<sourav.poddar-l0cyMroinI0@public.gmane.org>
>> ---
>> v1->v2:
>> use "MUX_MODE1" instead of numeric value
>>   arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
>>   arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
>>   2 files changed, 45 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> index 5babba0..4a57fdf 100644
>> --- a/arch/arm/boot/dts/dra7-evm.dts
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -93,6 +93,21 @@
>>   			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>>   		>;
>>   	};
>> +
>> +	qspi1_pins: pinmux_qspi1_pins {
>> +		pinctrl-single,pins =<
>> +			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
>> +			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
>> +			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
>> +			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
>> +			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
>> +			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
>> +			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
>> +			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
>> +			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
>> +			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
>> +		>;
>> +	};
>>   };
>>
>>   &i2c1 {
>> @@ -273,3 +288,20 @@
>>   &cpu0 {
>>   	cpu0-supply =<&smps123_reg>;
>>   };
>> +
>> +&qspi {
>> +	status = "okay";
>> +	pinctrl-names = "default";
>> +	pinctrl-0 =<&qspi1_pins>;
>> +
>> +	spi-max-frequency =<48000000>;
>> +	m25p80@0 {
>> +		compatible = "s25fl256s1";
>> +		spi-max-frequency =<48000000>;
>> +		reg =<0>;
>> +		spi-tx-bus-width =<1>;
>> +		spi-rx-bus-width =<4>;
>> +		spi-cpol;
>> +		spi-cpha;
>> +	};
>> +};
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 67275c8..b06d899 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -582,6 +582,19 @@
>>   			dma-names = "tx0", "rx0";
>>   			status = "disabled";
>>   		};
>> +
>> +		qspi: qspi@4b300000 {
>> +			compatible = "ti,dra7xxx-qspi";
>> +			reg =<0x4b300000 0x100>,<0x4a002558 0x4>,
>> +					<0x5c000000 0x3ffffff>;
>> +			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
>> +			#address-cells =<1>;
>> +			#size-cells =<0>;
>> +			ti,hwmods = "qspi";
>> +			num-cs =<4>;
>> +			interrupts =<0 124 0x4>;
>> +			status = "disabled";
>> +		};
>>   	};
>>
>>   	clocks {
>> -- 
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

On Monday 09 December 2013 11:12 PM, Tony Lindgren wrote:
> * Sourav Poddar<sourav.poddar@ti.com>  [131206 06:29]:
>> These add device tree entry for qspi controller driver on dra7.
> FYI these .dts changes need to be queued separately by Benoit and
> should be posted as a seprate series in general to avoid confusion.
>
Ok, thanks!
I posted this for review along with other code changes.

I will post them seperately to Benoit.
> Regards,
>
> Tony
>
>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>> ---
>> v1->v2:
>> use "MUX_MODE1" instead of numeric value
>>   arch/arm/boot/dts/dra7-evm.dts |   32 ++++++++++++++++++++++++++++++++
>>   arch/arm/boot/dts/dra7.dtsi    |   13 +++++++++++++
>>   2 files changed, 45 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> index 5babba0..4a57fdf 100644
>> --- a/arch/arm/boot/dts/dra7-evm.dts
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -93,6 +93,21 @@
>>   			0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
>>   		>;
>>   	};
>> +
>> +	qspi1_pins: pinmux_qspi1_pins {
>> +		pinctrl-single,pins =<
>> +			0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
>> +			0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
>> +			0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
>> +			0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
>> +			0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
>> +			0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
>> +			0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
>> +			0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
>> +			0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
>> +			0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
>> +		>;
>> +	};
>>   };
>>
>>   &i2c1 {
>> @@ -273,3 +288,20 @@
>>   &cpu0 {
>>   	cpu0-supply =<&smps123_reg>;
>>   };
>> +
>> +&qspi {
>> +	status = "okay";
>> +	pinctrl-names = "default";
>> +	pinctrl-0 =<&qspi1_pins>;
>> +
>> +	spi-max-frequency =<48000000>;
>> +	m25p80@0 {
>> +		compatible = "s25fl256s1";
>> +		spi-max-frequency =<48000000>;
>> +		reg =<0>;
>> +		spi-tx-bus-width =<1>;
>> +		spi-rx-bus-width =<4>;
>> +		spi-cpol;
>> +		spi-cpha;
>> +	};
>> +};
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index 67275c8..b06d899 100644
>> --- a/arch/arm/boot/dts/dra7.dtsi
>> +++ b/arch/arm/boot/dts/dra7.dtsi
>> @@ -582,6 +582,19 @@
>>   			dma-names = "tx0", "rx0";
>>   			status = "disabled";
>>   		};
>> +
>> +		qspi: qspi@4b300000 {
>> +			compatible = "ti,dra7xxx-qspi";
>> +			reg =<0x4b300000 0x100>,<0x4a002558 0x4>,
>> +					<0x5c000000 0x3ffffff>;
>> +			reg-names = "qspi_base", "qspi_ctrlmod", "qspi_mmap";
>> +			#address-cells =<1>;
>> +			#size-cells =<0>;
>> +			ti,hwmods = "qspi";
>> +			num-cs =<4>;
>> +			interrupts =<0 124 0x4>;
>> +			status = "disabled";
>> +		};
>>   	};
>>
>>   	clocks {
>> -- 
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 222 bytes --]

On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:

> I posted this for review along with other code changes.

> I will post them seperately to Benoit.

Please wait until the driver updates have been reviewed.

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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 222 bytes --]

On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:

> I posted this for review along with other code changes.

> I will post them seperately to Benoit.

Please wait until the driver updates have been reviewed.

[-- Attachment #2: Digital signature --]
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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:
>
>> I posted this for review along with other code changes.
>> I will post them seperately to Benoit.
> Please wait until the driver updates have been reviewed.
Ok.

Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:
>
>> I posted this for review along with other code changes.
>> I will post them seperately to Benoit.
> Please wait until the driver updates have been reviewed.
Ok.

Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:
>
>> I posted this for review along with other code changes.
>> I will post them seperately to Benoit.
> Please wait until the driver updates have been reviewed.
Ok.

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
> The patch series aims to add memory mapped support for TI qspi
> contoller and also add support for the same in serial flash driver(m25p80).

My question is, shall we not wait for the new SPI NOR framework to be well 
fleshed out and only then implement this controller driver on top of it ?

I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80 
driver, which would become dead code once converted to the SPI NOR framework.

Best regards,
Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
> The patch series aims to add memory mapped support for TI qspi
> contoller and also add support for the same in serial flash driver(m25p80).

My question is, shall we not wait for the new SPI NOR framework to be well 
fleshed out and only then implement this controller driver on top of it ?

I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80 
driver, which would become dead code once converted to the SPI NOR framework.

Best regards,
Marek Vasut

Re: [PATCHv2 03/10] spi/qspi: Add support to switc to memory mapped operation.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:44 PM, Sourav Poddar wrote:
> These add apis that can be used to switch to memory mapped operatons
> by configuring control module and qspi registers.
> It also add "master->mmap" property to show that qspi
> supports memory mapped operation.

Please fix the 'switc' in the subject, should be 'switch' :)

> Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
> ---
> v1->v2:
>  Squash a patch to add mater->mmap here itself.
>  drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>  1 files changed, 29 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index a0cee08..48294d1 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -113,6 +113,10 @@ struct ti_qspi {
>  #define QSPI_CSPOL(n)			(1 << (1 + n * 8))
>  #define QSPI_CKPOL(n)			(1 << (n * 8))
> 
> +#define MM_SWITCH	(1 << 0)
> +#define MEM_CS		(1 << 8)
> +#define MEM_CS_DIS	(0 << 8)

You might want to be consistent here, I'd use MEM_CS_EN and MEM_CS_DIS. But 
please see below first as MEM_CS_DIS won't be needed, so MEM_CS can be preserved 
as is and MEM_CS_DIS removed altogether.

> +
>  #define	QSPI_FRAME			4096
> 
>  #define QSPI_AUTOSUSPEND_TIMEOUT         2000
> @@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
>  	writel(val, qspi->base + reg);
>  }
> 
> +static void enable_qspi_memory_mapped(struct ti_qspi *qspi)
> +{
> +	u32 val;
> +
> +	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
> +	if (qspi->ctrl_mod) {
> +		val = readl(qspi->ctrl_base);
> +		val |= MEM_CS;
> +		writel(val, qspi->ctrl_base);
> +	}
> +}
> +
> +static void disable_qspi_memory_mapped(struct ti_qspi *qspi)
> +{
> +	u32 val;
> +
> +	ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
> +	if (qspi->ctrl_mod) {
> +		val = readl(qspi->ctrl_base);
> +		val &= MEM_CS_DIS;

This will likely break once SWITCH_REG contains more than one bit, you can fix 
this by using "val &= ~MEM_CS;" instead, which will also get rid of the 
MEM_CS_DIS bit.

> +		writel(val, qspi->ctrl_base);
> +	}
> +}
> +
>  static int ti_qspi_setup(struct spi_device *spi)
>  {
>  	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
> @@ -459,6 +487,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  	master->transfer_one_message = ti_qspi_start_transfer_one;
>  	master->dev.of_node = pdev->dev.of_node;
>  	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
> +	master->mmap = true;
> 
>  	if (!of_property_read_u32(np, "num-cs", &num_cs))
>  		master->num_chipselect = num_cs;

Best regards,
Marek Vasut
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Re: [PATCHv2 03/10] spi/qspi: Add support to switc to memory mapped operation.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:44 PM, Sourav Poddar wrote:
> These add apis that can be used to switch to memory mapped operatons
> by configuring control module and qspi registers.
> It also add "master->mmap" property to show that qspi
> supports memory mapped operation.

Please fix the 'switc' in the subject, should be 'switch' :)

> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> v1->v2:
>  Squash a patch to add mater->mmap here itself.
>  drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>  1 files changed, 29 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index a0cee08..48294d1 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -113,6 +113,10 @@ struct ti_qspi {
>  #define QSPI_CSPOL(n)			(1 << (1 + n * 8))
>  #define QSPI_CKPOL(n)			(1 << (n * 8))
> 
> +#define MM_SWITCH	(1 << 0)
> +#define MEM_CS		(1 << 8)
> +#define MEM_CS_DIS	(0 << 8)

You might want to be consistent here, I'd use MEM_CS_EN and MEM_CS_DIS. But 
please see below first as MEM_CS_DIS won't be needed, so MEM_CS can be preserved 
as is and MEM_CS_DIS removed altogether.

> +
>  #define	QSPI_FRAME			4096
> 
>  #define QSPI_AUTOSUSPEND_TIMEOUT         2000
> @@ -129,6 +133,30 @@ static inline void ti_qspi_write(struct ti_qspi *qspi,
>  	writel(val, qspi->base + reg);
>  }
> 
> +static void enable_qspi_memory_mapped(struct ti_qspi *qspi)
> +{
> +	u32 val;
> +
> +	ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
> +	if (qspi->ctrl_mod) {
> +		val = readl(qspi->ctrl_base);
> +		val |= MEM_CS;
> +		writel(val, qspi->ctrl_base);
> +	}
> +}
> +
> +static void disable_qspi_memory_mapped(struct ti_qspi *qspi)
> +{
> +	u32 val;
> +
> +	ti_qspi_write(qspi, ~MM_SWITCH, QSPI_SPI_SWITCH_REG);
> +	if (qspi->ctrl_mod) {
> +		val = readl(qspi->ctrl_base);
> +		val &= MEM_CS_DIS;

This will likely break once SWITCH_REG contains more than one bit, you can fix 
this by using "val &= ~MEM_CS;" instead, which will also get rid of the 
MEM_CS_DIS bit.

> +		writel(val, qspi->ctrl_base);
> +	}
> +}
> +
>  static int ti_qspi_setup(struct spi_device *spi)
>  {
>  	struct ti_qspi	*qspi = spi_master_get_devdata(spi->master);
> @@ -459,6 +487,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  	master->transfer_one_message = ti_qspi_start_transfer_one;
>  	master->dev.of_node = pdev->dev.of_node;
>  	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
> +	master->mmap = true;
> 
>  	if (!of_property_read_u32(np, "num-cs", &num_cs))
>  		master->num_chipselect = num_cs;

Best regards,
Marek Vasut

Re: [PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:45 PM, Sourav Poddar wrote:
> These add api to configure set up registers which will be used
> for memory mapped operations.
> 
> These was provided as a pointer in the earlier patch and can be
> used by the slave devices to configure the master controller as an
> when required according to the usecases.
> 
> Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
> ---
>  drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>  1 files changed, 29 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index 48294d1..e4a8afc 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -117,6 +117,10 @@ struct ti_qspi {
>  #define MEM_CS		(1 << 8)
>  #define MEM_CS_DIS	(0 << 8)
> 
> +#define QSPI_SETUP0_RD_NORMAL   (0x0 << 12)
> +#define QSPI_SETUP0_RD_DUAL     (0x1 << 12)
> +#define QSPI_SETUP0_RD_QUAD     (0x3 << 12)
> +
>  #define	QSPI_FRAME			4096
> 
>  #define QSPI_AUTOSUSPEND_TIMEOUT         2000
> @@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
>  	return 0;
>  }
> 
> +static void ti_qspi_configure_from_slave(struct spi_device *spi)
> +{
> +	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
> +	struct slave_info info = spi->info;
> +	u32 memval, mode;
> +
> +	mode = spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD);
> +	memval =  (info.read_opcode << 0) | (info.program_opcode << 16) |
> +		((info.addr_width - 1) << 8) | (info.dummy_cycles << 10);
> +
> +	switch (mode) {
> +	case SPI_RX_DUAL:
> +		memval |= QSPI_SETUP0_RD_DUAL;
> +		break;
> +	case SPI_RX_QUAD:
> +		memval |= QSPI_SETUP0_RD_QUAD;
> +		break;
> +	default:

You want to catch invalid/unsupported mode here instead, so please add 'case 0:' 
for 1-bit transfer and treat default: as an error .

> +		memval |= QSPI_SETUP0_RD_NORMAL;
> +		break;
> +	}
> +	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
> +}
> +
>  static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>  {
>  	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
> @@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  	master->dev.of_node = pdev->dev.of_node;
>  	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>  	master->mmap = true;
> +	master->configure_from_slave = ti_qspi_configure_from_slave;
> 
>  	if (!of_property_read_u32(np, "num-cs", &num_cs))
>  		master->num_chipselect = num_cs;

Best regards,
Marek Vasut
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Re: [PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:45 PM, Sourav Poddar wrote:
> These add api to configure set up registers which will be used
> for memory mapped operations.
> 
> These was provided as a pointer in the earlier patch and can be
> used by the slave devices to configure the master controller as an
> when required according to the usecases.
> 
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
>  drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>  1 files changed, 29 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index 48294d1..e4a8afc 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -117,6 +117,10 @@ struct ti_qspi {
>  #define MEM_CS		(1 << 8)
>  #define MEM_CS_DIS	(0 << 8)
> 
> +#define QSPI_SETUP0_RD_NORMAL   (0x0 << 12)
> +#define QSPI_SETUP0_RD_DUAL     (0x1 << 12)
> +#define QSPI_SETUP0_RD_QUAD     (0x3 << 12)
> +
>  #define	QSPI_FRAME			4096
> 
>  #define QSPI_AUTOSUSPEND_TIMEOUT         2000
> @@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
>  	return 0;
>  }
> 
> +static void ti_qspi_configure_from_slave(struct spi_device *spi)
> +{
> +	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
> +	struct slave_info info = spi->info;
> +	u32 memval, mode;
> +
> +	mode = spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD);
> +	memval =  (info.read_opcode << 0) | (info.program_opcode << 16) |
> +		((info.addr_width - 1) << 8) | (info.dummy_cycles << 10);
> +
> +	switch (mode) {
> +	case SPI_RX_DUAL:
> +		memval |= QSPI_SETUP0_RD_DUAL;
> +		break;
> +	case SPI_RX_QUAD:
> +		memval |= QSPI_SETUP0_RD_QUAD;
> +		break;
> +	default:

You want to catch invalid/unsupported mode here instead, so please add 'case 0:' 
for 1-bit transfer and treat default: as an error .

> +		memval |= QSPI_SETUP0_RD_NORMAL;
> +		break;
> +	}
> +	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
> +}
> +
>  static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>  {
>  	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
> @@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  	master->dev.of_node = pdev->dev.of_node;
>  	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>  	master->mmap = true;
> +	master->configure_from_slave = ti_qspi_configure_from_slave;
> 
>  	if (!of_property_read_u32(np, "num-cs", &num_cs))
>  		master->num_chipselect = num_cs;

Best regards,
Marek Vasut

Re: [PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:46 PM, Sourav Poddar wrote:
> Adapt qspi driver to use (get_buf/put_buf) pointers added
> earlier.
> These can be called just before the memcpy operations to get hold
> of the memory mapped address and to turn on the controller clocks.
> 
> Signed-off-by: Sourav Poddar <sourav.poddar-l0cyMroinI0@public.gmane.org>
> ---
> v1->v2:
>  enable/disable memory mapped only when get_buf/put_buf is
>  called (basicaaly only when memory mapped read operation is
>  desired).
>  drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
>  1 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index e4a8afc..b83583c 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct
> spi_device *spi) ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>  }
> 
> +static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)

Should this not be a 'void __iomem *' instead of 'int __iomem *' in any case ?

> +{
> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
> +
> +	pm_runtime_get_sync(qspi->dev);
> +	enable_qspi_memory_mapped(qspi);
> +	return qspi->mmap_base;
> +}
> +
> +static void ti_qspi_put_mem_buf(struct spi_master *master)
> +{
> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
> +
> +	disable_qspi_memory_mapped(qspi);
> +	pm_runtime_put(qspi->dev);
> +}
> +
>  static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>  {
>  	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
> @@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>  	master->mmap = true;
>  	master->configure_from_slave = ti_qspi_configure_from_slave;
> +	master->get_buf = ti_qspi_get_mem_buf;
> +	master->put_buf = ti_qspi_put_mem_buf;
> 
>  	if (!of_property_read_u32(np, "num-cs", &num_cs))
>  		master->num_chipselect = num_cs;

Best regards,
Marek Vasut
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Re: [PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Marek Vasut]

On Friday, December 06, 2013 at 03:24:46 PM, Sourav Poddar wrote:
> Adapt qspi driver to use (get_buf/put_buf) pointers added
> earlier.
> These can be called just before the memcpy operations to get hold
> of the memory mapped address and to turn on the controller clocks.
> 
> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
> ---
> v1->v2:
>  enable/disable memory mapped only when get_buf/put_buf is
>  called (basicaaly only when memory mapped read operation is
>  desired).
>  drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
>  1 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index e4a8afc..b83583c 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct
> spi_device *spi) ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>  }
> 
> +static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)

Should this not be a 'void __iomem *' instead of 'int __iomem *' in any case ?

> +{
> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
> +
> +	pm_runtime_get_sync(qspi->dev);
> +	enable_qspi_memory_mapped(qspi);
> +	return qspi->mmap_base;
> +}
> +
> +static void ti_qspi_put_mem_buf(struct spi_master *master)
> +{
> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
> +
> +	disable_qspi_memory_mapped(qspi);
> +	pm_runtime_put(qspi->dev);
> +}
> +
>  static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>  {
>  	struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
> @@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>  	master->mmap = true;
>  	master->configure_from_slave = ti_qspi_configure_from_slave;
> +	master->get_buf = ti_qspi_get_mem_buf;
> +	master->put_buf = ti_qspi_put_mem_buf;
> 
>  	if (!of_property_read_u32(np, "num-cs", &num_cs))
>  		master->num_chipselect = num_cs;

Best regards,
Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 648 bytes --]

On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:

> My question is, shall we not wait for the new SPI NOR framework to be well 
> fleshed out and only then implement this controller driver on top of it ?

> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80 
> driver, which would become dead code once converted to the SPI NOR framework.

There is some stuff that pushes up into the controller in that while the
device is in memory mapped mode as far as I can tell it's not safe to do
other accesses so if someone's put more than one device on the SPI bus
we need to handle interactions there.

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 648 bytes --]

On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:

> My question is, shall we not wait for the new SPI NOR framework to be well 
> fleshed out and only then implement this controller driver on top of it ?

> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80 
> driver, which would become dead code once converted to the SPI NOR framework.

There is some stuff that pushes up into the controller in that while the
device is in memory mapped mode as far as I can tell it's not safe to do
other accesses so if someone's put more than one device on the SPI bus
we need to handle interactions there.

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]

Re: [PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

On Tuesday 10 December 2013 06:28 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:46 PM, Sourav Poddar wrote:
>> Adapt qspi driver to use (get_buf/put_buf) pointers added
>> earlier.
>> These can be called just before the memcpy operations to get hold
>> of the memory mapped address and to turn on the controller clocks.
>>
>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>> ---
>> v1->v2:
>>   enable/disable memory mapped only when get_buf/put_buf is
>>   called (basicaaly only when memory mapped read operation is
>>   desired).
>>   drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
>>   1 files changed, 19 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
>> index e4a8afc..b83583c 100644
>> --- a/drivers/spi/spi-ti-qspi.c
>> +++ b/drivers/spi/spi-ti-qspi.c
>> @@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct
>> spi_device *spi) ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>>   }
>>
>> +static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
> Should this not be a 'void __iomem *' instead of 'int __iomem *' in any case ?
>
Yes, it should be. Will fix in v3.
>> +{
>> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
>> +
>> +	pm_runtime_get_sync(qspi->dev);
>> +	enable_qspi_memory_mapped(qspi);
>> +	return qspi->mmap_base;
>> +}
>> +
>> +static void ti_qspi_put_mem_buf(struct spi_master *master)
>> +{
>> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
>> +
>> +	disable_qspi_memory_mapped(qspi);
>> +	pm_runtime_put(qspi->dev);
>> +}
>> +
>>   static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>>   {
>>   	struct ti_qspi_regs *ctx_reg =&qspi->ctx_reg;
>> @@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
>>   	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>>   	master->mmap = true;
>>   	master->configure_from_slave = ti_qspi_configure_from_slave;
>> +	master->get_buf = ti_qspi_get_mem_buf;
>> +	master->put_buf = ti_qspi_put_mem_buf;
>>
>>   	if (!of_property_read_u32(np, "num-cs",&num_cs))
>>   		master->num_chipselect = num_cs;
> Best regards,
> Marek Vasut

Re: [PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

On Tuesday 10 December 2013 06:28 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:46 PM, Sourav Poddar wrote:
>> Adapt qspi driver to use (get_buf/put_buf) pointers added
>> earlier.
>> These can be called just before the memcpy operations to get hold
>> of the memory mapped address and to turn on the controller clocks.
>>
>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>> ---
>> v1->v2:
>>   enable/disable memory mapped only when get_buf/put_buf is
>>   called (basicaaly only when memory mapped read operation is
>>   desired).
>>   drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
>>   1 files changed, 19 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
>> index e4a8afc..b83583c 100644
>> --- a/drivers/spi/spi-ti-qspi.c
>> +++ b/drivers/spi/spi-ti-qspi.c
>> @@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct
>> spi_device *spi) ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>>   }
>>
>> +static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
> Should this not be a 'void __iomem *' instead of 'int __iomem *' in any case ?
>
Yes, it should be. Will fix in v3.
>> +{
>> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
>> +
>> +	pm_runtime_get_sync(qspi->dev);
>> +	enable_qspi_memory_mapped(qspi);
>> +	return qspi->mmap_base;
>> +}
>> +
>> +static void ti_qspi_put_mem_buf(struct spi_master *master)
>> +{
>> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
>> +
>> +	disable_qspi_memory_mapped(qspi);
>> +	pm_runtime_put(qspi->dev);
>> +}
>> +
>>   static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>>   {
>>   	struct ti_qspi_regs *ctx_reg =&qspi->ctx_reg;
>> @@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
>>   	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>>   	master->mmap = true;
>>   	master->configure_from_slave = ti_qspi_configure_from_slave;
>> +	master->get_buf = ti_qspi_get_mem_buf;
>> +	master->put_buf = ti_qspi_put_mem_buf;
>>
>>   	if (!of_property_read_u32(np, "num-cs",&num_cs))
>>   		master->num_chipselect = num_cs;
> Best regards,
> Marek Vasut

Re: [PATCHv2 05/10] spi/qspi: Add api for get_buf/put_buf.

[Sourav Poddar]

On Tuesday 10 December 2013 06:28 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:46 PM, Sourav Poddar wrote:
>> Adapt qspi driver to use (get_buf/put_buf) pointers added
>> earlier.
>> These can be called just before the memcpy operations to get hold
>> of the memory mapped address and to turn on the controller clocks.
>>
>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>> ---
>> v1->v2:
>>   enable/disable memory mapped only when get_buf/put_buf is
>>   called (basicaaly only when memory mapped read operation is
>>   desired).
>>   drivers/spi/spi-ti-qspi.c |   19 +++++++++++++++++++
>>   1 files changed, 19 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
>> index e4a8afc..b83583c 100644
>> --- a/drivers/spi/spi-ti-qspi.c
>> +++ b/drivers/spi/spi-ti-qspi.c
>> @@ -248,6 +248,23 @@ static void ti_qspi_configure_from_slave(struct
>> spi_device *spi) ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>>   }
>>
>> +static inline int  __iomem *ti_qspi_get_mem_buf(struct spi_master *master)
> Should this not be a 'void __iomem *' instead of 'int __iomem *' in any case ?
>
Yes, it should be. Will fix in v3.
>> +{
>> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
>> +
>> +	pm_runtime_get_sync(qspi->dev);
>> +	enable_qspi_memory_mapped(qspi);
>> +	return qspi->mmap_base;
>> +}
>> +
>> +static void ti_qspi_put_mem_buf(struct spi_master *master)
>> +{
>> +	struct ti_qspi *qspi = spi_master_get_devdata(master);
>> +
>> +	disable_qspi_memory_mapped(qspi);
>> +	pm_runtime_put(qspi->dev);
>> +}
>> +
>>   static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>>   {
>>   	struct ti_qspi_regs *ctx_reg =&qspi->ctx_reg;
>> @@ -517,6 +534,8 @@ static int ti_qspi_probe(struct platform_device *pdev)
>>   	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>>   	master->mmap = true;
>>   	master->configure_from_slave = ti_qspi_configure_from_slave;
>> +	master->get_buf = ti_qspi_get_mem_buf;
>> +	master->put_buf = ti_qspi_put_mem_buf;
>>
>>   	if (!of_property_read_u32(np, "num-cs",&num_cs))
>>   		master->num_chipselect = num_cs;
> Best regards,
> Marek Vasut

Re: [PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Sourav Poddar]

On Tuesday 10 December 2013 06:27 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:45 PM, Sourav Poddar wrote:
>> These add api to configure set up registers which will be used
>> for memory mapped operations.
>>
>> These was provided as a pointer in the earlier patch and can be
>> used by the slave devices to configure the master controller as an
>> when required according to the usecases.
>>
>> Signed-off-by: Sourav Poddar<sourav.poddar-l0cyMroinI0@public.gmane.org>
>> ---
>>   drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>>   1 files changed, 29 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
>> index 48294d1..e4a8afc 100644
>> --- a/drivers/spi/spi-ti-qspi.c
>> +++ b/drivers/spi/spi-ti-qspi.c
>> @@ -117,6 +117,10 @@ struct ti_qspi {
>>   #define MEM_CS		(1<<  8)
>>   #define MEM_CS_DIS	(0<<  8)
>>
>> +#define QSPI_SETUP0_RD_NORMAL   (0x0<<  12)
>> +#define QSPI_SETUP0_RD_DUAL     (0x1<<  12)
>> +#define QSPI_SETUP0_RD_QUAD     (0x3<<  12)
>> +
>>   #define	QSPI_FRAME			4096
>>
>>   #define QSPI_AUTOSUSPEND_TIMEOUT         2000
>> @@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
>>   	return 0;
>>   }
>>
>> +static void ti_qspi_configure_from_slave(struct spi_device *spi)
>> +{
>> +	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
>> +	struct slave_info info = spi->info;
>> +	u32 memval, mode;
>> +
>> +	mode = spi->mode&  (SPI_RX_DUAL | SPI_RX_QUAD);
>> +	memval =  (info.read_opcode<<  0) | (info.program_opcode<<  16) |
>> +		((info.addr_width - 1)<<  8) | (info.dummy_cycles<<  10);
>> +
>> +	switch (mode) {
>> +	case SPI_RX_DUAL:
>> +		memval |= QSPI_SETUP0_RD_DUAL;
>> +		break;
>> +	case SPI_RX_QUAD:
>> +		memval |= QSPI_SETUP0_RD_QUAD;
>> +		break;
>> +	default:
> You want to catch invalid/unsupported mode here instead, so please add 'case 0:'
> for 1-bit transfer and treat default: as an error .
>
Ok. make sense. will change that in v3.
>> +		memval |= QSPI_SETUP0_RD_NORMAL;
>> +		break;
>> +	}
>> +	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>> +}
>> +
>>   static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>>   {
>>   	struct ti_qspi_regs *ctx_reg =&qspi->ctx_reg;
>> @@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>>   	master->dev.of_node = pdev->dev.of_node;
>>   	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>>   	master->mmap = true;
>> +	master->configure_from_slave = ti_qspi_configure_from_slave;
>>
>>   	if (!of_property_read_u32(np, "num-cs",&num_cs))
>>   		master->num_chipselect = num_cs;
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Sourav Poddar]

On Tuesday 10 December 2013 06:27 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:45 PM, Sourav Poddar wrote:
>> These add api to configure set up registers which will be used
>> for memory mapped operations.
>>
>> These was provided as a pointer in the earlier patch and can be
>> used by the slave devices to configure the master controller as an
>> when required according to the usecases.
>>
>> Signed-off-by: Sourav Poddar<sourav.poddar-l0cyMroinI0@public.gmane.org>
>> ---
>>   drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>>   1 files changed, 29 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
>> index 48294d1..e4a8afc 100644
>> --- a/drivers/spi/spi-ti-qspi.c
>> +++ b/drivers/spi/spi-ti-qspi.c
>> @@ -117,6 +117,10 @@ struct ti_qspi {
>>   #define MEM_CS		(1<<  8)
>>   #define MEM_CS_DIS	(0<<  8)
>>
>> +#define QSPI_SETUP0_RD_NORMAL   (0x0<<  12)
>> +#define QSPI_SETUP0_RD_DUAL     (0x1<<  12)
>> +#define QSPI_SETUP0_RD_QUAD     (0x3<<  12)
>> +
>>   #define	QSPI_FRAME			4096
>>
>>   #define QSPI_AUTOSUSPEND_TIMEOUT         2000
>> @@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
>>   	return 0;
>>   }
>>
>> +static void ti_qspi_configure_from_slave(struct spi_device *spi)
>> +{
>> +	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
>> +	struct slave_info info = spi->info;
>> +	u32 memval, mode;
>> +
>> +	mode = spi->mode&  (SPI_RX_DUAL | SPI_RX_QUAD);
>> +	memval =  (info.read_opcode<<  0) | (info.program_opcode<<  16) |
>> +		((info.addr_width - 1)<<  8) | (info.dummy_cycles<<  10);
>> +
>> +	switch (mode) {
>> +	case SPI_RX_DUAL:
>> +		memval |= QSPI_SETUP0_RD_DUAL;
>> +		break;
>> +	case SPI_RX_QUAD:
>> +		memval |= QSPI_SETUP0_RD_QUAD;
>> +		break;
>> +	default:
> You want to catch invalid/unsupported mode here instead, so please add 'case 0:'
> for 1-bit transfer and treat default: as an error .
>
Ok. make sense. will change that in v3.
>> +		memval |= QSPI_SETUP0_RD_NORMAL;
>> +		break;
>> +	}
>> +	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>> +}
>> +
>>   static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>>   {
>>   	struct ti_qspi_regs *ctx_reg =&qspi->ctx_reg;
>> @@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>>   	master->dev.of_node = pdev->dev.of_node;
>>   	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>>   	master->mmap = true;
>> +	master->configure_from_slave = ti_qspi_configure_from_slave;
>>
>>   	if (!of_property_read_u32(np, "num-cs",&num_cs))
>>   		master->num_chipselect = num_cs;
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCHv2 04/10] spi/qspi: configure set up register for memory map.

[Sourav Poddar]

On Tuesday 10 December 2013 06:27 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:45 PM, Sourav Poddar wrote:
>> These add api to configure set up registers which will be used
>> for memory mapped operations.
>>
>> These was provided as a pointer in the earlier patch and can be
>> used by the slave devices to configure the master controller as an
>> when required according to the usecases.
>>
>> Signed-off-by: Sourav Poddar<sourav.poddar@ti.com>
>> ---
>>   drivers/spi/spi-ti-qspi.c |   29 +++++++++++++++++++++++++++++
>>   1 files changed, 29 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
>> index 48294d1..e4a8afc 100644
>> --- a/drivers/spi/spi-ti-qspi.c
>> +++ b/drivers/spi/spi-ti-qspi.c
>> @@ -117,6 +117,10 @@ struct ti_qspi {
>>   #define MEM_CS		(1<<  8)
>>   #define MEM_CS_DIS	(0<<  8)
>>
>> +#define QSPI_SETUP0_RD_NORMAL   (0x0<<  12)
>> +#define QSPI_SETUP0_RD_DUAL     (0x1<<  12)
>> +#define QSPI_SETUP0_RD_QUAD     (0x3<<  12)
>> +
>>   #define	QSPI_FRAME			4096
>>
>>   #define QSPI_AUTOSUSPEND_TIMEOUT         2000
>> @@ -220,6 +224,30 @@ static int ti_qspi_setup(struct spi_device *spi)
>>   	return 0;
>>   }
>>
>> +static void ti_qspi_configure_from_slave(struct spi_device *spi)
>> +{
>> +	struct ti_qspi  *qspi = spi_master_get_devdata(spi->master);
>> +	struct slave_info info = spi->info;
>> +	u32 memval, mode;
>> +
>> +	mode = spi->mode&  (SPI_RX_DUAL | SPI_RX_QUAD);
>> +	memval =  (info.read_opcode<<  0) | (info.program_opcode<<  16) |
>> +		((info.addr_width - 1)<<  8) | (info.dummy_cycles<<  10);
>> +
>> +	switch (mode) {
>> +	case SPI_RX_DUAL:
>> +		memval |= QSPI_SETUP0_RD_DUAL;
>> +		break;
>> +	case SPI_RX_QUAD:
>> +		memval |= QSPI_SETUP0_RD_QUAD;
>> +		break;
>> +	default:
> You want to catch invalid/unsupported mode here instead, so please add 'case 0:'
> for 1-bit transfer and treat default: as an error .
>
Ok. make sense. will change that in v3.
>> +		memval |= QSPI_SETUP0_RD_NORMAL;
>> +		break;
>> +	}
>> +	ti_qspi_write(qspi, memval, QSPI_SPI_SETUP0_REG);
>> +}
>> +
>>   static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
>>   {
>>   	struct ti_qspi_regs *ctx_reg =&qspi->ctx_reg;
>> @@ -488,6 +516,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>>   	master->dev.of_node = pdev->dev.of_node;
>>   	master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
>>   	master->mmap = true;
>> +	master->configure_from_slave = ti_qspi_configure_from_slave;
>>
>>   	if (!of_property_read_u32(np, "num-cs",&num_cs))
>>   		master->num_chipselect = num_cs;
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:
> > My question is, shall we not wait for the new SPI NOR framework to be
> > well fleshed out and only then implement this controller driver on top
> > of it ?
> > 
> > I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
> > m25p80 driver, which would become dead code once converted to the SPI
> > NOR framework.
> 
> There is some stuff that pushes up into the controller in that while the
> device is in memory mapped mode as far as I can tell it's not safe to do
> other accesses so if someone's put more than one device on the SPI bus
> we need to handle interactions there.

OK, so it's either-or . That seems OK, you might want to have two drivers for 
this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR 
block. ... that is of course, if these two modes can't work together.

Best regards,
Marek Vasut
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:
> > My question is, shall we not wait for the new SPI NOR framework to be
> > well fleshed out and only then implement this controller driver on top
> > of it ?
> > 
> > I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
> > m25p80 driver, which would become dead code once converted to the SPI
> > NOR framework.
> 
> There is some stuff that pushes up into the controller in that while the
> device is in memory mapped mode as far as I can tell it's not safe to do
> other accesses so if someone's put more than one device on the SPI bus
> we need to handle interactions there.

OK, so it's either-or . That seems OK, you might want to have two drivers for 
this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR 
block. ... that is of course, if these two modes can't work together.

Best regards,
Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Mark Brown]

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On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:

> > There is some stuff that pushes up into the controller in that while the
> > device is in memory mapped mode as far as I can tell it's not safe to do
> > other accesses so if someone's put more than one device on the SPI bus
> > we need to handle interactions there.

> OK, so it's either-or . That seems OK, you might want to have two drivers for 
> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR 
> block. ... that is of course, if these two modes can't work together.

Or the client disables the memory map when it's not actively being used
and the stops other transfers starting while the mapping is in place.
I'd expect we'll have to cope with shared use at some point, hardware
engineers will probably build such systems.

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[-- Attachment #2: Type: text/plain, Size: 144 bytes --]

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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Mark Brown]

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On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:

> > There is some stuff that pushes up into the controller in that while the
> > device is in memory mapped mode as far as I can tell it's not safe to do
> > other accesses so if someone's put more than one device on the SPI bus
> > we need to handle interactions there.

> OK, so it's either-or . That seems OK, you might want to have two drivers for 
> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR 
> block. ... that is of course, if these two modes can't work together.

Or the client disables the memory map when it's not actively being used
and the stops other transfers starting while the mapping is in place.
I'd expect we'll have to cope with shared use at some point, hardware
engineers will probably build such systems.

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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Tuesday, December 10, 2013 at 07:29:04 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
> > On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
> > > There is some stuff that pushes up into the controller in that while
> > > the device is in memory mapped mode as far as I can tell it's not safe
> > > to do other accesses so if someone's put more than one device on the
> > > SPI bus we need to handle interactions there.
> > 
> > OK, so it's either-or . That seems OK, you might want to have two drivers
> > for this ip block, one to handle it as a SPI block and one to handle it
> > as a SPI-NOR block. ... that is of course, if these two modes can't work
> > together.
> 
> Or the client disables the memory map when it's not actively being used
> and the stops other transfers starting while the mapping is in place.
> I'd expect we'll have to cope with shared use at some point, hardware
> engineers will probably build such systems.

Aren't we fixing the problem at the wrong place ? Maybe it's about time to fix 
the engineers ;-)

Best regards,
Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Tuesday, December 10, 2013 at 07:29:04 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
> > On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
> > > There is some stuff that pushes up into the controller in that while
> > > the device is in memory mapped mode as far as I can tell it's not safe
> > > to do other accesses so if someone's put more than one device on the
> > > SPI bus we need to handle interactions there.
> > 
> > OK, so it's either-or . That seems OK, you might want to have two drivers
> > for this ip block, one to handle it as a SPI block and one to handle it
> > as a SPI-NOR block. ... that is of course, if these two modes can't work
> > together.
> 
> Or the client disables the memory map when it's not actively being used
> and the stops other transfers starting while the mapping is in place.
> I'd expect we'll have to cope with shared use at some point, hardware
> engineers will probably build such systems.

Aren't we fixing the problem at the wrong place ? Maybe it's about time to fix 
the engineers ;-)

Best regards,
Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Marek,
On Tuesday 10 December 2013 06:19 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
>> The patch series aims to add memory mapped support for TI qspi
>> contoller and also add support for the same in serial flash driver(m25p80).
> My question is, shall we not wait for the new SPI NOR framework to be well
> fleshed out and only then implement this controller driver on top of it ?
I think it will still take lot of time for spi framework to come to 
alignment
and get merged in the mainline. Till then, m25p80 development should
go on independently. Once, the spi framework is ready, I can myself port
this into the new framework.
> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80
> driver, which would become dead code once converted to the SPI NOR framework.
>
I dont think that spi framework till now provides capabilities which can 
be used
to handle memory mapped cases.
I did a quad mode support for m25p80 which easily got cloned into the 
new spi framework.
Same can be done for the memory mapped support too


> Best regards,
> Marek Vasut

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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Marek,
On Tuesday 10 December 2013 06:19 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
>> The patch series aims to add memory mapped support for TI qspi
>> contoller and also add support for the same in serial flash driver(m25p80).
> My question is, shall we not wait for the new SPI NOR framework to be well
> fleshed out and only then implement this controller driver on top of it ?
I think it will still take lot of time for spi framework to come to 
alignment
and get merged in the mainline. Till then, m25p80 development should
go on independently. Once, the spi framework is ready, I can myself port
this into the new framework.
> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80
> driver, which would become dead code once converted to the SPI NOR framework.
>
I dont think that spi framework till now provides capabilities which can 
be used
to handle memory mapped cases.
I did a quad mode support for m25p80 which easily got cloned into the 
new spi framework.
Same can be done for the memory mapped support too


> Best regards,
> Marek Vasut

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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Marek,
On Tuesday 10 December 2013 06:19 PM, Marek Vasut wrote:
> On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
>> The patch series aims to add memory mapped support for TI qspi
>> contoller and also add support for the same in serial flash driver(m25p80).
> My question is, shall we not wait for the new SPI NOR framework to be well
> fleshed out and only then implement this controller driver on top of it ?
I think it will still take lot of time for spi framework to come to 
alignment
and get merged in the mainline. Till then, m25p80 development should
go on independently. Once, the spi framework is ready, I can myself port
this into the new framework.
> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the m25p80
> driver, which would become dead code once converted to the SPI NOR framework.
>
I dont think that spi framework till now provides capabilities which can 
be used
to handle memory mapped cases.
I did a quad mode support for m25p80 which easily got cloned into the 
new spi framework.
Same can be done for the memory mapped support too


> Best regards,
> Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

On Tuesday 10 December 2013 11:52 PM, Marek Vasut wrote:
> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
>> On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:
>>> My question is, shall we not wait for the new SPI NOR framework to be
>>> well fleshed out and only then implement this controller driver on top
>>> of it ?
>>>
>>> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
>>> m25p80 driver, which would become dead code once converted to the SPI
>>> NOR framework.
>> There is some stuff that pushes up into the controller in that while the
>> device is in memory mapped mode as far as I can tell it's not safe to do
>> other accesses so if someone's put more than one device on the SPI bus
>> we need to handle interactions there.
> OK, so it's either-or . That seems OK, you might want to have two drivers for
> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
> block. ... that is of course, if these two modes can't work together.
>
the two modes cant work together.
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

On Tuesday 10 December 2013 11:52 PM, Marek Vasut wrote:
> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
>> On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:
>>> My question is, shall we not wait for the new SPI NOR framework to be
>>> well fleshed out and only then implement this controller driver on top
>>> of it ?
>>>
>>> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
>>> m25p80 driver, which would become dead code once converted to the SPI
>>> NOR framework.
>> There is some stuff that pushes up into the controller in that while the
>> device is in memory mapped mode as far as I can tell it's not safe to do
>> other accesses so if someone's put more than one device on the SPI bus
>> we need to handle interactions there.
> OK, so it's either-or . That seems OK, you might want to have two drivers for
> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
> block. ... that is of course, if these two modes can't work together.
>
the two modes cant work together.
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

On Tuesday 10 December 2013 11:52 PM, Marek Vasut wrote:
> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
>> On Tue, Dec 10, 2013 at 01:49:13PM +0100, Marek Vasut wrote:
>>> My question is, shall we not wait for the new SPI NOR framework to be
>>> well fleshed out and only then implement this controller driver on top
>>> of it ?
>>>
>>> I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
>>> m25p80 driver, which would become dead code once converted to the SPI
>>> NOR framework.
>> There is some stuff that pushes up into the controller in that while the
>> device is in memory mapped mode as far as I can tell it's not safe to do
>> other accesses so if someone's put more than one device on the SPI bus
>> we need to handle interactions there.
> OK, so it's either-or . That seems OK, you might want to have two drivers for
> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
> block. ... that is of course, if these two modes can't work together.
>
the two modes cant work together.
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Mark,
On Tuesday 10 December 2013 11:59 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
>> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
>>> There is some stuff that pushes up into the controller in that while the
>>> device is in memory mapped mode as far as I can tell it's not safe to do
>>> other accesses so if someone's put more than one device on the SPI bus
>>> we need to handle interactions there.
>> OK, so it's either-or . That seems OK, you might want to have two drivers for
>> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
>> block. ... that is of course, if these two modes can't work together.
> Or the client disables the memory map when it's not actively being used
> and the stops other transfers starting while the mapping is in place.
> I'd expect we'll have to cope with shared use at some point, hardware
> engineers will probably build such systems.
So, what I am doing here in my code is that whenever I desired to use a
mmap operations I do a

a. flash_lock()
b. wait till the previous erase/write is finished
c. 'get_buf' which in turn does
       - get_sync
       - enable memory mapped

d. memcpy
e. 'put_buf' which in turn does
            - disable memory mapped
            - put_sync


f. flash_unlock

Do you see any point missing here?

On your comment about disabling transfers while doing a mmap..
Are you suggesting on having a check in qspi transfer api something like 
this..

transfer_one_message {
  if (mmap)
      return -EINPROGRESS;
}

Where mmap can be set/unset in get_buf/put_buf respectively.
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Mark,
On Tuesday 10 December 2013 11:59 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
>> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
>>> There is some stuff that pushes up into the controller in that while the
>>> device is in memory mapped mode as far as I can tell it's not safe to do
>>> other accesses so if someone's put more than one device on the SPI bus
>>> we need to handle interactions there.
>> OK, so it's either-or . That seems OK, you might want to have two drivers for
>> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
>> block. ... that is of course, if these two modes can't work together.
> Or the client disables the memory map when it's not actively being used
> and the stops other transfers starting while the mapping is in place.
> I'd expect we'll have to cope with shared use at some point, hardware
> engineers will probably build such systems.
So, what I am doing here in my code is that whenever I desired to use a
mmap operations I do a

a. flash_lock()
b. wait till the previous erase/write is finished
c. 'get_buf' which in turn does
       - get_sync
       - enable memory mapped

d. memcpy
e. 'put_buf' which in turn does
            - disable memory mapped
            - put_sync


f. flash_unlock

Do you see any point missing here?

On your comment about disabling transfers while doing a mmap..
Are you suggesting on having a check in qspi transfer api something like 
this..

transfer_one_message {
  if (mmap)
      return -EINPROGRESS;
}

Where mmap can be set/unset in get_buf/put_buf respectively.
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Sourav Poddar]

Hi Mark,
On Tuesday 10 December 2013 11:59 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 07:22:10PM +0100, Marek Vasut wrote:
>> On Tuesday, December 10, 2013 at 05:11:43 PM, Mark Brown wrote:
>>> There is some stuff that pushes up into the controller in that while the
>>> device is in memory mapped mode as far as I can tell it's not safe to do
>>> other accesses so if someone's put more than one device on the SPI bus
>>> we need to handle interactions there.
>> OK, so it's either-or . That seems OK, you might want to have two drivers for
>> this ip block, one to handle it as a SPI block and one to handle it as a SPI-NOR
>> block. ... that is of course, if these two modes can't work together.
> Or the client disables the memory map when it's not actively being used
> and the stops other transfers starting while the mapping is in place.
> I'd expect we'll have to cope with shared use at some point, hardware
> engineers will probably build such systems.
So, what I am doing here in my code is that whenever I desired to use a
mmap operations I do a

a. flash_lock()
b. wait till the previous erase/write is finished
c. 'get_buf' which in turn does
       - get_sync
       - enable memory mapped

d. memcpy
e. 'put_buf' which in turn does
            - disable memory mapped
            - put_sync


f. flash_unlock

Do you see any point missing here?

On your comment about disabling transfers while doing a mmap..
Are you suggesting on having a check in qspi transfer api something like 
this..

transfer_one_message {
  if (mmap)
      return -EINPROGRESS;
}

Where mmap can be set/unset in get_buf/put_buf respectively.

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Wednesday, December 11, 2013 at 05:18:45 AM, Sourav Poddar wrote:
> Hi Marek,
> 
> On Tuesday 10 December 2013 06:19 PM, Marek Vasut wrote:
> > On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
> >> The patch series aims to add memory mapped support for TI qspi
> >> contoller and also add support for the same in serial flash
> >> driver(m25p80).
> > 
> > My question is, shall we not wait for the new SPI NOR framework to be
> > well fleshed out and only then implement this controller driver on top
> > of it ?
> 
> I think it will still take lot of time for spi framework to come to
> alignment
> and get merged in the mainline. Till then, m25p80 development should
> go on independently. Once, the spi framework is ready, I can myself port
> this into the new framework.

Sure, but I also think Huang is coming close to the new framework. Have you seen 
his latest patchset ( Message-ID: <1386318764-15882-1-git-send-email-
b32955-KZfg59tc24xl57MIdRCFDg@public.gmane.org> ) ? I think you two should really start working on the new 
framework instead of bending drivers all around.

> > I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
> > m25p80 driver, which would become dead code once converted to the SPI
> > NOR framework.
> 
> I dont think that spi framework till now provides capabilities which can
> be used
> to handle memory mapped cases.

Not yet, so please bring it up in the discussion there :)

> I did a quad mode support for m25p80 which easily got cloned into the
> new spi framework.
> Same can be done for the memory mapped support too

The quad mode didn't need any new hooks in the m25p80, did it ? That's the 
difference here.

Best regards,
Marek Vasut
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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Marek Vasut]

On Wednesday, December 11, 2013 at 05:18:45 AM, Sourav Poddar wrote:
> Hi Marek,
> 
> On Tuesday 10 December 2013 06:19 PM, Marek Vasut wrote:
> > On Friday, December 06, 2013 at 03:24:41 PM, Sourav Poddar wrote:
> >> The patch series aims to add memory mapped support for TI qspi
> >> contoller and also add support for the same in serial flash
> >> driver(m25p80).
> > 
> > My question is, shall we not wait for the new SPI NOR framework to be
> > well fleshed out and only then implement this controller driver on top
> > of it ?
> 
> I think it will still take lot of time for spi framework to come to
> alignment
> and get merged in the mainline. Till then, m25p80 development should
> go on independently. Once, the spi framework is ready, I can myself port
> this into the new framework.

Sure, but I also think Huang is coming close to the new framework. Have you seen 
his latest patchset ( Message-ID: <1386318764-15882-1-git-send-email-
b32955@freescale.com> ) ? I think you two should really start working on the new 
framework instead of bending drivers all around.

> > I have a feeling this patchset adds quite a lot of ad-hoc hacks into the
> > m25p80 driver, which would become dead code once converted to the SPI
> > NOR framework.
> 
> I dont think that spi framework till now provides capabilities which can
> be used
> to handle memory mapped cases.

Not yet, so please bring it up in the discussion there :)

> I did a quad mode support for m25p80 which easily got cloned into the
> new spi framework.
> Same can be done for the memory mapped support too

The quad mode didn't need any new hooks in the m25p80, did it ? That's the 
difference here.

Best regards,
Marek Vasut

Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 499 bytes --]

On Wed, Dec 11, 2013 at 11:44:22AM +0100, Marek Vasut wrote:
> On Wednesday, December 11, 2013 at 05:18:45 AM, Sourav Poddar wrote:

> > I did a quad mode support for m25p80 which easily got cloned into the
> > new spi framework.
> > Same can be done for the memory mapped support too

> The quad mode didn't need any new hooks in the m25p80, did it ? That's the 
> difference here.

It did, there's explicit code in the flash driver for it.  However it's
rather more generic than this.

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[-- Type: application/pgp-signature, Size: 836 bytes --]

[-- Attachment #2: Type: text/plain, Size: 144 bytes --]

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Re: [PATCHv2 00/10] Add memory mapped support for ti qspi, m25p80 serial flash.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 499 bytes --]

On Wed, Dec 11, 2013 at 11:44:22AM +0100, Marek Vasut wrote:
> On Wednesday, December 11, 2013 at 05:18:45 AM, Sourav Poddar wrote:

> > I did a quad mode support for m25p80 which easily got cloned into the
> > new spi framework.
> > Same can be done for the memory mapped support too

> The quad mode didn't need any new hooks in the m25p80, did it ? That's the 
> difference here.

It did, there's explicit code in the flash driver for it.  However it's
rather more generic than this.

[-- Attachment #2: Digital signature --]
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Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

Hi Mark,
On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:
>
>> I posted this for review along with other code changes.
>> I will post them seperately to Benoit.
> Please wait until the driver updates have been reviewed.
I was thinking of sending this dts patches seperately to benoit, so that we
can enable atleast 1/4 bit mode for our controller. Anyways, there is no
memory mapped specific binding used. Once, we get our driver updates
reviewed and *if* there is anything memory mapped specific added, I can
send them as a seperate patch. Anyways with spi nor  framework in sight the
driver uodates can go anyewhere and might take some time.
.
Does this sound Ok to you?

______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCHv2 09/10] arm: dts: dra7: Add qspi device.

[Sourav Poddar]

Hi Mark,
On Tuesday 10 December 2013 04:01 PM, Mark Brown wrote:
> On Tue, Dec 10, 2013 at 09:55:15AM +0530, Sourav Poddar wrote:
>
>> I posted this for review along with other code changes.
>> I will post them seperately to Benoit.
> Please wait until the driver updates have been reviewed.
I was thinking of sending this dts patches seperately to benoit, so that we
can enable atleast 1/4 bit mode for our controller. Anyways, there is no
memory mapped specific binding used. Once, we get our driver updates
reviewed and *if* there is anything memory mapped specific added, I can
send them as a seperate patch. Anyways with spi nor  framework in sight the
driver uodates can go anyewhere and might take some time.
.
Does this sound Ok to you?

Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Huang Shijie]

On Fri, Dec 06, 2013 at 07:54:48PM +0530, Sourav Poddar wrote:
> Adapt driver to do a memory mapped read.
> @@ -109,6 +109,7 @@ struct m25p {
>  	u8			program_opcode;
>  	u8			*command;
>  	enum read_type		flash_read;
> +	void __iomem *mem_addr;

I think we can remove this field.
You can use a local variable in the m25p80_read.

>  };
>  
>  static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
> @@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>  	size_t *retlen, u_char *buf)
>  {
>  	struct m25p *flash = mtd_to_m25p(mtd);
> +	struct spi_master *master = flash->spi->master;
>  	struct spi_transfer t[2];
>  	struct spi_message m;
>  	uint8_t opcode;
> @@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>  	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
>  			__func__, (u32)from, len);
>  
> +	if (master->mmap) {
> +		mutex_lock(&flash->lock);
> +		/* Wait till previous write/erase is done. */
> +		if (wait_till_ready(flash)) {
> +			mutex_unlock(&flash->lock);
> +			return 1;
> +		}
> +		flash->mem_addr = master->get_buf(master);
> +		memcpy(buf, flash->mem_addr + from, len);
> +		master->put_buf(master);
> +		*retlen = len;
> +		goto out;
> +	}
> +
>  	spi_message_init(&m);
>  	memset(t, 0, (sizeof t));
>  
> @@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>  
>  	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
>  
> +out:
>  	mutex_unlock(&flash->lock);
>  
>  	return 0;
> @@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
>  		flash->addr_width = 3;
>  	}
>  
> +	if (spi->master->configure_from_slave)
> +		m25p80_fill_flash_information(flash);
> +
You have add a configure_from_slave hook in the SPI, why you also need 
a same hook in the SPI-NOR framework?

And i think the enable_mmap/disable_mmap is not needed too.

All the three hooks are used to set the SPI bus controller.

And the SPI-NOR framework only handles the issues between the 
SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
SPI-NOR.

thanks
Huang Shijie


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Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Huang Shijie]

On Fri, Dec 06, 2013 at 07:54:48PM +0530, Sourav Poddar wrote:
> Adapt driver to do a memory mapped read.
> @@ -109,6 +109,7 @@ struct m25p {
>  	u8			program_opcode;
>  	u8			*command;
>  	enum read_type		flash_read;
> +	void __iomem *mem_addr;

I think we can remove this field.
You can use a local variable in the m25p80_read.

>  };
>  
>  static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
> @@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>  	size_t *retlen, u_char *buf)
>  {
>  	struct m25p *flash = mtd_to_m25p(mtd);
> +	struct spi_master *master = flash->spi->master;
>  	struct spi_transfer t[2];
>  	struct spi_message m;
>  	uint8_t opcode;
> @@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>  	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
>  			__func__, (u32)from, len);
>  
> +	if (master->mmap) {
> +		mutex_lock(&flash->lock);
> +		/* Wait till previous write/erase is done. */
> +		if (wait_till_ready(flash)) {
> +			mutex_unlock(&flash->lock);
> +			return 1;
> +		}
> +		flash->mem_addr = master->get_buf(master);
> +		memcpy(buf, flash->mem_addr + from, len);
> +		master->put_buf(master);
> +		*retlen = len;
> +		goto out;
> +	}
> +
>  	spi_message_init(&m);
>  	memset(t, 0, (sizeof t));
>  
> @@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>  
>  	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
>  
> +out:
>  	mutex_unlock(&flash->lock);
>  
>  	return 0;
> @@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
>  		flash->addr_width = 3;
>  	}
>  
> +	if (spi->master->configure_from_slave)
> +		m25p80_fill_flash_information(flash);
> +
You have add a configure_from_slave hook in the SPI, why you also need 
a same hook in the SPI-NOR framework?

And i think the enable_mmap/disable_mmap is not needed too.

All the three hooks are used to set the SPI bus controller.

And the SPI-NOR framework only handles the issues between the 
SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
SPI-NOR.

thanks
Huang Shijie

Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
> On Fri, Dec 06, 2013 at 07:54:48PM +0530, Sourav Poddar wrote:
>> Adapt driver to do a memory mapped read.
>> @@ -109,6 +109,7 @@ struct m25p {
>>   	u8			program_opcode;
>>   	u8			*command;
>>   	enum read_type		flash_read;
>> +	void __iomem *mem_addr;
> I think we can remove this field.
> You can use a local variable in the m25p80_read.
>
>>   };
>>
>>   static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
>> @@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>   	size_t *retlen, u_char *buf)
>>   {
>>   	struct m25p *flash = mtd_to_m25p(mtd);
>> +	struct spi_master *master = flash->spi->master;
>>   	struct spi_transfer t[2];
>>   	struct spi_message m;
>>   	uint8_t opcode;
>> @@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>   	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
>>   			__func__, (u32)from, len);
>>
>> +	if (master->mmap) {
>> +		mutex_lock(&flash->lock);
>> +		/* Wait till previous write/erase is done. */
>> +		if (wait_till_ready(flash)) {
>> +			mutex_unlock(&flash->lock);
>> +			return 1;
>> +		}
>> +		flash->mem_addr = master->get_buf(master);
>> +		memcpy(buf, flash->mem_addr + from, len);
>> +		master->put_buf(master);
>> +		*retlen = len;
>> +		goto out;
>> +	}
>> +
>>   	spi_message_init(&m);
>>   	memset(t, 0, (sizeof t));
>>
>> @@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>
>>   	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
>>
>> +out:
>>   	mutex_unlock(&flash->lock);
>>
>>   	return 0;
>> @@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
>>   		flash->addr_width = 3;
>>   	}
>>
>> +	if (spi->master->configure_from_slave)
>> +		m25p80_fill_flash_information(flash);
>> +
> You have add a configure_from_slave hook in the SPI, why you also need
> a same hook in the SPI-NOR framework?
>
We need a way to provoke this, currently it is placed in m25p80. If m25p80
is removed, for where should I handle these in nor framework?
> And i think the enable_mmap/disable_mmap is not needed too.
>
> All the three hooks are used to set the SPI bus controller.

> And the SPI-NOR framework only handles the issues between the
> SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
> SPI-NOR.
My controller can be used as spi flash controller as well as a spi
controller.
> thanks
> Huang Shijie
>
>

Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
> On Fri, Dec 06, 2013 at 07:54:48PM +0530, Sourav Poddar wrote:
>> Adapt driver to do a memory mapped read.
>> @@ -109,6 +109,7 @@ struct m25p {
>>   	u8			program_opcode;
>>   	u8			*command;
>>   	enum read_type		flash_read;
>> +	void __iomem *mem_addr;
> I think we can remove this field.
> You can use a local variable in the m25p80_read.
>
>>   };
>>
>>   static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
>> @@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>   	size_t *retlen, u_char *buf)
>>   {
>>   	struct m25p *flash = mtd_to_m25p(mtd);
>> +	struct spi_master *master = flash->spi->master;
>>   	struct spi_transfer t[2];
>>   	struct spi_message m;
>>   	uint8_t opcode;
>> @@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>   	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
>>   			__func__, (u32)from, len);
>>
>> +	if (master->mmap) {
>> +		mutex_lock(&flash->lock);
>> +		/* Wait till previous write/erase is done. */
>> +		if (wait_till_ready(flash)) {
>> +			mutex_unlock(&flash->lock);
>> +			return 1;
>> +		}
>> +		flash->mem_addr = master->get_buf(master);
>> +		memcpy(buf, flash->mem_addr + from, len);
>> +		master->put_buf(master);
>> +		*retlen = len;
>> +		goto out;
>> +	}
>> +
>>   	spi_message_init(&m);
>>   	memset(t, 0, (sizeof t));
>>
>> @@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>
>>   	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
>>
>> +out:
>>   	mutex_unlock(&flash->lock);
>>
>>   	return 0;
>> @@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
>>   		flash->addr_width = 3;
>>   	}
>>
>> +	if (spi->master->configure_from_slave)
>> +		m25p80_fill_flash_information(flash);
>> +
> You have add a configure_from_slave hook in the SPI, why you also need
> a same hook in the SPI-NOR framework?
>
We need a way to provoke this, currently it is placed in m25p80. If m25p80
is removed, for where should I handle these in nor framework?
> And i think the enable_mmap/disable_mmap is not needed too.
>
> All the three hooks are used to set the SPI bus controller.

> And the SPI-NOR framework only handles the issues between the
> SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
> SPI-NOR.
My controller can be used as spi flash controller as well as a spi
controller.
> thanks
> Huang Shijie
>
>

Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Sourav Poddar]

On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
> On Fri, Dec 06, 2013 at 07:54:48PM +0530, Sourav Poddar wrote:
>> Adapt driver to do a memory mapped read.
>> @@ -109,6 +109,7 @@ struct m25p {
>>   	u8			program_opcode;
>>   	u8			*command;
>>   	enum read_type		flash_read;
>> +	void __iomem *mem_addr;
> I think we can remove this field.
> You can use a local variable in the m25p80_read.
>
>>   };
>>
>>   static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
>> @@ -515,6 +516,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>   	size_t *retlen, u_char *buf)
>>   {
>>   	struct m25p *flash = mtd_to_m25p(mtd);
>> +	struct spi_master *master = flash->spi->master;
>>   	struct spi_transfer t[2];
>>   	struct spi_message m;
>>   	uint8_t opcode;
>> @@ -523,6 +525,20 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>   	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
>>   			__func__, (u32)from, len);
>>
>> +	if (master->mmap) {
>> +		mutex_lock(&flash->lock);
>> +		/* Wait till previous write/erase is done. */
>> +		if (wait_till_ready(flash)) {
>> +			mutex_unlock(&flash->lock);
>> +			return 1;
>> +		}
>> +		flash->mem_addr = master->get_buf(master);
>> +		memcpy(buf, flash->mem_addr + from, len);
>> +		master->put_buf(master);
>> +		*retlen = len;
>> +		goto out;
>> +	}
>> +
>>   	spi_message_init(&m);
>>   	memset(t, 0, (sizeof t));
>>
>> @@ -558,6 +574,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
>>
>>   	*retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
>>
>> +out:
>>   	mutex_unlock(&flash->lock);
>>
>>   	return 0;
>> @@ -1286,6 +1303,9 @@ static int m25p_probe(struct spi_device *spi)
>>   		flash->addr_width = 3;
>>   	}
>>
>> +	if (spi->master->configure_from_slave)
>> +		m25p80_fill_flash_information(flash);
>> +
> You have add a configure_from_slave hook in the SPI, why you also need
> a same hook in the SPI-NOR framework?
>
We need a way to provoke this, currently it is placed in m25p80. If m25p80
is removed, for where should I handle these in nor framework?
> And i think the enable_mmap/disable_mmap is not needed too.
>
> All the three hooks are used to set the SPI bus controller.

> And the SPI-NOR framework only handles the issues between the
> SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
> SPI-NOR.
My controller can be used as spi flash controller as well as a spi
controller.
> thanks
> Huang Shijie
>
>

Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Huang Shijie]

On Thu, Dec 12, 2013 at 01:45:24PM +0530, Sourav Poddar wrote:
> On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
> >>
> >>+	if (spi->master->configure_from_slave)
> >>+		m25p80_fill_flash_information(flash);
> >>+
> >You have add a configure_from_slave hook in the SPI, why you also need
> >a same hook in the SPI-NOR framework?
> >
> We need a way to provoke this, currently it is placed in m25p80. If m25p80
> is removed, for where should I handle these in nor framework?

The m25p80 is not removed. it is easy to move your code in the
m25p_read.

Please read the patch 4.

> >And i think the enable_mmap/disable_mmap is not needed too.
> >
> >All the three hooks are used to set the SPI bus controller.
> 
> >And the SPI-NOR framework only handles the issues between the
> >SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
> >SPI-NOR.
> My controller can be used as spi flash controller as well as a spi
> controller.
> 
If you really think we need to do something before the do the real work.
we can add two hooks : prepare/unprepare.

   for you, you can put the the enable_mmap/disable_mmap in the
   prepare/unprepare separately.

   for other driver, we can put the enable/disable clocks in the
   prepare/unprepare hooks.

thanks
Huang Shijie 
   

Re: [PATCHv2 07/10] drivers: mtd: m25p80: Adapt driver to support memory mapped read.

[Huang Shijie]

On Thu, Dec 12, 2013 at 01:45:24PM +0530, Sourav Poddar wrote:
> On Thursday 12 December 2013 01:25 PM, Huang Shijie wrote:
> >>
> >>+	if (spi->master->configure_from_slave)
> >>+		m25p80_fill_flash_information(flash);
> >>+
> >You have add a configure_from_slave hook in the SPI, why you also need
> >a same hook in the SPI-NOR framework?
> >
> We need a way to provoke this, currently it is placed in m25p80. If m25p80
> is removed, for where should I handle these in nor framework?

The m25p80 is not removed. it is easy to move your code in the
m25p_read.

Please read the patch 4.

> >And i think the enable_mmap/disable_mmap is not needed too.
> >
> >All the three hooks are used to set the SPI bus controller.
> 
> >And the SPI-NOR framework only handles the issues between the
> >SPI bus controller and the SPI-NOR, or the SPI-NOR controller and the
> >SPI-NOR.
> My controller can be used as spi flash controller as well as a spi
> controller.
> 
If you really think we need to do something before the do the real work.
we can add two hooks : prepare/unprepare.

   for you, you can put the the enable_mmap/disable_mmap in the
   prepare/unprepare separately.

   for other driver, we can put the enable/disable clocks in the
   prepare/unprepare hooks.

thanks
Huang Shijie 
   

Re: [PATCHv2 01/10] spi/spi.h: Add get_buf/put_buf support in spi master.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 358 bytes --]

On Fri, Dec 06, 2013 at 07:54:42PM +0530, Sourav Poddar wrote:
> Add get_buf, put_buf api support in spi master.

Please add this stuff along with the code implementing it.

> +	void	(*configure_from_slave)(struct spi_device *spi);
> +

I don't understand this API at all - it takes no parameters and doesn't
have a possibility of returning any error codes?

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Re: [PATCHv2 01/10] spi/spi.h: Add get_buf/put_buf support in spi master.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 358 bytes --]

On Fri, Dec 06, 2013 at 07:54:42PM +0530, Sourav Poddar wrote:
> Add get_buf, put_buf api support in spi master.

Please add this stuff along with the code implementing it.

> +	void	(*configure_from_slave)(struct spi_device *spi);
> +

I don't understand this API at all - it takes no parameters and doesn't
have a possibility of returning any error codes?

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Re: [PATCHv2 02/10] spi/qspi: parse register by name.

[Mark Brown]

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On Fri, Dec 06, 2013 at 07:54:43PM +0530, Sourav Poddar wrote:
> Modify the qspi driver to parse reg information by name.
> If "reg names" is not found, then revert back to normal
> get resource.

Applied, thanks.

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Re: [PATCHv2 02/10] spi/qspi: parse register by name.

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 214 bytes --]

On Fri, Dec 06, 2013 at 07:54:43PM +0530, Sourav Poddar wrote:
> Modify the qspi driver to parse reg information by name.
> If "reg names" is not found, then revert back to normal
> get resource.

Applied, thanks.

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Re: [PATCHv2 08/10] Documentation: bindings: ti-qspi: update binding information.

[Mark Brown]

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On Fri, Dec 06, 2013 at 07:54:49PM +0530, Sourav Poddar wrote:
> These update binding information for ti qspi controller.

Applied, thanks.

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http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCHv2 08/10] Documentation: bindings: ti-qspi: update binding information.

[Mark Brown]

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On Fri, Dec 06, 2013 at 07:54:49PM +0530, Sourav Poddar wrote:
> These update binding information for ti qspi controller.

Applied, thanks.

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