* [PATCH v7 00/14] support subsets of scalar crypto extension
@ 2022-02-28 14:47 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v7
To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
or
"zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true" to enable K-extension support. This implementation can pass the ACT tests
for K with our extended act support for qemu (available at
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v7-with-act)
v7:
* simplify trans_* functions by using gen_arith* and gen_unary
* replace DEF_HELPER_* with DEF_HEPER_FLAG_*
* move aes64 related macros from patch 6 to patch 7
* create common helper gen_aes32_sm4 for aes32 and sm4 related instructions
* replace bs with shamt (bs << 3)
* modify trans function for sha256, sha512 and sm4 instructions to be generated inline
* add reviewed-by tags and rebase on riscv-to-apply.next
v6:
* add reviewed-by tags
* rebase on upstream
v5:
* split the big patches
v4:
* drop "x-" in exposed properties
* delete unrelated changes
v3:
* add extension check for SEED csr access
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei Li (14):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add support for zbkb extension
target/riscv: rvk: add support for zbkc extension
target/riscv: rvk: add support for zbkx extension
crypto: move sm4_sbox from target/arm
target/riscv: rvk: add support for zknd/zkne extension in RV32
target/riscv: rvk: add support for zkne/zknd extension in RV64
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
target/riscv: rvk: add support for sha512 related instructions for
RV32 in zknh extension
target/riscv: rvk: add support for sha512 related instructions for
RV64 in zknh extension
target/riscv: rvk: add support for zksed/zksh extension
target/riscv: rvk: add CSR support for Zkr
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: expose zbk* and zk* properties
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++++
disas/riscv.c | 170 +++++++++++++
include/crypto/sm4.h | 6 +
target/arm/crypto_helper.c | 36 +--
target/riscv/bitmanip_helper.c | 80 +++++++
target/riscv/cpu.c | 36 +++
target/riscv/cpu.h | 13 +
target/riscv/cpu_bits.h | 9 +
target/riscv/crypto_helper.c | 302 +++++++++++++++++++++++
target/riscv/csr.c | 64 +++++
target/riscv/helper.h | 22 ++
target/riscv/insn32.decode | 97 ++++++--
target/riscv/insn_trans/trans_rvb.c.inc | 116 +++++++--
target/riscv/insn_trans/trans_rvk.c.inc | 304 ++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/pmp.h | 8 +-
target/riscv/translate.c | 8 +
18 files changed, 1254 insertions(+), 70 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v7 00/14] support subsets of scalar crypto extension
@ 2022-02-28 14:47 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
This patchset implements RISC-V scalar crypto extension v1.0.0 version instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v7
To test rvk implementation, specify cpu argument with 'zks=true,zkn=true'
or
"zbkb=true,zbkc=true,zbkx=true,zknd=true,zkne=true,zknh=true,zksed=true,zksh=true,zkr=true" to enable K-extension support. This implementation can pass the ACT tests
for K with our extended act support for qemu (available at
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v7-with-act)
v7:
* simplify trans_* functions by using gen_arith* and gen_unary
* replace DEF_HELPER_* with DEF_HEPER_FLAG_*
* move aes64 related macros from patch 6 to patch 7
* create common helper gen_aes32_sm4 for aes32 and sm4 related instructions
* replace bs with shamt (bs << 3)
* modify trans function for sha256, sha512 and sm4 instructions to be generated inline
* add reviewed-by tags and rebase on riscv-to-apply.next
v6:
* add reviewed-by tags
* rebase on upstream
v5:
* split the big patches
v4:
* drop "x-" in exposed properties
* delete unrelated changes
v3:
* add extension check for SEED csr access
v2:
* optimize implementation for brev8, xperm, zip, unzip
* use aes related sbox array from crypto/aes.h
* move sm4_sbox to crypto/sm4.c, and share it with target/arm
Weiwei Li (14):
target/riscv: rvk: add cfg properties for zbk* and zk*
target/riscv: rvk: add support for zbkb extension
target/riscv: rvk: add support for zbkc extension
target/riscv: rvk: add support for zbkx extension
crypto: move sm4_sbox from target/arm
target/riscv: rvk: add support for zknd/zkne extension in RV32
target/riscv: rvk: add support for zkne/zknd extension in RV64
target/riscv: rvk: add support for sha256 related instructions in zknh
extension
target/riscv: rvk: add support for sha512 related instructions for
RV32 in zknh extension
target/riscv: rvk: add support for sha512 related instructions for
RV64 in zknh extension
target/riscv: rvk: add support for zksed/zksh extension
target/riscv: rvk: add CSR support for Zkr
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
target/riscv: rvk: expose zbk* and zk* properties
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++++
disas/riscv.c | 170 +++++++++++++
include/crypto/sm4.h | 6 +
target/arm/crypto_helper.c | 36 +--
target/riscv/bitmanip_helper.c | 80 +++++++
target/riscv/cpu.c | 36 +++
target/riscv/cpu.h | 13 +
target/riscv/cpu_bits.h | 9 +
target/riscv/crypto_helper.c | 302 +++++++++++++++++++++++
target/riscv/csr.c | 64 +++++
target/riscv/helper.h | 22 ++
target/riscv/insn32.decode | 97 ++++++--
target/riscv/insn_trans/trans_rvb.c.inc | 116 +++++++--
target/riscv/insn_trans/trans_rvk.c.inc | 304 ++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/pmp.h | 8 +-
target/riscv/translate.c | 8 +
18 files changed, 1254 insertions(+), 70 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
--
2.17.1
^ permalink raw reply [flat|nested] 58+ messages in thread
* [PATCH v7 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:47 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 13 +++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..9e8bbce6f1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -592,6 +592,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_zfinx = true;
}
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zkr = true;
+ cpu->cfg.ext_zkt = true;
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zkne = true;
+ cpu->cfg.ext_zknd = true;
+ cpu->cfg.ext_zknh = true;
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zksed = true;
+ cpu->cfg.ext_zksh = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9ba05042ed..ef4de326f2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -355,7 +355,20 @@ struct RISCVCPUConfig {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
bool ext_zbs;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
@ 2022-02-28 14:47 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 23 +++++++++++++++++++++++
target/riscv/cpu.h | 13 +++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..9e8bbce6f1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -592,6 +592,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_zfinx = true;
}
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zkr = true;
+ cpu->cfg.ext_zkt = true;
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zkne = true;
+ cpu->cfg.ext_zknd = true;
+ cpu->cfg.ext_zknh = true;
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zksed = true;
+ cpu->cfg.ext_zksh = true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9ba05042ed..ef4de326f2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -355,7 +355,20 @@ struct RISCVCPUConfig {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
bool ext_zbs;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:47 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/bitmanip_helper.c | 53 ++++++++++++++
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 45 +++++++-----
target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
target/riscv/translate.c | 7 ++
5 files changed, 174 insertions(+), 28 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index f1b5e5549f..e003e8b25b 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -49,3 +49,56 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
return result;
}
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+target_ulong HELPER(brev8)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+
+ x = do_swap(x, 0x5555555555555555ull, 1);
+ x = do_swap(x, 0x3333333333333333ull, 2);
+ x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
+ return x;
+}
+
+static const uint64_t shuf_masks[] = {
+ dup_const(MO_8, 0x44),
+ dup_const(MO_8, 0x30),
+ dup_const(MO_16, 0x0f00),
+ dup_const(MO_32, 0xff0000)
+};
+
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
+ uint64_t maskR, int shift)
+{
+ target_ulong x = src & ~(maskL | maskR);
+
+ x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
+ return x;
+}
+
+target_ulong HELPER(unzip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ return x;
+}
+
+target_ulong HELPER(zip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ return x;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 26bbab2fab..7331d32dbf 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,9 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1d3ff1efe1..fdceaf621a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
slli_uw 00001 ............ 001 ..... 0011011 @sh
-# *** RV32 Zbb Standard Extension ***
+# *** RV32 Zbb/Zbkb Standard Extension ***
andn 0100000 .......... 111 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rori 01100 ............ 101 ..... 0010011 @sh
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+ zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+ pack 0000100 ..... ..... 100 ..... 0110011 @r
+}
+xnor 0100000 .......... 100 ..... 0110011 @r
+# *** RV32 extra Zbb Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
@@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
-# The encoding for rev8 differs between RV32 and RV64.
-# rev8_32 denotes the RV32 variant.
-rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
-rol 0110000 .......... 001 ..... 0110011 @r
-ror 0110000 .......... 101 ..... 0110011 @r
-rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
-xnor 0100000 .......... 100 ..... 0110011 @r
-# The encoding for zext.h differs between RV32 and RV64.
-# zext_h_32 denotes the RV32 variant.
-zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+# *** RV32 extra Zbkb Standard Extension ***
+brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
+packh 0000100 .......... 111 ..... 0110011 @r
+unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
+zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
-# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
# The encoding for rev8 differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
@@ -755,7 +761,14 @@ rorw 0110000 .......... 101 ..... 0111011 @r
# The encoding for zext.h differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
-zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+{
+ zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+ packw 0000100 ..... ..... 100 ..... 0111011 @r
+}
+# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index e3c6b459d6..a6b733d5ff 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zb[abcs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -42,6 +42,12 @@
} \
} while (0)
+#define REQUIRE_ZBKB(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zbkb) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -85,19 +91,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_eqv_tl);
}
@@ -247,7 +253,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
}
@@ -264,7 +270,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_rotri_tl, gen_roriw, NULL);
}
@@ -289,7 +295,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
}
@@ -301,14 +307,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
@@ -403,7 +409,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
}
@@ -411,7 +417,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
}
@@ -419,7 +425,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
}
@@ -504,3 +510,67 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
}
+
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
+{
+ tcg_gen_deposit_tl(ret, src1, src2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_ext8u_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_ext16s_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
+ tcg_temp_free(t);
+}
+
+static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
+}
+
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
+}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
+}
+
+static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
+}
+
+static bool trans_zip(DisasContext *ctx, arg_zip *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fac998a6b5..9afb8a01e7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -688,6 +688,13 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
+ if (!ctx->cfg_ptr->ext_##A && \
+ !ctx->cfg_ptr->ext_##B) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension
@ 2022-02-28 14:47 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/bitmanip_helper.c | 53 ++++++++++++++
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 45 +++++++-----
target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
target/riscv/translate.c | 7 ++
5 files changed, 174 insertions(+), 28 deletions(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index f1b5e5549f..e003e8b25b 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -49,3 +49,56 @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
return result;
}
+
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
+{
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
+}
+
+target_ulong HELPER(brev8)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+
+ x = do_swap(x, 0x5555555555555555ull, 1);
+ x = do_swap(x, 0x3333333333333333ull, 2);
+ x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
+ return x;
+}
+
+static const uint64_t shuf_masks[] = {
+ dup_const(MO_8, 0x44),
+ dup_const(MO_8, 0x30),
+ dup_const(MO_16, 0x0f00),
+ dup_const(MO_32, 0xff0000)
+};
+
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
+ uint64_t maskR, int shift)
+{
+ target_ulong x = src & ~(maskL | maskR);
+
+ x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
+ return x;
+}
+
+target_ulong HELPER(unzip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ return x;
+}
+
+target_ulong HELPER(zip)(target_ulong rs1)
+{
+ target_ulong x = rs1;
+
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
+ return x;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 26bbab2fab..7331d32dbf 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,9 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
/* Bitmanip */
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1d3ff1efe1..fdceaf621a 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -717,8 +717,22 @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
slli_uw 00001 ............ 001 ..... 0011011 @sh
-# *** RV32 Zbb Standard Extension ***
+# *** RV32 Zbb/Zbkb Standard Extension ***
andn 0100000 .......... 111 ..... 0110011 @r
+rol 0110000 .......... 001 ..... 0110011 @r
+ror 0110000 .......... 101 ..... 0110011 @r
+rori 01100 ............ 101 ..... 0010011 @sh
+# The encoding for rev8 differs between RV32 and RV64.
+# rev8_32 denotes the RV32 variant.
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
+# The encoding for zext.h differs between RV32 and RV64.
+# zext_h_32 denotes the RV32 variant.
+{
+ zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+ pack 0000100 ..... ..... 100 ..... 0110011 @r
+}
+xnor 0100000 .......... 100 ..... 0110011 @r
+# *** RV32 extra Zbb Standard Extension ***
clz 011000 000000 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
@@ -728,23 +742,15 @@ min 0000101 .......... 100 ..... 0110011 @r
minu 0000101 .......... 101 ..... 0110011 @r
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
orn 0100000 .......... 110 ..... 0110011 @r
-# The encoding for rev8 differs between RV32 and RV64.
-# rev8_32 denotes the RV32 variant.
-rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
-rol 0110000 .......... 001 ..... 0110011 @r
-ror 0110000 .......... 101 ..... 0110011 @r
-rori 01100 ............ 101 ..... 0010011 @sh
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
-xnor 0100000 .......... 100 ..... 0110011 @r
-# The encoding for zext.h differs between RV32 and RV64.
-# zext_h_32 denotes the RV32 variant.
-zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
+# *** RV32 extra Zbkb Standard Extension ***
+brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
+packh 0000100 .......... 111 ..... 0110011 @r
+unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
+zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
-# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
# The encoding for rev8 differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
@@ -755,7 +761,14 @@ rorw 0110000 .......... 101 ..... 0111011 @r
# The encoding for zext.h differs between RV32 and RV64.
# When executing on RV64, the encoding used in RV32 is an illegal
# instruction, so we use different handler functions to differentiate.
-zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+{
+ zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
+ packw 0000100 ..... ..... 100 ..... 0111011 @r
+}
+# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
# *** RV32 Zbc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index e3c6b459d6..a6b733d5ff 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the Zb[abcs] Standard Extension.
+ * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
@@ -42,6 +42,12 @@
} \
} while (0)
+#define REQUIRE_ZBKB(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zbkb) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -85,19 +91,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_logic(ctx, a, tcg_gen_eqv_tl);
}
@@ -247,7 +253,7 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
}
@@ -264,7 +270,7 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
tcg_gen_rotri_tl, gen_roriw, NULL);
}
@@ -289,7 +295,7 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
}
@@ -301,14 +307,14 @@ static void gen_rev8_32(TCGv ret, TCGv src1)
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
}
@@ -403,7 +409,7 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
}
@@ -411,7 +417,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
}
@@ -419,7 +425,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
{
REQUIRE_64BIT(ctx);
- REQUIRE_ZBB(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
ctx->ol = MXL_RV32;
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
}
@@ -504,3 +510,67 @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
REQUIRE_ZBC(ctx);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
}
+
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
+{
+ tcg_gen_deposit_tl(ret, src1, src2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_ext8u_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
+{
+ TCGv t = tcg_temp_new();
+
+ tcg_gen_ext16s_tl(t, src2);
+ tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
+ tcg_temp_free(t);
+}
+
+static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
+}
+
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
+}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
+}
+
+static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
+}
+
+static bool trans_zip(DisasContext *ctx, arg_zip *a)
+{
+ REQUIRE_32BIT(ctx);
+ REQUIRE_ZBKB(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fac998a6b5..9afb8a01e7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -688,6 +688,13 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
+ if (!ctx->cfg_ptr->ext_##A && \
+ !ctx->cfg_ptr->ext_##B) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:47 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fdceaf621a..3a49acab37 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -770,9 +770,10 @@ clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
-# *** RV32 Zbc Standard Extension ***
+# *** RV32 Zbc/Zbkc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
+# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
# *** RV32 Zbs Standard Extension ***
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index a6b733d5ff..1980bfe971 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -489,7 +489,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
}
@@ -501,7 +501,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension
@ 2022-02-28 14:47 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:47 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fdceaf621a..3a49acab37 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -770,9 +770,10 @@ clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
-# *** RV32 Zbc Standard Extension ***
+# *** RV32 Zbc/Zbkc Standard Extension ***
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
+# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
# *** RV32 Zbs Standard Extension ***
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index a6b733d5ff..1980bfe971 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -489,7 +489,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
}
@@ -501,7 +501,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
{
- REQUIRE_ZBC(ctx);
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 04/14] target/riscv: rvk: add support for zbkx extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 18 +++++++++++++++++
4 files changed, 51 insertions(+)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e003e8b25b..b99c4a39a1 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -102,3 +102,30 @@ target_ulong HELPER(zip)(target_ulong rs1)
x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
return x;
}
+
+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
+ uint32_t sz_log2)
+{
+ target_ulong r = 0;
+ target_ulong sz = 1LL << sz_log2;
+ target_ulong mask = (1LL << sz) - 1;
+ target_ulong pos;
+
+ for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
+ pos = ((rs2 >> i) & mask) << sz_log2;
+ if (pos < sizeof(target_ulong) * 8) {
+ r |= ((rs1 >> pos) & mask) << i;
+ }
+ }
+ return r;
+}
+
+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 2);
+}
+
+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 3);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7331d32dbf..a1d28b257f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -69,6 +69,8 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3a49acab37..75ffac9c81 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -776,6 +776,10 @@ clmulh 0000101 .......... 011 ..... 0110011 @r
# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
+# *** RV32 Zbkx Standard Extension ***
+xperm4 0010100 .......... 010 ..... 0110011 @r
+xperm8 0010100 .......... 100 ..... 0110011 @r
+
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 1980bfe971..54927ba763 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -48,6 +48,12 @@
} \
} while (0)
+#define REQUIRE_ZBKX(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zbkx) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -574,3 +580,15 @@ static bool trans_zip(DisasContext *ctx, arg_zip *a)
REQUIRE_ZBKB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
}
+
+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
+}
+
+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 04/14] target/riscv: rvk: add support for zbkx extension
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++++++
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 18 +++++++++++++++++
4 files changed, 51 insertions(+)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e003e8b25b..b99c4a39a1 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -102,3 +102,30 @@ target_ulong HELPER(zip)(target_ulong rs1)
x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
return x;
}
+
+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
+ uint32_t sz_log2)
+{
+ target_ulong r = 0;
+ target_ulong sz = 1LL << sz_log2;
+ target_ulong mask = (1LL << sz) - 1;
+ target_ulong pos;
+
+ for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
+ pos = ((rs2 >> i) & mask) << sz_log2;
+ if (pos < sizeof(target_ulong) * 8) {
+ r |= ((rs1 >> pos) & mask) << i;
+ }
+ }
+ return r;
+}
+
+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 2);
+}
+
+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
+{
+ return do_xperm(rs1, rs2, 3);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7331d32dbf..a1d28b257f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -69,6 +69,8 @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Floating Point - Half Precision */
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3a49acab37..75ffac9c81 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -776,6 +776,10 @@ clmulh 0000101 .......... 011 ..... 0110011 @r
# *** RV32 extra Zbc Standard Extension ***
clmulr 0000101 .......... 010 ..... 0110011 @r
+# *** RV32 Zbkx Standard Extension ***
+xperm4 0010100 .......... 010 ..... 0110011 @r
+xperm8 0010100 .......... 100 ..... 0110011 @r
+
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .......... 001 ..... 0110011 @r
bclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 1980bfe971..54927ba763 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -48,6 +48,12 @@
} \
} while (0)
+#define REQUIRE_ZBKX(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zbkx) { \
+ return false; \
+ } \
+} while (0)
+
static void gen_clz(TCGv ret, TCGv arg1)
{
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
@@ -574,3 +580,15 @@ static bool trans_zip(DisasContext *ctx, arg_zip *a)
REQUIRE_ZBKB(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
}
+
+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
+}
+
+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
+{
+ REQUIRE_ZBKX(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 05/14] crypto: move sm4_sbox from target/arm
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
include/crypto/sm4.h | 6 +++++
target/arm/crypto_helper.c | 36 +---------------------------
4 files changed, 57 insertions(+), 35 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
diff --git a/crypto/meson.build b/crypto/meson.build
index 19c44bea89..b47352180f 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -40,6 +40,7 @@ if have_afalg
endif
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
+util_ss.add(files('sm4.c'))
util_ss.add(files('aes.c'))
util_ss.add(files('init.c'))
if gnutls.found()
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index 0000000000..9f0cd452c7
--- /dev/null
+++ b/crypto/sm4.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+ 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+ 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+ 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+ 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+ 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+ 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+ 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+ 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+ 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+ 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+ 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+ 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+ 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+ 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+ 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+ 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+ 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+ 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+ 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+ 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+ 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+ 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+ 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+ 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+ 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+ 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+ 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+ 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+ 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+ 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+ 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+ 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 0000000000..9bd3ebc62e
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 28a84c2dbd..390020672a 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -15,6 +15,7 @@
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "crypto/aes.h"
+#include "crypto/sm4.h"
#include "vec_internal.h"
union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
#undef DO_SM3TT
-static uint8_t const sm4_sbox[] = {
- 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
- 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
- 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
- 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
- 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
- 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
- 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
- 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
- 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
- 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
- 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
- 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
- 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
- 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
- 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
- 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
- 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
- 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
- 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
- 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
- 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
- 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
- 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
- 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
- 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
- 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
- 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
- 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
- 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
- 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
- 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
- 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
-};
-
static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
{
union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 05/14] crypto: move sm4_sbox from target/arm
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
include/crypto/sm4.h | 6 +++++
target/arm/crypto_helper.c | 36 +---------------------------
4 files changed, 57 insertions(+), 35 deletions(-)
create mode 100644 crypto/sm4.c
create mode 100644 include/crypto/sm4.h
diff --git a/crypto/meson.build b/crypto/meson.build
index 19c44bea89..b47352180f 100644
--- a/crypto/meson.build
+++ b/crypto/meson.build
@@ -40,6 +40,7 @@ if have_afalg
endif
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
+util_ss.add(files('sm4.c'))
util_ss.add(files('aes.c'))
util_ss.add(files('init.c'))
if gnutls.found()
diff --git a/crypto/sm4.c b/crypto/sm4.c
new file mode 100644
index 0000000000..9f0cd452c7
--- /dev/null
+++ b/crypto/sm4.c
@@ -0,0 +1,49 @@
+/*
+ * QEMU crypto sm4 support
+ *
+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "crypto/sm4.h"
+
+uint8_t const sm4_sbox[] = {
+ 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
+ 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
+ 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
+ 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
+ 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
+ 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
+ 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
+ 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
+ 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
+ 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
+ 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
+ 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
+ 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
+ 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
+ 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
+ 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
+ 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
+ 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
+ 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
+ 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
+ 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
+ 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
+ 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
+ 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
+ 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
+ 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
+ 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
+ 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
+ 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
+ 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
+ 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
+ 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
+};
+
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
new file mode 100644
index 0000000000..9bd3ebc62e
--- /dev/null
+++ b/include/crypto/sm4.h
@@ -0,0 +1,6 @@
+#ifndef QEMU_SM4_H
+#define QEMU_SM4_H
+
+extern const uint8_t sm4_sbox[256];
+
+#endif
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
index 28a84c2dbd..390020672a 100644
--- a/target/arm/crypto_helper.c
+++ b/target/arm/crypto_helper.c
@@ -15,6 +15,7 @@
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "crypto/aes.h"
+#include "crypto/sm4.h"
#include "vec_internal.h"
union CRYPTO_STATE {
@@ -694,41 +695,6 @@ DO_SM3TT(crypto_sm3tt2b, 3)
#undef DO_SM3TT
-static uint8_t const sm4_sbox[] = {
- 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
- 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
- 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
- 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
- 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
- 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
- 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
- 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
- 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
- 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
- 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
- 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
- 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
- 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
- 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
- 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
- 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
- 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
- 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
- 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
- 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
- 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
- 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
- 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
- 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
- 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
- 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
- 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
- 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
- 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
- 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
- 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
-};
-
static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
{
union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 105 ++++++++++++++++++++++++
target/riscv/helper.h | 6 ++
target/riscv/insn32.decode | 11 +++
target/riscv/insn_trans/trans_rvk.c.inc | 67 +++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/translate.c | 1 +
6 files changed, 192 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
new file mode 100644
index 0000000000..220d51c742
--- /dev/null
+++ b/target/riscv/crypto_helper.c
@@ -0,0 +1,105 @@
+/*
+ * RISC-V Crypto Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "crypto/aes.h"
+#include "crypto/sm4.h"
+
+#define AES_XTIME(a) \
+ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a, b) (( \
+ (((b) & 0x1) ? (a) : 0) ^ \
+ (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+ (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+ (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+{
+ uint32_t u;
+
+ if (fwd) {
+ u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
+ (AES_GFMUL(x, 2) << 0);
+ } else {
+ u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
+ (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
+ }
+ return u;
+}
+
+#define sext32_xlen(x) (target_ulong)(int32_t)(x)
+
+static inline target_ulong aes32_operation(target_ulong shamt,
+ target_ulong rs1, target_ulong rs2,
+ bool enc, bool mix)
+{
+ uint8_t si = rs2 >> shamt;
+ uint8_t so;
+ uint32_t mixed;
+ target_ulong res;
+
+ if (enc) {
+ so = AES_sbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, true);
+ } else {
+ mixed = so;
+ }
+ } else {
+ so = AES_isbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, false);
+ } else {
+ mixed = so;
+ }
+ }
+ mixed = rol32(mixed, shamt);
+ res = rs1 ^ mixed;
+
+ return sext32_xlen(res);
+}
+
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, false, false);
+}
+#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a1d28b257f..d31bfadb3e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1115,3 +1115,9 @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
+
+/* Crypto functions */
+DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 75ffac9c81..0f2e661583 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,6 +35,7 @@
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
+%imm_bs 30:2 !function=ex_shift_3
# Argument sets:
&empty
@@ -52,6 +53,7 @@
&rmr vm rd rs2
&r2nfvm vm rd rs1 nf
&rnfvm vm rd rs1 rs2 nf
+&k_aes shamt rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@@ -89,6 +91,8 @@
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
+
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@@ -834,3 +838,10 @@ sfence_w_inval 0001100 00000 00000 000 00000 1110011
sfence_inval_ir 0001100 00001 00000 000 00000 1110011
hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
+
+# *** RV32 Zknd Standard Extension ***
+aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
+aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV32 Zkne Standard Extension ***
+aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
+aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
new file mode 100644
index 0000000000..04eb806a89
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -0,0 +1,67 @@
+/*
+ * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZKND(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zknd) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKNE(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zkne) { \
+ return false; \
+ } \
+} while (0)
+
+static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
+ void (*func)(TCGv, TCGv, TCGv, TCGv))
+{
+ TCGv shamt = tcg_const_tl(a->shamt);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ func(dest, src1, src2, shamt);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32esmi);
+}
+
+static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32esi);
+}
+
+static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32dsmi);
+}
+
+static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 91f0ac32ff..ef320c9e32 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -19,7 +19,8 @@ riscv_ss.add(files(
'vector_helper.c',
'bitmanip_helper.c',
'translate.c',
- 'm128_helper.c'
+ 'm128_helper.c',
+ 'crypto_helper.c'
))
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9afb8a01e7..8be63ae972 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1007,6 +1007,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
+#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 105 ++++++++++++++++++++++++
target/riscv/helper.h | 6 ++
target/riscv/insn32.decode | 11 +++
target/riscv/insn_trans/trans_rvk.c.inc | 67 +++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/translate.c | 1 +
6 files changed, 192 insertions(+), 1 deletion(-)
create mode 100644 target/riscv/crypto_helper.c
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
new file mode 100644
index 0000000000..220d51c742
--- /dev/null
+++ b/target/riscv/crypto_helper.c
@@ -0,0 +1,105 @@
+/*
+ * RISC-V Crypto Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+#include "crypto/aes.h"
+#include "crypto/sm4.h"
+
+#define AES_XTIME(a) \
+ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
+
+#define AES_GFMUL(a, b) (( \
+ (((b) & 0x1) ? (a) : 0) ^ \
+ (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
+ (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
+ (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
+
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
+{
+ uint32_t u;
+
+ if (fwd) {
+ u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
+ (AES_GFMUL(x, 2) << 0);
+ } else {
+ u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
+ (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
+ }
+ return u;
+}
+
+#define sext32_xlen(x) (target_ulong)(int32_t)(x)
+
+static inline target_ulong aes32_operation(target_ulong shamt,
+ target_ulong rs1, target_ulong rs2,
+ bool enc, bool mix)
+{
+ uint8_t si = rs2 >> shamt;
+ uint8_t so;
+ uint32_t mixed;
+ target_ulong res;
+
+ if (enc) {
+ so = AES_sbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, true);
+ } else {
+ mixed = so;
+ }
+ } else {
+ so = AES_isbox[si];
+ if (mix) {
+ mixed = aes_mixcolumn_byte(so, false);
+ } else {
+ mixed = so;
+ }
+ }
+ mixed = rol32(mixed, shamt);
+ res = rs1 ^ mixed;
+
+ return sext32_xlen(res);
+}
+
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ return aes32_operation(shamt, rs1, rs2, false, false);
+}
+#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a1d28b257f..d31bfadb3e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1115,3 +1115,9 @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
+
+/* Crypto functions */
+DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 75ffac9c81..0f2e661583 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -35,6 +35,7 @@
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
+%imm_bs 30:2 !function=ex_shift_3
# Argument sets:
&empty
@@ -52,6 +53,7 @@
&rmr vm rd rs2
&r2nfvm vm rd rs1 nf
&rnfvm vm rd rs1 rs2 nf
+&k_aes shamt rs2 rs1 rd
# Formats 32:
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@@ -89,6 +91,8 @@
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
+@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
+
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@@ -834,3 +838,10 @@ sfence_w_inval 0001100 00000 00000 000 00000 1110011
sfence_inval_ir 0001100 00001 00000 000 00000 1110011
hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
+
+# *** RV32 Zknd Standard Extension ***
+aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
+aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV32 Zkne Standard Extension ***
+aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
+aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
new file mode 100644
index 0000000000..04eb806a89
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -0,0 +1,67 @@
+/*
+ * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
+ *
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZKND(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zknd) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKNE(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zkne) { \
+ return false; \
+ } \
+} while (0)
+
+static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
+ void (*func)(TCGv, TCGv, TCGv, TCGv))
+{
+ TCGv shamt = tcg_const_tl(a->shamt);
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+ func(dest, src1, src2, shamt);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32esmi);
+}
+
+static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32esi);
+}
+
+static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32dsmi);
+}
+
+static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 91f0ac32ff..ef320c9e32 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -19,7 +19,8 @@ riscv_ss.add(files(
'vector_helper.c',
'bitmanip_helper.c',
'translate.c',
- 'm128_helper.c'
+ 'm128_helper.c',
+ 'crypto_helper.c'
))
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9afb8a01e7..8be63ae972 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1007,6 +1007,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
#include "insn_trans/trans_rvzfh.c.inc"
+#include "insn_trans/trans_rvk.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_svinval.c.inc"
#include "insn_trans/trans_xventanacondops.c.inc"
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 169 ++++++++++++++++++++++++
target/riscv/helper.h | 8 ++
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvk.c.inc | 47 +++++++
4 files changed, 236 insertions(+)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 220d51c742..cb4783a1e9 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -102,4 +102,173 @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
{
return aes32_operation(shamt, rs1, rs2, false, false);
}
+
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+ (((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS1 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
+ (((RS2 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS1 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS1 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS2 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
+ BY(COL, B3) ^ BY(COL, B2) ^ AES_GFMUL(BY(COL, B1), 3) ^ \
+ AES_GFMUL(BY(COL, B0), 2))
+
+#define AES_MIXCOLUMN(COL) ( \
+ AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | AES_MIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
+ AES_GFMUL(BY(COL, B3), 0x9) ^ AES_GFMUL(BY(COL, B2), 0xd) ^ \
+ AES_GFMUL(BY(COL, B1), 0xb) ^ AES_GFMUL(BY(COL, B0), 0xe))
+
+#define AES_INVMIXCOLUMN(COL) ( \
+ AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+ AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+ bool enc, bool mix)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint64_t result;
+ uint64_t temp;
+ uint32_t col_0;
+ uint32_t col_1;
+
+ if (enc) {
+ temp = AES_SHIFROWS_LO(RS1, RS2);
+ temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32;
+
+ col_0 = AES_MIXCOLUMN(col_0);
+ col_1 = AES_MIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ } else {
+ temp = AES_INVSHIFROWS_LO(RS1, RS2);
+ temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ }
+
+ return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint32_t rs1_hi = RS1 >> 32;
+ uint32_t rs2_lo = RS2;
+ uint32_t rs2_hi = RS2 >> 32;
+
+ uint32_t r_lo = (rs1_hi ^ rs2_lo);
+ uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi);
+ target_ulong result = ((uint64_t)r_hi << 32) | r_lo;
+
+ return result;
+}
+
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
+{
+ uint64_t RS1 = rs1;
+ static const uint8_t round_consts[10] = {
+ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+ };
+
+ uint8_t enc_rnum = rnum;
+ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
+ uint8_t rcon_ = 0;
+ target_ulong result;
+
+ if (enc_rnum != 0xA) {
+ temp = ror32(temp, 8); /* Rotate right by 8 */
+ rcon_ = round_consts[enc_rnum];
+ }
+
+ temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
+
+ temp ^= rcon_;
+
+ result = ((uint64_t)temp << 32) | temp;
+
+ return result;
+}
+
+target_ulong HELPER(aes64im)(target_ulong rs1)
+{
+ uint64_t RS1 = rs1;
+ uint32_t col_0 = RS1 & 0xFFFFFFFF;
+ uint32_t col_1 = RS1 >> 32;
+ target_ulong result;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+
+ return result;
+}
#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d31bfadb3e..0df0a05b11 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1121,3 +1121,11 @@ DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+
+DEF_HELPER_FLAGS_2(aes64esm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64es, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ds, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0f2e661583..0b800b4093 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,6 +36,7 @@
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
%imm_bs 30:2 !function=ex_shift_3
+%imm_rnum 20:4
# Argument sets:
&empty
@@ -92,6 +93,7 @@
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
+@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@@ -842,6 +844,16 @@ hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
# *** RV32 Zknd Standard Extension ***
aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zknd Standard Extension ***
+aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
+aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
+aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
# *** RV32 Zkne Standard Extension ***
aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zkne Standard Extension ***
+aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
+aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zkne/zknd Standard Extension ***
+aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
+aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 04eb806a89..e315462e5a 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -65,3 +65,50 @@ static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
REQUIRE_ZKND(ctx);
return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
}
+
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64es, NULL);
+}
+
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64esm, NULL);
+}
+
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ds, NULL);
+}
+
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64dsm, NULL);
+}
+
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ks2, NULL);
+}
+
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+ if (a->imm > 0xA) {
+ return false;
+ }
+
+ return gen_arith_imm_tl(ctx, a, EXT_NONE, gen_helper_aes64ks1i, NULL);
+}
+
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 169 ++++++++++++++++++++++++
target/riscv/helper.h | 8 ++
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvk.c.inc | 47 +++++++
4 files changed, 236 insertions(+)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 220d51c742..cb4783a1e9 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -102,4 +102,173 @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
{
return aes32_operation(shamt, rs1, rs2, false, false);
}
+
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
+
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+ (((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS1 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
+ (((RS2 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+ (((RS1 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+ (((RS1 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+ (((RS2 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
+
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
+ BY(COL, B3) ^ BY(COL, B2) ^ AES_GFMUL(BY(COL, B1), 3) ^ \
+ AES_GFMUL(BY(COL, B0), 2))
+
+#define AES_MIXCOLUMN(COL) ( \
+ AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | AES_MIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
+ AES_GFMUL(BY(COL, B3), 0x9) ^ AES_GFMUL(BY(COL, B2), 0xd) ^ \
+ AES_GFMUL(BY(COL, B1), 0xb) ^ AES_GFMUL(BY(COL, B0), 0xe))
+
+#define AES_INVMIXCOLUMN(COL) ( \
+ AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
+ AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
+ AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
+ AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+ bool enc, bool mix)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint64_t result;
+ uint64_t temp;
+ uint32_t col_0;
+ uint32_t col_1;
+
+ if (enc) {
+ temp = AES_SHIFROWS_LO(RS1, RS2);
+ temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32;
+
+ col_0 = AES_MIXCOLUMN(col_0);
+ col_1 = AES_MIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ } else {
+ temp = AES_INVSHIFROWS_LO(RS1, RS2);
+ temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+ ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+ ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+ ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+ ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
+ if (mix) {
+ col_0 = temp & 0xFFFFFFFF;
+ col_1 = temp >> 32;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+ } else {
+ result = temp;
+ }
+ }
+
+ return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+ return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+ uint64_t RS1 = rs1;
+ uint64_t RS2 = rs2;
+ uint32_t rs1_hi = RS1 >> 32;
+ uint32_t rs2_lo = RS2;
+ uint32_t rs2_hi = RS2 >> 32;
+
+ uint32_t r_lo = (rs1_hi ^ rs2_lo);
+ uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi);
+ target_ulong result = ((uint64_t)r_hi << 32) | r_lo;
+
+ return result;
+}
+
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
+{
+ uint64_t RS1 = rs1;
+ static const uint8_t round_consts[10] = {
+ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+ };
+
+ uint8_t enc_rnum = rnum;
+ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
+ uint8_t rcon_ = 0;
+ target_ulong result;
+
+ if (enc_rnum != 0xA) {
+ temp = ror32(temp, 8); /* Rotate right by 8 */
+ rcon_ = round_consts[enc_rnum];
+ }
+
+ temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+ ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+ ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+ ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
+
+ temp ^= rcon_;
+
+ result = ((uint64_t)temp << 32) | temp;
+
+ return result;
+}
+
+target_ulong HELPER(aes64im)(target_ulong rs1)
+{
+ uint64_t RS1 = rs1;
+ uint32_t col_0 = RS1 & 0xFFFFFFFF;
+ uint32_t col_1 = RS1 >> 32;
+ target_ulong result;
+
+ col_0 = AES_INVMIXCOLUMN(col_0);
+ col_1 = AES_INVMIXCOLUMN(col_1);
+
+ result = ((uint64_t)col_1 << 32) | col_0;
+
+ return result;
+}
#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d31bfadb3e..0df0a05b11 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1121,3 +1121,11 @@ DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+
+DEF_HELPER_FLAGS_2(aes64esm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64es, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ds, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0f2e661583..0b800b4093 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -36,6 +36,7 @@
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
%imm_u 12:s20 !function=ex_shift_12
%imm_bs 30:2 !function=ex_shift_3
+%imm_rnum 20:4
# Argument sets:
&empty
@@ -92,6 +93,7 @@
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
+@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
@@ -842,6 +844,16 @@ hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
# *** RV32 Zknd Standard Extension ***
aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zknd Standard Extension ***
+aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
+aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
+aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
# *** RV32 Zkne Standard Extension ***
aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zkne Standard Extension ***
+aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
+aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zkne/zknd Standard Extension ***
+aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
+aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 04eb806a89..e315462e5a 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -65,3 +65,50 @@ static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
REQUIRE_ZKND(ctx);
return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
}
+
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64es, NULL);
+}
+
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
+{
+ REQUIRE_ZKNE(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64esm, NULL);
+}
+
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ds, NULL);
+}
+
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64dsm, NULL);
+}
+
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ks2, NULL);
+}
+
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
+{
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+ if (a->imm > 0xA) {
+ return false;
+ }
+
+ return gen_arith_imm_tl(ctx, a, EXT_NONE, gen_helper_aes64ks1i, NULL);
+}
+
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+{
+ REQUIRE_ZKND(ctx);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn32.decode | 5 ++++
target/riscv/insn_trans/trans_rvk.c.inc | 37 +++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0b800b4093..db28ecdd2b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -857,3 +857,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
# *** RV64 Zkne/zknd Standard Extension ***
aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
+# *** RV32 Zknh Standard Extension ***
+sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
+sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
+sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
+sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index e315462e5a..02a3261675 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -29,6 +29,12 @@
} \
} while (0)
+#define REQUIRE_ZKNH(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zknh) { \
+ return false; \
+ } \
+} while (0)
+
static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
void (*func)(TCGv, TCGv, TCGv, TCGv))
{
@@ -112,3 +118,34 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
REQUIRE_ZKND(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
}
+
+#define GEN_SHA256(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1) \
+{ \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ TCGv_i32 t1 = tcg_temp_new_i32(); \
+ TCGv_i32 t2 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, src1); \
+ tcg_gen_rotri_i32(t1, t0, NUM1); \
+ tcg_gen_rotri_i32(t2, t0, NUM2); \
+ tcg_gen_xor_i32(t1, t1, t2); \
+ tcg_gen_##OP##_i32(t2, t0, NUM3); \
+ tcg_gen_xor_i32(t1, t1, t2); \
+ tcg_gen_ext_i32_tl(dest, t1); \
+ \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_i32(t1); \
+ tcg_temp_free_i32(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_ZKNH(ctx); \
+ return gen_unary(ctx, a, EXT_NONE, gen_##NAME); \
+}
+
+GEN_SHA256(sha256sig0, shri, 7, 18, 3)
+GEN_SHA256(sha256sig1, shri, 17, 19, 10)
+GEN_SHA256(sha256sum0, rotri, 2, 13, 22)
+GEN_SHA256(sha256sum1, rotri, 6, 11, 25)
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn32.decode | 5 ++++
target/riscv/insn_trans/trans_rvk.c.inc | 37 +++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0b800b4093..db28ecdd2b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -857,3 +857,8 @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
# *** RV64 Zkne/zknd Standard Extension ***
aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
+# *** RV32 Zknh Standard Extension ***
+sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
+sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
+sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
+sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index e315462e5a..02a3261675 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -29,6 +29,12 @@
} \
} while (0)
+#define REQUIRE_ZKNH(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zknh) { \
+ return false; \
+ } \
+} while (0)
+
static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
void (*func)(TCGv, TCGv, TCGv, TCGv))
{
@@ -112,3 +118,34 @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
REQUIRE_ZKND(ctx);
return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
}
+
+#define GEN_SHA256(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1) \
+{ \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ TCGv_i32 t1 = tcg_temp_new_i32(); \
+ TCGv_i32 t2 = tcg_temp_new_i32(); \
+ \
+ tcg_gen_trunc_tl_i32(t0, src1); \
+ tcg_gen_rotri_i32(t1, t0, NUM1); \
+ tcg_gen_rotri_i32(t2, t0, NUM2); \
+ tcg_gen_xor_i32(t1, t1, t2); \
+ tcg_gen_##OP##_i32(t2, t0, NUM3); \
+ tcg_gen_xor_i32(t1, t1, t2); \
+ tcg_gen_ext_i32_tl(dest, t1); \
+ \
+ tcg_temp_free_i32(t0); \
+ tcg_temp_free_i32(t1); \
+ tcg_temp_free_i32(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_ZKNH(ctx); \
+ return gen_unary(ctx, a, EXT_NONE, gen_##NAME); \
+}
+
+GEN_SHA256(sha256sig0, shri, 7, 18, 3)
+GEN_SHA256(sha256sig1, shri, 17, 19, 10)
+GEN_SHA256(sha256sum0, rotri, 2, 13, 22)
+GEN_SHA256(sha256sum1, rotri, 6, 11, 25)
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvk.c.inc | 63 +++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index db28ecdd2b..02a0c71890 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -862,3 +862,9 @@ sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 02a3261675..f1dccc13c8 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -149,3 +149,66 @@ GEN_SHA256(sha256sig0, shri, 7, 18, 3)
GEN_SHA256(sha256sig1, shri, 17, 19, 10)
GEN_SHA256(sha256sum0, rotri, 2, 13, 22)
GEN_SHA256(sha256sum1, rotri, 6, 11, 25)
+
+#define GEN_SHA512_RV32(NAME, OP1, NUM1, OP2, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64 t2 = tcg_temp_new_i64(); \
+ \
+ tcg_gen_concat_tl_i64(t0, src1, src2); \
+ tcg_gen_##OP1##_i64(t1, t0, NUM1); \
+ tcg_gen_##OP2##_i64(t2, t0, NUM2); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_rotri_i64(t2, t0, NUM3); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_trunc_i64_tl(dest, t1); \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_32BIT(ctx); \
+ REQUIRE_ZKNH(ctx); \
+ return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \
+}
+
+GEN_SHA512_RV32(sha512sum0r, rotli, 25, rotli, 30, 28)
+GEN_SHA512_RV32(sha512sum1r, rotli, 23, rotri, 14, 18)
+GEN_SHA512_RV32(sha512sig0l, rotri, 1, rotri, 7, 8)
+GEN_SHA512_RV32(sha512sig1l, rotli, 3, rotri, 6, 19)
+
+#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64 t2 = tcg_temp_new_i64(); \
+ \
+ tcg_gen_concat_tl_i64(t0, src1, src2); \
+ tcg_gen_##OP##_i64(t1, t0, NUM1); \
+ tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
+ tcg_gen_shri_i64(t2, t2, NUM2); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_rotri_i64(t2, t0, NUM3); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_trunc_i64_tl(dest, t1); \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_32BIT(ctx); \
+ REQUIRE_ZKNH(ctx); \
+ return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \
+}
+
+GEN_SHA512H_RV32(sha512sig0h, rotri, 1, 7, 8)
+GEN_SHA512H_RV32(sha512sig1h, rotli, 3, 6, 19)
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvk.c.inc | 63 +++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index db28ecdd2b..02a0c71890 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -862,3 +862,9 @@ sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 02a3261675..f1dccc13c8 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -149,3 +149,66 @@ GEN_SHA256(sha256sig0, shri, 7, 18, 3)
GEN_SHA256(sha256sig1, shri, 17, 19, 10)
GEN_SHA256(sha256sum0, rotri, 2, 13, 22)
GEN_SHA256(sha256sum1, rotri, 6, 11, 25)
+
+#define GEN_SHA512_RV32(NAME, OP1, NUM1, OP2, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64 t2 = tcg_temp_new_i64(); \
+ \
+ tcg_gen_concat_tl_i64(t0, src1, src2); \
+ tcg_gen_##OP1##_i64(t1, t0, NUM1); \
+ tcg_gen_##OP2##_i64(t2, t0, NUM2); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_rotri_i64(t2, t0, NUM3); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_trunc_i64_tl(dest, t1); \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_32BIT(ctx); \
+ REQUIRE_ZKNH(ctx); \
+ return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \
+}
+
+GEN_SHA512_RV32(sha512sum0r, rotli, 25, rotli, 30, 28)
+GEN_SHA512_RV32(sha512sum1r, rotli, 23, rotri, 14, 18)
+GEN_SHA512_RV32(sha512sig0l, rotri, 1, rotri, 7, 8)
+GEN_SHA512_RV32(sha512sig1l, rotli, 3, rotri, 6, 19)
+
+#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64 t2 = tcg_temp_new_i64(); \
+ \
+ tcg_gen_concat_tl_i64(t0, src1, src2); \
+ tcg_gen_##OP##_i64(t1, t0, NUM1); \
+ tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
+ tcg_gen_shri_i64(t2, t2, NUM2); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_rotri_i64(t2, t0, NUM3); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_trunc_i64_tl(dest, t1); \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_32BIT(ctx); \
+ REQUIRE_ZKNH(ctx); \
+ return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \
+}
+
+GEN_SHA512H_RV32(sha512sig0h, rotri, 1, 7, 8)
+GEN_SHA512H_RV32(sha512sig1h, rotli, 3, 6, 19)
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn32.decode | 5 ++++
target/riscv/insn_trans/trans_rvk.c.inc | 32 +++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 02a0c71890..d9ebb138d1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -868,3 +868,8 @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zknh Standard Extension ***
+sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
+sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
+sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
+sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index f1dccc13c8..3fe2d32e19 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -212,3 +212,35 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
GEN_SHA512H_RV32(sha512sig0h, rotri, 1, 7, 8)
GEN_SHA512H_RV32(sha512sig1h, rotli, 3, 6, 19)
+
+#define GEN_SHA512_RV64(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64 t2 = tcg_temp_new_i64(); \
+ \
+ tcg_gen_extu_tl_i64(t0, src1); \
+ tcg_gen_rotri_i64(t1, t0, NUM1); \
+ tcg_gen_rotri_i64(t2, t0, NUM2); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_##OP##_i64(t2, t0, NUM3); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_trunc_i64_tl(dest, t1); \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_64BIT(ctx); \
+ REQUIRE_ZKNH(ctx); \
+ return gen_unary(ctx, a, EXT_NONE, gen_##NAME); \
+}
+
+GEN_SHA512_RV64(sha512sig0, shri, 1, 8, 7)
+GEN_SHA512_RV64(sha512sig1, shri, 19, 61, 6)
+GEN_SHA512_RV64(sha512sum0, rotri, 28, 34, 39)
+GEN_SHA512_RV64(sha512sum1, rotri, 14, 18, 41)
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn32.decode | 5 ++++
target/riscv/insn_trans/trans_rvk.c.inc | 32 +++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 02a0c71890..d9ebb138d1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -868,3 +868,8 @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zknh Standard Extension ***
+sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
+sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
+sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
+sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index f1dccc13c8..3fe2d32e19 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -212,3 +212,35 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
GEN_SHA512H_RV32(sha512sig0h, rotri, 1, 7, 8)
GEN_SHA512H_RV32(sha512sig1h, rotli, 3, 6, 19)
+
+#define GEN_SHA512_RV64(NAME, OP, NUM1, NUM2, NUM3) \
+static void gen_##NAME(TCGv dest, TCGv src1) \
+{ \
+ TCGv_i64 t0 = tcg_temp_new_i64(); \
+ TCGv_i64 t1 = tcg_temp_new_i64(); \
+ TCGv_i64 t2 = tcg_temp_new_i64(); \
+ \
+ tcg_gen_extu_tl_i64(t0, src1); \
+ tcg_gen_rotri_i64(t1, t0, NUM1); \
+ tcg_gen_rotri_i64(t2, t0, NUM2); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_##OP##_i64(t2, t0, NUM3); \
+ tcg_gen_xor_i64(t1, t1, t2); \
+ tcg_gen_trunc_i64_tl(dest, t1); \
+ \
+ tcg_temp_free_i64(t0); \
+ tcg_temp_free_i64(t1); \
+ tcg_temp_free_i64(t2); \
+} \
+\
+static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+{ \
+ REQUIRE_64BIT(ctx); \
+ REQUIRE_ZKNH(ctx); \
+ return gen_unary(ctx, a, EXT_NONE, gen_##NAME); \
+}
+
+GEN_SHA512_RV64(sha512sig0, shri, 1, 8, 7)
+GEN_SHA512_RV64(sha512sig1, shri, 19, 61, 6)
+GEN_SHA512_RV64(sha512sum0, rotri, 28, 34, 39)
+GEN_SHA512_RV64(sha512sum1, rotri, 14, 18, 41)
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 28 ++++++++++++
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
4 files changed, 95 insertions(+)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index cb4783a1e9..2ef30281b1 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -271,4 +271,32 @@ target_ulong HELPER(aes64im)(target_ulong rs1)
return result;
}
+
+target_ulong HELPER(sm4ed)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ uint32_t sb_in = (uint8_t)(rs2 >> shamt);
+ uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
+
+ uint32_t x = sb_out ^ (sb_out << 8) ^ (sb_out << 2) ^ (sb_out << 18) ^
+ ((sb_out & 0x3f) << 26) ^ ((sb_out & 0xC0) << 10);
+
+ uint32_t rotl = rol32(x, shamt);
+
+ return sext32_xlen(rotl ^ (uint32_t)rs1);
+}
+
+target_ulong HELPER(sm4ks)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ uint32_t sb_in = (uint8_t)(rs2 >> shamt);
+ uint32_t sb_out = sm4_sbox[sb_in];
+
+ uint32_t x = sb_out ^ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
+ ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13);
+
+ uint32_t rotl = rol32(x, shamt);
+
+ return sext32_xlen(rotl ^ (uint32_t)rs1);
+}
#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0df0a05b11..863e0edd84 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1129,3 +1129,6 @@ DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
+
+DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d9ebb138d1..4033565393 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -873,3 +873,9 @@ sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksh Standard Extension ***
+sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
+sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksed Standard Extension ***
+sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
+sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 3fe2d32e19..f6a331918a 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -35,6 +35,18 @@
} \
} while (0)
+#define REQUIRE_ZKSED(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zksed) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKSH(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zksh) { \
+ return false; \
+ } \
+} while (0)
+
static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
void (*func)(TCGv, TCGv, TCGv, TCGv))
{
@@ -244,3 +256,49 @@ GEN_SHA512_RV64(sha512sig0, shri, 1, 8, 7)
GEN_SHA512_RV64(sha512sig1, shri, 19, 61, 6)
GEN_SHA512_RV64(sha512sum0, rotri, 28, 34, 39)
GEN_SHA512_RV64(sha512sum1, rotri, 14, 18, 41)
+
+/* SM3 */
+static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32_t b, int32_t c)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t0, src1);
+ tcg_gen_rotli_i32(t1, t0, b);
+ tcg_gen_xor_i32(t1, t0, t1);
+ tcg_gen_rotli_i32(t0, t0, c);
+ tcg_gen_xor_i32(t1, t1, t0);
+ tcg_gen_ext_i32_tl(dest, t1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ return true;
+}
+
+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
+{
+ REQUIRE_ZKSH(ctx);
+ return gen_sm3(ctx, a, 9, 17);
+}
+
+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
+{
+ REQUIRE_ZKSH(ctx);
+ return gen_sm3(ctx, a, 15, 23);
+}
+
+/* SM4 */
+static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
+{
+ REQUIRE_ZKSED(ctx);
+ return gen_aes32_sm4(ctx, a , gen_helper_sm4ed);
+}
+
+static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
+{
+ REQUIRE_ZKSED(ctx);
+ return gen_aes32_sm4(ctx, a , gen_helper_sm4ks);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/crypto_helper.c | 28 ++++++++++++
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
4 files changed, 95 insertions(+)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index cb4783a1e9..2ef30281b1 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -271,4 +271,32 @@ target_ulong HELPER(aes64im)(target_ulong rs1)
return result;
}
+
+target_ulong HELPER(sm4ed)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ uint32_t sb_in = (uint8_t)(rs2 >> shamt);
+ uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
+
+ uint32_t x = sb_out ^ (sb_out << 8) ^ (sb_out << 2) ^ (sb_out << 18) ^
+ ((sb_out & 0x3f) << 26) ^ ((sb_out & 0xC0) << 10);
+
+ uint32_t rotl = rol32(x, shamt);
+
+ return sext32_xlen(rotl ^ (uint32_t)rs1);
+}
+
+target_ulong HELPER(sm4ks)(target_ulong rs1, target_ulong rs2,
+ target_ulong shamt)
+{
+ uint32_t sb_in = (uint8_t)(rs2 >> shamt);
+ uint32_t sb_out = sm4_sbox[sb_in];
+
+ uint32_t x = sb_out ^ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
+ ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13);
+
+ uint32_t rotl = rol32(x, shamt);
+
+ return sext32_xlen(rotl ^ (uint32_t)rs1);
+}
#undef sext32_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 0df0a05b11..863e0edd84 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1129,3 +1129,6 @@ DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
+
+DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
+DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d9ebb138d1..4033565393 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -873,3 +873,9 @@ sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksh Standard Extension ***
+sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
+sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
+# *** RV32 Zksed Standard Extension ***
+sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
+sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index 3fe2d32e19..f6a331918a 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -35,6 +35,18 @@
} \
} while (0)
+#define REQUIRE_ZKSED(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zksed) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_ZKSH(ctx) do { \
+ if (!ctx->cfg_ptr->ext_zksh) { \
+ return false; \
+ } \
+} while (0)
+
static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
void (*func)(TCGv, TCGv, TCGv, TCGv))
{
@@ -244,3 +256,49 @@ GEN_SHA512_RV64(sha512sig0, shri, 1, 8, 7)
GEN_SHA512_RV64(sha512sig1, shri, 19, 61, 6)
GEN_SHA512_RV64(sha512sum0, rotri, 28, 34, 39)
GEN_SHA512_RV64(sha512sum1, rotri, 14, 18, 41)
+
+/* SM3 */
+static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32_t b, int32_t c)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t0, src1);
+ tcg_gen_rotli_i32(t1, t0, b);
+ tcg_gen_xor_i32(t1, t0, t1);
+ tcg_gen_rotli_i32(t0, t0, c);
+ tcg_gen_xor_i32(t1, t1, t0);
+ tcg_gen_ext_i32_tl(dest, t1);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ return true;
+}
+
+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
+{
+ REQUIRE_ZKSH(ctx);
+ return gen_sm3(ctx, a, 9, 17);
+}
+
+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
+{
+ REQUIRE_ZKSH(ctx);
+ return gen_sm3(ctx, a, 15, 23);
+}
+
+/* SM4 */
+static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
+{
+ REQUIRE_ZKSED(ctx);
+ return gen_aes32_sm4(ctx, a , gen_helper_sm4ed);
+}
+
+static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
+{
+ REQUIRE_ZKSED(ctx);
+ return gen_aes32_sm4(ctx, a , gen_helper_sm4ks);
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu_bits.h | 9 ++++++
target/riscv/csr.c | 64 +++++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.h | 8 ++++--
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 0fe01d7da5..d0a4a16c73 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -446,6 +446,9 @@
#define CSR_VSPMMASK 0x2c1
#define CSR_VSPMBASE 0x2c2
+/* Crypto Extension */
+#define CSR_SEED 0x015
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -760,4 +763,10 @@ typedef enum RISCVException {
#define HVICTL_VALID_MASK \
(HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
+/* seed CSR bits */
+#define SEED_OPST (0b11 << 30)
+#define SEED_OPST_BIST (0b00 << 30)
+#define SEED_OPST_WAIT (0b01 << 30)
+#define SEED_OPST_ES16 (0b10 << 30)
+#define SEED_OPST_DEAD (0b11 << 30)
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aea82dff4a..784fb6894d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -23,6 +23,8 @@
#include "cpu.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -291,6 +293,39 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
}
#endif
+/* Predicates */
+static RISCVException seed(CPURISCVState *env, int csrno)
+{
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_zkr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#if !defined(CONFIG_USER_ONLY)
+ if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
+ /* Hypervisor extension is supported */
+ if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
+ if (env->mseccfg & MSECCFG_SSEED) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+ }
+ if (env->priv == PRV_M) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
+ return RISCV_EXCP_NONE;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#else
+ return RISCV_EXCP_NONE;
+#endif
+}
+
/* User Floating-Point CSRs */
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -2861,6 +2896,32 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
#endif
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ if (!write_mask) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ uint32_t return_status = SEED_OPST_ES16;
+
+ *ret_value = return_status;
+ if (return_status == SEED_OPST_ES16) {
+ uint16_t random_number;
+ qemu_guest_getrandom_nofail(&random_number, sizeof(random_number));
+ *ret_value = (*ret_value) | random_number;
+ } else if (return_status == SEED_OPST_BIST) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_WAIT) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_DEAD) {
+ /* Do nothing */
+ }
+ return RISCV_EXCP_NONE;
+}
+
/*
* riscv_csrrw - read and/or update control and status register
*
@@ -3087,6 +3148,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TIME] = { "time", ctr, read_time },
[CSR_TIMEH] = { "timeh", ctr32, read_timeh },
+ /* Crypto Extension */
+ [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed},
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_instret },
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index a9a0b363a7..83135849bb 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -37,9 +37,11 @@ typedef enum {
} pmp_am_t;
typedef enum {
- MSECCFG_MML = 1 << 0,
- MSECCFG_MMWP = 1 << 1,
- MSECCFG_RLB = 1 << 2
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2,
+ MSECCFG_USEED = 1 << 8,
+ MSECCFG_SSEED = 1 << 9
} mseccfg_field_t;
typedef struct {
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu_bits.h | 9 ++++++
target/riscv/csr.c | 64 +++++++++++++++++++++++++++++++++++++++++
target/riscv/pmp.h | 8 ++++--
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 0fe01d7da5..d0a4a16c73 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -446,6 +446,9 @@
#define CSR_VSPMMASK 0x2c1
#define CSR_VSPMBASE 0x2c2
+/* Crypto Extension */
+#define CSR_SEED 0x015
+
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
@@ -760,4 +763,10 @@ typedef enum RISCVException {
#define HVICTL_VALID_MASK \
(HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
+/* seed CSR bits */
+#define SEED_OPST (0b11 << 30)
+#define SEED_OPST_BIST (0b00 << 30)
+#define SEED_OPST_WAIT (0b01 << 30)
+#define SEED_OPST_ES16 (0b10 << 30)
+#define SEED_OPST_DEAD (0b11 << 30)
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aea82dff4a..784fb6894d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -23,6 +23,8 @@
#include "cpu.h"
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
@@ -291,6 +293,39 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
}
#endif
+/* Predicates */
+static RISCVException seed(CPURISCVState *env, int csrno)
+{
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!cpu->cfg.ext_zkr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#if !defined(CONFIG_USER_ONLY)
+ if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) {
+ /* Hypervisor extension is supported */
+ if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) {
+ if (env->mseccfg & MSECCFG_SSEED) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+ }
+ if (env->priv == PRV_M) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
+ return RISCV_EXCP_NONE;
+ } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
+ return RISCV_EXCP_NONE;
+ } else {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#else
+ return RISCV_EXCP_NONE;
+#endif
+}
+
/* User Floating-Point CSRs */
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -2861,6 +2896,32 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
#endif
+/* Crypto Extension */
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ if (!write_mask) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ uint32_t return_status = SEED_OPST_ES16;
+
+ *ret_value = return_status;
+ if (return_status == SEED_OPST_ES16) {
+ uint16_t random_number;
+ qemu_guest_getrandom_nofail(&random_number, sizeof(random_number));
+ *ret_value = (*ret_value) | random_number;
+ } else if (return_status == SEED_OPST_BIST) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_WAIT) {
+ /* Do nothing */
+ } else if (return_status == SEED_OPST_DEAD) {
+ /* Do nothing */
+ }
+ return RISCV_EXCP_NONE;
+}
+
/*
* riscv_csrrw - read and/or update control and status register
*
@@ -3087,6 +3148,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TIME] = { "time", ctr, read_time },
[CSR_TIMEH] = { "timeh", ctr32, read_timeh },
+ /* Crypto Extension */
+ [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed},
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_instret },
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index a9a0b363a7..83135849bb 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -37,9 +37,11 @@ typedef enum {
} pmp_am_t;
typedef enum {
- MSECCFG_MML = 1 << 0,
- MSECCFG_MMWP = 1 << 1,
- MSECCFG_RLB = 1 << 2
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2,
+ MSECCFG_USEED = 1 << 8,
+ MSECCFG_SSEED = 1 << 9
} mseccfg_field_t;
typedef struct {
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
disas/riscv.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -156,6 +156,8 @@ typedef enum {
rv_codec_css_swsp,
rv_codec_css_sdsp,
rv_codec_css_sqsp,
+ rv_codec_k_bs,
+ rv_codec_k_rnum,
} rv_codec;
typedef enum {
@@ -521,6 +523,43 @@ typedef enum {
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
+ rv_op_aes32esmi = 362,
+ rv_op_aes32esi = 363,
+ rv_op_aes32dsmi = 364,
+ rv_op_aes32dsi = 365,
+ rv_op_aes64ks1i = 366,
+ rv_op_aes64ks2 = 367,
+ rv_op_aes64im = 368,
+ rv_op_aes64esm = 369,
+ rv_op_aes64es = 370,
+ rv_op_aes64dsm = 371,
+ rv_op_aes64ds = 372,
+ rv_op_sha256sig0 = 373,
+ rv_op_sha256sig1 = 374,
+ rv_op_sha256sum0 = 375,
+ rv_op_sha256sum1 = 376,
+ rv_op_sha512sig0 = 377,
+ rv_op_sha512sig1 = 378,
+ rv_op_sha512sum0 = 379,
+ rv_op_sha512sum1 = 380,
+ rv_op_sha512sum0r = 381,
+ rv_op_sha512sum1r = 382,
+ rv_op_sha512sig0l = 383,
+ rv_op_sha512sig0h = 384,
+ rv_op_sha512sig1l = 385,
+ rv_op_sha512sig1h = 386,
+ rv_op_sm3p0 = 387,
+ rv_op_sm3p1 = 388,
+ rv_op_sm4ed = 389,
+ rv_op_sm4ks = 390,
+ rv_op_brev8 = 391,
+ rv_op_pack = 392,
+ rv_op_packh = 393,
+ rv_op_packw = 394,
+ rv_op_unzip = 395,
+ rv_op_zip = 396,
+ rv_op_xperm4 = 397,
+ rv_op_xperm8 = 398,
} rv_op;
/* structures */
@@ -540,6 +579,8 @@ typedef struct {
uint8_t succ;
uint8_t aq;
uint8_t rl;
+ uint8_t bs;
+ uint8_t rnum;
} rv_decode;
typedef struct {
@@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
#define rv_fmt_rd_rs2 "O\t0,2"
#define rv_fmt_rs1_offset "O\t1,o"
#define rv_fmt_rs2_offset "O\t2,o"
+#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
+#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
/* pseudo-instruction constraints */
@@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
{ rv_op_illegal, NULL }
};
+
static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
@@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
+ { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
};
/* CSR names */
@@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
+ case 0x0015: return "seed";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_zip; break;
+ }
+ break;
+ case 0b00010:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_sha256sum0; break;
+ case 0b0000001: op = rv_op_sha256sum1; break;
+ case 0b0000010: op = rv_op_sha256sig0; break;
+ case 0b0000011: op = rv_op_sha256sig1; break;
+ case 0b0000100: op = rv_op_sha512sum0; break;
+ case 0b0000101: op = rv_op_sha512sum1; break;
+ case 0b0000110: op = rv_op_sha512sig0; break;
+ case 0b0000111: op = rv_op_sha512sig1; break;
+ case 0b0001000: op = rv_op_sm3p0; break;
+ case 0b0001001: op = rv_op_sm3p1; break;
+ }
+ break;
case 0b00101: op = rv_op_bseti; break;
+ case 0b00110:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_aes64im; break;
+ default:
+ if (((inst >> 24) & 0x111) == 0b001) {
+ op = rv_op_aes64ks1i;
+ }
+ break;
+ }
+ break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
@@ -1615,6 +1726,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_unzip; break;
+ }
+ break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
@@ -1622,6 +1738,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0111000: op = rv_op_rev8; break;
+ case 0b0000111: op = rv_op_brev8; break;
}
break;
}
@@ -1742,8 +1859,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_pack; break;
}
break;
+ case 39: op = rv_op_packh; break;
+
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
@@ -1755,6 +1875,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
+ case 162: op = rv_op_xperm4; break;
+ case 164: op = rv_op_xperm8; break;
+ case 200: op = rv_op_aes64es; break;
+ case 216: op = rv_op_aes64esm; break;
+ case 232: op = rv_op_aes64ds; break;
+ case 248: op = rv_op_aes64dsm; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
@@ -1762,9 +1888,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
+ case 320: op = rv_op_sha512sum0r; break;
+ case 328: op = rv_op_sha512sum1r; break;
+ case 336: op = rv_op_sha512sig0l; break;
+ case 344: op = rv_op_sha512sig1l; break;
+ case 368: op = rv_op_sha512sig0h; break;
+ case 376: op = rv_op_sha512sig1h; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
+ case 504: op = rv_op_aes64ks2; break;
+ }
+ switch ((inst >> 25) & 0b0011111) {
+ case 17: op = rv_op_aes32esi; break;
+ case 19: op = rv_op_aes32esmi; break;
+ case 21: op = rv_op_aes32dsi; break;
+ case 23: op = rv_op_aes32esmi; break;
+ case 24: op = rv_op_sm4ed; break;
+ case 26: op = rv_op_sm4ks; break;
}
break;
case 13: op = rv_op_lui; break;
@@ -1782,6 +1923,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_packw; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
@@ -2374,6 +2516,16 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}
+static uint32_t operand_bs(rv_inst inst)
+{
+ return (inst << 32) >> 62;
+}
+
+static uint32_t operand_rnum(rv_inst inst)
+{
+ return (inst << 40) >> 60;
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec)
@@ -2653,6 +2805,16 @@ static void decode_inst_operands(rv_decode *dec)
dec->rs2 = operand_crs2(inst);
dec->imm = operand_cimmsqsp(inst);
break;
+ case rv_codec_k_bs:
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->bs = operand_bs(inst);
+ break;
+ case rv_codec_k_rnum:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rnum = operand_rnum(inst);
+ break;
};
}
@@ -2812,6 +2974,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
+ case 'b':
+ snprintf(tmp, sizeof(tmp), "%d", dec->bs);
+ append(buf, tmp, buflen);
+ break;
+ case 'n':
+ snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
+ append(buf, tmp, buflen);
+ break;
case '0':
append(buf, rv_ireg_name_sym[dec->rd], buflen);
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
disas/riscv.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -156,6 +156,8 @@ typedef enum {
rv_codec_css_swsp,
rv_codec_css_sdsp,
rv_codec_css_sqsp,
+ rv_codec_k_bs,
+ rv_codec_k_rnum,
} rv_codec;
typedef enum {
@@ -521,6 +523,43 @@ typedef enum {
rv_op_bclr = 359,
rv_op_binv = 360,
rv_op_bext = 361,
+ rv_op_aes32esmi = 362,
+ rv_op_aes32esi = 363,
+ rv_op_aes32dsmi = 364,
+ rv_op_aes32dsi = 365,
+ rv_op_aes64ks1i = 366,
+ rv_op_aes64ks2 = 367,
+ rv_op_aes64im = 368,
+ rv_op_aes64esm = 369,
+ rv_op_aes64es = 370,
+ rv_op_aes64dsm = 371,
+ rv_op_aes64ds = 372,
+ rv_op_sha256sig0 = 373,
+ rv_op_sha256sig1 = 374,
+ rv_op_sha256sum0 = 375,
+ rv_op_sha256sum1 = 376,
+ rv_op_sha512sig0 = 377,
+ rv_op_sha512sig1 = 378,
+ rv_op_sha512sum0 = 379,
+ rv_op_sha512sum1 = 380,
+ rv_op_sha512sum0r = 381,
+ rv_op_sha512sum1r = 382,
+ rv_op_sha512sig0l = 383,
+ rv_op_sha512sig0h = 384,
+ rv_op_sha512sig1l = 385,
+ rv_op_sha512sig1h = 386,
+ rv_op_sm3p0 = 387,
+ rv_op_sm3p1 = 388,
+ rv_op_sm4ed = 389,
+ rv_op_sm4ks = 390,
+ rv_op_brev8 = 391,
+ rv_op_pack = 392,
+ rv_op_packh = 393,
+ rv_op_packw = 394,
+ rv_op_unzip = 395,
+ rv_op_zip = 396,
+ rv_op_xperm4 = 397,
+ rv_op_xperm8 = 398,
} rv_op;
/* structures */
@@ -540,6 +579,8 @@ typedef struct {
uint8_t succ;
uint8_t aq;
uint8_t rl;
+ uint8_t bs;
+ uint8_t rnum;
} rv_decode;
typedef struct {
@@ -615,6 +656,8 @@ static const char rv_freg_name_sym[32][5] = {
#define rv_fmt_rd_rs2 "O\t0,2"
#define rv_fmt_rs1_offset "O\t1,o"
#define rv_fmt_rs2_offset "O\t2,o"
+#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
+#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
/* pseudo-instruction constraints */
@@ -766,6 +809,7 @@ static const rv_comp_data rvcp_csrrw[] = {
{ rv_op_illegal, NULL }
};
+
static const rv_comp_data rvcp_csrrs[] = {
{ rv_op_rdcycle, rvcc_rdcycle },
{ rv_op_rdtime, rvcc_rdtime },
@@ -1203,6 +1247,43 @@ const rv_opcode_data opcode_data[] = {
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
+ { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+ { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
+ { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
};
/* CSR names */
@@ -1216,6 +1297,7 @@ static const char *csr_name(int csrno)
case 0x0003: return "fcsr";
case 0x0004: return "uie";
case 0x0005: return "utvec";
+ case 0x0015: return "seed";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
@@ -1594,7 +1676,36 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_zip; break;
+ }
+ break;
+ case 0b00010:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_sha256sum0; break;
+ case 0b0000001: op = rv_op_sha256sum1; break;
+ case 0b0000010: op = rv_op_sha256sig0; break;
+ case 0b0000011: op = rv_op_sha256sig1; break;
+ case 0b0000100: op = rv_op_sha512sum0; break;
+ case 0b0000101: op = rv_op_sha512sum1; break;
+ case 0b0000110: op = rv_op_sha512sig0; break;
+ case 0b0000111: op = rv_op_sha512sig1; break;
+ case 0b0001000: op = rv_op_sm3p0; break;
+ case 0b0001001: op = rv_op_sm3p1; break;
+ }
+ break;
case 0b00101: op = rv_op_bseti; break;
+ case 0b00110:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0000000: op = rv_op_aes64im; break;
+ default:
+ if (((inst >> 24) & 0x111) == 0b001) {
+ op = rv_op_aes64ks1i;
+ }
+ break;
+ }
+ break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
@@ -1615,6 +1726,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
+ case 0b00001:
+ switch (((inst >> 20) & 0b1111111)) {
+ case 0b0001111: op = rv_op_unzip; break;
+ }
+ break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
@@ -1622,6 +1738,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0111000: op = rv_op_rev8; break;
+ case 0b0000111: op = rv_op_brev8; break;
}
break;
}
@@ -1742,8 +1859,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_pack; break;
}
break;
+ case 39: op = rv_op_packh; break;
+
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
@@ -1755,6 +1875,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
+ case 162: op = rv_op_xperm4; break;
+ case 164: op = rv_op_xperm8; break;
+ case 200: op = rv_op_aes64es; break;
+ case 216: op = rv_op_aes64esm; break;
+ case 232: op = rv_op_aes64ds; break;
+ case 248: op = rv_op_aes64dsm; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
@@ -1762,9 +1888,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
+ case 320: op = rv_op_sha512sum0r; break;
+ case 328: op = rv_op_sha512sum1r; break;
+ case 336: op = rv_op_sha512sig0l; break;
+ case 344: op = rv_op_sha512sig1l; break;
+ case 368: op = rv_op_sha512sig0h; break;
+ case 376: op = rv_op_sha512sig1h; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
+ case 504: op = rv_op_aes64ks2; break;
+ }
+ switch ((inst >> 25) & 0b0011111) {
+ case 17: op = rv_op_aes32esi; break;
+ case 19: op = rv_op_aes32esmi; break;
+ case 21: op = rv_op_aes32dsi; break;
+ case 23: op = rv_op_aes32esmi; break;
+ case 24: op = rv_op_sm4ed; break;
+ case 26: op = rv_op_sm4ks; break;
}
break;
case 13: op = rv_op_lui; break;
@@ -1782,6 +1923,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
+ default: op = rv_op_packw; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
@@ -2374,6 +2516,16 @@ static uint32_t operand_cimmq(rv_inst inst)
((inst << 57) >> 62) << 6;
}
+static uint32_t operand_bs(rv_inst inst)
+{
+ return (inst << 32) >> 62;
+}
+
+static uint32_t operand_rnum(rv_inst inst)
+{
+ return (inst << 40) >> 60;
+}
+
/* decode operands */
static void decode_inst_operands(rv_decode *dec)
@@ -2653,6 +2805,16 @@ static void decode_inst_operands(rv_decode *dec)
dec->rs2 = operand_crs2(inst);
dec->imm = operand_cimmsqsp(inst);
break;
+ case rv_codec_k_bs:
+ dec->rs1 = operand_rs1(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->bs = operand_bs(inst);
+ break;
+ case rv_codec_k_rnum:
+ dec->rd = operand_rd(inst);
+ dec->rs1 = operand_rs1(inst);
+ dec->rnum = operand_rnum(inst);
+ break;
};
}
@@ -2812,6 +2974,14 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
case ')':
append(buf, ")", buflen);
break;
+ case 'b':
+ snprintf(tmp, sizeof(tmp), "%d", dec->bs);
+ append(buf, tmp, buflen);
+ break;
+ case 'n':
+ snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
+ append(buf, tmp, buflen);
+ break;
case '0':
append(buf, rv_ireg_name_sym[dec->rd], buflen);
break;
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 14/14] target/riscv: rvk: expose zbk* and zk* properties
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 14:48 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser, luruibo2000, lustrew
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e8bbce6f1..11a35fb5d6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -816,7 +816,20 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* [PATCH v7 14/14] target/riscv: rvk: expose zbk* and zk* properties
@ 2022-02-28 14:48 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-02-28 14:48 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000, Weiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9e8bbce6f1..11a35fb5d6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -816,7 +816,20 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
+ DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
+ DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
+ DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
+ DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
+ DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
+ DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
+ DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
+ DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
+ DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
+ DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
+ DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
--
2.17.1
^ permalink raw reply related [flat|nested] 58+ messages in thread
* Re: [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 18:54 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 18:54 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:47, Weiwei Li wrote:
> - reuse partial instructions of zbb extension, update extension check for them
> - add brev8, pack, packh, packw, unzip, zip instructions
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> Acked-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/bitmanip_helper.c | 53 ++++++++++++++
> target/riscv/helper.h | 3 +
> target/riscv/insn32.decode | 45 +++++++-----
> target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
> target/riscv/translate.c | 7 ++
> 5 files changed, 174 insertions(+), 28 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension
@ 2022-02-28 18:54 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 18:54 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:47, Weiwei Li wrote:
> - reuse partial instructions of zbb extension, update extension check for them
> - add brev8, pack, packh, packw, unzip, zip instructions
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> Acked-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/bitmanip_helper.c | 53 ++++++++++++++
> target/riscv/helper.h | 3 +
> target/riscv/insn32.decode | 45 +++++++-----
> target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
> target/riscv/translate.c | 7 ++
> 5 files changed, 174 insertions(+), 28 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension
2022-02-28 14:47 ` Weiwei Li
@ 2022-02-28 18:55 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 18:55 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:47, Weiwei Li wrote:
> - reuse partial instructions of zbc extension, update extension check for them
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/insn32.decode | 3 ++-
> target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension
@ 2022-02-28 18:55 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 18:55 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:47, Weiwei Li wrote:
> - reuse partial instructions of zbc extension, update extension check for them
>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> Reviewed-by: Alistair Francis<alistair.francis@wdc.com>
> ---
> target/riscv/insn32.decode | 3 ++-
> target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 18:57 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 18:57 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> +static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
> + void (*func)(TCGv, TCGv, TCGv, TCGv))
> +{
> + TCGv shamt = tcg_const_tl(a->shamt);
tcg_constant_tl
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32
@ 2022-02-28 18:57 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 18:57 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> +static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
> + void (*func)(TCGv, TCGv, TCGv, TCGv))
> +{
> + TCGv shamt = tcg_const_tl(a->shamt);
tcg_constant_tl
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 19:01 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:01 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
>
> Co-authored-by: Ruibo Lu<luruibo2000@163.com>
> Co-authored-by: Zewen Ye<lustrew@foxmail.com>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/crypto_helper.c | 169 ++++++++++++++++++++++++
> target/riscv/helper.h | 8 ++
> target/riscv/insn32.decode | 12 ++
> target/riscv/insn_trans/trans_rvk.c.inc | 47 +++++++
> 4 files changed, 236 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64
@ 2022-02-28 19:01 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:01 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
>
> Co-authored-by: Ruibo Lu<luruibo2000@163.com>
> Co-authored-by: Zewen Ye<lustrew@foxmail.com>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/crypto_helper.c | 169 ++++++++++++++++++++++++
> target/riscv/helper.h | 8 ++
> target/riscv/insn32.decode | 12 ++
> target/riscv/insn_trans/trans_rvk.c.inc | 47 +++++++
> 4 files changed, 236 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 19:03 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:03 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
>
> Co-authored-by: Zewen Ye<lustrew@foxmail.com>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/insn32.decode | 5 ++++
> target/riscv/insn_trans/trans_rvk.c.inc | 37 +++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension
@ 2022-02-28 19:03 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:03 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> - add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
>
> Co-authored-by: Zewen Ye<lustrew@foxmail.com>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/insn32.decode | 5 ++++
> target/riscv/insn_trans/trans_rvk.c.inc | 37 +++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 19:38 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:38 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
> +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
> +{ \
> + TCGv_i64 t0 = tcg_temp_new_i64(); \
> + TCGv_i64 t1 = tcg_temp_new_i64(); \
> + TCGv_i64 t2 = tcg_temp_new_i64(); \
> + \
> + tcg_gen_concat_tl_i64(t0, src1, src2); \
> + tcg_gen_##OP##_i64(t1, t0, NUM1); \
> + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
The bug here is tcg_const_tl instead of tcg_constant_tl, which leaks a temporary.
It's not the best option for zero-extension, though, as we don't optimize a deposit of
zero like this (we probably should, but, hey).
Better would be
tcg_gen_extu_tl_i64(t2, src1);
tcg_gen_ext32u_i64(t2, t2);
Note that the first operation will *not* extend if TARGET_RISCV64, since it doesn't
actually change type. The second operation will be optimized away if TARGET_RISCV32,
since the zero-extend has already happened.
BTW, it would be better to not use a large macro for this, and in the previous patch.
Passing in parameters to a helper function would be easier to read and debug.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
@ 2022-02-28 19:38 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:38 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
> +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
> +{ \
> + TCGv_i64 t0 = tcg_temp_new_i64(); \
> + TCGv_i64 t1 = tcg_temp_new_i64(); \
> + TCGv_i64 t2 = tcg_temp_new_i64(); \
> + \
> + tcg_gen_concat_tl_i64(t0, src1, src2); \
> + tcg_gen_##OP##_i64(t1, t0, NUM1); \
> + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
The bug here is tcg_const_tl instead of tcg_constant_tl, which leaks a temporary.
It's not the best option for zero-extension, though, as we don't optimize a deposit of
zero like this (we probably should, but, hey).
Better would be
tcg_gen_extu_tl_i64(t2, src1);
tcg_gen_ext32u_i64(t2, t2);
Note that the first operation will *not* extend if TARGET_RISCV64, since it doesn't
actually change type. The second operation will be optimized away if TARGET_RISCV32,
since the zero-extend has already happened.
BTW, it would be better to not use a large macro for this, and in the previous patch.
Passing in parameters to a helper function would be easier to read and debug.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 19:40 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:40 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
>
> Co-authored-by: Zewen Ye<lustrew@foxmail.com>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/insn32.decode | 5 ++++
> target/riscv/insn_trans/trans_rvk.c.inc | 32 +++++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Same comment about the macro, though.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
@ 2022-02-28 19:40 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:40 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
>
> Co-authored-by: Zewen Ye<lustrew@foxmail.com>
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/insn32.decode | 5 ++++
> target/riscv/insn_trans/trans_rvk.c.inc | 32 +++++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Same comment about the macro, though.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 19:44 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:44 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> +static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
> +{
> + REQUIRE_ZKSED(ctx);
> + return gen_aes32_sm4(ctx, a , gen_helper_sm4ed);
> +}
> +
> +static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
> +{
> + REQUIRE_ZKSED(ctx);
> + return gen_aes32_sm4(ctx, a , gen_helper_sm4ks);
Extra space before comma. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension
@ 2022-02-28 19:44 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 19:44 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> +static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
> +{
> + REQUIRE_ZKSED(ctx);
> + return gen_aes32_sm4(ctx, a , gen_helper_sm4ed);
> +}
> +
> +static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
> +{
> + REQUIRE_ZKSED(ctx);
> + return gen_aes32_sm4(ctx, a , gen_helper_sm4ks);
Extra space before comma. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
2022-02-28 14:48 ` Weiwei Li
@ 2022-02-28 20:11 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 20:11 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 04:48, Weiwei Li wrote:
> +/* Crypto Extension */
> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
> + target_ulong *ret_value,
> + target_ulong new_value, target_ulong write_mask)
> +{
> + if (!write_mask) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
This is incorrect. The error should only be with a write-mask of the actual x0 register,
not another register which happens to contain 0. There is in fact no way to diagnose
exactly what you want here, which IIRC has an existing fixme comment somewhere.
> + uint32_t return_status = SEED_OPST_ES16;
> +
> + *ret_value = return_status;
> + if (return_status == SEED_OPST_ES16) {
> + uint16_t random_number;
> + qemu_guest_getrandom_nofail(&random_number, sizeof(random_number));
> + *ret_value = (*ret_value) | random_number;
> + } else if (return_status == SEED_OPST_BIST) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_WAIT) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_DEAD) {
> + /* Do nothing */
> + }
This is also incorrect. This should be
uint32_t result;
uint16_t random_v;
Error *random_e = NULL;
int random_r;
random_r = guest_getrandom(&random_v, 2, &random_e);
if (unlikely(random_r < 0)) {
/*
* Failed, for unknown reasons in the crypto subsystem.
* The best we can do is log the reason and return a
* failure indication to the guest. There is no reason
* we know to expect the failure to be transitory, so
* indicate DEAD to avoid having the guest spin on WAIT.
*/
qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
__func__, error_get_pretty(random_e));
error_free(random_e);
result = SEED_OPST_DEAD;
} else {
result = random_v | SEED_OPST_ES16;
}
C.f. target/arm/helper.c, rndr_readfn.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
@ 2022-02-28 20:11 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-02-28 20:11 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 04:48, Weiwei Li wrote:
> +/* Crypto Extension */
> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
> + target_ulong *ret_value,
> + target_ulong new_value, target_ulong write_mask)
> +{
> + if (!write_mask) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
This is incorrect. The error should only be with a write-mask of the actual x0 register,
not another register which happens to contain 0. There is in fact no way to diagnose
exactly what you want here, which IIRC has an existing fixme comment somewhere.
> + uint32_t return_status = SEED_OPST_ES16;
> +
> + *ret_value = return_status;
> + if (return_status == SEED_OPST_ES16) {
> + uint16_t random_number;
> + qemu_guest_getrandom_nofail(&random_number, sizeof(random_number));
> + *ret_value = (*ret_value) | random_number;
> + } else if (return_status == SEED_OPST_BIST) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_WAIT) {
> + /* Do nothing */
> + } else if (return_status == SEED_OPST_DEAD) {
> + /* Do nothing */
> + }
This is also incorrect. This should be
uint32_t result;
uint16_t random_v;
Error *random_e = NULL;
int random_r;
random_r = guest_getrandom(&random_v, 2, &random_e);
if (unlikely(random_r < 0)) {
/*
* Failed, for unknown reasons in the crypto subsystem.
* The best we can do is log the reason and return a
* failure indication to the guest. There is no reason
* we know to expect the failure to be transitory, so
* indicate DEAD to avoid having the guest spin on WAIT.
*/
qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
__func__, error_get_pretty(random_e));
error_free(random_e);
result = SEED_OPST_DEAD;
} else {
result = random_v | SEED_OPST_ES16;
}
C.f. target/arm/helper.c, rndr_readfn.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
2022-02-28 19:38 ` Richard Henderson
@ 2022-03-01 1:28 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-01 1:28 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
在 2022/3/1 上午3:38, Richard Henderson 写道:
> On 2/28/22 04:48, Weiwei Li wrote:
>> +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
>> +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
>> +{ \
>> + TCGv_i64 t0 = tcg_temp_new_i64(); \
>> + TCGv_i64 t1 = tcg_temp_new_i64(); \
>> + TCGv_i64 t2 = tcg_temp_new_i64(); \
>> + \
>> + tcg_gen_concat_tl_i64(t0, src1, src2); \
>> + tcg_gen_##OP##_i64(t1, t0, NUM1); \
>> + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
>
> The bug here is tcg_const_tl instead of tcg_constant_tl, which leaks a
> temporary.
>
> It's not the best option for zero-extension, though, as we don't
> optimize a deposit of zero like this (we probably should, but, hey).
>
> Better would be
>
> tcg_gen_extu_tl_i64(t2, src1);
> tcg_gen_ext32u_i64(t2, t2);
>
> Note that the first operation will *not* extend if TARGET_RISCV64,
> since it doesn't actually change type. The second operation will be
> optimized away if TARGET_RISCV32, since the zero-extend has already
> happened.
>
OK. I'll update this.
> BTW, it would be better to not use a large macro for this, and in the
> previous patch. Passing in parameters to a helper function would be
> easier to read and debug.
>
OK I'll try to replace this as parameters to a function.
Regards,
Weiwei Li
>
> r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
@ 2022-03-01 1:28 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-01 1:28 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
在 2022/3/1 上午3:38, Richard Henderson 写道:
> On 2/28/22 04:48, Weiwei Li wrote:
>> +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \
>> +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \
>> +{ \
>> + TCGv_i64 t0 = tcg_temp_new_i64(); \
>> + TCGv_i64 t1 = tcg_temp_new_i64(); \
>> + TCGv_i64 t2 = tcg_temp_new_i64(); \
>> + \
>> + tcg_gen_concat_tl_i64(t0, src1, src2); \
>> + tcg_gen_##OP##_i64(t1, t0, NUM1); \
>> + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \
>
> The bug here is tcg_const_tl instead of tcg_constant_tl, which leaks a
> temporary.
>
> It's not the best option for zero-extension, though, as we don't
> optimize a deposit of zero like this (we probably should, but, hey).
>
> Better would be
>
> tcg_gen_extu_tl_i64(t2, src1);
> tcg_gen_ext32u_i64(t2, t2);
>
> Note that the first operation will *not* extend if TARGET_RISCV64,
> since it doesn't actually change type. The second operation will be
> optimized away if TARGET_RISCV32, since the zero-extend has already
> happened.
>
OK. I'll update this.
> BTW, it would be better to not use a large macro for this, and in the
> previous patch. Passing in parameters to a helper function would be
> easier to read and debug.
>
OK I'll try to replace this as parameters to a function.
Regards,
Weiwei Li
>
> r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
2022-02-28 20:11 ` Richard Henderson
@ 2022-03-01 1:44 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-01 1:44 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
在 2022/3/1 上午4:11, Richard Henderson 写道:
> On 2/28/22 04:48, Weiwei Li wrote:
>> +/* Crypto Extension */
>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>> + target_ulong *ret_value,
>> + target_ulong new_value, target_ulong
>> write_mask)
>> +{
>> + if (!write_mask) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>
> This is incorrect. The error should only be with a write-mask of the
> actual x0 register, not another register which happens to contain 0.
> There is in fact no way to diagnose exactly what you want here, which
> IIRC has an existing fixme comment somewhere.
Yeah. write_mask is also used in riscv_csrrw_check to check whether the
read-only csr is written. We cannot distinguish x0 and reg which
contains 0 here without changing total progress of csr read/write.
>
>> + uint32_t return_status = SEED_OPST_ES16;
>> +
>> + *ret_value = return_status;
>> + if (return_status == SEED_OPST_ES16) {
>> + uint16_t random_number;
>> + qemu_guest_getrandom_nofail(&random_number,
>> sizeof(random_number));
>> + *ret_value = (*ret_value) | random_number;
>> + } else if (return_status == SEED_OPST_BIST) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_WAIT) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_DEAD) {
>> + /* Do nothing */
>> + }
>
> This is also incorrect. This should be
>
> uint32_t result;
> uint16_t random_v;
> Error *random_e = NULL;
> int random_r;
>
> random_r = guest_getrandom(&random_v, 2, &random_e);
> if (unlikely(random_r < 0)) {
> /*
> * Failed, for unknown reasons in the crypto subsystem.
> * The best we can do is log the reason and return a
> * failure indication to the guest. There is no reason
> * we know to expect the failure to be transitory, so
> * indicate DEAD to avoid having the guest spin on WAIT.
> */
> qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
> __func__, error_get_pretty(random_e));
> error_free(random_e);
> result = SEED_OPST_DEAD;
> } else {
> result = random_v | SEED_OPST_ES16;
> }
>
> C.f. target/arm/helper.c, rndr_readfn.
OK. I'll fix this.
Regards,
Weiwei Li
>
>
> r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
@ 2022-03-01 1:44 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-01 1:44 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
在 2022/3/1 上午4:11, Richard Henderson 写道:
> On 2/28/22 04:48, Weiwei Li wrote:
>> +/* Crypto Extension */
>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>> + target_ulong *ret_value,
>> + target_ulong new_value, target_ulong
>> write_mask)
>> +{
>> + if (!write_mask) {
>> + return RISCV_EXCP_ILLEGAL_INST;
>> + }
>
> This is incorrect. The error should only be with a write-mask of the
> actual x0 register, not another register which happens to contain 0.
> There is in fact no way to diagnose exactly what you want here, which
> IIRC has an existing fixme comment somewhere.
Yeah. write_mask is also used in riscv_csrrw_check to check whether the
read-only csr is written. We cannot distinguish x0 and reg which
contains 0 here without changing total progress of csr read/write.
>
>> + uint32_t return_status = SEED_OPST_ES16;
>> +
>> + *ret_value = return_status;
>> + if (return_status == SEED_OPST_ES16) {
>> + uint16_t random_number;
>> + qemu_guest_getrandom_nofail(&random_number,
>> sizeof(random_number));
>> + *ret_value = (*ret_value) | random_number;
>> + } else if (return_status == SEED_OPST_BIST) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_WAIT) {
>> + /* Do nothing */
>> + } else if (return_status == SEED_OPST_DEAD) {
>> + /* Do nothing */
>> + }
>
> This is also incorrect. This should be
>
> uint32_t result;
> uint16_t random_v;
> Error *random_e = NULL;
> int random_r;
>
> random_r = guest_getrandom(&random_v, 2, &random_e);
> if (unlikely(random_r < 0)) {
> /*
> * Failed, for unknown reasons in the crypto subsystem.
> * The best we can do is log the reason and return a
> * failure indication to the guest. There is no reason
> * we know to expect the failure to be transitory, so
> * indicate DEAD to avoid having the guest spin on WAIT.
> */
> qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
> __func__, error_get_pretty(random_e));
> error_free(random_e);
> result = SEED_OPST_DEAD;
> } else {
> result = random_v | SEED_OPST_ES16;
> }
>
> C.f. target/arm/helper.c, rndr_readfn.
OK. I'll fix this.
Regards,
Weiwei Li
>
>
> r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
2022-03-01 1:44 ` Weiwei Li
@ 2022-03-01 2:27 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-01 2:27 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
[-- Attachment #1: Type: text/plain, Size: 3342 bytes --]
在 2022/3/1 上午9:44, Weiwei Li 写道:
>
> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>> On 2/28/22 04:48, Weiwei Li wrote:
>>> +/* Crypto Extension */
>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>> + target_ulong *ret_value,
>>> + target_ulong new_value, target_ulong
>>> write_mask)
>>> +{
>>> + if (!write_mask) {
>>> + return RISCV_EXCP_ILLEGAL_INST;
>>> + }
>>
>> This is incorrect. The error should only be with a write-mask of the
>> actual x0 register, not another register which happens to contain 0.
>> There is in fact no way to diagnose exactly what you want here, which
>> IIRC has an existing fixme comment somewhere.
> Yeah. write_mask is also used in riscv_csrrw_check to check whether
> the read-only csr is written. We cannot distinguish x0 and reg which
> contains 0 here without changing total progress of csr read/write.
>>
I seems misunderstand the code for csr read/write: write_mask will be
set zero only for read-only operation (CSRRS/CSRRC with rs1=x0 or
CSRRSI/CSRRCI with uimm=0) via do_csrr --> helper_csrr -> riscv_csrrw
call-chain.
The write_mask for do_csrw and do_csrrw will not be zero.
As said in the spec :
"TheseedCSR must be accessed with a read-write instruction. A read-only
instruction such asCSRRS/CSRRC
withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction
exception. "
So it's suitable to check write_mask here.
>>> + uint32_t return_status = SEED_OPST_ES16;
>>> +
>>> + *ret_value = return_status;
>>> + if (return_status == SEED_OPST_ES16) {
>>> + uint16_t random_number;
>>> + qemu_guest_getrandom_nofail(&random_number,
>>> sizeof(random_number));
>>> + *ret_value = (*ret_value) | random_number;
>>> + } else if (return_status == SEED_OPST_BIST) {
>>> + /* Do nothing */
>>> + } else if (return_status == SEED_OPST_WAIT) {
>>> + /* Do nothing */
>>> + } else if (return_status == SEED_OPST_DEAD) {
>>> + /* Do nothing */
>>> + }
>>
>> This is also incorrect. This should be
>>
>> uint32_t result;
>> uint16_t random_v;
>> Error *random_e = NULL;
>> int random_r;
>>
>> random_r = guest_getrandom(&random_v, 2, &random_e);
>> if (unlikely(random_r < 0)) {
>> /*
>> * Failed, for unknown reasons in the crypto subsystem.
>> * The best we can do is log the reason and return a
>> * failure indication to the guest. There is no reason
>> * we know to expect the failure to be transitory, so
>> * indicate DEAD to avoid having the guest spin on WAIT.
>> */
>> qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
>> __func__, error_get_pretty(random_e));
>> error_free(random_e);
>> result = SEED_OPST_DEAD;
>> } else {
>> result = random_v | SEED_OPST_ES16;
>> }
>>
>> C.f. target/arm/helper.c, rndr_readfn.
>
> OK. I'll fix this.
>
> Regards,
>
> Weiwei Li
>
>>
>>
>> r~
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^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
@ 2022-03-01 2:27 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-01 2:27 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
[-- Attachment #1: Type: text/plain, Size: 3342 bytes --]
在 2022/3/1 上午9:44, Weiwei Li 写道:
>
> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>> On 2/28/22 04:48, Weiwei Li wrote:
>>> +/* Crypto Extension */
>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>> + target_ulong *ret_value,
>>> + target_ulong new_value, target_ulong
>>> write_mask)
>>> +{
>>> + if (!write_mask) {
>>> + return RISCV_EXCP_ILLEGAL_INST;
>>> + }
>>
>> This is incorrect. The error should only be with a write-mask of the
>> actual x0 register, not another register which happens to contain 0.
>> There is in fact no way to diagnose exactly what you want here, which
>> IIRC has an existing fixme comment somewhere.
> Yeah. write_mask is also used in riscv_csrrw_check to check whether
> the read-only csr is written. We cannot distinguish x0 and reg which
> contains 0 here without changing total progress of csr read/write.
>>
I seems misunderstand the code for csr read/write: write_mask will be
set zero only for read-only operation (CSRRS/CSRRC with rs1=x0 or
CSRRSI/CSRRCI with uimm=0) via do_csrr --> helper_csrr -> riscv_csrrw
call-chain.
The write_mask for do_csrw and do_csrrw will not be zero.
As said in the spec :
"TheseedCSR must be accessed with a read-write instruction. A read-only
instruction such asCSRRS/CSRRC
withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction
exception. "
So it's suitable to check write_mask here.
>>> + uint32_t return_status = SEED_OPST_ES16;
>>> +
>>> + *ret_value = return_status;
>>> + if (return_status == SEED_OPST_ES16) {
>>> + uint16_t random_number;
>>> + qemu_guest_getrandom_nofail(&random_number,
>>> sizeof(random_number));
>>> + *ret_value = (*ret_value) | random_number;
>>> + } else if (return_status == SEED_OPST_BIST) {
>>> + /* Do nothing */
>>> + } else if (return_status == SEED_OPST_WAIT) {
>>> + /* Do nothing */
>>> + } else if (return_status == SEED_OPST_DEAD) {
>>> + /* Do nothing */
>>> + }
>>
>> This is also incorrect. This should be
>>
>> uint32_t result;
>> uint16_t random_v;
>> Error *random_e = NULL;
>> int random_r;
>>
>> random_r = guest_getrandom(&random_v, 2, &random_e);
>> if (unlikely(random_r < 0)) {
>> /*
>> * Failed, for unknown reasons in the crypto subsystem.
>> * The best we can do is log the reason and return a
>> * failure indication to the guest. There is no reason
>> * we know to expect the failure to be transitory, so
>> * indicate DEAD to avoid having the guest spin on WAIT.
>> */
>> qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
>> __func__, error_get_pretty(random_e));
>> error_free(random_e);
>> result = SEED_OPST_DEAD;
>> } else {
>> result = random_v | SEED_OPST_ES16;
>> }
>>
>> C.f. target/arm/helper.c, rndr_readfn.
>
> OK. I'll fix this.
>
> Regards,
>
> Weiwei Li
>
>>
>>
>> r~
[-- Attachment #2: Type: text/html, Size: 9132 bytes --]
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
2022-03-01 2:27 ` Weiwei Li
@ 2022-03-01 15:59 ` Richard Henderson
-1 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-03-01 15:59 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
On 2/28/22 16:27, Weiwei Li wrote:
>
> 在 2022/3/1 上午9:44, Weiwei Li 写道:
>>
>> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>>> On 2/28/22 04:48, Weiwei Li wrote:
>>>> +/* Crypto Extension */
>>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>>> + target_ulong *ret_value,
>>>> + target_ulong new_value, target_ulong write_mask)
>>>> +{
>>>> + if (!write_mask) {
>>>> + return RISCV_EXCP_ILLEGAL_INST;
>>>> + }
>>>
>>> This is incorrect. The error should only be with a write-mask of the actual x0
>>> register, not another register which happens to contain 0. There is in fact no way to
>>> diagnose exactly what you want here, which IIRC has an existing fixme comment somewhere.
>> Yeah. write_mask is also used in riscv_csrrw_check to check whether the read-only csr is
>> written. We cannot distinguish x0 and reg which contains 0 here without changing total
>> progress of csr read/write.
>>>
> I seems misunderstand the code for csr read/write: write_mask will be set zero only for
> read-only operation (CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0) via do_csrr -->
> helper_csrr -> riscv_csrrw call-chain.
>
> The write_mask for do_csrw and do_csrrw will not be zero.
>
> As said in the spec :
>
> "TheseedCSR must be accessed with a read-write instruction. A read-only instruction such
> asCSRRS/CSRRC
> withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction exception. "
>
> So it's suitable to check write_mask here.
Consider CSRRS with rs1=x31. In that case mask will be the value in x31. Even if the
value is 0, this is still considered a read-write instruction.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
@ 2022-03-01 15:59 ` Richard Henderson
0 siblings, 0 replies; 58+ messages in thread
From: Richard Henderson @ 2022-03-01 15:59 UTC (permalink / raw)
To: Weiwei Li, palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
On 2/28/22 16:27, Weiwei Li wrote:
>
> 在 2022/3/1 上午9:44, Weiwei Li 写道:
>>
>> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>>> On 2/28/22 04:48, Weiwei Li wrote:
>>>> +/* Crypto Extension */
>>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>>> + target_ulong *ret_value,
>>>> + target_ulong new_value, target_ulong write_mask)
>>>> +{
>>>> + if (!write_mask) {
>>>> + return RISCV_EXCP_ILLEGAL_INST;
>>>> + }
>>>
>>> This is incorrect. The error should only be with a write-mask of the actual x0
>>> register, not another register which happens to contain 0. There is in fact no way to
>>> diagnose exactly what you want here, which IIRC has an existing fixme comment somewhere.
>> Yeah. write_mask is also used in riscv_csrrw_check to check whether the read-only csr is
>> written. We cannot distinguish x0 and reg which contains 0 here without changing total
>> progress of csr read/write.
>>>
> I seems misunderstand the code for csr read/write: write_mask will be set zero only for
> read-only operation (CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0) via do_csrr -->
> helper_csrr -> riscv_csrrw call-chain.
>
> The write_mask for do_csrw and do_csrrw will not be zero.
>
> As said in the spec :
>
> "TheseedCSR must be accessed with a read-write instruction. A read-only instruction such
> asCSRRS/CSRRC
> withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction exception. "
>
> So it's suitable to check write_mask here.
Consider CSRRS with rs1=x31. In that case mask will be the value in x31. Even if the
value is 0, this is still considered a read-write instruction.
r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
2022-03-01 15:59 ` Richard Henderson
@ 2022-03-02 0:57 ` Weiwei Li
-1 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-02 0:57 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, luruibo2000, lustrew
在 2022/3/1 下午11:59, Richard Henderson 写道:
> On 2/28/22 16:27, Weiwei Li wrote:
>>
>> 在 2022/3/1 上午9:44, Weiwei Li 写道:
>>>
>>> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>>>> On 2/28/22 04:48, Weiwei Li wrote:
>>>>> +/* Crypto Extension */
>>>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>>>> + target_ulong *ret_value,
>>>>> + target_ulong new_value,
>>>>> target_ulong write_mask)
>>>>> +{
>>>>> + if (!write_mask) {
>>>>> + return RISCV_EXCP_ILLEGAL_INST;
>>>>> + }
>>>>
>>>> This is incorrect. The error should only be with a write-mask of
>>>> the actual x0 register, not another register which happens to
>>>> contain 0. There is in fact no way to diagnose exactly what you
>>>> want here, which IIRC has an existing fixme comment somewhere.
>>> Yeah. write_mask is also used in riscv_csrrw_check to check whether
>>> the read-only csr is written. We cannot distinguish x0 and reg which
>>> contains 0 here without changing total progress of csr read/write.
>>>>
>> I seems misunderstand the code for csr read/write: write_mask will
>> be set zero only for read-only operation (CSRRS/CSRRC with rs1=x0 or
>> CSRRSI/CSRRCI with uimm=0) via do_csrr --> helper_csrr -> riscv_csrrw
>> call-chain.
>>
>> The write_mask for do_csrw and do_csrrw will not be zero.
>>
>> As said in the spec :
>>
>> "TheseedCSR must be accessed with a read-write instruction. A
>> read-only instruction such asCSRRS/CSRRC
>> withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction
>> exception. "
>>
>> So it's suitable to check write_mask here.
>
> Consider CSRRS with rs1=x31. In that case mask will be the value in
> x31. Even if the value is 0, this is still considered a read-write
> instruction.
Yeah. I lost this kind of case . So this is a bug. Maybe we can add a
new parameter like 'write' to helper_csrrw to indicate that write
operation should be done.
>
>
> r~
^ permalink raw reply [flat|nested] 58+ messages in thread
* Re: [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr
@ 2022-03-02 0:57 ` Weiwei Li
0 siblings, 0 replies; 58+ messages in thread
From: Weiwei Li @ 2022-03-02 0:57 UTC (permalink / raw)
To: Richard Henderson, palmer, alistair.francis, bin.meng,
qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, lustrew, luruibo2000
在 2022/3/1 下午11:59, Richard Henderson 写道:
> On 2/28/22 16:27, Weiwei Li wrote:
>>
>> 在 2022/3/1 上午9:44, Weiwei Li 写道:
>>>
>>> 在 2022/3/1 上午4:11, Richard Henderson 写道:
>>>> On 2/28/22 04:48, Weiwei Li wrote:
>>>>> +/* Crypto Extension */
>>>>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
>>>>> + target_ulong *ret_value,
>>>>> + target_ulong new_value,
>>>>> target_ulong write_mask)
>>>>> +{
>>>>> + if (!write_mask) {
>>>>> + return RISCV_EXCP_ILLEGAL_INST;
>>>>> + }
>>>>
>>>> This is incorrect. The error should only be with a write-mask of
>>>> the actual x0 register, not another register which happens to
>>>> contain 0. There is in fact no way to diagnose exactly what you
>>>> want here, which IIRC has an existing fixme comment somewhere.
>>> Yeah. write_mask is also used in riscv_csrrw_check to check whether
>>> the read-only csr is written. We cannot distinguish x0 and reg which
>>> contains 0 here without changing total progress of csr read/write.
>>>>
>> I seems misunderstand the code for csr read/write: write_mask will
>> be set zero only for read-only operation (CSRRS/CSRRC with rs1=x0 or
>> CSRRSI/CSRRCI with uimm=0) via do_csrr --> helper_csrr -> riscv_csrrw
>> call-chain.
>>
>> The write_mask for do_csrw and do_csrrw will not be zero.
>>
>> As said in the spec :
>>
>> "TheseedCSR must be accessed with a read-write instruction. A
>> read-only instruction such asCSRRS/CSRRC
>> withrs1=x0orCSRRSI/CSRRCIwithuimm=0will raise an illegal instruction
>> exception. "
>>
>> So it's suitable to check write_mask here.
>
> Consider CSRRS with rs1=x31. In that case mask will be the value in
> x31. Even if the value is 0, this is still considered a read-write
> instruction.
Yeah. I lost this kind of case . So this is a bug. Maybe we can add a
new parameter like 'write' to helper_csrrw to indicate that write
operation should be done.
>
>
> r~
^ permalink raw reply [flat|nested] 58+ messages in thread
end of thread, other threads:[~2022-03-02 1:02 UTC | newest]
Thread overview: 58+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-28 14:47 [PATCH v7 00/14] support subsets of scalar crypto extension Weiwei Li
2022-02-28 14:47 ` Weiwei Li
2022-02-28 14:47 ` [PATCH v7 01/14] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li
2022-02-28 14:47 ` Weiwei Li
2022-02-28 14:47 ` [PATCH v7 02/14] target/riscv: rvk: add support for zbkb extension Weiwei Li
2022-02-28 14:47 ` Weiwei Li
2022-02-28 18:54 ` Richard Henderson
2022-02-28 18:54 ` Richard Henderson
2022-02-28 14:47 ` [PATCH v7 03/14] target/riscv: rvk: add support for zbkc extension Weiwei Li
2022-02-28 14:47 ` Weiwei Li
2022-02-28 18:55 ` Richard Henderson
2022-02-28 18:55 ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 04/14] target/riscv: rvk: add support for zbkx extension Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 05/14] crypto: move sm4_sbox from target/arm Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32 Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 18:57 ` Richard Henderson
2022-02-28 18:57 ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64 Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 19:01 ` Richard Henderson
2022-02-28 19:01 ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 19:03 ` Richard Henderson
2022-02-28 19:03 ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 " Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 19:38 ` Richard Henderson
2022-02-28 19:38 ` Richard Henderson
2022-03-01 1:28 ` Weiwei Li
2022-03-01 1:28 ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 " Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 19:40 ` Richard Henderson
2022-02-28 19:40 ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 11/14] target/riscv: rvk: add support for zksed/zksh extension Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 19:44 ` Richard Henderson
2022-02-28 19:44 ` Richard Henderson
2022-02-28 14:48 ` [PATCH v7 12/14] target/riscv: rvk: add CSR support for Zkr Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 20:11 ` Richard Henderson
2022-02-28 20:11 ` Richard Henderson
2022-03-01 1:44 ` Weiwei Li
2022-03-01 1:44 ` Weiwei Li
2022-03-01 2:27 ` Weiwei Li
2022-03-01 2:27 ` Weiwei Li
2022-03-01 15:59 ` Richard Henderson
2022-03-01 15:59 ` Richard Henderson
2022-03-02 0:57 ` Weiwei Li
2022-03-02 0:57 ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li
2022-02-28 14:48 ` Weiwei Li
2022-02-28 14:48 ` [PATCH v7 14/14] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li
2022-02-28 14:48 ` Weiwei Li
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