[Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Hi,

This is a second round of AArch64 EL2/3 patches working on the exception
model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and
Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal
delivery method.

This conflicts slightly with the PSCI emulation patches that Rob posted.
A rebase should be trivial, hooking in the PSCI emulation calls in the
HVC/SMC code.

Cheers,
Edgar

v6 -> v7:
* Fix SCR offsetoflow32
* Change pattern to get hold of CPUARMState* in arm_excep_target_el
* S/NS mode -> S/NS state, in pre_smc helper comment
* udef -> undef in HVC and SMC helpers
* Remove spurious blank line
* Reorganize arm_excep_target_el and drop HCR.TGE support
* hw_error in VIRQ/VFIQ on cores without EL2 support
* Update comment regarding IRQ routing to EL2

v5 -> v6:
* Another try at SCR RES0/RES1
* Make SCR RES0 masks more readable
* Wake CPUs that receive VIRQs/VFIQs
* Make SCR an uint64_t
* Rebase with the single-step support. Split HVC/SMC to use a pre hvc/smc
  handler for cases where the exception is raised before advancing PC.

v4 -> v5:
* Fix RES0/1 masks for SCR
* Use scr_write for aarch32 SCR
* Revert the move of aarch32 SCR to the el3 cpreg defs to avoid breakage
  of existing code relying on SCR existing in current 32bit CPUs.
  The 32bit TZ series will need to address this and enable EL3 for 32bit CPUs.

v3 -> v4:
* Coding style changes.
* Add access spec for v8_el3_no_el2_cp_reginfo.HCR_EL2.
* Move SCR to the el3 cpreg defs and add NO_MIGRATE to SCR_EL3.
* Correct HCR.HCD and HCR.TSC RES0 behaviour.
* Comment on hcr_write TLB flush.
* Use uint32_t with explicit masking for imm16 in syndrome generator.
* Add table lookup of interrupt masks in arm_cpu_set_irq.
* Move M profile irq handling comment from cpu-exec.c to cpu.h.
* Correct trap address for disabled HVC/SMD and for SMC routed to EL2.

v2 -> v3:
* Add more HCR bitfield macros
* Flush TLB on hcr_write change of HCR RW, DC and PTW.
* Fix hvc helper, HVC is undefined in secure mode.
* Remove uint16_t imm16 syndrome gen change.
* Replace c1_scr with scr_el3

v1 -> v2:
* Avoid imm16 mask in syndrome generation
* Use g_assert_not_reached() in arm_excp_unmasked()
* Avoid some logic duplication in arm_excp_target_el and arm_excp_unmasked.
* Put arm_excp_target_el in helper.c to start with.
* Fix SMC disable (SMD or SCD) for ARMv7 only applies if EL2 exists
* SCR_RES0_MASK -> SCR_MASK
* HCR_RES0_MASK -> HCR_MASK
* Fix SMC routing to EL2, only applies for NS EL1.
* Fix CPreg defs for ESR_EL2/3
* Fix SMC helper, SMC routing to EL2 and SCR.SMD for AArch32.

Edgar E. Iglesias (11):
  target-arm: Add HCR_EL2
  target-arm: Add SCR_EL3
  target-arm: A64: Refactor aarch64_cpu_do_interrupt
  target-arm: Break out exception masking to a separate func
  target-arm: Don't take interrupts targeting lower ELs
  target-arm: A64: Correct updates to FAR and ESR on exceptions
  target-arm: A64: Emulate the HVC insn
  target-arm: Add a Hypervisor Trap exception type
  target-arm: A64: Emulate the SMC insn
  target-arm: Add IRQ and FIQ routing to EL2 and 3
  target-arm: Add support for VIRQ and VFIQ

 cpu-exec.c                 |  17 ++++--
 target-arm/cpu.c           |  35 +++++++++----
 target-arm/cpu.h           | 128 ++++++++++++++++++++++++++++++++++++++++++++-
 target-arm/helper-a64.c    |  32 +++++++-----
 target-arm/helper.c        | 125 ++++++++++++++++++++++++++++++++++++++++++-
 target-arm/helper.h        |   2 +
 target-arm/internals.h     |  15 ++++++
 target-arm/op_helper.c     |  57 ++++++++++++++++++++
 target-arm/translate-a64.c |  44 ++++++++++++----
 9 files changed, 415 insertions(+), 40 deletions(-)

-- 
1.9.1