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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Rob Herring" <rob.herring@linaro.org>,
	"Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	"Fabian Aggeler" <aggelerf@ethz.ch>,
	"Greg Bellows" <greg.bellows@linaro.org>,
	"Alexander Graf" <agraf@suse.de>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Sergey Fedorov" <serge.fdrv@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v7 02/11] target-arm: Add SCR_EL3
Date: Sat, 27 Sep 2014 05:45:04 +1000	[thread overview]
Message-ID: <CAJy5ezqZyUukr3GEb7MaDB1PZS1m8npW-kyQ56eGGuLO2z1oLA@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA_AG5gsWKQMUsUAgk9CNb+PSpPbsw-oMRZQkgy3-sY0Ew@mail.gmail.com>

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Oops, thanks!

---
Sent from my phone
On Sep 27, 2014 12:46 AM, "Peter Maydell" <peter.maydell@linaro.org> wrote:

> On 26 September 2014 09:08, Edgar E. Iglesias <edgar.iglesias@gmail.com>
> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> >  static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> >  {
> >      ARMCPU *cpu = arm_env_get_cpu(env);
> > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> >        .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
> >        .resetvalue = 0 },
> >      { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> > -      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.c1_scr),
> > -      .resetvalue = 0, },
> > +      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.scr_el3),
> > +      .resetvalue = 0, .writefn = scr_write },
> >      { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
> >        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
> >        .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE
> },
> > @@ -2314,6 +2340,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
> >        .access = PL3_RW, .writefn = vbar_write,
> >        .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
> >        .resetvalue = 0 },
> > +    { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
> > +      .type = ARM_CP_NO_MIGRATE,
> > +      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
> > +      .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
> cp15.scr_el3),
> > +      .writefn = scr_write },
> >      REGINFO_SENTINEL
> >  };
>
> You've applied the "offsetoflow32" to the wrong reginfo:
> it goes on the one for the 32 bit reg, not the one for
> the 64 bit reg.
>
> Since this is a trivial thing I'm going to just fix it
> up as I put this patch into target-arm.next. (I don't
> know yet if I can put the whole series in but I'm
> planning to put at least the start of it in.)
>
> thanks
> -- PMM
>

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  reply	other threads:[~2014-09-26 19:50 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-26  8:08 [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 01/11] target-arm: Add HCR_EL2 Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 02/11] target-arm: Add SCR_EL3 Edgar E. Iglesias
2014-09-26 14:46   ` Peter Maydell
2014-09-26 19:45     ` Edgar E. Iglesias [this message]
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 03/11] target-arm: A64: Refactor aarch64_cpu_do_interrupt Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 04/11] target-arm: Break out exception masking to a separate func Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 05/11] target-arm: Don't take interrupts targeting lower ELs Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 06/11] target-arm: A64: Correct updates to FAR and ESR on exceptions Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 07/11] target-arm: A64: Emulate the HVC insn Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exception type Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 09/11] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3 Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ Edgar E. Iglesias
2014-09-26 15:23 ` [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model Peter Maydell
2014-09-29 10:31   ` Jan Kiszka
2014-09-29 10:41     ` Peter Maydell
2014-09-29 10:48       ` Jan Kiszka

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