[PATCH i-g-t 01/26] skl: Add SKL PCI ids

[PATCH i-g-t 01/26] skl: Add SKL PCI ids

[Damien Lespiau]

v2: Update to the latest PCI ids

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 lib/intel_chipset.h | 58 +++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 52 insertions(+), 6 deletions(-)

diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 404c632..e3ce603 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -189,6 +189,22 @@ void intel_check_pch(void);
 #define PCI_CHIP_CHERRYVIEW_2		0x22b2
 #define PCI_CHIP_CHERRYVIEW_3		0x22b3
 
+#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
+#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
+#define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
+#define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
+#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
+#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
+#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
+#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
+#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
+#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
+#define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
+#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
+#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
+#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
+#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
+
 #endif /* __GTK_DOC_IGNORE__ */
 
 #define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
@@ -350,18 +366,44 @@ void intel_check_pch(void);
 #define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
 				 IS_CHERRYVIEW(devid))
 
+#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
+
+#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
+
+#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
+
+#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
+				 IS_SKL_GT2(devid) || \
+				 IS_SKL_GT3(devid))
+
+#define IS_GEN9(devid)		IS_SKYLAKE(devid)
+
 #define IS_965(devid)		(IS_GEN4(devid) || \
 				 IS_GEN5(devid) || \
 				 IS_GEN6(devid) || \
 				 IS_GEN7(devid) || \
-				 IS_GEN8(devid))
+				 IS_GEN8(devid) || \
+				 IS_GEN9(devid))
 
 #define IS_9XX(devid)		(IS_GEN3(devid) || \
 				 IS_GEN4(devid) || \
 				 IS_GEN5(devid) || \
 				 IS_GEN6(devid) || \
 				 IS_GEN7(devid) || \
-				 IS_GEN8(devid))
+				 IS_GEN8(devid) || \
+				 IS_GEN9(devid))
 
 #define IS_INTEL(devid)		(IS_GEN2(devid) || \
 				 IS_GEN3(devid) || \
@@ -369,21 +411,25 @@ void intel_check_pch(void);
 				 IS_GEN5(devid) || \
 				 IS_GEN6(devid) || \
 				 IS_GEN7(devid) || \
-				 IS_GEN8(devid))
+				 IS_GEN8(devid) || \
+				 IS_GEN9(devid))
 
 #define HAS_PCH_SPLIT(devid)	(IS_GEN5(devid) || \
 				 IS_GEN6(devid) || \
 				 IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
-				 IS_GEN8(devid))
+				 IS_GEN8(devid) || \
+				 IS_GEN9(devid))
 
 #define HAS_BLT_RING(devid)	(IS_GEN6(devid) || \
 				 IS_GEN7(devid) || \
-				 IS_GEN8(devid))
+				 IS_GEN8(devid) || \
+				 IS_GEN9(devid))
 
 #define HAS_BSD_RING(devid)	(IS_GEN5(devid) || \
 				 IS_GEN6(devid) || \
 				 IS_GEN7(devid) || \
-				 IS_GEN8(devid))
+				 IS_GEN8(devid) || \
+				 IS_GEN9(devid))
 
 #define IS_BROADWATER(devid)	((devid) == PCI_CHIP_I946_GZ || \
 				 (devid) == PCI_CHIP_I965_G_1 || \
-- 
1.8.3.1

[PATCH i-g-t 02/26] skl: Add gen9 to intel_gen()

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 lib/intel_chipset.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
index 0828e44..fafd232 100644
--- a/lib/intel_chipset.c
+++ b/lib/intel_chipset.c
@@ -172,6 +172,8 @@ int intel_gen(uint32_t devid)
 		return 7;
 	if (IS_GEN8(devid))
 		return 8;
+	if (IS_GEN9(devid))
+		return 9;
 
 	return -1;
 }
-- 
1.8.3.1

[PATCH i-g-t 03/26] skl: initialize instdone bits for gen9

[Damien Lespiau]

gen9 uses the same bits as gen8.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 lib/instdone.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/lib/instdone.c b/lib/instdone.c
index 51cdff9..fffb949 100644
--- a/lib/instdone.c
+++ b/lib/instdone.c
@@ -417,10 +417,18 @@ init_gen8_instdone(void)
 	init_gen75_instdone();
 }
 
+static void
+init_gen9_instdone(void)
+{
+	init_gen8_instdone();
+}
+
 void
 init_instdone_definitions(uint32_t devid)
 {
-	if (IS_GEN8(devid)) {
+	if (IS_GEN9(devid)) {
+		init_gen9_instdone();
+	} else if (IS_GEN8(devid)) {
 		init_gen8_instdone();
 	} else if (IS_GEN7(devid)) {
 		init_gen7_instdone();
-- 
1.8.3.1

[PATCH i-g-t 04/26] list-workarounds/skl: Add Skylake to the list of valid platorms

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 scripts/list-workarounds | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/list-workarounds b/scripts/list-workarounds
index 5a84ee8..620d02f 100755
--- a/scripts/list-workarounds
+++ b/scripts/list-workarounds
@@ -18,7 +18,7 @@ def find_nth(haystack, needle, n):
 	return start
 
 valid_platforms = ('ctg', 'elk', 'ilk', 'snb', 'ivb', 'vlv', 'hsw', 'bdw',
-		   'chv')
+		   'chv', 'skl')
 def parse_platforms(p):
 	l =  p.split(',')
 	for p in l:
-- 
1.8.3.1

[PATCH i-g-t 05/26] rendercopy/skl: Start the gen9 rendercopy from the gen8 version

[Damien Lespiau]

v2 (Ben): Rebased on:
 commit ea11d103e0617e33bce6f11328521d15b13422b0
Author: Oscar Mateo <oscar.mateo@intel.com>
Date:   Tue Nov 12 11:50:35 2013 +0000

    build: list all test/tool/lib source files in their own Makefile.sources

v3: (Ben): Rebased on the doc/API rework. Probably needs review

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 lib/Makefile.sources  |   2 +
 lib/gen9_render.h     |   7 +
 lib/rendercopy.h      |   4 +
 lib/rendercopy_gen9.c | 971 ++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 984 insertions(+)
 create mode 100644 lib/gen9_render.h
 create mode 100644 lib/rendercopy_gen9.c

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 242d2e0..82e306d 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -33,9 +33,11 @@ libintel_tools_la_SOURCES = 	\
 	gen6_render.h		\
 	gen7_render.h		\
 	gen8_render.h		\
+	gen9_render.h		\
 	rendercopy_gen6.c	\
 	rendercopy_gen7.c	\
 	rendercopy_gen8.c	\
+	rendercopy_gen9.c	\
 	rendercopy.h		\
 	intel_reg_map.c		\
 	intel_iosf.c		\
diff --git a/lib/gen9_render.h b/lib/gen9_render.h
new file mode 100644
index 0000000..170b1fc
--- /dev/null
+++ b/lib/gen9_render.h
@@ -0,0 +1,7 @@
+#ifndef GEN9_RENDER_H
+#define GEN9_RENDER_H
+
+#include "gen8_render.h"
+
+
+#endif
diff --git a/lib/rendercopy.h b/lib/rendercopy.h
index 20619d6..f15df0e 100644
--- a/lib/rendercopy.h
+++ b/lib/rendercopy.h
@@ -23,6 +23,10 @@ static inline void emit_vertex_normalized(struct intel_batchbuffer *batch,
 	OUT_BATCH(u.ui);
 }
 
+void gen9_render_copyfunc(struct intel_batchbuffer *batch,
+			  struct igt_buf *src, unsigned src_x, unsigned src_y,
+			  unsigned width, unsigned height,
+			  struct igt_buf *dst, unsigned dst_x, unsigned dst_y);
 void gen8_render_copyfunc(struct intel_batchbuffer *batch,
 			  drm_intel_context *context,
 			  struct igt_buf *src, unsigned src_x, unsigned src_y,
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
new file mode 100644
index 0000000..97ed541
--- /dev/null
+++ b/lib/rendercopy_gen9.c
@@ -0,0 +1,971 @@
+#include <assert.h>
+#include <stdlib.h>
+#include <sys/ioctl.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <getopt.h>
+
+#include <drm.h>
+#include <i915_drm.h>
+
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_io.h"
+#include "rendercopy.h"
+#include "gen8_render.h"
+#include "intel_reg.h"
+#include "igt_aux.h"
+
+#include <intel_aub.h>
+
+#define VERTEX_SIZE (3*4)
+
+#if DEBUG_RENDERCPY
+static void dump_batch(struct intel_batchbuffer *batch) {
+	int fd = open("/tmp/i965-batchbuffers.dump", O_WRONLY | O_CREAT,  0666);
+	if (fd != -1) {
+		write(fd, batch->buffer, 4096);
+		fd = close(fd);
+	}
+}
+#else
+#define dump_batch(x) do { } while(0)
+#endif
+
+struct {
+	uint32_t cc_state;
+	uint32_t blend_state;
+} cc;
+
+struct {
+	uint32_t cc_state;
+	uint32_t sf_clip_state;
+} viewport;
+
+/* see shaders/ps/blit.g7a */
+static const uint32_t ps_kernel[][4] = {
+#if 1
+   { 0x0060005a, 0x21403ae8, 0x3a0000c0, 0x008d0040 },
+   { 0x0060005a, 0x21603ae8, 0x3a0000c0, 0x008d0080 },
+   { 0x0060005a, 0x21803ae8, 0x3a0000d0, 0x008d0040 },
+   { 0x0060005a, 0x21a03ae8, 0x3a0000d0, 0x008d0080 },
+   { 0x02800031, 0x2e0022e8, 0x0e000140, 0x08840001 },
+   { 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
+#else
+   /* Write all -1 */
+   { 0x00600001, 0x2e000608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2e200608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2e400608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2e600608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2e800608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2ea00608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2ec00608, 0x00000000, 0x3f800000 },
+   { 0x00600001, 0x2ee00608, 0x00000000, 0x3f800000 },
+   { 0x05800031, 0x200022e0, 0x0e000e00, 0x90031000 },
+#endif
+};
+
+/* AUB annotation support */
+#define MAX_ANNOTATIONS	33
+struct annotations_context {
+	drm_intel_aub_annotation annotations[MAX_ANNOTATIONS];
+	int index;
+	uint32_t offset;
+} aub_annotations;
+
+static void annotation_init(struct annotations_context *ctx)
+{
+	/* ctx->annotations is an array keeping a list of annotations of the
+	 * batch buffer ordered by offset. ctx->annotations[0] is thus left
+	 * for the command stream and will be filled just before executing
+	 * the batch buffer with annotations_add_batch() */
+	ctx->index = 1;
+}
+
+static void add_annotation(drm_intel_aub_annotation *a,
+			   uint32_t type, uint32_t subtype,
+			   uint32_t ending_offset)
+{
+	a->type = type;
+	a->subtype = subtype;
+	a->ending_offset = ending_offset;
+}
+
+static void annotation_add_batch(struct annotations_context *ctx, size_t size)
+{
+	add_annotation(&ctx->annotations[0], AUB_TRACE_TYPE_BATCH, 0, size);
+}
+
+static void annotation_add_state(struct annotations_context *ctx,
+				 uint32_t state_type,
+				 uint32_t start_offset,
+				 size_t   size)
+{
+	assert(ctx->index < MAX_ANNOTATIONS);
+
+	add_annotation(&ctx->annotations[ctx->index++],
+		       AUB_TRACE_TYPE_NOTYPE, 0,
+		       start_offset);
+	add_annotation(&ctx->annotations[ctx->index++],
+		       AUB_TRACE_TYPE(state_type),
+		       AUB_TRACE_SUBTYPE(state_type),
+		       start_offset + size);
+}
+
+static void annotation_flush(struct annotations_context *ctx,
+			     struct intel_batchbuffer *batch)
+{
+	if (!igt_aub_dump_enabled())
+		return;
+
+	drm_intel_bufmgr_gem_set_aub_annotations(batch->bo,
+						 ctx->annotations,
+						 ctx->index);
+}
+
+static uint32_t
+batch_used(struct intel_batchbuffer *batch)
+{
+	return batch->ptr - batch->buffer;
+}
+
+static uint32_t
+batch_align(struct intel_batchbuffer *batch, uint32_t align)
+{
+	uint32_t offset = batch_used(batch);
+	offset = ALIGN(offset, align);
+	batch->ptr = batch->buffer + offset;
+	return offset;
+}
+
+static void *
+batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
+{
+	uint32_t offset = batch_align(batch, align);
+	batch->ptr += size;
+	return memset(batch->buffer + offset, 0, size);
+}
+
+static uint32_t
+batch_offset(struct intel_batchbuffer *batch, void *ptr)
+{
+	return (uint8_t *)ptr - batch->buffer;
+}
+
+static uint32_t
+batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
+{
+	return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
+}
+
+static void
+gen6_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
+{
+	int ret;
+
+	ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
+	if (ret == 0)
+		ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
+					    NULL, 0, 0, 0);
+	assert(ret == 0);
+}
+
+/* Mostly copy+paste from gen6, except height, width, pitch moved */
+static uint32_t
+gen8_bind_buf(struct intel_batchbuffer *batch, struct igt_buf *buf,
+	      uint32_t format, int is_dst) {
+	struct gen8_surface_state *ss;
+	uint32_t write_domain, read_domain, offset;
+	int ret;
+
+	if (is_dst) {
+		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domain = I915_GEM_DOMAIN_SAMPLER;
+	}
+
+	ss = batch_alloc(batch, sizeof(*ss), 64);
+	offset = batch_offset(batch, ss);
+	annotation_add_state(&aub_annotations, AUB_TRACE_SURFACE_STATE,
+			     offset, sizeof(*ss));
+
+	ss->ss0.surface_type = GEN6_SURFACE_2D;
+	ss->ss0.surface_format = format;
+	ss->ss0.render_cache_read_write = 1;
+	ss->ss0.vertical_alignment = 1; /* align 4 */
+	ss->ss0.horizontal_alignment = 1; /* align 4 */
+	if (buf->tiling == I915_TILING_X)
+		ss->ss0.tiled_mode = 2;
+	else if (buf->tiling == I915_TILING_Y)
+		ss->ss0.tiled_mode = 3;
+
+	ss->ss8.base_addr = buf->bo->offset;
+
+	ret = drm_intel_bo_emit_reloc(batch->bo,
+				      batch_offset(batch, ss) + 8 * 4,
+				      buf->bo, 0,
+				      read_domain, write_domain);
+	assert(ret == 0);
+
+	ss->ss2.height = igt_buf_height(buf) - 1;
+	ss->ss2.width  = igt_buf_width(buf) - 1;
+	ss->ss3.pitch  = buf->stride - 1;
+
+	ss->ss7.shader_chanel_select_r = 4;
+	ss->ss7.shader_chanel_select_g = 5;
+	ss->ss7.shader_chanel_select_b = 6;
+	ss->ss7.shader_chanel_select_a = 7;
+
+	return offset;
+}
+
+static uint32_t
+gen8_bind_surfaces(struct intel_batchbuffer *batch,
+		   struct igt_buf *src,
+		   struct igt_buf *dst)
+{
+	uint32_t *binding_table, offset;
+
+	binding_table = batch_alloc(batch, 8, 32);
+	offset = batch_offset(batch, binding_table);
+	annotation_add_state(&aub_annotations, AUB_TRACE_BINDING_TABLE,
+			     offset, 8);
+
+	binding_table[0] =
+		gen8_bind_buf(batch, dst, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 1);
+	binding_table[1] =
+		gen8_bind_buf(batch, src, GEN6_SURFACEFORMAT_B8G8R8A8_UNORM, 0);
+
+	return offset;
+}
+
+/* Mostly copy+paste from gen6, except wrap modes moved */
+static uint32_t
+gen8_create_sampler(struct intel_batchbuffer *batch) {
+	struct gen8_sampler_state *ss;
+	uint32_t offset;
+
+	ss = batch_alloc(batch, sizeof(*ss), 64);
+	offset = batch_offset(batch, ss);
+	annotation_add_state(&aub_annotations, AUB_TRACE_SAMPLER_STATE,
+			     offset, sizeof(*ss));
+
+	ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
+	ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+	ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+	ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+	ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+
+	/* I've experimented with non-normalized coordinates and using the LD
+	 * sampler fetch, but couldn't make it work. */
+	ss->ss3.non_normalized_coord = 0;
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_ps(struct intel_batchbuffer *batch,
+	     const uint32_t kernel[][4],
+	     size_t size)
+{
+	uint32_t offset;
+
+	offset = batch_copy(batch, kernel, size, 64);
+	annotation_add_state(&aub_annotations, AUB_TRACE_KERNEL_INSTRUCTIONS,
+			     offset, size);
+
+	return offset;
+}
+
+/**
+ * gen7_fill_vertex_buffer_data populate vertex buffer with data.
+ *
+ * The vertex buffer consists of 3 vertices to construct a RECTLIST. The 4th
+ * vertex is implied (automatically derived by the HW). Each element has the
+ * destination offset, and the normalized texture offset (src). The rectangle
+ * itself will span the entire subsurface to be copied.
+ *
+ * see gen6_emit_vertex_elements
+ */
+static uint32_t
+gen7_fill_vertex_buffer_data(struct intel_batchbuffer *batch,
+			     struct igt_buf *src,
+			     uint32_t src_x, uint32_t src_y,
+			     uint32_t dst_x, uint32_t dst_y,
+			     uint32_t width, uint32_t height)
+{
+	void *start;
+	uint32_t offset;
+
+	batch_align(batch, 8);
+	start = batch->ptr;
+
+	emit_vertex_2s(batch, dst_x + width, dst_y + height);
+	emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
+	emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
+
+	emit_vertex_2s(batch, dst_x, dst_y + height);
+	emit_vertex_normalized(batch, src_x, igt_buf_width(src));
+	emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
+
+	emit_vertex_2s(batch, dst_x, dst_y);
+	emit_vertex_normalized(batch, src_x, igt_buf_width(src));
+	emit_vertex_normalized(batch, src_y, igt_buf_height(src));
+
+	offset = batch_offset(batch, start);
+	annotation_add_state(&aub_annotations, AUB_TRACE_VERTEX_BUFFER,
+			     offset, 3 * VERTEX_SIZE);
+	return offset;
+}
+
+/**
+ * gen6_emit_vertex_elements - The vertex elements describe the contents of the
+ * vertex buffer. We pack the vertex buffer in a semi weird way, conforming to
+ * what gen6_rendercopy did. The most straightforward would be to store
+ * everything as floats.
+ *
+ * see gen7_fill_vertex_buffer_data() for where the corresponding elements are
+ * packed.
+ */
+static void
+gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
+	/*
+	 * The VUE layout
+	 *    dword 0-3: pad (0, 0, 0. 0)
+	 *    dword 4-7: position (x, y, 0, 1.0),
+	 *    dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0)
+	 */
+	OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
+
+	/* Element state 0. These are 4 dwords of 0 required for the VUE format.
+	 * We don't really know or care what they do.
+	 */
+	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+		  GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
+		  0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */
+	OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+
+	/* Element state 1 - Our "destination" vertices. These are passed down
+	 * through the pipeline, and eventually make it to the pixel shader as
+	 * the offsets in the destination surface. It's packed as the 16
+	 * signed/scaled because of gen6 rendercopy. I see no particular reason
+	 * for doing this though.
+	 */
+	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+		  GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+		  0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
+	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+
+	/* Element state 2. Last but not least we store the U,V components as
+	 * normalized floats. These will be used in the pixel shader to sample
+	 * from the source buffer.
+	 */
+	OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+		  GEN6_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
+		  4 << VE0_OFFSET_SHIFT);	/* offset vb in bytes */
+	OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+		  GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+}
+
+/**
+ * gen7_emit_vertex_buffer emit the vertex buffers command
+ *
+ * @batch
+ * @offset - bytw offset within the @batch where the vertex buffer starts.
+ */
+static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
+				    uint32_t offset) {
+	OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
+	OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
+		  GEN7_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */
+		  VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
+	OUT_BATCH(0);
+	OUT_BATCH(3 * VERTEX_SIZE);
+}
+
+static uint32_t
+gen6_create_cc_state(struct intel_batchbuffer *batch)
+{
+	struct gen6_color_calc_state *cc_state;
+	uint32_t offset;
+
+	cc_state = batch_alloc(batch, sizeof(*cc_state), 64);
+	offset = batch_offset(batch, cc_state);
+	annotation_add_state(&aub_annotations, AUB_TRACE_CC_STATE,
+			     offset, sizeof(*cc_state));
+
+	return offset;
+}
+
+static uint32_t
+gen8_create_blend_state(struct intel_batchbuffer *batch)
+{
+	struct gen8_blend_state *blend;
+	int i;
+	uint32_t offset;
+
+	blend = batch_alloc(batch, sizeof(*blend), 64);
+	offset = batch_offset(batch, blend);
+	annotation_add_state(&aub_annotations, AUB_TRACE_BLEND_STATE,
+			     offset, sizeof(*blend));
+
+	for (i = 0; i < 16; i++) {
+		blend->bs[i].dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
+		blend->bs[i].source_blend_factor = GEN6_BLENDFACTOR_ONE;
+		blend->bs[i].color_blend_func = GEN6_BLENDFUNCTION_ADD;
+		blend->bs[i].pre_blend_color_clamp = 1;
+		blend->bs[i].color_buffer_blend = 0;
+	}
+
+	return offset;
+}
+
+static uint32_t
+gen6_create_cc_viewport(struct intel_batchbuffer *batch)
+{
+	struct gen6_cc_viewport *vp;
+	uint32_t offset;
+
+	vp = batch_alloc(batch, sizeof(*vp), 32);
+	offset = batch_offset(batch, vp);
+	annotation_add_state(&aub_annotations, AUB_TRACE_CC_VP_STATE,
+			     offset, sizeof(*vp));
+
+	/* XXX I don't understand this */
+	vp->min_depth = -1.e35;
+	vp->max_depth = 1.e35;
+
+	return offset;
+}
+
+static uint32_t
+gen7_create_sf_clip_viewport(struct intel_batchbuffer *batch) {
+	/* XXX these are likely not needed */
+	struct gen7_sf_clip_viewport *scv_state;
+	uint32_t offset;
+
+	scv_state = batch_alloc(batch, sizeof(*scv_state), 64);
+	offset = batch_offset(batch, scv_state);
+	annotation_add_state(&aub_annotations, AUB_TRACE_CLIP_VP_STATE,
+			     offset, sizeof(*scv_state));
+
+	scv_state->guardband.xmin = 0;
+	scv_state->guardband.xmax = 1.0f;
+	scv_state->guardband.ymin = 0;
+	scv_state->guardband.ymax = 1.0f;
+
+	return offset;
+}
+
+static uint32_t
+gen6_create_scissor_rect(struct intel_batchbuffer *batch)
+{
+	struct gen6_scissor_rect *scissor;
+	uint32_t offset;
+
+	scissor = batch_alloc(batch, sizeof(*scissor), 64);
+	offset = batch_offset(batch, scissor);
+	annotation_add_state(&aub_annotations, AUB_TRACE_SCISSOR_STATE,
+			     offset, sizeof(*scissor));
+
+	return offset;
+}
+
+static void
+gen6_emit_sip(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN6_STATE_SIP | 0);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_push_constants(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS);
+	OUT_BATCH(0);
+	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS);
+	OUT_BATCH(0);
+	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS);
+	OUT_BATCH(0);
+	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS);
+	OUT_BATCH(0);
+	OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS);
+	OUT_BATCH(0);
+}
+
+static void
+gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
+
+	/* general */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* stateless data port */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
+
+	/* surface */
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* dynamic */
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
+		  0, BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* indirect */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	/* instruction */
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* general state buffer size */
+	OUT_BATCH(0xfffff000 | 1);
+	/* dynamic state buffer size */
+	OUT_BATCH(1 << 12 | 1);
+	/* indirect object buffer size */
+	OUT_BATCH(0xfffff000 | 1);
+	/* intruction buffer size */
+	OUT_BATCH(1 << 12);
+}
+
+static void
+gen7_emit_urb(struct intel_batchbuffer *batch) {
+	/* XXX: Min valid values from mesa */
+	const int vs_entries = 64;
+	const int vs_size = 2;
+	const int vs_start = 2;
+
+	OUT_BATCH(GEN7_3DSTATE_URB_VS);
+	OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
+	OUT_BATCH(GEN7_3DSTATE_URB_GS);
+	OUT_BATCH(vs_start << 25);
+	OUT_BATCH(GEN7_3DSTATE_URB_HS);
+	OUT_BATCH(vs_start << 25);
+	OUT_BATCH(GEN7_3DSTATE_URB_DS);
+	OUT_BATCH(vs_start << 25);
+}
+
+static void
+gen8_emit_cc(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS);
+	OUT_BATCH(cc.blend_state | 1);
+
+	OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS);
+	OUT_BATCH(cc.cc_state | 1);
+}
+
+static void
+gen8_emit_multisample(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE | 2);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK);
+	OUT_BATCH(1);
+}
+
+static void
+gen7_emit_vs(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_VS | (6-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_hs(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_HS | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_gs(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_GS | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_ds(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_DS | (6-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_null_state(struct intel_batchbuffer *batch) {
+	gen7_emit_hs(batch);
+	OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	gen7_emit_gs(batch);
+	gen7_emit_ds(batch);
+	gen7_emit_vs(batch);
+}
+
+static void
+gen7_emit_clip(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0); /*  pass-through */
+	OUT_BATCH(0);
+}
+
+static void
+gen8_emit_sf(struct intel_batchbuffer *batch)
+{
+	int i;
+
+	OUT_BATCH(GEN7_3DSTATE_SBE | (4 - 2));
+	OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
+		  GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
+		  GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET |
+		  1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
+		  1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN8_3DSTATE_SBE_SWIZ | (11 - 2));
+	for (i = 0; i < 8; i++)
+		OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN8_3DSTATE_RASTER | (5 - 2));
+	OUT_BATCH(GEN8_RASTER_FRONT_WINDING_CCW | GEN8_RASTER_CULL_NONE);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void
+gen8_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel) {
+	const int max_threads = 63;
+
+	OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2));
+	OUT_BATCH(/* XXX: I don't understand the BARYCENTRIC stuff, but it
+		   * appears we need it to put our setup data in the place we
+		   * expect (g6, see below) */
+		  GEN7_3DSTATE_PS_PERSPECTIVE_PIXEL_BARYCENTRIC);
+
+	OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (11-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_PS | (12-2));
+	OUT_BATCH(kernel);
+	OUT_BATCH(0); /* kernel hi */
+	OUT_BATCH(1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT |
+		  2 << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
+	OUT_BATCH(0); /* scratch space stuff */
+	OUT_BATCH(0); /* scratch hi */
+	OUT_BATCH((max_threads - 1) << GEN8_3DSTATE_PS_MAX_THREADS_SHIFT |
+		  GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
+	OUT_BATCH(6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT);
+	OUT_BATCH(0); // kernel 1
+	OUT_BATCH(0); /* kernel 1 hi */
+	OUT_BATCH(0); // kernel 2
+	OUT_BATCH(0); /* kernel 2 hi */
+
+	OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2));
+	OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT);
+
+	OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2));
+	OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID | GEN8_PSX_ATTRIBUTE_ENABLE);
+}
+
+static void
+gen8_emit_depth(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER | (3-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER | (3-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void
+gen7_emit_clear(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3-2));
+	OUT_BATCH(0);
+	OUT_BATCH(1); // clear valid
+}
+
+static void
+gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
+{
+	OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
+	OUT_BATCH(0);
+}
+
+static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY);
+	OUT_BATCH(_3DPRIM_RECTLIST);
+}
+
+/* Vertex elements MUST be defined before this according to spec */
+static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset)
+{
+	OUT_BATCH(GEN8_3DSTATE_VF_INSTANCING | (3 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
+	OUT_BATCH(0);	/* gen8+ ignore the topology type field */
+	OUT_BATCH(3);	/* vertex count */
+	OUT_BATCH(0);	/*  We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */
+	OUT_BATCH(1);	/* single instance */
+	OUT_BATCH(0);	/* start instance location */
+	OUT_BATCH(0);	/* index buffer offset, ignored */
+}
+
+/* The general rule is if it's named gen6 it is directly copied from
+ * gen6_render_copyfunc.
+ *
+ * This sets up most of the 3d pipeline, and most of that to NULL state. The
+ * docs aren't specific about exactly what must be set up NULL, but the general
+ * rule is we could be run at any time, and so the most state we set to NULL,
+ * the better our odds of success.
+ *
+ * +---------------+ <---- 4096
+ * |       ^       |
+ * |       |       |
+ * |    various    |
+ * |      state    |
+ * |       |       |
+ * |_______|_______| <---- 2048 + ?
+ * |       ^       |
+ * |       |       |
+ * |   batch       |
+ * |    commands   |
+ * |       |       |
+ * |       |       |
+ * +---------------+ <---- 0 + ?
+ *
+ * The batch commands point to state within tthe batch, so all state offsets should be
+ * 0 < offset < 4096. Both commands and state build upwards, and are constructed
+ * in that order. This means too many batch commands can delete state if not
+ * careful.
+ *
+ */
+
+#define BATCH_STATE_SPLIT 2048
+
+void gen9_render_copyfunc(struct intel_batchbuffer *batch,
+			  struct igt_buf *src, unsigned src_x, unsigned src_y,
+			  unsigned width, unsigned height,
+			  struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
+{
+	uint32_t ps_sampler_state, ps_kernel_off, ps_binding_table;
+	uint32_t scissor_state;
+	uint32_t vertex_buffer;
+	uint32_t batch_end;
+
+	intel_batchbuffer_flush(batch);
+
+	batch_align(batch, 8);
+
+	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+	annotation_init(&aub_annotations);
+
+	ps_binding_table  = gen8_bind_surfaces(batch, src, dst);
+	ps_sampler_state  = gen8_create_sampler(batch);
+	ps_kernel_off = gen8_fill_ps(batch, ps_kernel, sizeof(ps_kernel));
+	vertex_buffer = gen7_fill_vertex_buffer_data(batch, src,
+						     src_x, src_y,
+						     dst_x, dst_y,
+						     width, height);
+	cc.cc_state = gen6_create_cc_state(batch);
+	cc.blend_state = gen8_create_blend_state(batch);
+	viewport.cc_state = gen6_create_cc_viewport(batch);
+	viewport.sf_clip_state = gen7_create_sf_clip_viewport(batch);
+	scissor_state = gen6_create_scissor_rect(batch);
+	/* TODO: theree is other state which isn't setup */
+
+	assert(batch->ptr < &batch->buffer[4095]);
+
+	batch->ptr = batch->buffer;
+
+	/* Start emitting the commands. The order roughly follows the mesa blorp
+	 * order */
+	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+	gen6_emit_sip(batch);
+
+	gen7_emit_push_constants(batch);
+
+	gen8_emit_state_base_address(batch);
+
+	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC);
+	OUT_BATCH(viewport.cc_state);
+	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP);
+	OUT_BATCH(viewport.sf_clip_state);
+
+	gen7_emit_urb(batch);
+
+	gen8_emit_cc(batch);
+
+	gen8_emit_multisample(batch);
+
+	gen7_emit_null_state(batch);
+
+	OUT_BATCH(GEN7_3DSTATE_STREAMOUT | 1);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	gen7_emit_clip(batch);
+
+	gen8_emit_sf(batch);
+
+	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS);
+	OUT_BATCH(ps_binding_table);
+
+	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS);
+	OUT_BATCH(ps_sampler_state);
+
+	gen8_emit_ps(batch, ps_kernel_off);
+
+	OUT_BATCH(GEN6_3DSTATE_SCISSOR_STATE_POINTERS);
+	OUT_BATCH(scissor_state);
+
+	gen8_emit_depth(batch);
+
+	gen7_emit_clear(batch);
+
+	gen6_emit_drawing_rectangle(batch, dst);
+
+	gen7_emit_vertex_buffer(batch, vertex_buffer);
+	gen6_emit_vertex_elements(batch);
+
+	gen8_emit_vf_topology(batch);
+	gen8_emit_primitive(batch, vertex_buffer);
+
+	OUT_BATCH(MI_BATCH_BUFFER_END);
+
+	batch_end = batch_align(batch, 8);
+	assert(batch_end < BATCH_STATE_SPLIT);
+	annotation_add_batch(&aub_annotations, batch_end);
+
+	dump_batch(batch);
+
+	annotation_flush(&aub_annotations, batch);
+
+	gen6_render_flush(batch, batch_end);
+	intel_batchbuffer_reset(batch);
+}
-- 
1.8.3.1

[PATCH i-g-t 06/26] rendercopy/skl: Set the 3DSTATE_VF state

[Damien Lespiau]

This is to ensure the "Component Packing Enable" bit is set to 0.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 lib/gen9_render.h     | 1 +
 lib/rendercopy_gen9.c | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 170b1fc..6de4a91 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -3,5 +3,6 @@
 
 #include "gen8_render.h"
 
+#define GEN7_3DSTATE_VF				GEN6_3D(3, 0, 0x0c)
 
 #endif
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 97ed541..ae4893f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -19,7 +19,7 @@
 #include "intel_batchbuffer.h"
 #include "intel_io.h"
 #include "rendercopy.h"
-#include "gen8_render.h"
+#include "gen9_render.h"
 #include "intel_reg.h"
 #include "igt_aux.h"
 
@@ -821,6 +821,9 @@ static void gen8_emit_vf_topology(struct intel_batchbuffer *batch)
 /* Vertex elements MUST be defined before this according to spec */
 static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset)
 {
+	OUT_BATCH(GEN7_3DSTATE_VF | (2 - 2));
+	OUT_BATCH(0);
+
 	OUT_BATCH(GEN8_3DSTATE_VF_INSTANCING | (3 - 2));
 	OUT_BATCH(0);
 	OUT_BATCH(0);
-- 
1.8.3.1

[PATCH i-g-t 07/26] rendercopy/skl: Update 3DSTATE_SBE

[Damien Lespiau]

SBE has now to be explicitely told which channels of which components
are used by the pixel shader.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 lib/gen9_render.h     | 5 +++++
 lib/rendercopy_gen9.c | 4 +++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 6de4a91..8d6398c 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -5,4 +5,9 @@
 
 #define GEN7_3DSTATE_VF				GEN6_3D(3, 0, 0x0c)
 
+#define GEN9_SBE_ACTIVE_COMPONENT_NONE		0
+#define GEN9_SBE_ACTIVE_COMPONENT_XY		1
+#define GEN9_SBE_ACTIVE_COMPONENT_XYZ		2
+#define GEN9_SBE_ACTIVE_COMPONENT_XYZW		3
+
 #endif
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index ae4893f..01d5ef3 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -706,7 +706,7 @@ gen8_emit_sf(struct intel_batchbuffer *batch)
 {
 	int i;
 
-	OUT_BATCH(GEN7_3DSTATE_SBE | (4 - 2));
+	OUT_BATCH(GEN7_3DSTATE_SBE | (6 - 2));
 	OUT_BATCH(1 << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 		  GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH |
 		  GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET |
@@ -714,6 +714,8 @@ gen8_emit_sf(struct intel_batchbuffer *batch)
 		  1 << GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
+	OUT_BATCH(GEN9_SBE_ACTIVE_COMPONENT_XYZW << 0);
+	OUT_BATCH(0);
 
 	OUT_BATCH(GEN8_3DSTATE_SBE_SWIZ | (11 - 2));
 	for (i = 0; i < 8; i++)
-- 
1.8.3.1

[PATCH i-g-t 08/26] rendercopy/skl: Pass the context to rendercopy function on SKL

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 lib/rendercopy.h           |  1 +
 lib/rendercopy_gen9.c      | 12 +++++++-----
 tools/intel_error_decode.c |  1 +
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/lib/rendercopy.h b/lib/rendercopy.h
index f15df0e..fdc3cab 100644
--- a/lib/rendercopy.h
+++ b/lib/rendercopy.h
@@ -24,6 +24,7 @@ static inline void emit_vertex_normalized(struct intel_batchbuffer *batch,
 }
 
 void gen9_render_copyfunc(struct intel_batchbuffer *batch,
+			  drm_intel_context *context,
 			  struct igt_buf *src, unsigned src_x, unsigned src_y,
 			  unsigned width, unsigned height,
 			  struct igt_buf *dst, unsigned dst_x, unsigned dst_y);
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 01d5ef3..40f1c6f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -166,14 +166,15 @@ batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint
 }
 
 static void
-gen6_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
+gen6_render_flush(struct intel_batchbuffer *batch,
+		  drm_intel_context *context, uint32_t batch_end)
 {
 	int ret;
 
 	ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
 	if (ret == 0)
-		ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
-					    NULL, 0, 0, 0);
+		ret = drm_intel_gem_bo_context_exec(batch->bo, context,
+						    batch_end, 0);
 	assert(ret == 0);
 }
 
@@ -872,6 +873,7 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
 #define BATCH_STATE_SPLIT 2048
 
 void gen9_render_copyfunc(struct intel_batchbuffer *batch,
+			  drm_intel_context *context,
 			  struct igt_buf *src, unsigned src_x, unsigned src_y,
 			  unsigned width, unsigned height,
 			  struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
@@ -881,7 +883,7 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	uint32_t vertex_buffer;
 	uint32_t batch_end;
 
-	intel_batchbuffer_flush(batch);
+	intel_batchbuffer_flush_with_context(batch, context);
 
 	batch_align(batch, 8);
 
@@ -971,6 +973,6 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 	annotation_flush(&aub_annotations, batch);
 
-	gen6_render_flush(batch, batch_end);
+	gen6_render_flush(batch, context, batch_end);
 	intel_batchbuffer_reset(batch);
 }
diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
index 1eeff07..14589a3 100644
--- a/tools/intel_error_decode.c
+++ b/tools/intel_error_decode.c
@@ -56,6 +56,7 @@
 #include "intel_io.h"
 #include "instdone.h"
 #include "intel_reg.h"
+#include "drmtest.h"
 
 static uint32_t
 print_head(unsigned int reg)
-- 
1.8.3.1

[PATCH i-g-t 09/26] rendercopy/skl: update instruction length

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

This is ported from that on BDW.

v2: Only bump the prefix when we need to program the instruction
differently with the previous generations.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/rendercopy_gen9.c | 89 +++++++++++++++++++++++++++++++++++----------------
 1 file changed, 61 insertions(+), 28 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 40f1c6f..2c769bc 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -490,8 +490,9 @@ gen6_create_scissor_rect(struct intel_batchbuffer *batch)
 }
 
 static void
-gen6_emit_sip(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN6_STATE_SIP | 0);
+gen8_emit_sip(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN6_STATE_SIP | (3 - 2));
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 }
 
@@ -575,9 +576,7 @@ gen8_emit_cc(struct intel_batchbuffer *batch) {
 
 static void
 gen8_emit_multisample(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE | 2);
-	OUT_BATCH(0);
-	OUT_BATCH(0);
+	OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE | 0);
 	OUT_BATCH(0);
 
 	OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK);
@@ -585,14 +584,18 @@ gen8_emit_multisample(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen7_emit_vs(struct intel_batchbuffer *batch) {
+gen8_emit_vs(struct intel_batchbuffer *batch) {
 	OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS);
 	OUT_BATCH(0);
 
 	OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (7-2));
+	OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (11-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -600,7 +603,10 @@ gen7_emit_vs(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN6_3DSTATE_VS | (6-2));
+	OUT_BATCH(GEN6_3DSTATE_VS | (9-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -609,8 +615,12 @@ gen7_emit_vs(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen7_emit_hs(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7-2));
+gen8_emit_hs(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (11-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -618,7 +628,9 @@ gen7_emit_hs(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN7_3DSTATE_HS | (7-2));
+	OUT_BATCH(GEN7_3DSTATE_HS | (9-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -634,8 +646,12 @@ gen7_emit_hs(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen7_emit_gs(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (7-2));
+gen8_emit_gs(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (11-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -643,7 +659,10 @@ gen7_emit_gs(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN7_3DSTATE_GS | (7-2));
+	OUT_BATCH(GEN7_3DSTATE_GS | (10-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -659,8 +678,12 @@ gen7_emit_gs(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen7_emit_ds(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7-2));
+gen8_emit_ds(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (11-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -668,7 +691,10 @@ gen7_emit_ds(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN7_3DSTATE_DS | (6-2));
+	OUT_BATCH(GEN7_3DSTATE_DS | (9-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -683,15 +709,15 @@ gen7_emit_ds(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen7_emit_null_state(struct intel_batchbuffer *batch) {
-	gen7_emit_hs(batch);
+gen8_emit_null_state(struct intel_batchbuffer *batch) {
+	gen8_emit_hs(batch);
 	OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
-	gen7_emit_gs(batch);
-	gen7_emit_ds(batch);
-	gen7_emit_vs(batch);
+	gen8_emit_gs(batch);
+	gen8_emit_ds(batch);
+	gen8_emit_vs(batch);
 }
 
 static void
@@ -782,7 +808,8 @@ gen8_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel) {
 
 static void
 gen8_emit_depth(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7-2));
+	OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (8-2));
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -790,11 +817,15 @@ gen8_emit_depth(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER | (3-2));
+	OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER | (5-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER | (3-2));
+	OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER | (5-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 }
@@ -913,7 +944,7 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 	 * order */
 	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
 
-	gen6_emit_sip(batch);
+	gen8_emit_sip(batch);
 
 	gen7_emit_push_constants(batch);
 
@@ -930,9 +961,11 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 	gen8_emit_multisample(batch);
 
-	gen7_emit_null_state(batch);
+	gen8_emit_null_state(batch);
 
-	OUT_BATCH(GEN7_3DSTATE_STREAMOUT | 1);
+	OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (5 - 2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-- 
1.8.3.1

[PATCH i-g-t 10/26] rendercopy/skl: Set Instruction Buffer size Modify Enable to 1

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

This is ported from that on BDW.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/rendercopy_gen9.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 2c769bc..dce63ae 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -545,7 +545,7 @@ gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
 	/* indirect object buffer size */
 	OUT_BATCH(0xfffff000 | 1);
 	/* intruction buffer size */
-	OUT_BATCH(1 << 12);
+	OUT_BATCH(1 << 12 | 1);
 }
 
 static void
-- 
1.8.3.1

[PATCH i-g-t 11/26] rendercopy/skl: Fix the STATE_BASE_ADDRESS instruction length

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/rendercopy_gen9.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index dce63ae..f98019e 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -511,8 +511,8 @@ gen7_emit_push_constants(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
-	OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
+gen9_emit_state_base_address(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (19 - 2));
 
 	/* general */
 	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
@@ -546,6 +546,11 @@ gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0xfffff000 | 1);
 	/* intruction buffer size */
 	OUT_BATCH(1 << 12 | 1);
+
+	/* Bindless surface state base address */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+	OUT_BATCH(0xfffff000);
 }
 
 static void
@@ -948,7 +953,7 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 	gen7_emit_push_constants(batch);
 
-	gen8_emit_state_base_address(batch);
+	gen9_emit_state_base_address(batch);
 
 	OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC);
 	OUT_BATCH(viewport.cc_state);
-- 
1.8.3.1

[PATCH i-g-t 12/26] rendercopy/skl: Fix the 3DSTATE_DS instruction length

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/rendercopy_gen9.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index f98019e..1aacaa2 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -683,7 +683,7 @@ gen8_emit_gs(struct intel_batchbuffer *batch) {
 }
 
 static void
-gen8_emit_ds(struct intel_batchbuffer *batch) {
+gen9_emit_ds(struct intel_batchbuffer *batch) {
 	OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (11-2));
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -696,7 +696,9 @@ gen8_emit_ds(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 
-	OUT_BATCH(GEN7_3DSTATE_DS | (9-2));
+	OUT_BATCH(GEN7_3DSTATE_DS | (11-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	OUT_BATCH(0);
@@ -721,7 +723,7 @@ gen8_emit_null_state(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 	OUT_BATCH(0);
 	gen8_emit_gs(batch);
-	gen8_emit_ds(batch);
+	gen9_emit_ds(batch);
 	gen8_emit_vs(batch);
 }
 
-- 
1.8.3.1

[PATCH i-g-t 13/26] rendercopy/skl: Emit 3DSTATE_WM_HZ_OP

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

This is from that on BDW. Without it, the pixel pipeline can't work well.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/rendercopy_gen9.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 1aacaa2..52fc90f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -715,8 +715,19 @@ gen9_emit_ds(struct intel_batchbuffer *batch) {
 	OUT_BATCH(0);
 }
 
+
+static void
+gen8_emit_wm_hz_op(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
 static void
 gen8_emit_null_state(struct intel_batchbuffer *batch) {
+	gen8_emit_wm_hz_op(batch);
 	gen8_emit_hs(batch);
 	OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
 	OUT_BATCH(0);
-- 
1.8.3.1

[PATCH i-g-t 14/26] rendercopy/skl: Follow the spec to add the Pipeline selection mask

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/gen9_render.h     | 2 ++
 lib/rendercopy_gen9.c | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 8d6398c..2cd7530 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -10,4 +10,6 @@
 #define GEN9_SBE_ACTIVE_COMPONENT_XYZ		2
 #define GEN9_SBE_ACTIVE_COMPONENT_XYZW		3
 
+#define GEN9_PIPELINE_SELECTION_MASK		(3 << 8)
+
 #endif
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 52fc90f..8621f7f 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -960,7 +960,8 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
 
 	/* Start emitting the commands. The order roughly follows the mesa blorp
 	 * order */
-	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+	OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D |
+				GEN9_PIPELINE_SELECTION_MASK);
 
 	gen8_emit_sip(batch);
 
-- 
1.8.3.1

[PATCH i-g-t 15/26] rendercopy/skl: Set the URB VS start address to 4

[Damien Lespiau]

From: "Xiang, Haihao" <haihao.xiang@intel.com>

A value less than 4 might result in GPU hang on simulation

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/rendercopy_gen9.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 8621f7f..92265c1 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -558,7 +558,7 @@ gen7_emit_urb(struct intel_batchbuffer *batch) {
 	/* XXX: Min valid values from mesa */
 	const int vs_entries = 64;
 	const int vs_size = 2;
-	const int vs_start = 2;
+	const int vs_start = 4;
 
 	OUT_BATCH(GEN7_3DSTATE_URB_VS);
 	OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25));
-- 
1.8.3.1

[PATCH i-g-t 16/26] assembler/skl: Add gen 9 to the -g option

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 assembler/disasm-main.c | 4 ++--
 assembler/main.c        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/assembler/disasm-main.c b/assembler/disasm-main.c
index 5e4cb0e..b365556 100644
--- a/assembler/disasm-main.c
+++ b/assembler/disasm-main.c
@@ -100,7 +100,7 @@ static void usage(void)
     fprintf(stderr, "usage: intel-gen4disasm [options] inputfile\n");
     fprintf(stderr, "\t-b, --binary                         C style binary output\n");
     fprintf(stderr, "\t-o, --output {outputfile}            Specify output file\n");
-    fprintf(stderr, "\t-g, --gen <4|5|6|7|8>                Specify GPU generation\n");
+    fprintf(stderr, "\t-g, --gen <4|5|6|7|8|9>              Specify GPU generation\n");
 }
 
 int main(int argc, char **argv)
@@ -127,7 +127,7 @@ int main(int argc, char **argv)
 	case 'g':
 	    gen = strtol(optarg, NULL, 10);
 
-	    if (gen < 4 || gen > 8) {
+	    if (gen < 4 || gen > 9) {
 		    usage();
 		    exit(1);
 	    }
diff --git a/assembler/main.c b/assembler/main.c
index 469406a..a1eca52 100644
--- a/assembler/main.c
+++ b/assembler/main.c
@@ -97,7 +97,7 @@ static void usage(void)
 	fprintf(stderr, "\t-e, --export {exportfile}            Export label file\n");
 	fprintf(stderr, "\t-l, --input_list {entrytablefile}    Input entry_table_list file\n");
 	fprintf(stderr, "\t-o, --output {outputfile}            Specify output file\n");
-	fprintf(stderr, "\t-g, --gen <4|5|6|7|8>                Specify GPU generation\n");
+	fprintf(stderr, "\t-g, --gen <4|5|6|7|8|9>              Specify GPU generation\n");
 }
 
 static int hash(char *key)
@@ -311,7 +311,7 @@ int main(int argc, char **argv)
 				}
 			}
 
-			if (gen_level < 40 || gen_level > 80) {
+			if (gen_level < 40 || gen_level > 90) {
 				usage();
 				exit(1);
 			}
-- 
1.8.3.1

[PATCH i-g-t 17/26] assembler/skl: Redefine the cache agent type for some fixed functions

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

The different cache agent type is defined for SKL although it still uses
the same function ID as the previous generations.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 assembler/brw_defines.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/assembler/brw_defines.h b/assembler/brw_defines.h
index f74342c..6ca3e17 100644
--- a/assembler/brw_defines.h
+++ b/assembler/brw_defines.h
@@ -880,6 +880,13 @@ enum brw_message_target {
 
    HSW_SFID_DATAPORT_DATA_CACHE1     = 0x0c,
    HSW_SFID_CRE                      = 0x0d,
+
+   /* There is no Sampler data port cache(0x04) on SKL and it is used
+    * as the extension of DP_DC0/DP_DC1.
+    */
+   SKL_SFID_DATAPORT_DATA_CACHE2     = 0x4,
+   /* Data Read only Data port cache */
+   SKL_SFID_DATAPORT_DCR0            = 0x9,
 };
 
 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
-- 
1.8.3.1

[PATCH i-g-t 18/26] assembler/skl: update read(...)

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

READ(...) is used for Render Target read and Media Block read. But there is no
sampler cache agent on gen9. At the same time two message types don't
share the same cache agent any more. So a parameter is needed for cache agent.
The 2th parameter of read(...) is not used for gen6/gen7/gen8. Hence it is
reused as cache agent for SKL as that on ILK.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 assembler/gram.y | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/assembler/gram.y b/assembler/gram.y
index e56533d..157ce79 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -1609,7 +1609,27 @@ msgtarget:	NULL_TOKEN
 		| READ  LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA
                 INTEGER RPAREN
 		{
-		  if (IS_GENp(8)) {
+                  if (IS_GENp(9)) {
+                      if ($5 != 0 &&
+			  $5 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
+			  $5 != GEN7_SFID_DATAPORT_DATA_CACHE &&
+			  $5 != HSW_SFID_DATAPORT_DATA_CACHE1 &&
+			  $5 != SKL_SFID_DATAPORT_DCR0 &&
+			  $5 != SKL_SFID_DATAPORT_DATA_CACHE2) {
+			  error (&@9, "error: wrong cache type\n");
+		      }
+
+		      if ($5 == 0)
+			  gen8_set_sfid(GEN8(&$$), HSW_SFID_DATAPORT_DATA_CACHE1);
+		      else
+			  gen8_set_sfid(GEN8(&$$), $5);
+
+                      gen8_set_header_present(GEN8(&$$), 1);
+                      gen8_set_dp_binding_table_index(GEN8(&$$), $3);
+                      gen8_set_dp_message_control(GEN8(&$$), $7);
+                      gen8_set_dp_message_type(GEN8(&$$), $9);
+                      gen8_set_dp_category(GEN8(&$$), 0);
+                  } else if (IS_GENp(8)) {
                       gen8_set_sfid(GEN8(&$$), GEN6_SFID_DATAPORT_SAMPLER_CACHE);
                       gen8_set_header_present(GEN8(&$$), 1);
                       gen8_set_dp_binding_table_index(GEN8(&$$), $3);
-- 
1.8.3.1

[PATCH i-g-t 19/26] assembler/skl: Add more cache agent for write(...)

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 assembler/gram.y | 40 ++++++++++++++++++++++++++++++----------
 1 file changed, 30 insertions(+), 10 deletions(-)

diff --git a/assembler/gram.y b/assembler/gram.y
index 157ce79..9689352 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -1671,11 +1671,21 @@ msgtarget:	NULL_TOKEN
 		INTEGER RPAREN
 		{
 		  if (IS_GENp(8)) {
-                      if ($9 != 0 &&
-			  $9 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
-			  $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
-			  $9 != HSW_SFID_DATAPORT_DATA_CACHE1) {
-			  error (&@9, "error: wrong cache type\n");
+                      if (IS_GENp(9)) {
+                          if ($9 != 0 &&
+			      $9 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
+			      $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
+			      $9 != HSW_SFID_DATAPORT_DATA_CACHE1 &&
+			      $9 != SKL_SFID_DATAPORT_DATA_CACHE2) {
+			      error (&@9, "error: wrong cache type\n");
+                          }
+                      } else {
+                          if ($9 != 0 &&
+			      $9 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
+			      $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
+			      $9 != HSW_SFID_DATAPORT_DATA_CACHE1) {
+			      error (&@9, "error: wrong cache type\n");
+                          }
 		      }
 
 		      if ($9 == 0)
@@ -1732,11 +1742,21 @@ msgtarget:	NULL_TOKEN
 		INTEGER COMMA INTEGER RPAREN
 		{
 		  if (IS_GENp(8)) {
-                      if ($9 != 0 &&
-			  $9 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
-			  $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
-			  $9 != HSW_SFID_DATAPORT_DATA_CACHE1) {
-			  error (&@9, "error: wrong cache type\n");
+                      if (IS_GENp(9)) {
+                          if ($9 != 0 &&
+			      $9 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
+			      $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
+			      $9 != HSW_SFID_DATAPORT_DATA_CACHE1 &&
+			      $9 != SKL_SFID_DATAPORT_DATA_CACHE2) {
+			      error (&@9, "error: wrong cache type\n");
+                          }
+                      } else {
+                          if ($9 != 0 &&
+			      $9 != GEN6_SFID_DATAPORT_RENDER_CACHE &&
+			      $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
+			      $9 != HSW_SFID_DATAPORT_DATA_CACHE1) {
+			      error (&@9, "error: wrong cache type\n");
+                          }
 		      }
 
 		      if ($9 == 0)
-- 
1.8.3.1

[PATCH i-g-t 20/26] assembler/skl: update the extdesc field for SEND instruction

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate
for the extended message descriptors. And some bits of SEND instruction are defined
as the extdesc field.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 assembler/brw_defines.h      |  2 ++
 assembler/gen8_instruction.c | 20 ++++++++++++++++++++
 assembler/gen8_instruction.h |  2 ++
 assembler/gram.y             | 16 ++++++++++++++--
 4 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/assembler/brw_defines.h b/assembler/brw_defines.h
index 6ca3e17..24e5e30 100644
--- a/assembler/brw_defines.h
+++ b/assembler/brw_defines.h
@@ -1647,4 +1647,6 @@ enum brw_wm_barycentric_interp_mode {
 #define EX_DESC_SFID_MASK 0xF
 #define EX_DESC_EOT_MASK  0x20
 
+#define EX_DESC_FUNC_MASK 0xFFFFFFC0
+
 #endif
diff --git a/assembler/gen8_instruction.c b/assembler/gen8_instruction.c
index 31c15ca..fe0067e 100644
--- a/assembler/gen8_instruction.c
+++ b/assembler/gen8_instruction.c
@@ -423,3 +423,23 @@ gen8_set_dp_message(struct gen8_instruction *inst,
    gen8_set_function_control(inst,
          binding_table_index | msg_type << 14 | msg_control << 8);
 }
+
+
+void
+gen9_set_send_extdesc(struct gen8_instruction *inst,
+		     unsigned int value)
+{
+   unsigned int extdesc;
+
+   extdesc = (value >> 16) & 0x0f;
+   gen8_set_bits(inst, 67, 64, extdesc);
+
+   extdesc = (value >> 20) & 0x0f;
+   gen8_set_bits(inst, 83, 80, extdesc);
+
+   extdesc = (value >> 24) & 0x0f;
+   gen8_set_bits(inst, 88, 85, extdesc);
+
+   extdesc = (value >> 28) & 0x0f;
+   gen8_set_bits(inst, 94, 91, extdesc);
+}
diff --git a/assembler/gen8_instruction.h b/assembler/gen8_instruction.h
index 5e72e45..7db4746 100644
--- a/assembler/gen8_instruction.h
+++ b/assembler/gen8_instruction.h
@@ -357,4 +357,6 @@ gen8_set_bits(struct gen8_instruction *insn,
    insn->data[word] = (insn->data[word] & ~mask) | ((value << low) & mask);
 }
 
+void gen9_set_send_extdesc(struct gen8_instruction *insn, unsigned int value);
+
 #endif
diff --git a/assembler/gram.y b/assembler/gram.y
index 9689352..23e1a57 100644
--- a/assembler/gram.y
+++ b/assembler/gram.y
@@ -1190,7 +1190,11 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
                           YYERROR;
 		  }
 
-		  if (IS_GENp(8)) {
+		  if (IS_GENp(9)) {
+		      gen8_set_src1_reg_file(GEN8(&$$), BRW_IMMEDIATE_VALUE);
+		      gen8_set_src1_reg_type(GEN8(&$$), BRW_REGISTER_TYPE_D);
+		      gen9_set_send_extdesc(GEN8(&$$), 0);
+		  } else if (IS_GENp(8)) {
 		      gen8_set_src1_reg_file(GEN8(&$$), BRW_IMMEDIATE_VALUE);
 		      gen8_set_src1_reg_type(GEN8(&$$), BRW_REGISTER_TYPE_D);
 		  } else {
@@ -1308,7 +1312,11 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
                   set_instruction_src0(&$$, &src0, NULL);
 		  set_instruction_src1(&$$, &$7, NULL);
 
-                  if (IS_GENp(8)) {
+                  if (IS_GENp(9)) {
+                      gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK);
+                      gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK));
+                      gen9_set_send_extdesc(GEN8(&$$), $6 & EX_DESC_FUNC_MASK);
+                  } else if (IS_GENp(8)) {
                       gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK);
                       gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK));
 		  } else {
@@ -1358,6 +1366,10 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget
                   if (IS_GENp(8)) {
                       gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK);
                       gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK));
+                      gen9_set_send_extdesc(GEN8(&$$), $6 & EX_DESC_FUNC_MASK);
+		  } else if (IS_GENp(8)) {
+                      gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK);
+                      gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK));
 		  } else {
                       GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */
                       GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK);
-- 
1.8.3.1

[PATCH i-g-t 21/26] mediafill/skl: Start the gen9 media_fill from the gen8 version

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/Makefile.sources  |   1 +
 lib/media_fill.c      |  16 +++
 lib/media_fill.h      |   7 +
 lib/media_fill_gen9.c | 378 ++++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 402 insertions(+)
 create mode 100644 lib/media_fill.c
 create mode 100644 lib/media_fill_gen9.c

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 82e306d..eee145f 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -26,6 +26,7 @@ libintel_tools_la_SOURCES = 	\
 	media_fill_gen7.c       \
 	media_fill_gen8.c       \
 	media_fill_gen8lp.c     \
+	media_fill_gen9.c       \
 	gen7_media.h            \
 	gen8_media.h            \
 	rendercopy_i915.c	\
diff --git a/lib/media_fill.c b/lib/media_fill.c
new file mode 100644
index 0000000..1d212b8
--- /dev/null
+++ b/lib/media_fill.c
@@ -0,0 +1,16 @@
+#include "i830_reg.h"
+#include "media_fill.h"
+
+media_fillfunc_t get_media_fillfunc(int devid)
+{
+	media_fillfunc_t fill = NULL;
+
+	if (IS_GEN8(devid))
+		fill = gen8_media_fillfunc;
+	else if (IS_GEN7(devid))
+		fill = gen7_media_fillfunc;
+	else if (IS_GEN9(devid))
+		fill = gen9_media_fillfunc;
+
+	return fill;
+}
diff --git a/lib/media_fill.h b/lib/media_fill.h
index ca35aeb..226489c 100644
--- a/lib/media_fill.h
+++ b/lib/media_fill.h
@@ -25,4 +25,11 @@ gen8lp_media_fillfunc(struct intel_batchbuffer *batch,
 		unsigned width, unsigned height,
 		uint8_t color);
 
+void
+gen9_media_fillfunc(struct intel_batchbuffer *batch,
+                struct igt_buf *dst,
+                unsigned x, unsigned y,
+                unsigned width, unsigned height,
+                uint8_t color);
+
 #endif /* RENDE_MEDIA_FILL_H */
diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
new file mode 100644
index 0000000..98e2403
--- /dev/null
+++ b/lib/media_fill_gen9.c
@@ -0,0 +1,378 @@
+#include <intel_bufmgr.h>
+#include <i915_drm.h>
+
+#include "media_fill.h"
+#include "gen8_media.h"
+#include "intel_reg.h"
+
+#include <assert.h>
+
+#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
+
+static const uint32_t media_kernel[][4] = {
+	{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
+	{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
+	{ 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
+	{ 0x00000001, 0x20880608, 0x00000000, 0x000f000f },
+	{ 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
+	{ 0x00800001, 0x20e00208, 0x00000020, 0x00000000 },
+	{ 0x00800001, 0x21200208, 0x00000020, 0x00000000 },
+	{ 0x00800001, 0x21600208, 0x00000020, 0x00000000 },
+	{ 0x0c800031, 0x24000a40, 0x0e000080, 0x120a8000 },
+	{ 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
+	{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
+};
+
+static uint32_t
+batch_used(struct intel_batchbuffer *batch)
+{
+	return batch->ptr - batch->buffer;
+}
+
+static uint32_t
+batch_align(struct intel_batchbuffer *batch, uint32_t align)
+{
+	uint32_t offset = batch_used(batch);
+	offset = ALIGN(offset, align);
+	batch->ptr = batch->buffer + offset;
+	return offset;
+}
+
+static void *
+batch_alloc(struct intel_batchbuffer *batch, uint32_t size, uint32_t align)
+{
+	uint32_t offset = batch_align(batch, align);
+	batch->ptr += size;
+	return memset(batch->buffer + offset, 0, size);
+}
+
+static uint32_t
+batch_offset(struct intel_batchbuffer *batch, void *ptr)
+{
+	return (uint8_t *)ptr - batch->buffer;
+}
+
+static uint32_t
+batch_copy(struct intel_batchbuffer *batch, const void *ptr, uint32_t size, uint32_t align)
+{
+	return batch_offset(batch, memcpy(batch_alloc(batch, size, align), ptr, size));
+}
+
+static void
+gen8_render_flush(struct intel_batchbuffer *batch, uint32_t batch_end)
+{
+	int ret;
+
+	ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
+	if (ret == 0)
+		ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
+					NULL, 0, 0, 0);
+	assert(ret == 0);
+}
+
+static uint32_t
+gen8_fill_curbe_buffer_data(struct intel_batchbuffer *batch,
+			uint8_t color)
+{
+	uint8_t *curbe_buffer;
+	uint32_t offset;
+
+	curbe_buffer = batch_alloc(batch, sizeof(uint32_t) * 8, 64);
+	offset = batch_offset(batch, curbe_buffer);
+	*curbe_buffer = color;
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_surface_state(struct intel_batchbuffer *batch,
+			struct igt_buf *buf,
+			uint32_t format,
+			int is_dst)
+{
+	struct gen8_surface_state *ss;
+	uint32_t write_domain, read_domain, offset;
+	int ret;
+
+	if (is_dst) {
+		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domain = I915_GEM_DOMAIN_SAMPLER;
+	}
+
+	ss = batch_alloc(batch, sizeof(*ss), 64);
+	offset = batch_offset(batch, ss);
+
+	ss->ss0.surface_type = GEN8_SURFACE_2D;
+	ss->ss0.surface_format = format;
+	ss->ss0.render_cache_read_write = 1;
+	ss->ss0.vertical_alignment = 1; /* align 4 */
+	ss->ss0.horizontal_alignment = 1; /* align 4 */
+
+	if (buf->tiling == I915_TILING_X)
+		ss->ss0.tiled_mode = 2;
+	else if (buf->tiling == I915_TILING_Y)
+		ss->ss0.tiled_mode = 3;
+
+	ss->ss8.base_addr = buf->bo->offset;
+
+	ret = drm_intel_bo_emit_reloc(batch->bo,
+				batch_offset(batch, ss) + 8 * 4,
+				buf->bo, 0,
+				read_domain, write_domain);
+	assert(ret == 0);
+
+	ss->ss2.height = igt_buf_height(buf) - 1;
+	ss->ss2.width  = igt_buf_width(buf) - 1;
+	ss->ss3.pitch  = buf->stride - 1;
+
+	ss->ss7.shader_chanel_select_r = 4;
+	ss->ss7.shader_chanel_select_g = 5;
+	ss->ss7.shader_chanel_select_b = 6;
+	ss->ss7.shader_chanel_select_a = 7;
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_binding_table(struct intel_batchbuffer *batch,
+			struct igt_buf *dst)
+{
+	uint32_t *binding_table, offset;
+
+	binding_table = batch_alloc(batch, 32, 64);
+	offset = batch_offset(batch, binding_table);
+
+	binding_table[0] = gen8_fill_surface_state(batch, dst, GEN8_SURFACEFORMAT_R8_UNORM, 1);
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_media_kernel(struct intel_batchbuffer *batch,
+		const uint32_t kernel[][4],
+		size_t size)
+{
+	uint32_t offset;
+
+	offset = batch_copy(batch, kernel, size, 64);
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *dst)
+{
+	struct gen8_interface_descriptor_data *idd;
+	uint32_t offset;
+	uint32_t binding_table_offset, kernel_offset;
+
+	binding_table_offset = gen8_fill_binding_table(batch, dst);
+	kernel_offset = gen8_fill_media_kernel(batch, media_kernel, sizeof(media_kernel));
+
+	idd = batch_alloc(batch, sizeof(*idd), 64);
+	offset = batch_offset(batch, idd);
+
+	idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+	idd->desc2.single_program_flow = 1;
+	idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754;
+
+	idd->desc3.sampler_count = 0;      /* 0 samplers used */
+	idd->desc3.sampler_state_pointer = 0;
+
+	idd->desc4.binding_table_entry_count = 0;
+	idd->desc4.binding_table_pointer = (binding_table_offset >> 5);
+
+	idd->desc5.constant_urb_entry_read_offset = 0;
+	idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */
+
+	return offset;
+}
+
+static void
+gen8_emit_state_base_address(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
+
+	/* general */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* stateless data port */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
+
+	/* surface */
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* dynamic */
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION,
+		0, BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* indirect */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	/* instruction */
+	OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+
+	/* general state buffer size */
+	OUT_BATCH(0xfffff000 | 1);
+	/* dynamic state buffer size */
+	OUT_BATCH(1 << 12 | 1);
+	/* indirect object buffer size */
+	OUT_BATCH(0xfffff000 | 1);
+	/* intruction buffer size, must set modify enable bit, otherwise it may result in GPU hang */
+	OUT_BATCH(1 << 12 | 1);
+}
+
+static void
+gen8_emit_vfe_state(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN8_MEDIA_VFE_STATE | (9 - 2));
+
+	/* scratch buffer */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+
+	/* number of threads & urb entries */
+	OUT_BATCH(1 << 16 |
+		2 << 8);
+
+	OUT_BATCH(0);
+
+	/* urb entry size & curbe size */
+	OUT_BATCH(2 << 16 |
+		2);
+
+	/* scoreboard */
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void
+gen8_emit_curbe_load(struct intel_batchbuffer *batch, uint32_t curbe_buffer)
+{
+	OUT_BATCH(GEN8_MEDIA_CURBE_LOAD | (4 - 2));
+	OUT_BATCH(0);
+	/* curbe total data length */
+	OUT_BATCH(64);
+	/* curbe data start address, is relative to the dynamics base address */
+	OUT_BATCH(curbe_buffer);
+}
+
+static void
+gen8_emit_interface_descriptor_load(struct intel_batchbuffer *batch, uint32_t interface_descriptor)
+{
+	OUT_BATCH(GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
+	OUT_BATCH(0);
+	/* interface descriptor data length */
+	OUT_BATCH(sizeof(struct gen8_interface_descriptor_data));
+	/* interface descriptor address, is relative to the dynamics base address */
+	OUT_BATCH(interface_descriptor);
+}
+
+static void
+gen8_emit_media_state_flush(struct intel_batchbuffer *batch)
+{
+	OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2));
+	OUT_BATCH(0);
+}
+
+static void
+gen8_emit_media_objects(struct intel_batchbuffer *batch,
+			unsigned x, unsigned y,
+			unsigned width, unsigned height)
+{
+	int i, j;
+
+	for (i = 0; i < width / 16; i++) {
+		for (j = 0; j < height / 16; j++) {
+			OUT_BATCH(GEN8_MEDIA_OBJECT | (8 - 2));
+
+			/* interface descriptor offset */
+			OUT_BATCH(0);
+
+			/* without indirect data */
+			OUT_BATCH(0);
+			OUT_BATCH(0);
+
+			/* scoreboard */
+			OUT_BATCH(0);
+			OUT_BATCH(0);
+
+			/* inline data (xoffset, yoffset) */
+			OUT_BATCH(x + i * 16);
+			OUT_BATCH(y + j * 16);
+			gen8_emit_media_state_flush(batch);
+		}
+	}
+}
+
+/*
+ * This sets up the media pipeline,
+ *
+ * +---------------+ <---- 4096
+ * |       ^       |
+ * |       |       |
+ * |    various    |
+ * |      state    |
+ * |       |       |
+ * |_______|_______| <---- 2048 + ?
+ * |       ^       |
+ * |       |       |
+ * |   batch       |
+ * |    commands   |
+ * |       |       |
+ * |       |       |
+ * +---------------+ <---- 0 + ?
+ *
+ */
+
+#define BATCH_STATE_SPLIT 2048
+
+void
+gen9_media_fillfunc(struct intel_batchbuffer *batch,
+		struct igt_buf *dst,
+		unsigned x, unsigned y,
+		unsigned width, unsigned height,
+		uint8_t color)
+{
+	uint32_t curbe_buffer, interface_descriptor;
+	uint32_t batch_end;
+
+	intel_batchbuffer_flush(batch);
+
+	/* setup states */
+	batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+	curbe_buffer = gen8_fill_curbe_buffer_data(batch, color);
+	interface_descriptor = gen8_fill_interface_descriptor(batch, dst);
+	assert(batch->ptr < &batch->buffer[4095]);
+
+	/* media pipeline */
+	batch->ptr = batch->buffer;
+	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
+	gen8_emit_state_base_address(batch);
+
+	gen8_emit_vfe_state(batch);
+
+	gen8_emit_curbe_load(batch, curbe_buffer);
+
+	gen8_emit_interface_descriptor_load(batch, interface_descriptor);
+
+	gen8_emit_media_objects(batch, x, y, width, height);
+
+	OUT_BATCH(MI_BATCH_BUFFER_END);
+
+	batch_end = batch_align(batch, 8);
+	assert(batch_end < BATCH_STATE_SPLIT);
+
+	gen8_render_flush(batch, batch_end);
+	intel_batchbuffer_reset(batch);
+}
-- 
1.8.3.1

[PATCH i-g-t 22/26] mediafill/skl: follow the spec to update STATE_BASE_ADDRESS command

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/media_fill_gen9.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
index 98e2403..a067221 100644
--- a/lib/media_fill_gen9.c
+++ b/lib/media_fill_gen9.c
@@ -192,9 +192,9 @@ gen8_fill_interface_descriptor(struct intel_batchbuffer *batch, struct igt_buf *
 }
 
 static void
-gen8_emit_state_base_address(struct intel_batchbuffer *batch)
+gen9_emit_state_base_address(struct intel_batchbuffer *batch)
 {
-	OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2));
+	OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (19 - 2));
 
 	/* general */
 	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
@@ -228,6 +228,11 @@ gen8_emit_state_base_address(struct intel_batchbuffer *batch)
 	OUT_BATCH(0xfffff000 | 1);
 	/* intruction buffer size, must set modify enable bit, otherwise it may result in GPU hang */
 	OUT_BATCH(1 << 12 | 1);
+
+	/* Bindless surface state base address */
+	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
+	OUT_BATCH(0);
+	OUT_BATCH(0xfffff000);
 }
 
 static void
@@ -358,7 +363,7 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
 	/* media pipeline */
 	batch->ptr = batch->buffer;
 	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
-	gen8_emit_state_base_address(batch);
+	gen9_emit_state_base_address(batch);
 
 	gen8_emit_vfe_state(batch);
 
-- 
1.8.3.1

[PATCH i-g-t 23/26] mediafill/skl: Follow the spec to add pipeline_select mask

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/gen8_media.h      | 3 +++
 lib/media_fill_gen9.c | 3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/gen8_media.h b/lib/gen8_media.h
index 1214cd1..d1df8b9 100644
--- a/lib/gen8_media.h
+++ b/lib/gen8_media.h
@@ -371,4 +371,7 @@ struct gen8_surface_state
 	} ss15;
 };
 
+
+#define GEN9_PIPELINE_SELECTION_MASK		(3 << 8)
+
 #endif /* GEN8_MEDIA_H */
diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
index a067221..df0407d 100644
--- a/lib/media_fill_gen9.c
+++ b/lib/media_fill_gen9.c
@@ -362,7 +362,8 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
 
 	/* media pipeline */
 	batch->ptr = batch->buffer;
-	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
+	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+			GEN9_PIPELINE_SELECTION_MASK);
 	gen9_emit_state_base_address(batch);
 
 	gen8_emit_vfe_state(batch);
-- 
1.8.3.1

[PATCH i-g-t 24/26] mediafill/skl: Follow spec to configure FORCE_MEDIA_AWAKE in PIPELINE_SELECTION

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

The FORCE_MEDIA_AWAKE bit is added for the PIPELINE_SELECTION command and
some instructions requires that the media enginee is awake.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/gen8_media.h      | 7 +++++++
 lib/media_fill_gen9.c | 9 ++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/lib/gen8_media.h b/lib/gen8_media.h
index d1df8b9..f654215 100644
--- a/lib/gen8_media.h
+++ b/lib/gen8_media.h
@@ -374,4 +374,11 @@ struct gen8_surface_state
 
 #define GEN9_PIPELINE_SELECTION_MASK		(3 << 8)
 
+/*  If enabled, it will force awake media enginee and the following instructions
+ *  will require that the media enginee is awake.
+ */
+#define GEN9_FORCE_MEDIA_AWAKE_DISABLE		(0 << 5)
+#define GEN9_FORCE_MEDIA_AWAKE_ENABLE		(1 << 5)
+#define GEN9_FORCE_MEDIA_AWAKE_MASK		(1 << 13)
+
 #endif /* GEN8_MEDIA_H */
diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
index df0407d..4ecf268 100644
--- a/lib/media_fill_gen9.c
+++ b/lib/media_fill_gen9.c
@@ -363,7 +363,9 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
 	/* media pipeline */
 	batch->ptr = batch->buffer;
 	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
-			GEN9_PIPELINE_SELECTION_MASK);
+			GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+			GEN9_PIPELINE_SELECTION_MASK |
+			GEN9_FORCE_MEDIA_AWAKE_MASK);
 	gen9_emit_state_base_address(batch);
 
 	gen8_emit_vfe_state(batch);
@@ -374,6 +376,11 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
 
 	gen8_emit_media_objects(batch, x, y, width, height);
 
+	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
+			GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+			GEN9_PIPELINE_SELECTION_MASK |
+			GEN9_FORCE_MEDIA_AWAKE_MASK);
+
 	OUT_BATCH(MI_BATCH_BUFFER_END);
 
 	batch_end = batch_align(batch, 8);
-- 
1.8.3.1

[PATCH i-g-t 25/26] mediafill/skl: Follow spec to configure media sampler DOP clock gating in PIPELINE_SELECTION

[Damien Lespiau]

From: Zhao Yakui <yakui.zhao@intel.com>

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/gen8_media.h      | 4 ++++
 lib/media_fill_gen9.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/lib/gen8_media.h b/lib/gen8_media.h
index f654215..15cd799 100644
--- a/lib/gen8_media.h
+++ b/lib/gen8_media.h
@@ -381,4 +381,8 @@ struct gen8_surface_state
 #define GEN9_FORCE_MEDIA_AWAKE_ENABLE		(1 << 5)
 #define GEN9_FORCE_MEDIA_AWAKE_MASK		(1 << 13)
 
+#define GEN9_SAMPLER_DOP_GATE_DISABLE		(0 << 4)
+#define GEN9_SAMPLER_DOP_GATE_ENABLE		(1 << 4)
+#define GEN9_SAMPLER_DOP_GATE_MASK		(1 << 12)
+
 #endif /* GEN8_MEDIA_H */
diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
index 4ecf268..6c6ba89 100644
--- a/lib/media_fill_gen9.c
+++ b/lib/media_fill_gen9.c
@@ -364,7 +364,9 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
 	batch->ptr = batch->buffer;
 	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
 			GEN9_FORCE_MEDIA_AWAKE_ENABLE |
+			GEN9_SAMPLER_DOP_GATE_DISABLE |
 			GEN9_PIPELINE_SELECTION_MASK |
+			GEN9_SAMPLER_DOP_GATE_MASK |
 			GEN9_FORCE_MEDIA_AWAKE_MASK);
 	gen9_emit_state_base_address(batch);
 
@@ -378,7 +380,9 @@ gen9_media_fillfunc(struct intel_batchbuffer *batch,
 
 	OUT_BATCH(GEN8_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA |
 			GEN9_FORCE_MEDIA_AWAKE_DISABLE |
+			GEN9_SAMPLER_DOP_GATE_ENABLE |
 			GEN9_PIPELINE_SELECTION_MASK |
+			GEN9_SAMPLER_DOP_GATE_MASK |
 			GEN9_FORCE_MEDIA_AWAKE_MASK);
 
 	OUT_BATCH(MI_BATCH_BUFFER_END);
-- 
1.8.3.1

[PATCH i-g-t 26/26] lib/skl: Return the render copy and media fill functions

[Damien Lespiau]

From: "Xiang, Haihao" <haihao.xiang@intel.com>

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
[Ben: Reordered if tree]
Signed-off-by: Ben Widawsky <benjamin.widawsky@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 lib/intel_batchbuffer.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 952b86a..c1b0e3d 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -481,6 +481,8 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
 		copy = gen7_render_copyfunc;
 	else if (IS_GEN8(devid))
 		copy = gen8_render_copyfunc;
+	else if (IS_GEN9(devid))
+		copy = gen9_render_copyfunc;
 
 	return copy;
 }
@@ -498,7 +500,9 @@ igt_media_fillfunc_t igt_get_media_fillfunc(int devid)
 {
 	igt_media_fillfunc_t fill = NULL;
 
-	if (IS_BROADWELL(devid))
+	if (IS_GEN9(devid))
+		fill = gen9_media_fillfunc;
+	else if (IS_BROADWELL(devid))
 		fill = gen8_media_fillfunc;
 	else if (IS_GEN7(devid))
 		fill = gen7_media_fillfunc;
-- 
1.8.3.1

Re: [PATCH i-g-t 01/26] skl: Add SKL PCI ids

[Damien Lespiau]

On Fri, Sep 26, 2014 at 03:02:59PM +0100, Damien Lespiau wrote:
> v2: Update to the latest PCI ids
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---

Pushed the whole series to i-g-t.

-- 
Damien