* [Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type for Transactional Memory
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 2/9] target-ppc: Introduce Feature Flag " Tom Musta
` (8 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Add a category (PPC2_TM) for the Transactional Memory instructions
introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/cpu.h | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 068fcb2..3510083 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2010,6 +2010,8 @@ enum {
PPC2_ISA207S = 0x0000000000008000ULL,
/* Double precision floating point conversion for signed integer 64 */
PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
+ /* Transactional Memory (ISA 2.07, Book II) */
+ PPC2_TM = 0x0000000000020000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2017,7 +2019,7 @@ enum {
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
- PPC2_FP_CVT_S64)
+ PPC2_FP_CVT_S64 | PPC2_TM)
};
/*****************************************************************************/
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 2/9] target-ppc: Introduce Feature Flag for Transactional Memory
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type " Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State Tom Musta
` (7 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Add a flag (POWERPC_FLAG_TM) for the Transactional Memory
Facility introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/cpu.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3510083..38176c0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -584,6 +584,8 @@ enum {
POWERPC_FLAG_CFAR = 0x00040000,
/* Has VSX */
POWERPC_FLAG_VSX = 0x00080000,
+ /* Has Transaction Memory (ISA 2.07) */
+ POWERPC_FLAG_TM = 0x00100000,
};
/*****************************************************************************/
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 1/9] target-ppc: Introduce Instruction Type " Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 2/9] target-ppc: Introduce Feature Flag " Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory Tom Musta
` (6 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit.
This is analogous to the other "available" bits in the MSR (FP,
VSX, etc.).
NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped
with a PPC64 bit check.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d381632..7217041 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -203,6 +203,7 @@ typedef struct DisasContext {
int altivec_enabled;
int vsx_enabled;
int spe_enabled;
+ int tm_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -11311,6 +11312,13 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
} else {
ctx.vsx_enabled = 0;
}
+#if defined(TARGET_PPC64)
+ if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
+ ctx.tm_enabled = msr_tm;
+ } else {
+ ctx.tm_enabled = 0;
+ }
+#endif
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
ctx.singlestep_enabled = CPU_SINGLE_STEP;
else
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (2 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields Tom Musta
` (5 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
The Power8 processor implements the Transactional Memory Facility
as defined in Power ISA 2.07. Update the initialization code to
indicate this.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate_init.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1fece7b..72cc9d0 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8219,7 +8219,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
- PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64;
+ PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
+ PPC2_TM;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_TM) |
(1ull << MSR_VR) |
@@ -8247,7 +8248,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
- POWERPC_FLAG_VSX;
+ POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (3 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 4/9] target-ppc: Power8 Supports Transactional Memory Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 17:02 ` Alexander Graf
2014-12-18 16:34 ` [Qemu-devel] [PATCH 6/9] target-ppc: Introduce tbegin Tom Musta
` (4 subsequent siblings)
9 siblings, 1 reply; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Define mnemonics for the various bit fields in the Transaction
EXception And Summary Register (TEXASR).
---
target-ppc/cpu.h | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 38176c0..91a03f6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -558,6 +558,26 @@ struct ppc_slb_t {
#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
+/* Transaction EXception And Summary Register bits */
+#define TEXASR_FAILURE_PERSISTENT (63 - 7)
+#define TEXASR_DISALLOWED (63 - 8)
+#define TEXASR_NESTING_OVERFLOW (63 - 9)
+#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
+#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
+#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
+#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
+#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
+#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
+#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
+#define TEXASR_ABORT (63 - 31)
+#define TEXASR_SUSPENDED (63 - 32)
+#define TEXASR_PRIVILEGE_HV (63 - 34)
+#define TEXASR_PRIVILEGE_PR (63 - 35)
+#define TEXASR_FAILURE_SUMMARY (63 - 36)
+#define TEXASR_TFIAR_EXACT (63 - 37)
+#define TEXASR_ROT (63 - 38)
+#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
+
enum {
POWERPC_FLAG_NONE = 0x00000000,
/* Flag for MSR bit 25 signification (VRE/SPE) */
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
2014-12-18 16:34 ` [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields Tom Musta
@ 2014-12-18 17:02 ` Alexander Graf
2014-12-18 18:10 ` Tom Musta
0 siblings, 1 reply; 17+ messages in thread
From: Alexander Graf @ 2014-12-18 17:02 UTC (permalink / raw)
To: Tom Musta, qemu-devel, qemu-ppc
On 18.12.14 17:34, Tom Musta wrote:
> Define mnemonics for the various bit fields in the Transaction
> EXception And Summary Register (TEXASR).
This is missing an SoB line.
Alex
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
2014-12-18 17:02 ` Alexander Graf
@ 2014-12-18 18:10 ` Tom Musta
2014-12-18 18:29 ` Alexander Graf
0 siblings, 1 reply; 17+ messages in thread
From: Tom Musta @ 2014-12-18 18:10 UTC (permalink / raw)
To: Alexander Graf, qemu-devel, qemu-ppc
On 12/18/2014 11:02 AM, Alexander Graf wrote:
>
>
> On 18.12.14 17:34, Tom Musta wrote:
>> Define mnemonics for the various bit fields in the Transaction
>> EXception And Summary Register (TEXASR).
>
> This is missing an SoB line.
>
>
> Alex
>
Sorry about that. I will publish a V2 but may wait a day or so for any other other comments.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
2014-12-18 18:10 ` Tom Musta
@ 2014-12-18 18:29 ` Alexander Graf
2014-12-18 18:41 ` Tom Musta
0 siblings, 1 reply; 17+ messages in thread
From: Alexander Graf @ 2014-12-18 18:29 UTC (permalink / raw)
To: Tom Musta, qemu-devel, qemu-ppc
On 18.12.14 19:10, Tom Musta wrote:
> On 12/18/2014 11:02 AM, Alexander Graf wrote:
>>
>>
>> On 18.12.14 17:34, Tom Musta wrote:
>>> Define mnemonics for the various bit fields in the Transaction
>>> EXception And Summary Register (TEXASR).
>>
>> This is missing an SoB line.
>>
>>
>> Alex
>>
>
> Sorry about that. I will publish a V2 but may wait a day or so for any other other comments.
The patches look good IMHO, just reply with your SoB line and I'll apply
the rest too :)
Alex
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields
2014-12-18 18:29 ` Alexander Graf
@ 2014-12-18 18:41 ` Tom Musta
0 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 18:41 UTC (permalink / raw)
To: Alexander Graf, qemu-devel, qemu-ppc
On 12/18/2014 12:29 PM, Alexander Graf wrote:
>
>
> On 18.12.14 19:10, Tom Musta wrote:
>> On 12/18/2014 11:02 AM, Alexander Graf wrote:
>>>
>>>
>>> On 18.12.14 17:34, Tom Musta wrote:
>>>> Define mnemonics for the various bit fields in the Transaction
>>>> EXception And Summary Register (TEXASR).
>>>
>>> This is missing an SoB line.
>>>
>>>
>>> Alex
>>>
>>
>> Sorry about that. I will publish a V2 but may wait a day or so for any other other comments.
>
> The patches look good IMHO, just reply with your SoB line and I'll apply
> the rest too :)
>
>
> Alex
>
Signed-off-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 6/9] target-ppc: Introduce tbegin
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (4 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 5/9] target-ppc: Introduce TEXASRU Bit Fields Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 7/9] target-ppc: Introduce TM Noops Tom Musta
` (3 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Provide a degenerate implementation of the tbegin instruction. This
implementation always fails the transaction, recording the failure
per Book II Section 5.3.2 of the Power ISA V2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/helper.h | 2 ++
target-ppc/mem_helper.c | 22 ++++++++++++++++++++++
target-ppc/translate.c | 12 ++++++++++++
3 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 210fd97..c2bf6d2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -665,3 +665,5 @@ DEF_HELPER_4(dscri, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscriq, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscli, void, env, fprp, fprp, i32)
DEF_HELPER_4(dscliq, void, env, fprp, fprp, i32)
+
+DEF_HELPER_1(tbegin, void, env)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 50344b8..6d37dae 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -269,3 +269,25 @@ STVE(stvewx, cpu_stl_data, bswap32, u32)
#undef HI_IDX
#undef LO_IDX
+
+void helper_tbegin(CPUPPCState *env)
+{
+ /* As a degenerate implementation, always fail tbegin. The reason
+ * given is "Nesting overflow". The "persistent" bit is set,
+ * providing a hint to the error handler to not retry. The TFIAR
+ * captures the address of the failure, which is this tbegin
+ * instruction. Instruction execution will continue with the
+ * next instruction in memory, which is precisely what we want.
+ */
+
+ env->spr[SPR_TEXASR] =
+ (1ULL << TEXASR_FAILURE_PERSISTENT) |
+ (1ULL << TEXASR_NESTING_OVERFLOW) |
+ (msr_hv << TEXASR_PRIVILEGE_HV) |
+ (msr_pr << TEXASR_PRIVILEGE_PR) |
+ (1ULL << TEXASR_FAILURE_SUMMARY) |
+ (1ULL << TEXASR_TFIAR_EXACT);
+ env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
+ env->spr[SPR_TFHAR] = env->nip + 4;
+ env->crf[0] = 0xB; /* 0b1010 = transaction failure */
+}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7217041..cddfc36 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9643,6 +9643,15 @@ GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE
GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
+static void gen_tbegin(DisasContext *ctx)
+{
+ if (unlikely(!ctx->tm_enabled)) {
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
+ return;
+ }
+ gen_helper_tbegin(cpu_env);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11055,6 +11064,9 @@ GEN_SPEOP_LDST(evstwhe, 0x18, 2),
GEN_SPEOP_LDST(evstwho, 0x1A, 2),
GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
+
+GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 7/9] target-ppc: Introduce TM Noops
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (5 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 6/9] target-ppc: Introduce tbegin Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 8/9] target-ppc: Introduce tcheck Tom Musta
` (2 subsequent siblings)
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Add degenerate implementations of the non-privileged Transactional
Memory instructions tend., tabort*. and tsr. This implementation
simply checks the MSR[TM] bit and then sets CR0 to 0b0000. This
is a reasonable degenerate implementation since transactions are
never allowed to begin and hence MSR[TS] is always 0b00.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cddfc36..f468a5d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9652,6 +9652,30 @@ static void gen_tbegin(DisasContext *ctx)
gen_helper_tbegin(cpu_env);
}
+#define GEN_TM_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(!ctx->tm_enabled)) { \
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
+ return; \
+ } \
+ /* Because tbegin always fails in QEMU, these user \
+ * space instructions all have a simple implementation: \
+ * \
+ * CR[0] = 0b0 || MSR[TS] || 0b0 \
+ * = 0b0 || 0b00 || 0b0 \
+ */ \
+ tcg_gen_movi_i32(cpu_crf[0], 0); \
+}
+
+GEN_TM_NOOP(tend);
+GEN_TM_NOOP(tabort);
+GEN_TM_NOOP(tabortwc);
+GEN_TM_NOOP(tabortwci);
+GEN_TM_NOOP(tabortdc);
+GEN_TM_NOOP(tabortdci);
+GEN_TM_NOOP(tsr);
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11067,6 +11091,20 @@ GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 8/9] target-ppc: Introduce tcheck
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (6 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 7/9] target-ppc: Introduce TM Noops Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-18 16:34 ` [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops Tom Musta
2014-12-18 22:52 ` [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Alexander Graf
9 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Add a degenerate implementation of the Transaction Check (tcheck)
instruction. Since transaction always immediately fail, this
implementation simply sets CR[BF] to 0b1000, i.e. TDOOMED = 1
and MSR[TS] == 0.
Signed-off-by: Tom Musta <tommusta@gmail.com>
---
target-ppc/translate.c | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f468a5d..a3c79a6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9676,6 +9676,21 @@ GEN_TM_NOOP(tabortdc);
GEN_TM_NOOP(tabortdci);
GEN_TM_NOOP(tsr);
+static void gen_tcheck(DisasContext *ctx)
+{
+ if (unlikely(!ctx->tm_enabled)) {
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
+ return;
+ }
+ /* Because tbegin always fails, the tcheck implementation
+ * is simple:
+ *
+ * CR[CRF] = TDOOMED || MSR[TS] || 0b0
+ * = 0b1 || 0b00 || 0b0
+ */
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11105,6 +11120,8 @@ GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
PPC_NONE, PPC2_TM),
GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (7 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 8/9] target-ppc: Introduce tcheck Tom Musta
@ 2014-12-18 16:34 ` Tom Musta
2014-12-19 10:20 ` Fam Zheng
2014-12-18 22:52 ` [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Alexander Graf
9 siblings, 1 reply; 17+ messages in thread
From: Tom Musta @ 2014-12-18 16:34 UTC (permalink / raw)
To: qemu-devel, qemu-ppc; +Cc: Tom Musta, agraf
Add the supervisory Transactional Memory instructions treclaim. and
trechkpt. The implementation is a degenerate one that simply
checks privileged state, TM availability and then sets CR[0] to
0b0000, just like the unprivileged noops.
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a3c79a6..b4a4297 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9691,6 +9691,40 @@ static void gen_tcheck(DisasContext *ctx)
tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
}
+#if defined(CONFIG_USER_ONLY)
+#define GEN_TM_PRIV_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
+}
+
+#else
+
+#define GEN_TM_PRIV_NOOP(name) \
+static inline void gen_##name(DisasContext *ctx) \
+{ \
+ if (unlikely(ctx->pr)) { \
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
+ return; \
+ } \
+ if (unlikely(!ctx->tm_enabled)) { \
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
+ return; \
+ } \
+ /* Because tbegin always fails, the implementation is \
+ * simple: \
+ * \
+ * CR[0] = 0b0 || MSR[TS] || 0b0 \
+ * = 0b0 || 0b00 | 0b0 \
+ */ \
+ tcg_gen_movi_i32(cpu_crf[0], 0); \
+}
+
+#endif
+
+GEN_TM_PRIV_NOOP(treclaim);
+GEN_TM_PRIV_NOOP(trechkpt);
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11122,6 +11156,10 @@ GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
PPC_NONE, PPC2_TM),
GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
+ PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.7.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops
2014-12-18 16:34 ` [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops Tom Musta
@ 2014-12-19 10:20 ` Fam Zheng
2014-12-20 21:22 ` Tom Musta
0 siblings, 1 reply; 17+ messages in thread
From: Fam Zheng @ 2014-12-19 10:20 UTC (permalink / raw)
To: Tom Musta; +Cc: qemu-ppc, qemu-devel, agraf
On Thu, 12/18 10:34, Tom Musta wrote:
> Add the supervisory Transactional Memory instructions treclaim. and
> trechkpt. The implementation is a degenerate one that simply
> checks privileged state, TM availability and then sets CR[0] to
> 0b0000, just like the unprivileged noops.
And also s-o-b for this :)
Fam
> ---
> target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 files changed, 38 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a3c79a6..b4a4297 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -9691,6 +9691,40 @@ static void gen_tcheck(DisasContext *ctx)
> tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
> }
>
> +#if defined(CONFIG_USER_ONLY)
> +#define GEN_TM_PRIV_NOOP(name) \
> +static inline void gen_##name(DisasContext *ctx) \
> +{ \
> + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
> +}
> +
> +#else
> +
> +#define GEN_TM_PRIV_NOOP(name) \
> +static inline void gen_##name(DisasContext *ctx) \
> +{ \
> + if (unlikely(ctx->pr)) { \
> + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
> + return; \
> + } \
> + if (unlikely(!ctx->tm_enabled)) { \
> + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
> + return; \
> + } \
> + /* Because tbegin always fails, the implementation is \
> + * simple: \
> + * \
> + * CR[0] = 0b0 || MSR[TS] || 0b0 \
> + * = 0b0 || 0b00 | 0b0 \
> + */ \
> + tcg_gen_movi_i32(cpu_crf[0], 0); \
> +}
> +
> +#endif
> +
> +GEN_TM_PRIV_NOOP(treclaim);
> +GEN_TM_PRIV_NOOP(trechkpt);
> +
> static opcode_t opcodes[] = {
> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
> GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
> @@ -11122,6 +11156,10 @@ GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
> PPC_NONE, PPC2_TM),
> GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
> PPC_NONE, PPC2_TM),
> +GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
> + PPC_NONE, PPC2_TM),
> +GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
> + PPC_NONE, PPC2_TM),
> };
>
> #include "helper_regs.h"
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops
2014-12-19 10:20 ` Fam Zheng
@ 2014-12-20 21:22 ` Tom Musta
0 siblings, 0 replies; 17+ messages in thread
From: Tom Musta @ 2014-12-20 21:22 UTC (permalink / raw)
To: Fam Zheng; +Cc: qemu-ppc, qemu-devel, agraf
On 12/19/2014 4:20 AM, Fam Zheng wrote:
> On Thu, 12/18 10:34, Tom Musta wrote:
>> Add the supervisory Transactional Memory instructions treclaim. and
>> trechkpt. The implementation is a degenerate one that simply
>> checks privileged state, TM availability and then sets CR[0] to
>> 0b0000, just like the unprivileged noops.
>
> And also s-o-b for this :)
>
> Fam
>
>> ---
>> target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 38 insertions(+), 0 deletions(-)
>>
>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
>> index a3c79a6..b4a4297 100644
>> --- a/target-ppc/translate.c
>> +++ b/target-ppc/translate.c
>> @@ -9691,6 +9691,40 @@ static void gen_tcheck(DisasContext *ctx)
>> tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
>> }
>>
>> +#if defined(CONFIG_USER_ONLY)
>> +#define GEN_TM_PRIV_NOOP(name) \
>> +static inline void gen_##name(DisasContext *ctx) \
>> +{ \
>> + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
>> +}
>> +
>> +#else
>> +
>> +#define GEN_TM_PRIV_NOOP(name) \
>> +static inline void gen_##name(DisasContext *ctx) \
>> +{ \
>> + if (unlikely(ctx->pr)) { \
>> + gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
>> + return; \
>> + } \
>> + if (unlikely(!ctx->tm_enabled)) { \
>> + gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
>> + return; \
>> + } \
>> + /* Because tbegin always fails, the implementation is \
>> + * simple: \
>> + * \
>> + * CR[0] = 0b0 || MSR[TS] || 0b0 \
>> + * = 0b0 || 0b00 | 0b0 \
>> + */ \
>> + tcg_gen_movi_i32(cpu_crf[0], 0); \
>> +}
>> +
>> +#endif
>> +
>> +GEN_TM_PRIV_NOOP(treclaim);
>> +GEN_TM_PRIV_NOOP(trechkpt);
>> +
>> static opcode_t opcodes[] = {
>> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
>> GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
>> @@ -11122,6 +11156,10 @@ GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
>> PPC_NONE, PPC2_TM),
>> GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
>> PPC_NONE, PPC2_TM),
>> +GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
>> + PPC_NONE, PPC2_TM),
>> +GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
>> + PPC_NONE, PPC2_TM),
>> };
>>
>> #include "helper_regs.h"
>> --
>> 1.7.1
>>
>>
Signed-off-by: Tom Musta <tommusta@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory
2014-12-18 16:34 [Qemu-devel] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory Tom Musta
` (8 preceding siblings ...)
2014-12-18 16:34 ` [Qemu-devel] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops Tom Musta
@ 2014-12-18 22:52 ` Alexander Graf
9 siblings, 0 replies; 17+ messages in thread
From: Alexander Graf @ 2014-12-18 22:52 UTC (permalink / raw)
To: Tom Musta, qemu-devel, qemu-ppc
On 18.12.14 17:34, Tom Musta wrote:
> This patch series introduces rudimentary support for the Transactional Memory
> (TM) feature of Power ISA V2.07. In a nutshell, software uses the feature by
> initiating a transaction via the tbegin instruction. Hardware then accumulates
> storage accesses until the transaction is committed via the tend instruction).
> At this point, either the instruction completes and all storage accesses are
> atomic with respect to other processors; or the transaction fails and processor
> state reverts to the point of tbegin. Transaction success or failure is recorded
> in CR[0] and the instruction immediately following tbegin is expected to inspect
> this field and provide an error path to properly handle failure.
>
> Accurately emulating such a feature in QEMU is quite difficult. Instead, the
> approach taken here simply fails the transaction at the point of tbegin and
> thus immediately takes software down the error handlling path. As such, this can
> be considered a toleration mode for any software that utilizes the TM feature.
> Valgrind has taken a similar approach. There are no immediate plans to implement
> a more sophisticated model.
>
> Currently, Power8 is the only Power processor that supports TM.
Thanks, applied all to ppc-next.
Alex
^ permalink raw reply [flat|nested] 17+ messages in thread