From: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> To: <linux-mips@linux-mips.org> Cc: <devicetree@vger.kernel.org>, <linux-serial@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <Zubair.Kakakhel@imgtec.com>, <gregkh@linuxfoundation.org>, <mturquette@linaro.org>, <sboyd@codeaurora.org>, <ralf@linux-mips.org>, <jslaby@suse.cz>, <tglx@linutronix.de>, <jason@lakedaemon.net>, <lars@metafoo.de>, <paul.burton@imgtec.com> Subject: [PATCH_V2 28/34] dt: clk: Add ingenic,jz4780-cgu binding documentation Date: Wed, 4 Feb 2015 15:21:57 +0000 [thread overview] Message-ID: <1423063323-19419-29-git-send-email-Zubair.Kakakhel@imgtec.com> (raw) In-Reply-To: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> From: Paul Burton <paul.burton@imgtec.com> Document the devictree binding for the Ingenic jz4780 CGU driver. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: devicetree@vger.kernel.org --- .../bindings/clock/ingenic,jz4780-cgu.txt | 52 +++++++++++++ include/dt-bindings/clock/jz4780-cgu.h | 88 ++++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt create mode 100644 include/dt-bindings/clock/jz4780-cgu.h diff --git a/Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt new file mode 100644 index 0000000..2432a49 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt @@ -0,0 +1,52 @@ +Ingenic jz4780 SoC CGU binding + +The CGU in a jz4780 SoC provides all the clocks generated on-chip. It includes +PLLs, multiplexers, dividers & gates in order to provide a variety of different +clock signals derived from only 2 external source clocks. + +Required properties: +- compatible: Should be "ingenic,jz4780-cgu" +- reg: Should be the address & length of the CGU registers +- clocks: Should contain the phandle & clock specifier for two clocks external + to the TCU. First the external crystal "ext" and second the RTC + clock source "rtc". +- clock-names: Should be set to strings naming the clocks specified in the + "clocks" property. +- #clock-cells: Should be 1. + Clock consumers specify this argument to identify a clock. The + valid values may be found in <dt-bindings/clock/jz4780-cgu.h>. + +Example SoC include file: + +/ { + cgu: jz4780-cgu { + compatible = "ingenic,jz4780-cgu"; + reg = <0x10000000 0x100>; + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + clocks = <&cgu JZ4780_CLK_UART0>; + }; +}; + +Example board file: + +/ { + ext: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + rtc: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + &cgu { + clocks = <&ext> <&rtc>; + clock-names: "ext", "rtc"; + }; +}; diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h new file mode 100644 index 0000000..467165e --- /dev/null +++ b/include/dt-bindings/clock/jz4780-cgu.h @@ -0,0 +1,88 @@ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> To: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Zubair.Kakakhel@imgtec.com, gregkh@linuxfoundation.org, mturquette@linaro.org, sboyd@codeaurora.org, ralf@linux-mips.org, jslaby@suse.cz, tglx@linutronix.de, jason@lakedaemon.net, lars@metafoo.de, paul.burton@imgtec.com Subject: [PATCH_V2 28/34] dt: clk: Add ingenic,jz4780-cgu binding documentation Date: Wed, 4 Feb 2015 15:21:57 +0000 [thread overview] Message-ID: <1423063323-19419-29-git-send-email-Zubair.Kakakhel@imgtec.com> (raw) In-Reply-To: <1423063323-19419-1-git-send-email-Zubair.Kakakhel@imgtec.com> From: Paul Burton <paul.burton@imgtec.com> Document the devictree binding for the Ingenic jz4780 CGU driver. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: devicetree@vger.kernel.org --- .../bindings/clock/ingenic,jz4780-cgu.txt | 52 +++++++++++++ include/dt-bindings/clock/jz4780-cgu.h | 88 ++++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt create mode 100644 include/dt-bindings/clock/jz4780-cgu.h diff --git a/Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt b/Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt new file mode 100644 index 0000000..2432a49 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ingenic,jz4780-cgu.txt @@ -0,0 +1,52 @@ +Ingenic jz4780 SoC CGU binding + +The CGU in a jz4780 SoC provides all the clocks generated on-chip. It includes +PLLs, multiplexers, dividers & gates in order to provide a variety of different +clock signals derived from only 2 external source clocks. + +Required properties: +- compatible: Should be "ingenic,jz4780-cgu" +- reg: Should be the address & length of the CGU registers +- clocks: Should contain the phandle & clock specifier for two clocks external + to the TCU. First the external crystal "ext" and second the RTC + clock source "rtc". +- clock-names: Should be set to strings naming the clocks specified in the + "clocks" property. +- #clock-cells: Should be 1. + Clock consumers specify this argument to identify a clock. The + valid values may be found in <dt-bindings/clock/jz4780-cgu.h>. + +Example SoC include file: + +/ { + cgu: jz4780-cgu { + compatible = "ingenic,jz4780-cgu"; + reg = <0x10000000 0x100>; + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + clocks = <&cgu JZ4780_CLK_UART0>; + }; +}; + +Example board file: + +/ { + ext: clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + rtc: clock@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + &cgu { + clocks = <&ext> <&rtc>; + clock-names: "ext", "rtc"; + }; +}; diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h new file mode 100644 index 0000000..467165e --- /dev/null +++ b/include/dt-bindings/clock/jz4780-cgu.h @@ -0,0 +1,88 @@ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ -- 1.9.1
next prev parent reply other threads:[~2015-02-04 15:27 UTC|newest] Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-02-04 15:21 [PATCH_V2 00/34] jz4780 & CI20 support Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 01/34] dt: Add Ingenic Semiconductor vendor prefix Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 02/34] MIPS: jz4740: require & include DT Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 03/34] MIPS: irq_cpu: declare irqchip table entry Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 04/34] MIPS: jz4740: probe CPU interrupt controller via DT Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 17:05 ` Sergei Shtylyov 2015-02-04 15:21 ` [PATCH_V2 05/34] MIPS: jz4740: use generic plat_irq_dispatch Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 06/34] MIPS: jz4740: move arch_init_irq out of arch/mips/jz4740/irq.c Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 07/34] dt: interrupt-controller: Add ingenic,jz4740-intc binding doc Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 17:07 ` Sergei Shtylyov 2015-02-04 15:21 ` [PATCH_V2 08/34] MIPS: jz4740: allow interrupt controller probe via DT Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 09/34] MIPS: jz4740: probe interrupt controller " Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 17:09 ` Sergei Shtylyov 2015-02-04 15:21 ` [PATCH_V2 10/34] MIPS: jz4740: remove non-DT interrupt controller init Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 11/34] MIPS: jz4740: register an irq_domain for the interrupt controller Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 16:19 ` Arnd Bergmann 2015-02-04 16:19 ` Arnd Bergmann 2015-02-04 15:21 ` [PATCH_V2 12/34] MIPS: jz4740: call jz4740_clock_init earlier Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 13/34] MIPS: jz4740: replace use of jz4740_clock_bdata Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 14/34] clk: jz47xx-cgu: add driver for Ingenic jz47xx series CGU clocks Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 15/34] dt: clk: Add ingenic,jz4740-cgu binding documentation Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 16:27 ` Arnd Bergmann 2015-02-04 15:21 ` [PATCH_V2 16/34] MIPS: clk: migrate jz4740 to common clock framework Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 17/34] MIPS: clk: move jz4740_clock_set_wait_mode to jz4740-cgu Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 18/34] MIPS: clk: move jz4740 UDC auto suspend functions " Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 19/34] MIPS: clk: move jz4740 clock suspend, resume " Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 20/34] MIPS: jz4740: remove clock.h Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 21/34] MIPS: jz4740: only detect RAM size if not specified in DT Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 22/34] MIPS: jz4740: support >32 interrupts Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 23/34] MIPS: jz4740: define IRQ numbers based on number of intc IRQs Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 24/34] dt: serial: Add ingenic,jz4740-uart binding Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 25/34] serial: 8250_jz47xx: support for Ingenic jz47xx UARTs Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 21:02 ` Paul Bolle 2015-02-04 15:21 ` [PATCH_V2 26/34] MIPS: allow mach-provided serial.h Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 27/34] MIPS: jz4740: use jz47xx-uart & DT for UART output Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 16:32 ` Arnd Bergmann 2015-02-04 16:32 ` Arnd Bergmann 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel [this message] 2015-02-04 15:21 ` [PATCH_V2 28/34] dt: clk: Add ingenic,jz4780-cgu binding documentation Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 29/34] clk: add Ingenic jz4780 CGU driver Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` [PATCH_V2 30/34] MIPS: jz4740: add jz4780 interrupt controller support Zubair Lutfullah Kakakhel 2015-02-04 15:21 ` Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` [PATCH_V2 31/34] MIPS: add jz4780 Ingenic vendor ID Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` [PATCH_V2 32/34] MIPS: initial Ingenic jz4780 support Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` [PATCH_V2 33/34] MIPS: initial MIPS Creator CI20 board support Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` Zubair Lutfullah Kakakhel 2015-02-04 20:56 ` Paul Bolle 2015-02-04 20:56 ` Paul Bolle 2015-02-04 15:22 ` [PATCH_V2 34/34] MIPS: allow jz4780 to be selected in Kconfig Zubair Lutfullah Kakakhel 2015-02-04 15:22 ` Zubair Lutfullah Kakakhel 2015-02-04 16:47 ` [PATCH_V2 00/34] jz4780 & CI20 support Paul Burton 2015-02-04 16:47 ` Paul Burton
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