[PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Adds support for the Cadence UART in Xilinx ZynqMP. The
rest of the ZynqMP platform is discovered via device-tree.

Cheers,
Edgar

Changelog:

v2 -> v3:
* Fix coding style issues. (Julien review)

v1 -> v2:
* Rebase with upstream/staging to fix the device-tree device matching. (Ian review)

Edgar E. Iglesias (2):
  xen/arm: Add Cadence UART driver
  xen/arm: Add Xilinx ZynqMP early printk support

 config/arm64.mk                      |   1 +
 docs/misc/arm/early-printk.txt       |   1 +
 xen/arch/arm/Rules.mk                |   6 +
 xen/arch/arm/arm64/debug-cadence.inc |  45 +++++++
 xen/drivers/char/Makefile            |   1 +
 xen/drivers/char/cadence-uart.c      | 224 +++++++++++++++++++++++++++++++++++
 xen/include/asm-arm/cadence-uart.h   |  55 +++++++++
 7 files changed, 333 insertions(+)
 create mode 100644 xen/arch/arm/arm64/debug-cadence.inc
 create mode 100644 xen/drivers/char/cadence-uart.c
 create mode 100644 xen/include/asm-arm/cadence-uart.h

-- 
1.9.1

[PATCH v3 1/2] xen/arm: Add Cadence UART driver

[Edgar E. Iglesias]

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 config/arm64.mk                    |   1 +
 xen/drivers/char/Makefile          |   1 +
 xen/drivers/char/cadence-uart.c    | 224 +++++++++++++++++++++++++++++++++++++
 xen/include/asm-arm/cadence-uart.h |  55 +++++++++
 4 files changed, 281 insertions(+)
 create mode 100644 xen/drivers/char/cadence-uart.c
 create mode 100644 xen/include/asm-arm/cadence-uart.h

diff --git a/config/arm64.mk b/config/arm64.mk
index 6eafda2..df6ad0a 100644
--- a/config/arm64.mk
+++ b/config/arm64.mk
@@ -7,6 +7,7 @@ CONFIG_XEN_INSTALL_SUFFIX :=
 CFLAGS += #-marm -march= -mcpu= etc
 
 HAS_PL011 := y
+HAS_CADENCE_UART := y
 HAS_NS16550 := y
 
 # Use only if calling $(LD) directly.
diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile
index 9e94195..47fc3f9 100644
--- a/xen/drivers/char/Makefile
+++ b/xen/drivers/char/Makefile
@@ -1,5 +1,6 @@
 obj-y += console.o
 obj-$(HAS_NS16550) += ns16550.o
+obj-$(HAS_CADENCE_UART) += cadence-uart.o
 obj-$(HAS_PL011) += pl011.o
 obj-$(HAS_EXYNOS4210) += exynos4210-uart.o
 obj-$(HAS_OMAP) += omap-uart.o
diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uart.c
new file mode 100644
index 0000000..933672f
--- /dev/null
+++ b/xen/drivers/char/cadence-uart.c
@@ -0,0 +1,224 @@
+/*
+ * xen/drivers/char/cadence-uart.c
+ *
+ * Driver for Cadence UART in Xilinx ZynqMP.
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@gmail.com>
+ * Copyright (c) 2015 Xilinx Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <xen/console.h>
+#include <xen/serial.h>
+#include <xen/init.h>
+#include <xen/irq.h>
+#include <xen/device_tree.h>
+#include <xen/errno.h>
+#include <asm/device.h>
+#include <xen/mm.h>
+#include <xen/vmap.h>
+#include <asm/cadence-uart.h>
+#include <asm/io.h>
+
+static struct cuart {
+    unsigned int irq;
+    void __iomem *regs;
+    /* UART with IRQ line: interrupt-driven I/O. */
+    struct irqaction irqaction;
+    struct vuart_info vuart;
+} cuart_com = {0};
+
+#define cuart_read(uart, off)           readl((uart)->regs + (off))
+#define cuart_write(uart, off,val)      writel((val), (uart)->regs + (off))
+
+static void cuart_interrupt(int irq, void *data, struct cpu_user_regs *regs)
+{
+    struct serial_port *port = data;
+    struct cuart *uart = port->uart;
+    unsigned int status;
+
+    do {
+        status = cuart_read(uart, R_UART_SR);
+        /* ACK.  */
+        if ( status & UART_SR_INTR_RTRIG )
+        {
+            serial_rx_interrupt(port, regs);
+            cuart_write(uart, R_UART_CISR, UART_SR_INTR_RTRIG);
+        }
+    } while ( status & UART_SR_INTR_RTRIG );
+}
+
+static void __init cuart_init_preirq(struct serial_port *port)
+{
+    struct cuart *uart = port->uart;
+
+    cuart_write(uart, R_UART_MR, UART_MR_NO_PARITY);
+    /* Enable and Reset both the RX and TX paths.  */
+    cuart_write(uart, R_UART_CR, UART_CR_RX_RST | UART_CR_TX_RST |
+                      UART_CR_RX_ENABLE | UART_CR_TX_ENABLE);
+}
+
+static void __init cuart_init_postirq(struct serial_port *port)
+{
+    struct cuart *uart = port->uart;
+    int rc;
+
+    if ( uart->irq > 0 )
+    {
+        uart->irqaction.handler = cuart_interrupt;
+        uart->irqaction.name    = "cadence-uart";
+        uart->irqaction.dev_id  = port;
+        if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 )
+            printk("ERROR: Failed to allocate cadence-uart IRQ %d\n", uart->irq);
+    }
+
+    /* Clear pending error interrupts */
+    cuart_write(uart, R_UART_RTRIG, 1);
+    cuart_write(uart, R_UART_CISR, ~0);
+
+    /* Unmask interrupts */
+    cuart_write(uart, R_UART_IDR, ~0);
+    cuart_write(uart, R_UART_IER, UART_SR_INTR_RTRIG);
+}
+
+static void cuart_suspend(struct serial_port *port)
+{
+    BUG();
+}
+
+static void cuart_resume(struct serial_port *port)
+{
+    BUG();
+}
+
+static int cuart_tx_ready(struct serial_port *port)
+{
+    struct cuart *uart = port->uart;
+    unsigned int status = cuart_read(uart, R_UART_SR);
+
+    return !( status & UART_SR_INTR_TFUL );
+}
+
+static void cuart_putc(struct serial_port *port, char c)
+{
+    struct cuart *uart = port->uart;
+
+    cuart_write(uart, R_UART_TX, (uint32_t)(unsigned char)c);
+}
+
+static int cuart_getc(struct serial_port *port, char *pc)
+{
+    struct cuart *uart = port->uart;
+
+    if ( cuart_read(uart, R_UART_SR) & UART_SR_INTR_REMPTY )
+        return 0;
+
+    *pc = cuart_read(uart, R_UART_RX) & 0xff;
+    return 1;
+}
+
+static int __init cuart_irq(struct serial_port *port)
+{
+    struct cuart *uart = port->uart;
+
+    return ( (uart->irq > 0) ? uart->irq : -1 );
+}
+
+static const struct vuart_info *cuart_vuart(struct serial_port *port)
+{
+    struct cuart *uart = port->uart;
+
+    return &uart->vuart;
+}
+
+static struct uart_driver __read_mostly cuart_driver = {
+    .init_preirq  = cuart_init_preirq,
+    .init_postirq = cuart_init_postirq,
+    .endboot      = NULL,
+    .suspend      = cuart_suspend,
+    .resume       = cuart_resume,
+    .tx_ready     = cuart_tx_ready,
+    .putc         = cuart_putc,
+    .getc         = cuart_getc,
+    .irq          = cuart_irq,
+    .vuart_info   = cuart_vuart,
+};
+
+static int __init cuart_init(struct dt_device_node *dev, const void *data)
+{
+    const char *config = data;
+    struct cuart *uart;
+    int res;
+    u64 addr, size;
+
+    if ( strcmp(config, "") )
+        printk("WARNING: UART configuration is not supported\n");
+
+    uart = &cuart_com;
+
+    res = dt_device_get_address(dev, 0, &addr, &size);
+    if ( res )
+    {
+        printk("cadence: Unable to retrieve the base"
+               " address of the UART\n");
+        return res;
+    }
+
+    res = platform_get_irq(dev, 0);
+    if ( res < 0 )
+    {
+        printk("cadence: Unable to retrieve the IRQ\n");
+        return -EINVAL;
+    }
+    uart->irq = res;
+
+    uart->regs = ioremap_nocache(addr, size);
+    if ( !uart->regs )
+    {
+        printk("cadence: Unable to map the UART memory\n");
+        return -ENOMEM;
+    }
+
+    uart->vuart.base_addr = addr;
+    uart->vuart.size = size;
+    uart->vuart.data_off = R_UART_RX;
+    uart->vuart.status_off = R_UART_SR;
+    uart->vuart.status = UART_SR_INTR_TEMPTY;
+
+    /* Register with generic serial driver. */
+    serial_register_uart(SERHND_DTUART, &cuart_driver, uart);
+
+    dt_device_set_used_by(dev, DOMID_XEN);
+
+    return 0;
+}
+
+static const struct dt_device_match cuart_dt_match[] __initconst =
+{
+    DT_MATCH_COMPATIBLE("cdns,uart-r1p8"),
+    { /* sentinel */ },
+};
+
+DT_DEVICE_START(cuart, "Cadence UART", DEVICE_SERIAL)
+    .dt_match = cuart_dt_match,
+    .init = cuart_init,
+DT_DEVICE_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/cadence-uart.h b/xen/include/asm-arm/cadence-uart.h
new file mode 100644
index 0000000..48680ee
--- /dev/null
+++ b/xen/include/asm-arm/cadence-uart.h
@@ -0,0 +1,55 @@
+/*
+ * xen/include/asm-arm/cadence-uart.h
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ * Copyright (C) 2015 Xilinx Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_CADENCE_UART_H__
+#define __ASM_ARM_CADENCE_UART_H__
+
+#define R_UART_CR    0x00
+#define UART_CR_RX_RST       0x01
+#define UART_CR_TX_RST       0x02
+#define UART_CR_RX_ENABLE    0x04
+#define UART_CR_RX_DISABLE   0x08
+#define UART_CR_TX_ENABLE    0x10
+#define UART_CR_TX_DISABLE   0x20
+
+#define R_UART_MR    0x04
+#define UART_MR_NO_PARITY    0x20
+
+#define R_UART_IER   0x08
+#define R_UART_IDR   0x0C
+#define R_UART_IMR   0x10
+#define R_UART_CISR  0x14
+#define R_UART_RTRIG 0x20
+#define R_UART_SR    0x2C
+#define UART_SR_INTR_RTRIG   0x01
+#define UART_SR_INTR_REMPTY  0x02
+#define UART_SR_INTR_TEMPTY  0x08
+#define UART_SR_INTR_TFUL    0x10
+
+#define R_UART_TX    0x30
+#define R_UART_RX    0x30
+
+#endif /* __ASM_ARM_CADENCE_UART_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
-- 
1.9.1

[PATCH v3 2/2] xen/arm: Add Xilinx ZynqMP early printk support

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Reviewed-by: Julien Grall <julien.grall@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 docs/misc/arm/early-printk.txt       |  1 +
 xen/arch/arm/Rules.mk                |  6 +++++
 xen/arch/arm/arm64/debug-cadence.inc | 45 ++++++++++++++++++++++++++++++++++++
 3 files changed, 52 insertions(+)
 create mode 100644 xen/arch/arm/arm64/debug-cadence.inc

diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt
index 859c635..710f07e 100644
--- a/docs/misc/arm/early-printk.txt
+++ b/docs/misc/arm/early-printk.txt
@@ -21,6 +21,7 @@ where mach is the name of the machine:
   - seattle: printk with pl011 for AMD Seattle processor
   - lager: printk with SCIF0 on Renesas R-Car H2 processors
   - thunderx: printk with pl011 for Cavium ThunderX processor
+  - zynqmp: printk with Cadence UART for Xilinx ZynqMP SoCs
 
 The base address and baud rate is hardcoded in xen/arch/arm/Rules.mk,
 see there when adding support for new machines.
diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk
index 54efa91..818a5bc 100644
--- a/xen/arch/arm/Rules.mk
+++ b/xen/arch/arm/Rules.mk
@@ -118,6 +118,12 @@ EARLY_PRINTK_INC := pl011
 EARLY_UART_BASE_ADDRESS := 0x87e024000000
 endif
 
+ifeq ($(CONFIG_EARLY_PRINTK), zynqmp)
+EARLY_PRINTK_INC := cadence
+EARLY_PRINTK_BAUD := 115200
+EARLY_UART_BASE_ADDRESS := 0xff000000
+endif
+
 ifneq ($(EARLY_PRINTK_INC),)
 EARLY_PRINTK := y
 endif
diff --git a/xen/arch/arm/arm64/debug-cadence.inc b/xen/arch/arm/arm64/debug-cadence.inc
new file mode 100644
index 0000000..84dee4c
--- /dev/null
+++ b/xen/arch/arm/arm64/debug-cadence.inc
@@ -0,0 +1,45 @@
+/*
+ * xen/arch/arm/arm64/debug-cadence.S
+ *
+ * Cadence UART specific debug code
+ *
+ * Copyright (c) 2015 Xilinx Inc.
+ * Written by Edgar E. Iglesias.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/asm_defns.h>
+#include <asm/cadence-uart.h>
+
+/* Cadence UART wait UART to be ready to transmit
+ * xb: register which contains the UART base address
+ * c: scratch register number */
+.macro early_uart_ready xb, c
+1:
+        ldrh  w\c, [\xb, #R_UART_SR]
+        tst   w\c, #UART_SR_INTR_TFUL
+        b.ne  1b
+.endm
+
+/* Cadence UART transmit character
+ * xb: register which contains the UART base address
+ * wt: register which contains the character to transmit */
+.macro early_uart_transmit xb, wt
+        strb  \wt, [\xb, #R_UART_TX]
+.endm
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
-- 
1.9.1

Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[Julien Grall]

Hello Edgar,

Thank you for adding support of the ZynqMP.

On 10/03/15 02:49, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Adds support for the Cadence UART in Xilinx ZynqMP. The
> rest of the ZynqMP platform is discovered via device-tree.

Did you make sure that the default grant table range (0xb0000000 -
0xb0020000) don't overlap with an hardware region?

Regards,

-- 
Julien Grall

Re: [PATCH v3 1/2] xen/arm: Add Cadence UART driver

[Julien Grall]

Hello Edgar,

On 10/03/15 02:49, Edgar E. Iglesias wrote:
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Julien Grall <julien.grall@linaro.org>

Regards,

-- 
Julien Grall

Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[Edgar E. Iglesias]

On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote:
> Hello Edgar,
> 
> Thank you for adding support of the ZynqMP.
> 
> On 10/03/15 02:49, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > 
> > Adds support for the Cadence UART in Xilinx ZynqMP. The
> > rest of the ZynqMP platform is discovered via device-tree.
> 
> Did you make sure that the default grant table range (0xb0000000 -
> 0xb0020000) don't overlap with an hardware region?

No I didn't, thanks for pointing that out. I need to move these to
another address.

So now I'm back to needing platform specific code. Long term,
Maybe it would make sense making the grant table range somehow
configurable via DT?

Anyway, I'll send a v4 with the platform code to move the gnt
into a reserved area in the memory map.

Thanks,
Edgar


> 
> Regards,
> 
> -- 
> Julien Grall

Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[Ian Campbell]

On Wed, 2015-03-11 at 09:59 +1000, Edgar E. Iglesias wrote:
> On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote:
> > Hello Edgar,
> > 
> > Thank you for adding support of the ZynqMP.
> > 
> > On 10/03/15 02:49, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > > 
> > > Adds support for the Cadence UART in Xilinx ZynqMP. The
> > > rest of the ZynqMP platform is discovered via device-tree.
> > 
> > Did you make sure that the default grant table range (0xb0000000 -
> > 0xb0020000) don't overlap with an hardware region?
> 
> No I didn't, thanks for pointing that out. I need to move these to
> another address.
> 
> So now I'm back to needing platform specific code. Long term,
> Maybe it would make sense making the grant table range somehow
> configurable via DT?

The plan is to have Xen preallocate the grant table pages and expose
their physical address to dom0, so when dom0 then maps it 1:1 it won't
clash with either memory used by Xen or by the dom0's actual assigned
memory and since it is RAM it can't possibly clash with any MMIO.

> Anyway, I'll send a v4 with the platform code to move the gnt
> into a reserved area in the memory map.

Ian.

Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[Edgar E. Iglesias]

[-- Attachment #1.1: Type: text/plain, Size: 1423 bytes --]

Sorry for top post.

That makes sense, thanks!

Cheers,
Edgar

---
Sent from my phone
On 11/03/2015 7:46 pm, "Ian Campbell" <ian.campbell@citrix.com> wrote:

> On Wed, 2015-03-11 at 09:59 +1000, Edgar E. Iglesias wrote:
> > On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote:
> > > Hello Edgar,
> > >
> > > Thank you for adding support of the ZynqMP.
> > >
> > > On 10/03/15 02:49, Edgar E. Iglesias wrote:
> > > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > > >
> > > > Adds support for the Cadence UART in Xilinx ZynqMP. The
> > > > rest of the ZynqMP platform is discovered via device-tree.
> > >
> > > Did you make sure that the default grant table range (0xb0000000 -
> > > 0xb0020000) don't overlap with an hardware region?
> >
> > No I didn't, thanks for pointing that out. I need to move these to
> > another address.
> >
> > So now I'm back to needing platform specific code. Long term,
> > Maybe it would make sense making the grant table range somehow
> > configurable via DT?
>
> The plan is to have Xen preallocate the grant table pages and expose
> their physical address to dom0, so when dom0 then maps it 1:1 it won't
> clash with either memory used by Xen or by the dom0's actual assigned
> memory and since it is RAM it can't possibly clash with any MMIO.
>
> > Anyway, I'll send a v4 with the platform code to move the gnt
> > into a reserved area in the memory map.
>
> Ian.
>
>

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