* [PATCH v10] Add Mediatek thermal support @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Sascha changes since v9: - rebase on v4.3 - Add support for reading the calibration values from nvmem fuses - Only register a single thermal zone instead of four as it seems that's everything needed changes since v8: - Add commit description to binding patch - rebase on v4.3-rc2 changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency ------------- fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v10] Add Mediatek thermal support @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-arm-kernel This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Sascha changes since v9: - rebase on v4.3 - Add support for reading the calibration values from nvmem fuses - Only register a single thermal zone instead of four as it seems that's everything needed changes since v8: - Add commit description to binding patch - rebase on v4.3-rc2 changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency ------------- fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v10] Add Mediatek thermal support @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, Eduardo Valentin Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Matthias Brugger, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Sascha changes since v9: - rebase on v4.3 - Add support for reading the calibration values from nvmem fuses - Only register a single thermal zone instead of four as it seems that's everything needed changes since v8: - Add commit description to binding patch - rebase on v4.3-rc2 changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency ------------- fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 1/3] dt-bindings: thermal: Add binding document for Mediatek thermal controller @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt, Sascha Hauer This adds the device tree binding documentation for the mediatek thermal controller found on Mediatek MT8173 and other SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- .../bindings/thermal/mediatek-thermal.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt new file mode 100644 index 0000000..81f9a51 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -0,0 +1,43 @@ +* Mediatek Thermal + +This describes the device tree binding for the Mediatek thermal controller +which measures the on-SoC temperatures. This device does not have its own ADC, +instead it directly controls the AUXADC via AHB bus accesses. For this reason +this device needs phandles to the AUXADC. Also it controls a mux in the +apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS +is also needed. + +Required properties: +- compatible: "mediatek,mt8173-thermal" +- reg: Address range of the thermal controller +- interrupts: IRQ for the thermal controller +- clocks, clock-names: Clocks needed for the thermal controller. required + clocks are: + "therm": Main clock needed for register access + "auxadc": The AUXADC clock +- resets: Reference to the reset controller controlling the thermal controller. +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. + +Optional properties: +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If + unspecified default values shall be used. +- nvmem-cell-names: Should be "calibration-data" + +Example: + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration_data>; + nvmem-cell-names = "calibration-data"; + }; -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 1/3] dt-bindings: thermal: Add binding document for Mediatek thermal controller @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-arm-kernel This adds the device tree binding documentation for the mediatek thermal controller found on Mediatek MT8173 and other SoCs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- .../bindings/thermal/mediatek-thermal.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt new file mode 100644 index 0000000..81f9a51 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -0,0 +1,43 @@ +* Mediatek Thermal + +This describes the device tree binding for the Mediatek thermal controller +which measures the on-SoC temperatures. This device does not have its own ADC, +instead it directly controls the AUXADC via AHB bus accesses. For this reason +this device needs phandles to the AUXADC. Also it controls a mux in the +apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS +is also needed. + +Required properties: +- compatible: "mediatek,mt8173-thermal" +- reg: Address range of the thermal controller +- interrupts: IRQ for the thermal controller +- clocks, clock-names: Clocks needed for the thermal controller. required + clocks are: + "therm": Main clock needed for register access + "auxadc": The AUXADC clock +- resets: Reference to the reset controller controlling the thermal controller. +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. + +Optional properties: +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If + unspecified default values shall be used. +- nvmem-cell-names: Should be "calibration-data" + +Example: + + thermal: thermal at 1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration_data>; + nvmem-cell-names = "calibration-data"; + }; -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 1/3] dt-bindings: thermal: Add binding document for Mediatek thermal controller @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, Eduardo Valentin Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Matthias Brugger, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r This adds the device tree binding documentation for the mediatek thermal controller found on Mediatek MT8173 and other SoCs. Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> --- .../bindings/thermal/mediatek-thermal.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt new file mode 100644 index 0000000..81f9a51 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -0,0 +1,43 @@ +* Mediatek Thermal + +This describes the device tree binding for the Mediatek thermal controller +which measures the on-SoC temperatures. This device does not have its own ADC, +instead it directly controls the AUXADC via AHB bus accesses. For this reason +this device needs phandles to the AUXADC. Also it controls a mux in the +apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS +is also needed. + +Required properties: +- compatible: "mediatek,mt8173-thermal" +- reg: Address range of the thermal controller +- interrupts: IRQ for the thermal controller +- clocks, clock-names: Clocks needed for the thermal controller. required + clocks are: + "therm": Main clock needed for register access + "auxadc": The AUXADC clock +- resets: Reference to the reset controller controlling the thermal controller. +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. + +Optional properties: +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If + unspecified default values shall be used. +- nvmem-cell-names: Should be "calibration-data" + +Example: + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + reset-names = "therm"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration_data>; + nvmem-cell-names = "calibration-data"; + }; -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 1/3] dt-bindings: thermal: Add binding document for Mediatek thermal controller 2015-11-09 10:13 ` Sascha Hauer @ 2015-11-09 15:59 ` Rob Herring -1 siblings, 0 replies; 139+ messages in thread From: Rob Herring @ 2015-11-09 15:59 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland On Mon, Nov 09, 2015 at 11:13:31AM +0100, Sascha Hauer wrote: > This adds the device tree binding documentation for the mediatek thermal > controller found on Mediatek MT8173 and other SoCs. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Rob Herring <robh@kernel.org> > --- > .../bindings/thermal/mediatek-thermal.txt | 43 ++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > new file mode 100644 > index 0000000..81f9a51 > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > @@ -0,0 +1,43 @@ > +* Mediatek Thermal > + > +This describes the device tree binding for the Mediatek thermal controller > +which measures the on-SoC temperatures. This device does not have its own ADC, > +instead it directly controls the AUXADC via AHB bus accesses. For this reason > +this device needs phandles to the AUXADC. Also it controls a mux in the > +apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS > +is also needed. > + > +Required properties: > +- compatible: "mediatek,mt8173-thermal" > +- reg: Address range of the thermal controller > +- interrupts: IRQ for the thermal controller > +- clocks, clock-names: Clocks needed for the thermal controller. required > + clocks are: > + "therm": Main clock needed for register access > + "auxadc": The AUXADC clock > +- resets: Reference to the reset controller controlling the thermal controller. > +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses > +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. > +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. > + > +Optional properties: > +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If > + unspecified default values shall be used. > +- nvmem-cell-names: Should be "calibration-data" > + > +Example: > + > + thermal: thermal@1100b000 { > + #thermal-sensor-cells = <1>; > + compatible = "mediatek,mt8173-thermal"; > + reg = <0 0x1100b000 0 0x1000>; > + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; > + clock-names = "therm", "auxadc"; > + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; > + reset-names = "therm"; > + mediatek,auxadc = <&auxadc>; > + mediatek,apmixedsys = <&apmixedsys>; > + nvmem-cells = <&thermal_calibration_data>; > + nvmem-cell-names = "calibration-data"; > + }; > -- > 2.6.1 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 1/3] dt-bindings: thermal: Add binding document for Mediatek thermal controller @ 2015-11-09 15:59 ` Rob Herring 0 siblings, 0 replies; 139+ messages in thread From: Rob Herring @ 2015-11-09 15:59 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 09, 2015 at 11:13:31AM +0100, Sascha Hauer wrote: > This adds the device tree binding documentation for the mediatek thermal > controller found on Mediatek MT8173 and other SoCs. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Rob Herring <robh@kernel.org> > --- > .../bindings/thermal/mediatek-thermal.txt | 43 ++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > new file mode 100644 > index 0000000..81f9a51 > --- /dev/null > +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > @@ -0,0 +1,43 @@ > +* Mediatek Thermal > + > +This describes the device tree binding for the Mediatek thermal controller > +which measures the on-SoC temperatures. This device does not have its own ADC, > +instead it directly controls the AUXADC via AHB bus accesses. For this reason > +this device needs phandles to the AUXADC. Also it controls a mux in the > +apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS > +is also needed. > + > +Required properties: > +- compatible: "mediatek,mt8173-thermal" > +- reg: Address range of the thermal controller > +- interrupts: IRQ for the thermal controller > +- clocks, clock-names: Clocks needed for the thermal controller. required > + clocks are: > + "therm": Main clock needed for register access > + "auxadc": The AUXADC clock > +- resets: Reference to the reset controller controlling the thermal controller. > +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses > +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. > +- #thermal-sensor-cells : Should be 0. See ./thermal.txt for a description. > + > +Optional properties: > +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If > + unspecified default values shall be used. > +- nvmem-cell-names: Should be "calibration-data" > + > +Example: > + > + thermal: thermal at 1100b000 { > + #thermal-sensor-cells = <1>; > + compatible = "mediatek,mt8173-thermal"; > + reg = <0 0x1100b000 0 0x1000>; > + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; > + clock-names = "therm", "auxadc"; > + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; > + reset-names = "therm"; > + mediatek,auxadc = <&auxadc>; > + mediatek,apmixedsys = <&apmixedsys>; > + nvmem-cells = <&thermal_calibration_data>; > + nvmem-cell-names = "calibration-data"; > + }; > -- > 2.6.1 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 619 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 628 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..2d2e97c --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,619 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + int t; + + mtk_thermal_get_bank(bank); + + t = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + if (t > tempmax) + tempmax = t; + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 619 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 628 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..2d2e97c --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,619 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + int t; + + mtk_thermal_get_bank(bank); + + t = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + if (t > tempmax) + tempmax = t; + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, Eduardo Valentin Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Matthias Brugger, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 619 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 628 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..2d2e97c --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,619 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + int t; + + mtk_thermal_get_bank(bank); + + t = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + if (t > tempmax) + tempmax = t; + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-09 10:13 ` Sascha Hauer @ 2015-11-09 14:39 ` Andy Shevchenko -1 siblings, 0 replies; 139+ messages in thread From: Andy Shevchenko @ 2015-11-09 14:39 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sascha Hauer, linux-mediatek, linux-arm Mailing List, Matthias Brugger, devicetree, Mark Rutland, Rob Herring On Mon, Nov 9, 2015 at 12:13 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Few style nitpicks. > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + int t; > + > + mtk_thermal_get_bank(bank); > + > + t = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + if (t > tempmax) > + tempmax = t; Would it be tempmax = max_t(int, tempmax, mtk_thermal_bank_temperature(bank)); ? > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); 0x0 like below ? > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret; > + > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) > + return PTR_ERR(cell); > + return 0; > + } > + > + buf = (u32 *)nvmem_cell_read(cell, &len); > + > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + if (len < 3 * sizeof(u32)) { > + dev_warn(dev, "invalid calibration data\n"); > + ret = -EINVAL; > + goto out; > + } > + > + if (buf[0] & MT8173_CALIB_BUF0_VALID) { > + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); > + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); > + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); > + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); > + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); > + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); > + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); > + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); > + } else { > + dev_info(dev, "Device not calibrated, using default calibration values\n"); > + } > + > +out: > + kfree(buf); > + > + return ret; > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); > + if (ret) > + return ret; > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + > + of_node_put(auxadc); > + > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + > + of_node_put(apmixedsys); > + > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, > + &mtk_thermal_ops); > + if (IS_ERR(mt->tzd)) > + goto err_register; > + > + return 0; > + > +err_register: > + clk_disable_unprepare(mt->clk_peri_therm); > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); And Author in the head? -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-09 14:39 ` Andy Shevchenko 0 siblings, 0 replies; 139+ messages in thread From: Andy Shevchenko @ 2015-11-09 14:39 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 9, 2015 at 12:13 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Few style nitpicks. > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + int t; > + > + mtk_thermal_get_bank(bank); > + > + t = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + if (t > tempmax) > + tempmax = t; Would it be tempmax = max_t(int, tempmax, mtk_thermal_bank_temperature(bank)); ? > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); 0x0 like below ? > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret; > + > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) > + return PTR_ERR(cell); > + return 0; > + } > + > + buf = (u32 *)nvmem_cell_read(cell, &len); > + > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + if (len < 3 * sizeof(u32)) { > + dev_warn(dev, "invalid calibration data\n"); > + ret = -EINVAL; > + goto out; > + } > + > + if (buf[0] & MT8173_CALIB_BUF0_VALID) { > + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); > + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); > + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); > + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); > + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); > + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); > + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); > + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); > + } else { > + dev_info(dev, "Device not calibrated, using default calibration values\n"); > + } > + > +out: > + kfree(buf); > + > + return ret; > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); > + if (ret) > + return ret; > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + > + of_node_put(auxadc); > + > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + > + of_node_put(apmixedsys); > + > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, > + &mtk_thermal_ops); > + if (IS_ERR(mt->tzd)) > + goto err_register; > + > + return 0; > + > +err_register: > + clk_disable_unprepare(mt->clk_peri_therm); > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); And Author in the head? -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-18 8:11 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:11 UTC (permalink / raw) To: Andy Shevchenko Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sascha Hauer, linux-mediatek, linux-arm Mailing List, Matthias Brugger, devicetree, Mark Rutland, Rob Herring On Mon, Nov 09, 2015 at 04:39:37PM +0200, Andy Shevchenko wrote: > On Mon, Nov 9, 2015 at 12:13 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Few style nitpicks. > > > > +#include <linux/clk.h> > > +#include <linux/delay.h> > > +#include <linux/interrupt.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/nvmem-consumer.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/platform_device.h> > > +#include <linux/slab.h> > > +#include <linux/io.h> > > +#include <linux/thermal.h> > > +#include <linux/reset.h> > > +#include <linux/types.h> > > +#include <linux/nvmem-consumer.h> > > + > > +/* AUXADC Registers */ > > +#define AUXADC_CON0_V 0x000 > > +#define AUXADC_CON1_V 0x004 > > +#define AUXADC_CON1_SET_V 0x008 > > +#define AUXADC_CON1_CLR_V 0x00c > > +#define AUXADC_CON2_V 0x010 > > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > > +#define AUXADC_MISC_V 0x094 > > + > > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > > + > > +#define APMIXED_SYS_TS_CON1 0x604 > > + > > +/* Thermal Controller Registers */ > > +#define TEMP_MONCTL0 0x000 > > +#define TEMP_MONCTL1 0x004 > > +#define TEMP_MONCTL2 0x008 > > +#define TEMP_MONIDET0 0x014 > > +#define TEMP_MONIDET1 0x018 > > +#define TEMP_MSRCTL0 0x038 > > +#define TEMP_AHBPOLL 0x040 > > +#define TEMP_AHBTO 0x044 > > +#define TEMP_ADCPNP0 0x048 > > +#define TEMP_ADCPNP1 0x04c > > +#define TEMP_ADCPNP2 0x050 > > +#define TEMP_ADCPNP3 0x0b4 > > + > > +#define TEMP_ADCMUX 0x054 > > +#define TEMP_ADCEN 0x060 > > +#define TEMP_PNPMUXADDR 0x064 > > +#define TEMP_ADCMUXADDR 0x068 > > +#define TEMP_ADCENADDR 0x074 > > +#define TEMP_ADCVALIDADDR 0x078 > > +#define TEMP_ADCVOLTADDR 0x07c > > +#define TEMP_RDCTRL 0x080 > > +#define TEMP_ADCVALIDMASK 0x084 > > +#define TEMP_ADCVOLTAGESHIFT 0x088 > > +#define TEMP_ADCWRITECTRL 0x08c > > +#define TEMP_MSR0 0x090 > > +#define TEMP_MSR1 0x094 > > +#define TEMP_MSR2 0x098 > > +#define TEMP_MSR3 0x0B8 > > + > > +#define TEMP_SPARE0 0x0f0 > > + > > +#define PTPCORESEL 0x400 > > + > > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > > + > > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > > + > > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > > + > > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > > + > > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > > + > > +#define MT8173_TS1 0 > > +#define MT8173_TS2 1 > > +#define MT8173_TS3 2 > > +#define MT8173_TS4 3 > > +#define MT8173_TSABB 4 > > + > > +/* AUXADC channel 11 is used for the temperature sensors */ > > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > > + > > +/* The total number of temperature sensors in the MT8173 */ > > +#define MT8173_NUM_SENSORS 5 > > + > > +/* The number of banks in the MT8173 */ > > +#define MT8173_NUM_ZONES 4 > > + > > +/* The number of sensing points per bank */ > > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > > + > > +/* Layout of the fuses providing the calibration data */ > > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > > + > > +#define THERMAL_NAME "mtk-thermal" > > + > > +struct mtk_thermal; > > + > > +struct mtk_thermal_bank { > > + struct mtk_thermal *mt; > > + int id; > > +}; > > + > > +struct mtk_thermal { > > + struct device *dev; > > + void __iomem *thermal_base; > > + > > + struct clk *clk_peri_therm; > > + struct clk *clk_auxadc; > > + > > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > > + > > + struct mutex lock; > > + > > + /* Calibration values */ > > + s32 adc_ge; > > + s32 degc_cali; > > + s32 o_slope; > > + s32 vts[MT8173_NUM_SENSORS]; > > + > > + struct thermal_zone_device *tzd; > > +}; > > + > > +struct mtk_thermal_bank_cfg { > > + unsigned int num_sensors; > > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > > +}; > > + > > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > > + > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; > > + > > +struct mtk_thermal_sense_point { > > + int msr; > > + int adcpnp; > > +}; > > + > > +static const struct mtk_thermal_sense_point > > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > > + { > > + .msr = TEMP_MSR0, > > + .adcpnp = TEMP_ADCPNP0, > > + }, { > > + .msr = TEMP_MSR1, > > + .adcpnp = TEMP_ADCPNP1, > > + }, { > > + .msr = TEMP_MSR2, > > + .adcpnp = TEMP_ADCPNP2, > > + }, { > > + .msr = TEMP_MSR3, > > + .adcpnp = TEMP_ADCPNP3, > > + }, > > +}; > > + > > +/** > > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > > + * @mt: The thermal controller > > + * @raw: raw ADC value > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > > +{ > > + s32 tmp; > > + > > + raw &= 0xfff; > > + > > + tmp = 203450520 << 3; > > + tmp /= 165 + mt->o_slope; > > + tmp /= 10000 + mt->adc_ge; > > + tmp *= raw - mt->vts[sensno] - 3350; > > + tmp >>= 3; > > + > > + return mt->degc_cali * 500 - tmp; > > +} > > + > > +/** > > + * mtk_thermal_get_bank - get bank > > + * @bank: The bank > > + * > > + * The bank registers are banked, we have to select a bank in the > > + * PTPCORESEL register to access it. > > + */ > > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + u32 val; > > + > > + mutex_lock(&mt->lock); > > + > > + val = readl(mt->thermal_base + PTPCORESEL); > > + val &= ~0xf; > > + val |= bank->id; > > + writel(val, mt->thermal_base + PTPCORESEL); > > +} > > + > > +/** > > + * mtk_thermal_put_bank - release bank > > + * @bank: The bank > > + * > > + * release a bank previously taken with mtk_thermal_get_bank, > > + */ > > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + > > + mutex_unlock(&mt->lock); > > +} > > + > > +/** > > + * mtk_thermal_bank_temperature - get the temperature of a bank > > + * @bank: The bank > > + * > > + * The temperature of a bank is considered the maximum temperature of > > + * the sensors associated to the bank. > > + */ > > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > + if (temp > max) > > + max = temp; > > + } > > + > > + return max; > > +} > > + > > +static int mtk_read_temp(void *data, int *temperature) > > +{ > > + struct mtk_thermal *mt = data; > > + int i; > > + int tempmax = INT_MIN; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + int t; > > + > > + mtk_thermal_get_bank(bank); > > + > > + t = mtk_thermal_bank_temperature(bank); > > + > > + mtk_thermal_put_bank(bank); > > + > > + if (t > tempmax) > > + tempmax = t; > > Would it be > tempmax = max_t(int, tempmax, mtk_thermal_bank_temperature(bank)); > ? Yes, even max() works here. Fixed. > > + > > + mtk_thermal_get_bank(bank); > > + > > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > > + > > + /* > > + * filt interval is 1 * 46.540us = 46.54us, > > + * sen interval is 429 * 46.540us = 19.96ms > > + */ > > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > > + mt->thermal_base + TEMP_MONCTL2); > > + > > + /* poll is set to 10u */ > > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > > + mt->thermal_base + TEMP_AHBPOLL); > > + > > + /* temperature sampling control, 1 sample */ > > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > > 0x0 like below ? Ok. > > +static struct platform_driver mtk_thermal_driver = { > > + .probe = mtk_thermal_probe, > > + .remove = mtk_thermal_remove, > > + .driver = { > > + .name = THERMAL_NAME, > > + .of_match_table = mtk_thermal_of_match, > > + }, > > +}; > > + > > +module_platform_driver(mtk_thermal_driver); > > + > > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > > And Author in the head? Added. Thanks for reviewing. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-18 8:11 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:11 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 09, 2015 at 04:39:37PM +0200, Andy Shevchenko wrote: > On Mon, Nov 9, 2015 at 12:13 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Few style nitpicks. > > > > +#include <linux/clk.h> > > +#include <linux/delay.h> > > +#include <linux/interrupt.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/nvmem-consumer.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/platform_device.h> > > +#include <linux/slab.h> > > +#include <linux/io.h> > > +#include <linux/thermal.h> > > +#include <linux/reset.h> > > +#include <linux/types.h> > > +#include <linux/nvmem-consumer.h> > > + > > +/* AUXADC Registers */ > > +#define AUXADC_CON0_V 0x000 > > +#define AUXADC_CON1_V 0x004 > > +#define AUXADC_CON1_SET_V 0x008 > > +#define AUXADC_CON1_CLR_V 0x00c > > +#define AUXADC_CON2_V 0x010 > > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > > +#define AUXADC_MISC_V 0x094 > > + > > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > > + > > +#define APMIXED_SYS_TS_CON1 0x604 > > + > > +/* Thermal Controller Registers */ > > +#define TEMP_MONCTL0 0x000 > > +#define TEMP_MONCTL1 0x004 > > +#define TEMP_MONCTL2 0x008 > > +#define TEMP_MONIDET0 0x014 > > +#define TEMP_MONIDET1 0x018 > > +#define TEMP_MSRCTL0 0x038 > > +#define TEMP_AHBPOLL 0x040 > > +#define TEMP_AHBTO 0x044 > > +#define TEMP_ADCPNP0 0x048 > > +#define TEMP_ADCPNP1 0x04c > > +#define TEMP_ADCPNP2 0x050 > > +#define TEMP_ADCPNP3 0x0b4 > > + > > +#define TEMP_ADCMUX 0x054 > > +#define TEMP_ADCEN 0x060 > > +#define TEMP_PNPMUXADDR 0x064 > > +#define TEMP_ADCMUXADDR 0x068 > > +#define TEMP_ADCENADDR 0x074 > > +#define TEMP_ADCVALIDADDR 0x078 > > +#define TEMP_ADCVOLTADDR 0x07c > > +#define TEMP_RDCTRL 0x080 > > +#define TEMP_ADCVALIDMASK 0x084 > > +#define TEMP_ADCVOLTAGESHIFT 0x088 > > +#define TEMP_ADCWRITECTRL 0x08c > > +#define TEMP_MSR0 0x090 > > +#define TEMP_MSR1 0x094 > > +#define TEMP_MSR2 0x098 > > +#define TEMP_MSR3 0x0B8 > > + > > +#define TEMP_SPARE0 0x0f0 > > + > > +#define PTPCORESEL 0x400 > > + > > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > > + > > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > > + > > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > > + > > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > > + > > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > > + > > +#define MT8173_TS1 0 > > +#define MT8173_TS2 1 > > +#define MT8173_TS3 2 > > +#define MT8173_TS4 3 > > +#define MT8173_TSABB 4 > > + > > +/* AUXADC channel 11 is used for the temperature sensors */ > > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > > + > > +/* The total number of temperature sensors in the MT8173 */ > > +#define MT8173_NUM_SENSORS 5 > > + > > +/* The number of banks in the MT8173 */ > > +#define MT8173_NUM_ZONES 4 > > + > > +/* The number of sensing points per bank */ > > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > > + > > +/* Layout of the fuses providing the calibration data */ > > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > > + > > +#define THERMAL_NAME "mtk-thermal" > > + > > +struct mtk_thermal; > > + > > +struct mtk_thermal_bank { > > + struct mtk_thermal *mt; > > + int id; > > +}; > > + > > +struct mtk_thermal { > > + struct device *dev; > > + void __iomem *thermal_base; > > + > > + struct clk *clk_peri_therm; > > + struct clk *clk_auxadc; > > + > > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > > + > > + struct mutex lock; > > + > > + /* Calibration values */ > > + s32 adc_ge; > > + s32 degc_cali; > > + s32 o_slope; > > + s32 vts[MT8173_NUM_SENSORS]; > > + > > + struct thermal_zone_device *tzd; > > +}; > > + > > +struct mtk_thermal_bank_cfg { > > + unsigned int num_sensors; > > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > > +}; > > + > > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > > + > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; > > + > > +struct mtk_thermal_sense_point { > > + int msr; > > + int adcpnp; > > +}; > > + > > +static const struct mtk_thermal_sense_point > > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > > + { > > + .msr = TEMP_MSR0, > > + .adcpnp = TEMP_ADCPNP0, > > + }, { > > + .msr = TEMP_MSR1, > > + .adcpnp = TEMP_ADCPNP1, > > + }, { > > + .msr = TEMP_MSR2, > > + .adcpnp = TEMP_ADCPNP2, > > + }, { > > + .msr = TEMP_MSR3, > > + .adcpnp = TEMP_ADCPNP3, > > + }, > > +}; > > + > > +/** > > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > > + * @mt: The thermal controller > > + * @raw: raw ADC value > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > > +{ > > + s32 tmp; > > + > > + raw &= 0xfff; > > + > > + tmp = 203450520 << 3; > > + tmp /= 165 + mt->o_slope; > > + tmp /= 10000 + mt->adc_ge; > > + tmp *= raw - mt->vts[sensno] - 3350; > > + tmp >>= 3; > > + > > + return mt->degc_cali * 500 - tmp; > > +} > > + > > +/** > > + * mtk_thermal_get_bank - get bank > > + * @bank: The bank > > + * > > + * The bank registers are banked, we have to select a bank in the > > + * PTPCORESEL register to access it. > > + */ > > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + u32 val; > > + > > + mutex_lock(&mt->lock); > > + > > + val = readl(mt->thermal_base + PTPCORESEL); > > + val &= ~0xf; > > + val |= bank->id; > > + writel(val, mt->thermal_base + PTPCORESEL); > > +} > > + > > +/** > > + * mtk_thermal_put_bank - release bank > > + * @bank: The bank > > + * > > + * release a bank previously taken with mtk_thermal_get_bank, > > + */ > > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + > > + mutex_unlock(&mt->lock); > > +} > > + > > +/** > > + * mtk_thermal_bank_temperature - get the temperature of a bank > > + * @bank: The bank > > + * > > + * The temperature of a bank is considered the maximum temperature of > > + * the sensors associated to the bank. > > + */ > > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > + if (temp > max) > > + max = temp; > > + } > > + > > + return max; > > +} > > + > > +static int mtk_read_temp(void *data, int *temperature) > > +{ > > + struct mtk_thermal *mt = data; > > + int i; > > + int tempmax = INT_MIN; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + int t; > > + > > + mtk_thermal_get_bank(bank); > > + > > + t = mtk_thermal_bank_temperature(bank); > > + > > + mtk_thermal_put_bank(bank); > > + > > + if (t > tempmax) > > + tempmax = t; > > Would it be > tempmax = max_t(int, tempmax, mtk_thermal_bank_temperature(bank)); > ? Yes, even max() works here. Fixed. > > + > > + mtk_thermal_get_bank(bank); > > + > > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > > + > > + /* > > + * filt interval is 1 * 46.540us = 46.54us, > > + * sen interval is 429 * 46.540us = 19.96ms > > + */ > > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > > + mt->thermal_base + TEMP_MONCTL2); > > + > > + /* poll is set to 10u */ > > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > > + mt->thermal_base + TEMP_AHBPOLL); > > + > > + /* temperature sampling control, 1 sample */ > > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > > 0x0 like below ? Ok. > > +static struct platform_driver mtk_thermal_driver = { > > + .probe = mtk_thermal_probe, > > + .remove = mtk_thermal_remove, > > + .driver = { > > + .name = THERMAL_NAME, > > + .of_match_table = mtk_thermal_of_match, > > + }, > > +}; > > + > > +module_platform_driver(mtk_thermal_driver); > > + > > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > > And Author in the head? Added. Thanks for reviewing. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-18 8:11 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:11 UTC (permalink / raw) To: Andy Shevchenko Cc: Mark Rutland, devicetree, linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Eduardo Valentin, Rob Herring, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sascha Hauer, Matthias Brugger, Zhang Rui, linux-arm Mailing List On Mon, Nov 09, 2015 at 04:39:37PM +0200, Andy Shevchenko wrote: > On Mon, Nov 9, 2015 at 12:13 PM, Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Few style nitpicks. > > > > +#include <linux/clk.h> > > +#include <linux/delay.h> > > +#include <linux/interrupt.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/nvmem-consumer.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/platform_device.h> > > +#include <linux/slab.h> > > +#include <linux/io.h> > > +#include <linux/thermal.h> > > +#include <linux/reset.h> > > +#include <linux/types.h> > > +#include <linux/nvmem-consumer.h> > > + > > +/* AUXADC Registers */ > > +#define AUXADC_CON0_V 0x000 > > +#define AUXADC_CON1_V 0x004 > > +#define AUXADC_CON1_SET_V 0x008 > > +#define AUXADC_CON1_CLR_V 0x00c > > +#define AUXADC_CON2_V 0x010 > > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > > +#define AUXADC_MISC_V 0x094 > > + > > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > > + > > +#define APMIXED_SYS_TS_CON1 0x604 > > + > > +/* Thermal Controller Registers */ > > +#define TEMP_MONCTL0 0x000 > > +#define TEMP_MONCTL1 0x004 > > +#define TEMP_MONCTL2 0x008 > > +#define TEMP_MONIDET0 0x014 > > +#define TEMP_MONIDET1 0x018 > > +#define TEMP_MSRCTL0 0x038 > > +#define TEMP_AHBPOLL 0x040 > > +#define TEMP_AHBTO 0x044 > > +#define TEMP_ADCPNP0 0x048 > > +#define TEMP_ADCPNP1 0x04c > > +#define TEMP_ADCPNP2 0x050 > > +#define TEMP_ADCPNP3 0x0b4 > > + > > +#define TEMP_ADCMUX 0x054 > > +#define TEMP_ADCEN 0x060 > > +#define TEMP_PNPMUXADDR 0x064 > > +#define TEMP_ADCMUXADDR 0x068 > > +#define TEMP_ADCENADDR 0x074 > > +#define TEMP_ADCVALIDADDR 0x078 > > +#define TEMP_ADCVOLTADDR 0x07c > > +#define TEMP_RDCTRL 0x080 > > +#define TEMP_ADCVALIDMASK 0x084 > > +#define TEMP_ADCVOLTAGESHIFT 0x088 > > +#define TEMP_ADCWRITECTRL 0x08c > > +#define TEMP_MSR0 0x090 > > +#define TEMP_MSR1 0x094 > > +#define TEMP_MSR2 0x098 > > +#define TEMP_MSR3 0x0B8 > > + > > +#define TEMP_SPARE0 0x0f0 > > + > > +#define PTPCORESEL 0x400 > > + > > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > > + > > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > > + > > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > > + > > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > > + > > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > > + > > +#define MT8173_TS1 0 > > +#define MT8173_TS2 1 > > +#define MT8173_TS3 2 > > +#define MT8173_TS4 3 > > +#define MT8173_TSABB 4 > > + > > +/* AUXADC channel 11 is used for the temperature sensors */ > > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > > + > > +/* The total number of temperature sensors in the MT8173 */ > > +#define MT8173_NUM_SENSORS 5 > > + > > +/* The number of banks in the MT8173 */ > > +#define MT8173_NUM_ZONES 4 > > + > > +/* The number of sensing points per bank */ > > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > > + > > +/* Layout of the fuses providing the calibration data */ > > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > > + > > +#define THERMAL_NAME "mtk-thermal" > > + > > +struct mtk_thermal; > > + > > +struct mtk_thermal_bank { > > + struct mtk_thermal *mt; > > + int id; > > +}; > > + > > +struct mtk_thermal { > > + struct device *dev; > > + void __iomem *thermal_base; > > + > > + struct clk *clk_peri_therm; > > + struct clk *clk_auxadc; > > + > > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > > + > > + struct mutex lock; > > + > > + /* Calibration values */ > > + s32 adc_ge; > > + s32 degc_cali; > > + s32 o_slope; > > + s32 vts[MT8173_NUM_SENSORS]; > > + > > + struct thermal_zone_device *tzd; > > +}; > > + > > +struct mtk_thermal_bank_cfg { > > + unsigned int num_sensors; > > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > > +}; > > + > > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > > + > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; > > + > > +struct mtk_thermal_sense_point { > > + int msr; > > + int adcpnp; > > +}; > > + > > +static const struct mtk_thermal_sense_point > > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > > + { > > + .msr = TEMP_MSR0, > > + .adcpnp = TEMP_ADCPNP0, > > + }, { > > + .msr = TEMP_MSR1, > > + .adcpnp = TEMP_ADCPNP1, > > + }, { > > + .msr = TEMP_MSR2, > > + .adcpnp = TEMP_ADCPNP2, > > + }, { > > + .msr = TEMP_MSR3, > > + .adcpnp = TEMP_ADCPNP3, > > + }, > > +}; > > + > > +/** > > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > > + * @mt: The thermal controller > > + * @raw: raw ADC value > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > > +{ > > + s32 tmp; > > + > > + raw &= 0xfff; > > + > > + tmp = 203450520 << 3; > > + tmp /= 165 + mt->o_slope; > > + tmp /= 10000 + mt->adc_ge; > > + tmp *= raw - mt->vts[sensno] - 3350; > > + tmp >>= 3; > > + > > + return mt->degc_cali * 500 - tmp; > > +} > > + > > +/** > > + * mtk_thermal_get_bank - get bank > > + * @bank: The bank > > + * > > + * The bank registers are banked, we have to select a bank in the > > + * PTPCORESEL register to access it. > > + */ > > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + u32 val; > > + > > + mutex_lock(&mt->lock); > > + > > + val = readl(mt->thermal_base + PTPCORESEL); > > + val &= ~0xf; > > + val |= bank->id; > > + writel(val, mt->thermal_base + PTPCORESEL); > > +} > > + > > +/** > > + * mtk_thermal_put_bank - release bank > > + * @bank: The bank > > + * > > + * release a bank previously taken with mtk_thermal_get_bank, > > + */ > > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + > > + mutex_unlock(&mt->lock); > > +} > > + > > +/** > > + * mtk_thermal_bank_temperature - get the temperature of a bank > > + * @bank: The bank > > + * > > + * The temperature of a bank is considered the maximum temperature of > > + * the sensors associated to the bank. > > + */ > > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > + if (temp > max) > > + max = temp; > > + } > > + > > + return max; > > +} > > + > > +static int mtk_read_temp(void *data, int *temperature) > > +{ > > + struct mtk_thermal *mt = data; > > + int i; > > + int tempmax = INT_MIN; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + int t; > > + > > + mtk_thermal_get_bank(bank); > > + > > + t = mtk_thermal_bank_temperature(bank); > > + > > + mtk_thermal_put_bank(bank); > > + > > + if (t > tempmax) > > + tempmax = t; > > Would it be > tempmax = max_t(int, tempmax, mtk_thermal_bank_temperature(bank)); > ? Yes, even max() works here. Fixed. > > + > > + mtk_thermal_get_bank(bank); > > + > > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > > + > > + /* > > + * filt interval is 1 * 46.540us = 46.54us, > > + * sen interval is 429 * 46.540us = 19.96ms > > + */ > > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > > + mt->thermal_base + TEMP_MONCTL2); > > + > > + /* poll is set to 10u */ > > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > > + mt->thermal_base + TEMP_AHBPOLL); > > + > > + /* temperature sampling control, 1 sample */ > > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > > 0x0 like below ? Ok. > > +static struct platform_driver mtk_thermal_driver = { > > + .probe = mtk_thermal_probe, > > + .remove = mtk_thermal_remove, > > + .driver = { > > + .name = THERMAL_NAME, > > + .of_match_table = mtk_thermal_of_match, > > + }, > > +}; > > + > > +module_platform_driver(mtk_thermal_driver); > > + > > +MODULE_AUTHOR("Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org"); > > And Author in the head? Added. Thanks for reviewing. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-09 10:13 ` Sascha Hauer @ 2015-11-10 12:05 ` Javi Merino -1 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-10 12:05 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, mark.rutland, devicetree, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 619 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 628 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 5aabc4b..503448a 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..2d2e97c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,619 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + int t; > + > + mtk_thermal_get_bank(bank); > + > + t = mtk_thermal_bank_temperature(bank); IIUIC, when you had multiple thermal zones mtk_thermal_bank_temperature() made sense, but now it looks like you're just doing the maximum of all sensors. Why bother with the banks any more? Aren't you just calculating the maximum of all sensors? As TS2 is present in all banks, there's no point in reading it four times just to get the maximum of all sensors. > + mtk_thermal_put_bank(bank); > + > + if (t > tempmax) > + tempmax = t; > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-10 12:05 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-10 12:05 UTC (permalink / raw) To: linux-arm-kernel On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 619 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 628 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 5aabc4b..503448a 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..2d2e97c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,619 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + int t; > + > + mtk_thermal_get_bank(bank); > + > + t = mtk_thermal_bank_temperature(bank); IIUIC, when you had multiple thermal zones mtk_thermal_bank_temperature() made sense, but now it looks like you're just doing the maximum of all sensors. Why bother with the banks any more? Aren't you just calculating the maximum of all sensors? As TS2 is present in all banks, there's no point in reading it four times just to get the maximum of all sensors. > + mtk_thermal_put_bank(bank); > + > + if (t > tempmax) > + tempmax = t; > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-10 12:05 ` Javi Merino @ 2015-11-10 18:26 ` Eduardo Valentin -1 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-11-10 18:26 UTC (permalink / raw) To: Javi Merino Cc: Sascha Hauer, linux-pm, Zhang Rui, mark.rutland, devicetree, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: <cut> > > + > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; Would it make sense to simply expose all sensors and let the configuration of their aggregation be done by DT? There is already ongoing effort to get aggregation functions generalized. > > + > > +struct mtk_thermal_sense_point { > > + int msr; > > + int adcpnp; > > +}; > > + > > +static const struct mtk_thermal_sense_point > > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > > + { > > + .msr = TEMP_MSR0, > > + .adcpnp = TEMP_ADCPNP0, > > + }, { > > + .msr = TEMP_MSR1, > > + .adcpnp = TEMP_ADCPNP1, > > + }, { > > + .msr = TEMP_MSR2, > > + .adcpnp = TEMP_ADCPNP2, > > + }, { > > + .msr = TEMP_MSR3, > > + .adcpnp = TEMP_ADCPNP3, > > + }, > > +}; > > + > > +/** > > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > > + * @mt: The thermal controller > > + * @raw: raw ADC value > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > > +{ > > + s32 tmp; > > + > > + raw &= 0xfff; > > + > > + tmp = 203450520 << 3; > > + tmp /= 165 + mt->o_slope; > > + tmp /= 10000 + mt->adc_ge; > > + tmp *= raw - mt->vts[sensno] - 3350; > > + tmp >>= 3; > > + > > + return mt->degc_cali * 500 - tmp; > > +} > > + > > +/** > > + * mtk_thermal_get_bank - get bank > > + * @bank: The bank > > + * > > + * The bank registers are banked, we have to select a bank in the > > + * PTPCORESEL register to access it. > > + */ > > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + u32 val; > > + > > + mutex_lock(&mt->lock); > > + > > + val = readl(mt->thermal_base + PTPCORESEL); > > + val &= ~0xf; > > + val |= bank->id; > > + writel(val, mt->thermal_base + PTPCORESEL); > > +} > > + > > +/** > > + * mtk_thermal_put_bank - release bank > > + * @bank: The bank > > + * > > + * release a bank previously taken with mtk_thermal_get_bank, > > + */ > > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + > > + mutex_unlock(&mt->lock); > > +} > > + > > +/** > > + * mtk_thermal_bank_temperature - get the temperature of a bank > > + * @bank: The bank > > + * > > + * The temperature of a bank is considered the maximum temperature of > > + * the sensors associated to the bank. > > + */ > > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > + if (temp > max) > > + max = temp; > > + } > > + > > + return max; > > +} > > + > > +static int mtk_read_temp(void *data, int *temperature) > > +{ > > + struct mtk_thermal *mt = data; > > + int i; > > + int tempmax = INT_MIN; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + int t; > > + > > + mtk_thermal_get_bank(bank); > > + > > + t = mtk_thermal_bank_temperature(bank); > > IIUIC, when you had multiple thermal zones > mtk_thermal_bank_temperature() made sense, but now it looks like > you're just doing the maximum of all sensors. Why bother with the > banks any more? Aren't you just calculating the maximum of all > sensors? As TS2 is present in all banks, there's no point in reading > it four times just to get the maximum of all sensors. > Yeah, agreed here. If that is your intention, maybe read each sensor one time, then compute the max of each subset from memory instead. > > + mtk_thermal_put_bank(bank); > > + > > + if (t > tempmax) > > + tempmax = t; > > + } > > + > > + *temperature = tempmax; > > + > > + return 0; > > +} > > + > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > + .get_temp = mtk_read_temp, > > +}; > > Cheers, > Javi > ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-10 18:26 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-11-10 18:26 UTC (permalink / raw) To: linux-arm-kernel On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: <cut> > > + > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; Would it make sense to simply expose all sensors and let the configuration of their aggregation be done by DT? There is already ongoing effort to get aggregation functions generalized. > > + > > +struct mtk_thermal_sense_point { > > + int msr; > > + int adcpnp; > > +}; > > + > > +static const struct mtk_thermal_sense_point > > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > > + { > > + .msr = TEMP_MSR0, > > + .adcpnp = TEMP_ADCPNP0, > > + }, { > > + .msr = TEMP_MSR1, > > + .adcpnp = TEMP_ADCPNP1, > > + }, { > > + .msr = TEMP_MSR2, > > + .adcpnp = TEMP_ADCPNP2, > > + }, { > > + .msr = TEMP_MSR3, > > + .adcpnp = TEMP_ADCPNP3, > > + }, > > +}; > > + > > +/** > > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > > + * @mt: The thermal controller > > + * @raw: raw ADC value > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > > +{ > > + s32 tmp; > > + > > + raw &= 0xfff; > > + > > + tmp = 203450520 << 3; > > + tmp /= 165 + mt->o_slope; > > + tmp /= 10000 + mt->adc_ge; > > + tmp *= raw - mt->vts[sensno] - 3350; > > + tmp >>= 3; > > + > > + return mt->degc_cali * 500 - tmp; > > +} > > + > > +/** > > + * mtk_thermal_get_bank - get bank > > + * @bank: The bank > > + * > > + * The bank registers are banked, we have to select a bank in the > > + * PTPCORESEL register to access it. > > + */ > > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + u32 val; > > + > > + mutex_lock(&mt->lock); > > + > > + val = readl(mt->thermal_base + PTPCORESEL); > > + val &= ~0xf; > > + val |= bank->id; > > + writel(val, mt->thermal_base + PTPCORESEL); > > +} > > + > > +/** > > + * mtk_thermal_put_bank - release bank > > + * @bank: The bank > > + * > > + * release a bank previously taken with mtk_thermal_get_bank, > > + */ > > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + > > + mutex_unlock(&mt->lock); > > +} > > + > > +/** > > + * mtk_thermal_bank_temperature - get the temperature of a bank > > + * @bank: The bank > > + * > > + * The temperature of a bank is considered the maximum temperature of > > + * the sensors associated to the bank. > > + */ > > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > > +{ > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > + if (temp > max) > > + max = temp; > > + } > > + > > + return max; > > +} > > + > > +static int mtk_read_temp(void *data, int *temperature) > > +{ > > + struct mtk_thermal *mt = data; > > + int i; > > + int tempmax = INT_MIN; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + int t; > > + > > + mtk_thermal_get_bank(bank); > > + > > + t = mtk_thermal_bank_temperature(bank); > > IIUIC, when you had multiple thermal zones > mtk_thermal_bank_temperature() made sense, but now it looks like > you're just doing the maximum of all sensors. Why bother with the > banks any more? Aren't you just calculating the maximum of all > sensors? As TS2 is present in all banks, there's no point in reading > it four times just to get the maximum of all sensors. > Yeah, agreed here. If that is your intention, maybe read each sensor one time, then compute the max of each subset from memory instead. > > + mtk_thermal_put_bank(bank); > > + > > + if (t > tempmax) > > + tempmax = t; > > + } > > + > > + *temperature = tempmax; > > + > > + return 0; > > +} > > + > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > + .get_temp = mtk_read_temp, > > +}; > > Cheers, > Javi > ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-10 18:26 ` Eduardo Valentin @ 2015-11-11 7:27 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-11 7:27 UTC (permalink / raw) To: Eduardo Valentin Cc: Javi Merino, linux-pm, Zhang Rui, mark.rutland, devicetree, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > <cut> > > > > + > > > +/* > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > + * temperature sensors. We use each bank to measure a certain area of the > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > + * areas, hence is used in different banks. > > > + */ > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > + { > > > + .num_sensors = 2, > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > + }, { > > > + .num_sensors = 2, > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > + }, { > > > + .num_sensors = 3, > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > + }, { > > > + .num_sensors = 1, > > > + .sensors = { MT8173_TS2 }, > > > + }, > > > +}; > > Would it make sense to simply expose all sensors and let the > configuration of their aggregation be done by DT? This particular layout has been chosen because there's also the Smart Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for measuring temperatures. I don't know the details yet, I just asked the Mediatek guys. > > There is already ongoing effort to get aggregation functions > generalized. Do you have any pointers? I haven't seen these efforts yet. > > > +static int mtk_read_temp(void *data, int *temperature) > > > +{ > > > + struct mtk_thermal *mt = data; > > > + int i; > > > + int tempmax = INT_MIN; > > > + > > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > > + int t; > > > + > > > + mtk_thermal_get_bank(bank); > > > + > > > + t = mtk_thermal_bank_temperature(bank); > > > > IIUIC, when you had multiple thermal zones > > mtk_thermal_bank_temperature() made sense, but now it looks like > > you're just doing the maximum of all sensors. Why bother with the > > banks any more? Aren't you just calculating the maximum of all > > sensors? As TS2 is present in all banks, there's no point in reading > > it four times just to get the maximum of all sensors. > > > > Yeah, agreed here. If that is your intention, maybe read each sensor one > time, then compute the max of each subset from memory instead. I would have done that if there wasn't this SVS engine. I'll ask internally what the constraint of this SVS engine actually are and let you know. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-11 7:27 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-11 7:27 UTC (permalink / raw) To: linux-arm-kernel On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > <cut> > > > > + > > > +/* > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > + * temperature sensors. We use each bank to measure a certain area of the > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > + * areas, hence is used in different banks. > > > + */ > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > + { > > > + .num_sensors = 2, > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > + }, { > > > + .num_sensors = 2, > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > + }, { > > > + .num_sensors = 3, > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > + }, { > > > + .num_sensors = 1, > > > + .sensors = { MT8173_TS2 }, > > > + }, > > > +}; > > Would it make sense to simply expose all sensors and let the > configuration of their aggregation be done by DT? This particular layout has been chosen because there's also the Smart Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for measuring temperatures. I don't know the details yet, I just asked the Mediatek guys. > > There is already ongoing effort to get aggregation functions > generalized. Do you have any pointers? I haven't seen these efforts yet. > > > +static int mtk_read_temp(void *data, int *temperature) > > > +{ > > > + struct mtk_thermal *mt = data; > > > + int i; > > > + int tempmax = INT_MIN; > > > + > > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > > + int t; > > > + > > > + mtk_thermal_get_bank(bank); > > > + > > > + t = mtk_thermal_bank_temperature(bank); > > > > IIUIC, when you had multiple thermal zones > > mtk_thermal_bank_temperature() made sense, but now it looks like > > you're just doing the maximum of all sensors. Why bother with the > > banks any more? Aren't you just calculating the maximum of all > > sensors? As TS2 is present in all banks, there's no point in reading > > it four times just to get the maximum of all sensors. > > > > Yeah, agreed here. If that is your intention, maybe read each sensor one > time, then compute the max of each subset from memory instead. I would have done that if there wasn't this SVS engine. I'll ask internally what the constraint of this SVS engine actually are and let you know. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-11 9:40 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-11 9:40 UTC (permalink / raw) To: Sascha Hauer Cc: Eduardo Valentin, linux-pm, Zhang Rui, mark.rutland, devicetree, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > <cut> > > > > > > + > > > > +/* > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > + * areas, hence is used in different banks. > > > > + */ > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > + { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > + }, { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > + }, { > > > > + .num_sensors = 3, > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > + }, { > > > > + .num_sensors = 1, > > > > + .sensors = { MT8173_TS2 }, > > > > + }, > > > > +}; > > > > Would it make sense to simply expose all sensors and let the > > configuration of their aggregation be done by DT? > > This particular layout has been chosen because there's also the Smart > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > measuring temperatures. I don't know the details yet, I just asked the > Mediatek guys. > > > > > There is already ongoing effort to get aggregation functions > > generalized. > > Do you have any pointers? I haven't seen these efforts yet. Hierarchical thermal zones http://thread.gmane.org/gmane.linux.power-management.general/67785 You could keep your thermal zones per bank and then use the hierarchical thermal zone to create a thermal zone that calculates the maximum of all banks. You can put the trip points in this thermal zone. > > > > +static int mtk_read_temp(void *data, int *temperature) > > > > +{ > > > > + struct mtk_thermal *mt = data; > > > > + int i; > > > > + int tempmax = INT_MIN; > > > > + > > > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > > > + int t; > > > > + > > > > + mtk_thermal_get_bank(bank); > > > > + > > > > + t = mtk_thermal_bank_temperature(bank); > > > > > > IIUIC, when you had multiple thermal zones > > > mtk_thermal_bank_temperature() made sense, but now it looks like > > > you're just doing the maximum of all sensors. Why bother with the > > > banks any more? Aren't you just calculating the maximum of all > > > sensors? As TS2 is present in all banks, there's no point in reading > > > it four times just to get the maximum of all sensors. > > > > > > > Yeah, agreed here. If that is your intention, maybe read each sensor one > > time, then compute the max of each subset from memory instead. > > I would have done that if there wasn't this SVS engine. I'll ask > internally what the constraint of this SVS engine actually are and let > you know. > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-11 9:40 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-11 9:40 UTC (permalink / raw) To: linux-arm-kernel On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > <cut> > > > > > > + > > > > +/* > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > + * areas, hence is used in different banks. > > > > + */ > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > + { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > + }, { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > + }, { > > > > + .num_sensors = 3, > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > + }, { > > > > + .num_sensors = 1, > > > > + .sensors = { MT8173_TS2 }, > > > > + }, > > > > +}; > > > > Would it make sense to simply expose all sensors and let the > > configuration of their aggregation be done by DT? > > This particular layout has been chosen because there's also the Smart > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > measuring temperatures. I don't know the details yet, I just asked the > Mediatek guys. > > > > > There is already ongoing effort to get aggregation functions > > generalized. > > Do you have any pointers? I haven't seen these efforts yet. Hierarchical thermal zones http://thread.gmane.org/gmane.linux.power-management.general/67785 You could keep your thermal zones per bank and then use the hierarchical thermal zone to create a thermal zone that calculates the maximum of all banks. You can put the trip points in this thermal zone. > > > > +static int mtk_read_temp(void *data, int *temperature) > > > > +{ > > > > + struct mtk_thermal *mt = data; > > > > + int i; > > > > + int tempmax = INT_MIN; > > > > + > > > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > > > + int t; > > > > + > > > > + mtk_thermal_get_bank(bank); > > > > + > > > > + t = mtk_thermal_bank_temperature(bank); > > > > > > IIUIC, when you had multiple thermal zones > > > mtk_thermal_bank_temperature() made sense, but now it looks like > > > you're just doing the maximum of all sensors. Why bother with the > > > banks any more? Aren't you just calculating the maximum of all > > > sensors? As TS2 is present in all banks, there's no point in reading > > > it four times just to get the maximum of all sensors. > > > > > > > Yeah, agreed here. If that is your intention, maybe read each sensor one > > time, then compute the max of each subset from memory instead. > > I would have done that if there wasn't this SVS engine. I'll ask > internally what the constraint of this SVS engine actually are and let > you know. > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-11 9:40 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-11 9:40 UTC (permalink / raw) To: Sascha Hauer Cc: Eduardo Valentin, linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Matthias Brugger, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > <cut> > > > > > > + > > > > +/* > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > + * areas, hence is used in different banks. > > > > + */ > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > + { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > + }, { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > + }, { > > > > + .num_sensors = 3, > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > + }, { > > > > + .num_sensors = 1, > > > > + .sensors = { MT8173_TS2 }, > > > > + }, > > > > +}; > > > > Would it make sense to simply expose all sensors and let the > > configuration of their aggregation be done by DT? > > This particular layout has been chosen because there's also the Smart > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > measuring temperatures. I don't know the details yet, I just asked the > Mediatek guys. > > > > > There is already ongoing effort to get aggregation functions > > generalized. > > Do you have any pointers? I haven't seen these efforts yet. Hierarchical thermal zones http://thread.gmane.org/gmane.linux.power-management.general/67785 You could keep your thermal zones per bank and then use the hierarchical thermal zone to create a thermal zone that calculates the maximum of all banks. You can put the trip points in this thermal zone. > > > > +static int mtk_read_temp(void *data, int *temperature) > > > > +{ > > > > + struct mtk_thermal *mt = data; > > > > + int i; > > > > + int tempmax = INT_MIN; > > > > + > > > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > > > + int t; > > > > + > > > > + mtk_thermal_get_bank(bank); > > > > + > > > > + t = mtk_thermal_bank_temperature(bank); > > > > > > IIUIC, when you had multiple thermal zones > > > mtk_thermal_bank_temperature() made sense, but now it looks like > > > you're just doing the maximum of all sensors. Why bother with the > > > banks any more? Aren't you just calculating the maximum of all > > > sensors? As TS2 is present in all banks, there's no point in reading > > > it four times just to get the maximum of all sensors. > > > > > > > Yeah, agreed here. If that is your intention, maybe read each sensor one > > time, then compute the max of each subset from memory instead. > > I would have done that if there wasn't this SVS engine. I'll ask > internally what the constraint of this SVS engine actually are and let > you know. > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-11 7:27 ` Sascha Hauer @ 2015-11-13 10:09 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-13 10:09 UTC (permalink / raw) To: Eduardo Valentin Cc: mark.rutland, devicetree, Javi Merino, linux-pm, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > <cut> > > > > > > + > > > > +/* > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > + * areas, hence is used in different banks. > > > > + */ > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > + { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > + }, { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > + }, { > > > > + .num_sensors = 3, > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > + }, { > > > > + .num_sensors = 1, > > > > + .sensors = { MT8173_TS2 }, > > > > + }, > > > > +}; > > > > Would it make sense to simply expose all sensors and let the > > configuration of their aggregation be done by DT? > > This particular layout has been chosen because there's also the Smart > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > measuring temperatures. I don't know the details yet, I just asked the > Mediatek guys. Ok, the job of the SVS is to always pick the best voltage for a given CPU frequency based on the temperature of the CPU cluster. How I understand it the SVS engine automatically reads temperatures from bank0 for the first CPU cluster and from bank1 for the second CPU cluster. For this to work we are not free to assign the sensors to the banks arbitrarily. I was told that controlling the CPU frequency the performance is better if we use the maximum temperature of the whole die rather than the temperature of individual clusters. I would prefer to keep the sensor/bank association like it currently is as it allows for easy SVS engine integration. Also I would prefer to expose a single thermal zone for now, it will be easier to add additional zones later than it is to remove them later once we have exposed them to the device tree. Is that ok with you? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-13 10:09 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-13 10:09 UTC (permalink / raw) To: linux-arm-kernel On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > <cut> > > > > > > + > > > > +/* > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > + * areas, hence is used in different banks. > > > > + */ > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > + { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > + }, { > > > > + .num_sensors = 2, > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > + }, { > > > > + .num_sensors = 3, > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > + }, { > > > > + .num_sensors = 1, > > > > + .sensors = { MT8173_TS2 }, > > > > + }, > > > > +}; > > > > Would it make sense to simply expose all sensors and let the > > configuration of their aggregation be done by DT? > > This particular layout has been chosen because there's also the Smart > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > measuring temperatures. I don't know the details yet, I just asked the > Mediatek guys. Ok, the job of the SVS is to always pick the best voltage for a given CPU frequency based on the temperature of the CPU cluster. How I understand it the SVS engine automatically reads temperatures from bank0 for the first CPU cluster and from bank1 for the second CPU cluster. For this to work we are not free to assign the sensors to the banks arbitrarily. I was told that controlling the CPU frequency the performance is better if we use the maximum temperature of the whole die rather than the temperature of individual clusters. I would prefer to keep the sensor/bank association like it currently is as it allows for easy SVS engine integration. Also I would prefer to expose a single thermal zone for now, it will be easier to add additional zones later than it is to remove them later once we have exposed them to the device tree. Is that ok with you? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-13 10:09 ` Sascha Hauer @ 2015-11-13 11:26 ` Javi Merino -1 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-13 11:26 UTC (permalink / raw) To: Sascha Hauer Cc: Eduardo Valentin, mark.rutland, devicetree, linux-pm, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Fri, Nov 13, 2015 at 11:09:12AM +0100, Sascha Hauer wrote: > On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > > > <cut> > > > > > > > > + > > > > > +/* > > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > > + * areas, hence is used in different banks. > > > > > + */ > > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > > + { > > > > > + .num_sensors = 2, > > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > > + }, { > > > > > + .num_sensors = 2, > > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > > + }, { > > > > > + .num_sensors = 3, > > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > > + }, { > > > > > + .num_sensors = 1, > > > > > + .sensors = { MT8173_TS2 }, > > > > > + }, > > > > > +}; > > > > > > Would it make sense to simply expose all sensors and let the > > > configuration of their aggregation be done by DT? > > > > This particular layout has been chosen because there's also the Smart > > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > > measuring temperatures. I don't know the details yet, I just asked the > > Mediatek guys. > > Ok, the job of the SVS is to always pick the best voltage for a given > CPU frequency based on the temperature of the CPU cluster. How I > understand it the SVS engine automatically reads temperatures from bank0 > for the first CPU cluster and from bank1 for the second CPU cluster. For > this to work we are not free to assign the sensors to the banks > arbitrarily. > > I was told that controlling the CPU frequency the performance is better > if we use the maximum temperature of the whole die rather than the > temperature of individual clusters. > > I would prefer to keep the sensor/bank association like it currently is > as it allows for easy SVS engine integration. Also I would prefer to > expose a single thermal zone for now, it will be easier to add > additional zones later than it is to remove them later once we have > exposed them to the device tree. > > Is that ok with you? Fair enough. I agree that it's easier to add thermal zones in the future than to remove it. Thanks for the explanation. Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-13 11:26 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2015-11-13 11:26 UTC (permalink / raw) To: linux-arm-kernel On Fri, Nov 13, 2015 at 11:09:12AM +0100, Sascha Hauer wrote: > On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > > > <cut> > > > > > > > > + > > > > > +/* > > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > > + * areas, hence is used in different banks. > > > > > + */ > > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > > + { > > > > > + .num_sensors = 2, > > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > > + }, { > > > > > + .num_sensors = 2, > > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > > + }, { > > > > > + .num_sensors = 3, > > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > > + }, { > > > > > + .num_sensors = 1, > > > > > + .sensors = { MT8173_TS2 }, > > > > > + }, > > > > > +}; > > > > > > Would it make sense to simply expose all sensors and let the > > > configuration of their aggregation be done by DT? > > > > This particular layout has been chosen because there's also the Smart > > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > > measuring temperatures. I don't know the details yet, I just asked the > > Mediatek guys. > > Ok, the job of the SVS is to always pick the best voltage for a given > CPU frequency based on the temperature of the CPU cluster. How I > understand it the SVS engine automatically reads temperatures from bank0 > for the first CPU cluster and from bank1 for the second CPU cluster. For > this to work we are not free to assign the sensors to the banks > arbitrarily. > > I was told that controlling the CPU frequency the performance is better > if we use the maximum temperature of the whole die rather than the > temperature of individual clusters. > > I would prefer to keep the sensor/bank association like it currently is > as it allows for easy SVS engine integration. Also I would prefer to > expose a single thermal zone for now, it will be easier to add > additional zones later than it is to remove them later once we have > exposed them to the device tree. > > Is that ok with you? Fair enough. I agree that it's easier to add thermal zones in the future than to remove it. Thanks for the explanation. Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-13 11:26 ` Javi Merino @ 2015-11-18 8:18 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:18 UTC (permalink / raw) To: Javi Merino Cc: Eduardo Valentin, mark.rutland, devicetree, linux-pm, linux-kernel, robh+dt, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Fri, Nov 13, 2015 at 11:26:37AM +0000, Javi Merino wrote: > On Fri, Nov 13, 2015 at 11:09:12AM +0100, Sascha Hauer wrote: > > On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > > > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > > > > > <cut> > > > > > > > > > > + > > > > > > +/* > > > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > > > + * areas, hence is used in different banks. > > > > > > + */ > > > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > > > + { > > > > > > + .num_sensors = 2, > > > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > > > + }, { > > > > > > + .num_sensors = 2, > > > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > > > + }, { > > > > > > + .num_sensors = 3, > > > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > > > + }, { > > > > > > + .num_sensors = 1, > > > > > > + .sensors = { MT8173_TS2 }, > > > > > > + }, > > > > > > +}; > > > > > > > > Would it make sense to simply expose all sensors and let the > > > > configuration of their aggregation be done by DT? > > > > > > This particular layout has been chosen because there's also the Smart > > > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > > > measuring temperatures. I don't know the details yet, I just asked the > > > Mediatek guys. > > > > Ok, the job of the SVS is to always pick the best voltage for a given > > CPU frequency based on the temperature of the CPU cluster. How I > > understand it the SVS engine automatically reads temperatures from bank0 > > for the first CPU cluster and from bank1 for the second CPU cluster. For > > this to work we are not free to assign the sensors to the banks > > arbitrarily. > > > > I was told that controlling the CPU frequency the performance is better > > if we use the maximum temperature of the whole die rather than the > > temperature of individual clusters. > > > > I would prefer to keep the sensor/bank association like it currently is > > as it allows for easy SVS engine integration. Also I would prefer to > > expose a single thermal zone for now, it will be easier to add > > additional zones later than it is to remove them later once we have > > exposed them to the device tree. > > > > Is that ok with you? > > Fair enough. I agree that it's easier to add thermal zones in the > future than to remove it. Thanks for the explanation. I added this comment to make this a bit clearer for the next version: /* * The thermal core only gets the maximum temperature of all banks, so * the bank concept wouldn't be necessary here. However, the SVS (Smart * Voltage Scaling) unit makes its decisions based on the same bank * data, and this indeed needs the temperatures of the individual * banks * for making better decisions. */ -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-18 8:18 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:18 UTC (permalink / raw) To: linux-arm-kernel On Fri, Nov 13, 2015 at 11:26:37AM +0000, Javi Merino wrote: > On Fri, Nov 13, 2015 at 11:09:12AM +0100, Sascha Hauer wrote: > > On Wed, Nov 11, 2015 at 08:27:47AM +0100, Sascha Hauer wrote: > > > On Tue, Nov 10, 2015 at 10:26:30AM -0800, Eduardo Valentin wrote: > > > > On Tue, Nov 10, 2015 at 12:05:54PM +0000, Javi Merino wrote: > > > > > On Mon, Nov 09, 2015 at 11:13:32AM +0100, Sascha Hauer wrote: > > > > > > > > <cut> > > > > > > > > > > + > > > > > > +/* > > > > > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > > > > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > > > > > + * temperature sensors. We use each bank to measure a certain area of the > > > > > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > > > > > + * areas, hence is used in different banks. > > > > > > + */ > > > > > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > > > > > + { > > > > > > + .num_sensors = 2, > > > > > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > > > > > + }, { > > > > > > + .num_sensors = 2, > > > > > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > > > > > + }, { > > > > > > + .num_sensors = 3, > > > > > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > > > > > + }, { > > > > > > + .num_sensors = 1, > > > > > > + .sensors = { MT8173_TS2 }, > > > > > > + }, > > > > > > +}; > > > > > > > > Would it make sense to simply expose all sensors and let the > > > > configuration of their aggregation be done by DT? > > > > > > This particular layout has been chosen because there's also the Smart > > > Voltage Scaler (SVS) in the SoC. The SVS uses the same banks for > > > measuring temperatures. I don't know the details yet, I just asked the > > > Mediatek guys. > > > > Ok, the job of the SVS is to always pick the best voltage for a given > > CPU frequency based on the temperature of the CPU cluster. How I > > understand it the SVS engine automatically reads temperatures from bank0 > > for the first CPU cluster and from bank1 for the second CPU cluster. For > > this to work we are not free to assign the sensors to the banks > > arbitrarily. > > > > I was told that controlling the CPU frequency the performance is better > > if we use the maximum temperature of the whole die rather than the > > temperature of individual clusters. > > > > I would prefer to keep the sensor/bank association like it currently is > > as it allows for easy SVS engine integration. Also I would prefer to > > expose a single thermal zone for now, it will be easier to add > > additional zones later than it is to remove them later once we have > > exposed them to the device tree. > > > > Is that ok with you? > > Fair enough. I agree that it's easier to add thermal zones in the > future than to remove it. Thanks for the explanation. I added this comment to make this a bit clearer for the next version: /* * The thermal core only gets the maximum temperature of all banks, so * the bank concept wouldn't be necessary here. However, the SVS (Smart * Voltage Scaling) unit makes its decisions based on the same bank * data, and this indeed needs the temperatures of the individual * banks * for making better decisions. */ -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 3/3] ARM64: dts: mt8173: Add thermal/auxadc device nodes 2015-11-09 10:13 ` Sascha Hauer @ 2015-11-09 10:13 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt, Sascha Hauer This adds the thermal controller and auxadc nodes to the Mediatek MT8173 dtsi file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 06a1564..e2ddd03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -277,6 +277,11 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", "mediatek,mt6577-uart"; @@ -487,6 +492,18 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; }; }; -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 3/3] ARM64: dts: mt8173: Add thermal/auxadc device nodes @ 2015-11-09 10:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-09 10:13 UTC (permalink / raw) To: linux-arm-kernel This adds the thermal controller and auxadc nodes to the Mediatek MT8173 dtsi file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 06a1564..e2ddd03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -277,6 +277,11 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + auxadc: auxadc at 11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + }; + uart0: serial at 11002000 { compatible = "mediatek,mt8173-uart", "mediatek,mt6577-uart"; @@ -487,6 +492,18 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + thermal: thermal at 1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; }; }; -- 2.6.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH v12] Add Mediatek thermal support @ 2015-11-30 11:42 Sascha Hauer 2015-11-30 11:42 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-11-30 11:42 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Sascha Changes since v11: - Fix usage of uninitialized variable gcc didn't warn about changes since v10: - Some style cleanup - Add comment to make clear why we use the sensors in banks even if we currently only use the maximum of all banks changes since v9: - rebase on v4.3 - Add support for reading the calibration values from nvmem fuses - Only register a single thermal zone instead of four as it seems that's everything needed changes since v8: - Add commit description to binding patch - rebase on v4.3-rc2 changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency ------------- fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-30 11:42 [PATCH v12] Add Mediatek thermal support Sascha Hauer @ 2015-11-30 11:42 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-30 11:42 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 632 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..589a138 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + * + * The thermal core only gets the maximum temperature of all banks, so + * the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data, and this indeed needs the temperatures of the individual banks + * for making better decisions. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + mtk_thermal_get_bank(bank); + + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); + + mtk_thermal_put_bank(bank); + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret = 0; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.2 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-30 11:42 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-30 11:42 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 632 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..589a138 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + * + * The thermal core only gets the maximum temperature of all banks, so + * the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data, and this indeed needs the temperatures of the individual banks + * for making better decisions. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + mtk_thermal_get_bank(bank); + + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); + + mtk_thermal_put_bank(bank); + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret = 0; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de"); +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.2 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-30 11:42 ` Sascha Hauer @ 2015-12-17 19:33 ` Eduardo Valentin -1 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-12-17 19:33 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger Sascha, Yeah, sorry for the long delay. I was planing on applying this patch for the next merge window, but it just came across one point, see below. On Mon, Nov 30, 2015 at 12:42:32PM +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + <big cut> > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + * > + * The thermal core only gets the maximum temperature of all banks, so > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > + * Voltage Scaling) unit makes its decisions based on the same bank > + * data, and this indeed needs the temperatures of the individual banks > + * for making better decisions. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; Why can't we expose all these as thermal zones? That should remove the policy of computing the maximum from this driver. Please have a look on the work being done [1] to add grouping and aggregation of thermal zones. With that in place, you should be a matter of configuring the grouping and selecting max as the aggregation function, from the thermal core, instead in the driver. Which should give the system engineer, more flexibility to compose whatever policy based on the exposed sensors. BR, Eduardo Valentin [1] - https://lkml.org/lkml/2015/11/25/446 ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-12-17 19:33 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-12-17 19:33 UTC (permalink / raw) To: linux-arm-kernel Sascha, Yeah, sorry for the long delay. I was planing on applying this patch for the next merge window, but it just came across one point, see below. On Mon, Nov 30, 2015 at 12:42:32PM +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + <big cut> > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + * > + * The thermal core only gets the maximum temperature of all banks, so > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > + * Voltage Scaling) unit makes its decisions based on the same bank > + * data, and this indeed needs the temperatures of the individual banks > + * for making better decisions. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; Why can't we expose all these as thermal zones? That should remove the policy of computing the maximum from this driver. Please have a look on the work being done [1] to add grouping and aggregation of thermal zones. With that in place, you should be a matter of configuring the grouping and selecting max as the aggregation function, from the thermal core, instead in the driver. Which should give the system engineer, more flexibility to compose whatever policy based on the exposed sensors. BR, Eduardo Valentin [1] - https://lkml.org/lkml/2015/11/25/446 ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-12-17 19:33 ` Eduardo Valentin @ 2016-01-04 14:19 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-04 14:19 UTC (permalink / raw) To: Eduardo Valentin Cc: linux-pm, Zhang Rui, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger Hi Eduardo, On Thu, Dec 17, 2015 at 11:33:33AM -0800, Eduardo Valentin wrote: > Sascha, > > Yeah, sorry for the long delay. I was planing on applying this patch for > the next merge window, but it just came across one point, see below. > > On Mon, Nov 30, 2015 at 12:42:32PM +0100, Sascha Hauer wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > > + > > <big cut> > > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + * > > + * The thermal core only gets the maximum temperature of all banks, so > > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > > + * Voltage Scaling) unit makes its decisions based on the same bank > > + * data, and this indeed needs the temperatures of the individual banks > > + * for making better decisions. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; > > Why can't we expose all these as thermal zones? > > That should remove the policy of computing the maximum from this driver. > Please have a look on the work being done [1] to add grouping and > aggregation of thermal zones. With that in place, you should be a matter > of configuring the grouping and selecting max as the aggregation function, > from the thermal core, instead in the driver. Which should give the > system engineer, more flexibility to compose whatever policy based on > the exposed sensors. I think the aggregation of thermal zones is quite useful when it comes to putting different chips together to a system. I am not so sure how useful it is to expose different thermal zones of a single SoC to the device tree. Currently the only control knob we have is the CPU frequency. When any of the sensors on the SoC gets too hot then the only thing we can do is to decrease the CPU frequency. This does not leave much space for configuration in the device tree. What I need to be able is to attach multiple sensors to one thermal zone. The aggregation patch series only partly solves that and I think is inconsistent, but I commented on the series directly. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-01-04 14:19 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-04 14:19 UTC (permalink / raw) To: linux-arm-kernel Hi Eduardo, On Thu, Dec 17, 2015 at 11:33:33AM -0800, Eduardo Valentin wrote: > Sascha, > > Yeah, sorry for the long delay. I was planing on applying this patch for > the next merge window, but it just came across one point, see below. > > On Mon, Nov 30, 2015 at 12:42:32PM +0100, Sascha Hauer wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > > + > > <big cut> > > > +/* > > + * The MT8173 thermal controller has four banks. Each bank can read up to > > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > > + * temperature sensors. We use each bank to measure a certain area of the > > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > > + * areas, hence is used in different banks. > > + * > > + * The thermal core only gets the maximum temperature of all banks, so > > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > > + * Voltage Scaling) unit makes its decisions based on the same bank > > + * data, and this indeed needs the temperatures of the individual banks > > + * for making better decisions. > > + */ > > +static const struct mtk_thermal_bank_cfg bank_data[] = { > > + { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS3 }, > > + }, { > > + .num_sensors = 2, > > + .sensors = { MT8173_TS2, MT8173_TS4 }, > > + }, { > > + .num_sensors = 3, > > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > > + }, { > > + .num_sensors = 1, > > + .sensors = { MT8173_TS2 }, > > + }, > > +}; > > Why can't we expose all these as thermal zones? > > That should remove the policy of computing the maximum from this driver. > Please have a look on the work being done [1] to add grouping and > aggregation of thermal zones. With that in place, you should be a matter > of configuring the grouping and selecting max as the aggregation function, > from the thermal core, instead in the driver. Which should give the > system engineer, more flexibility to compose whatever policy based on > the exposed sensors. I think the aggregation of thermal zones is quite useful when it comes to putting different chips together to a system. I am not so sure how useful it is to expose different thermal zones of a single SoC to the device tree. Currently the only control knob we have is the CPU frequency. When any of the sensors on the SoC gets too hot then the only thing we can do is to decrease the CPU frequency. This does not leave much space for configuration in the device tree. What I need to be able is to attach multiple sensors to one thermal zone. The aggregation patch series only partly solves that and I think is inconsistent, but I commented on the series directly. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-01-04 14:19 ` Sascha Hauer @ 2016-01-19 7:29 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-19 7:29 UTC (permalink / raw) To: Eduardo Valentin Cc: linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel Eduardo, On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > Hi Eduardo, > > > > > That should remove the policy of computing the maximum from this driver. > > Please have a look on the work being done [1] to add grouping and > > aggregation of thermal zones. With that in place, you should be a matter > > of configuring the grouping and selecting max as the aggregation function, > > from the thermal core, instead in the driver. Which should give the > > system engineer, more flexibility to compose whatever policy based on > > the exposed sensors. > > I think the aggregation of thermal zones is quite useful when it comes > to putting different chips together to a system. I am not so sure how > useful it is to expose different thermal zones of a single SoC to the > device tree. > Currently the only control knob we have is the CPU frequency. When any > of the sensors on the SoC gets too hot then the only thing we can do is > to decrease the CPU frequency. This does not leave much space for > configuration in the device tree. > What I need to be able is to attach multiple sensors to one thermal > zone. The aggregation patch series only partly solves that and I think > is inconsistent, but I commented on the series directly. Any input on this? I really like to get this driver upstream as it is currently blocking other Mediatek drivers. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-01-19 7:29 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-19 7:29 UTC (permalink / raw) To: linux-arm-kernel Eduardo, On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > Hi Eduardo, > > > > > That should remove the policy of computing the maximum from this driver. > > Please have a look on the work being done [1] to add grouping and > > aggregation of thermal zones. With that in place, you should be a matter > > of configuring the grouping and selecting max as the aggregation function, > > from the thermal core, instead in the driver. Which should give the > > system engineer, more flexibility to compose whatever policy based on > > the exposed sensors. > > I think the aggregation of thermal zones is quite useful when it comes > to putting different chips together to a system. I am not so sure how > useful it is to expose different thermal zones of a single SoC to the > device tree. > Currently the only control knob we have is the CPU frequency. When any > of the sensors on the SoC gets too hot then the only thing we can do is > to decrease the CPU frequency. This does not leave much space for > configuration in the device tree. > What I need to be able is to attach multiple sensors to one thermal > zone. The aggregation patch series only partly solves that and I think > is inconsistent, but I commented on the series directly. Any input on this? I really like to get this driver upstream as it is currently blocking other Mediatek drivers. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-01-19 7:29 ` Sascha Hauer (?) @ 2016-02-01 2:54 ` Eddie Huang -1 siblings, 0 replies; 139+ messages in thread From: Eddie Huang @ 2016-02-01 2:54 UTC (permalink / raw) To: Eduardo Valentin, Sascha Hauer Cc: linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: > Eduardo, > > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > > Hi Eduardo, > > > > > > > > That should remove the policy of computing the maximum from this driver. > > > Please have a look on the work being done [1] to add grouping and > > > aggregation of thermal zones. With that in place, you should be a matter > > > of configuring the grouping and selecting max as the aggregation function, > > > from the thermal core, instead in the driver. Which should give the > > > system engineer, more flexibility to compose whatever policy based on > > > the exposed sensors. > > > > I think the aggregation of thermal zones is quite useful when it comes > > to putting different chips together to a system. I am not so sure how > > useful it is to expose different thermal zones of a single SoC to the > > device tree. > > Currently the only control knob we have is the CPU frequency. When any > > of the sensors on the SoC gets too hot then the only thing we can do is > > to decrease the CPU frequency. This does not leave much space for > > configuration in the device tree. > > What I need to be able is to attach multiple sensors to one thermal > > zone. The aggregation patch series only partly solves that and I think > > is inconsistent, but I commented on the series directly. > > Any input on this? I really like to get this driver upstream as it is > currently blocking other Mediatek drivers. > Hi Eduardo, Do you have any comment about Sascha's response ? We really hope get your comment since Mediatek thermal driver already reviewed in public over half years, and we have other patches [0] [1] depend on thermal driver. [0]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html Regards, Eddie ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-01 2:54 ` Eddie Huang 0 siblings, 0 replies; 139+ messages in thread From: Eddie Huang @ 2016-02-01 2:54 UTC (permalink / raw) To: linux-arm-kernel On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: > Eduardo, > > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > > Hi Eduardo, > > > > > > > > That should remove the policy of computing the maximum from this driver. > > > Please have a look on the work being done [1] to add grouping and > > > aggregation of thermal zones. With that in place, you should be a matter > > > of configuring the grouping and selecting max as the aggregation function, > > > from the thermal core, instead in the driver. Which should give the > > > system engineer, more flexibility to compose whatever policy based on > > > the exposed sensors. > > > > I think the aggregation of thermal zones is quite useful when it comes > > to putting different chips together to a system. I am not so sure how > > useful it is to expose different thermal zones of a single SoC to the > > device tree. > > Currently the only control knob we have is the CPU frequency. When any > > of the sensors on the SoC gets too hot then the only thing we can do is > > to decrease the CPU frequency. This does not leave much space for > > configuration in the device tree. > > What I need to be able is to attach multiple sensors to one thermal > > zone. The aggregation patch series only partly solves that and I think > > is inconsistent, but I commented on the series directly. > > Any input on this? I really like to get this driver upstream as it is > currently blocking other Mediatek drivers. > Hi Eduardo, Do you have any comment about Sascha's response ? We really hope get your comment since Mediatek thermal driver already reviewed in public over half years, and we have other patches [0] [1] depend on thermal driver. [0]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html Regards, Eddie ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-01 2:54 ` Eddie Huang 0 siblings, 0 replies; 139+ messages in thread From: Eddie Huang @ 2016-02-01 2:54 UTC (permalink / raw) To: Eduardo Valentin, Sascha Hauer Cc: linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: > Eduardo, > > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > > Hi Eduardo, > > > > > > > > That should remove the policy of computing the maximum from this driver. > > > Please have a look on the work being done [1] to add grouping and > > > aggregation of thermal zones. With that in place, you should be a matter > > > of configuring the grouping and selecting max as the aggregation function, > > > from the thermal core, instead in the driver. Which should give the > > > system engineer, more flexibility to compose whatever policy based on > > > the exposed sensors. > > > > I think the aggregation of thermal zones is quite useful when it comes > > to putting different chips together to a system. I am not so sure how > > useful it is to expose different thermal zones of a single SoC to the > > device tree. > > Currently the only control knob we have is the CPU frequency. When any > > of the sensors on the SoC gets too hot then the only thing we can do is > > to decrease the CPU frequency. This does not leave much space for > > configuration in the device tree. > > What I need to be able is to attach multiple sensors to one thermal > > zone. The aggregation patch series only partly solves that and I think > > is inconsistent, but I commented on the series directly. > > Any input on this? I really like to get this driver upstream as it is > currently blocking other Mediatek drivers. > Hi Eduardo, Do you have any comment about Sascha's response ? We really hope get your comment since Mediatek thermal driver already reviewed in public over half years, and we have other patches [0] [1] depend on thermal driver. [0]: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html [1]: http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html Regards, Eddie ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-01 2:54 ` Eddie Huang (?) @ 2016-02-15 2:11 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-02-15 2:11 UTC (permalink / raw) To: Eddie Huang Cc: Eduardo Valentin, Sascha Hauer, linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel Hi Eduardo, Sascha, On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: > > On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: > > Eduardo, > > > > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > > > Hi Eduardo, > > > > > > > > > > > That should remove the policy of computing the maximum from this driver. > > > > Please have a look on the work being done [1] to add grouping and > > > > aggregation of thermal zones. With that in place, you should be a matter > > > > of configuring the grouping and selecting max as the aggregation function, > > > > from the thermal core, instead in the driver. Which should give the > > > > system engineer, more flexibility to compose whatever policy based on > > > > the exposed sensors. > > > > > > I think the aggregation of thermal zones is quite useful when it comes > > > to putting different chips together to a system. I am not so sure how > > > useful it is to expose different thermal zones of a single SoC to the > > > device tree. > > > Currently the only control knob we have is the CPU frequency. When any > > > of the sensors on the SoC gets too hot then the only thing we can do is > > > to decrease the CPU frequency. This does not leave much space for > > > configuration in the device tree. > > > What I need to be able is to attach multiple sensors to one thermal > > > zone. The aggregation patch series only partly solves that and I think > > > is inconsistent, but I commented on the series directly. > > > > Any input on this? I really like to get this driver upstream as it is > > currently blocking other Mediatek drivers. > > > > Hi Eduardo, > > Do you have any comment about Sascha's response ? We really hope get > your comment since Mediatek thermal driver already reviewed in public > over half years, and we have other patches [0] [1] depend on thermal > driver. > > [0]: > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > [1]: > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html Friendly ping on the Mediatek thermal driver. The "EFUSE" dependency has now landed in v4.5-rc4. So, AFAICT, the only thing left that may be blocking landing Mediatek thermal driver is resolution of this discussion about thermal zones. Can we kindly resolve this soon so we have a chance to land it in v4.6. Thanks, -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-15 2:11 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-02-15 2:11 UTC (permalink / raw) To: linux-arm-kernel Hi Eduardo, Sascha, On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: > > On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: > > Eduardo, > > > > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > > > Hi Eduardo, > > > > > > > > > > > That should remove the policy of computing the maximum from this driver. > > > > Please have a look on the work being done [1] to add grouping and > > > > aggregation of thermal zones. With that in place, you should be a matter > > > > of configuring the grouping and selecting max as the aggregation function, > > > > from the thermal core, instead in the driver. Which should give the > > > > system engineer, more flexibility to compose whatever policy based on > > > > the exposed sensors. > > > > > > I think the aggregation of thermal zones is quite useful when it comes > > > to putting different chips together to a system. I am not so sure how > > > useful it is to expose different thermal zones of a single SoC to the > > > device tree. > > > Currently the only control knob we have is the CPU frequency. When any > > > of the sensors on the SoC gets too hot then the only thing we can do is > > > to decrease the CPU frequency. This does not leave much space for > > > configuration in the device tree. > > > What I need to be able is to attach multiple sensors to one thermal > > > zone. The aggregation patch series only partly solves that and I think > > > is inconsistent, but I commented on the series directly. > > > > Any input on this? I really like to get this driver upstream as it is > > currently blocking other Mediatek drivers. > > > > Hi Eduardo, > > Do you have any comment about Sascha's response ? We really hope get > your comment since Mediatek thermal driver already reviewed in public > over half years, and we have other patches [0] [1] depend on thermal > driver. > > [0]: > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > [1]: > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html Friendly ping on the Mediatek thermal driver. The "EFUSE" dependency has now landed in v4.5-rc4. So, AFAICT, the only thing left that may be blocking landing Mediatek thermal driver is resolution of this discussion about thermal zones. Can we kindly resolve this soon so we have a chance to land it in v4.6. Thanks, -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-15 2:11 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-02-15 2:11 UTC (permalink / raw) To: Eddie Huang Cc: Eduardo Valentin, Sascha Hauer, linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel Hi Eduardo, Sascha, On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: > > On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: > > Eduardo, > > > > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: > > > Hi Eduardo, > > > > > > > > > > > That should remove the policy of computing the maximum from this driver. > > > > Please have a look on the work being done [1] to add grouping and > > > > aggregation of thermal zones. With that in place, you should be a matter > > > > of configuring the grouping and selecting max as the aggregation function, > > > > from the thermal core, instead in the driver. Which should give the > > > > system engineer, more flexibility to compose whatever policy based on > > > > the exposed sensors. > > > > > > I think the aggregation of thermal zones is quite useful when it comes > > > to putting different chips together to a system. I am not so sure how > > > useful it is to expose different thermal zones of a single SoC to the > > > device tree. > > > Currently the only control knob we have is the CPU frequency. When any > > > of the sensors on the SoC gets too hot then the only thing we can do is > > > to decrease the CPU frequency. This does not leave much space for > > > configuration in the device tree. > > > What I need to be able is to attach multiple sensors to one thermal > > > zone. The aggregation patch series only partly solves that and I think > > > is inconsistent, but I commented on the series directly. > > > > Any input on this? I really like to get this driver upstream as it is > > currently blocking other Mediatek drivers. > > > > Hi Eduardo, > > Do you have any comment about Sascha's response ? We really hope get > your comment since Mediatek thermal driver already reviewed in public > over half years, and we have other patches [0] [1] depend on thermal > driver. > > [0]: > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > [1]: > http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html Friendly ping on the Mediatek thermal driver. The "EFUSE" dependency has now landed in v4.5-rc4. So, AFAICT, the only thing left that may be blocking landing Mediatek thermal driver is resolution of this discussion about thermal zones. Can we kindly resolve this soon so we have a chance to land it in v4.6. Thanks, -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-15 2:11 ` Daniel Kurtz (?) @ 2016-02-15 2:14 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-02-15 2:14 UTC (permalink / raw) To: Eddie Huang Cc: Eduardo Valentin, Sascha Hauer, linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > Hi Eduardo, Sascha, > > On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: >> >> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: >> > Eduardo, >> > >> > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: >> > > Hi Eduardo, >> > > >> > > > >> > > > That should remove the policy of computing the maximum from this driver. >> > > > Please have a look on the work being done [1] to add grouping and >> > > > aggregation of thermal zones. With that in place, you should be a matter >> > > > of configuring the grouping and selecting max as the aggregation function, >> > > > from the thermal core, instead in the driver. Which should give the >> > > > system engineer, more flexibility to compose whatever policy based on >> > > > the exposed sensors. >> > > >> > > I think the aggregation of thermal zones is quite useful when it comes >> > > to putting different chips together to a system. I am not so sure how >> > > useful it is to expose different thermal zones of a single SoC to the >> > > device tree. >> > > Currently the only control knob we have is the CPU frequency. When any >> > > of the sensors on the SoC gets too hot then the only thing we can do is >> > > to decrease the CPU frequency. This does not leave much space for >> > > configuration in the device tree. >> > > What I need to be able is to attach multiple sensors to one thermal >> > > zone. The aggregation patch series only partly solves that and I think >> > > is inconsistent, but I commented on the series directly. >> > >> > Any input on this? I really like to get this driver upstream as it is >> > currently blocking other Mediatek drivers. >> > >> >> Hi Eduardo, >> >> Do you have any comment about Sascha's response ? We really hope get >> your comment since Mediatek thermal driver already reviewed in public >> over half years, and we have other patches [0] [1] depend on thermal >> driver. >> >> [0]: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html >> [1]: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > Friendly ping on the Mediatek thermal driver. > The "EFUSE" dependency has now landed in v4.5-rc4. Actually, it landed in char-misc-next, not v4.5-rc4. > So, AFAICT, the only thing left that may be blocking landing Mediatek > thermal driver is resolution of this discussion about thermal zones. > Can we kindly resolve this soon so we have a chance to land it in v4.6. > > Thanks, > -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-15 2:14 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-02-15 2:14 UTC (permalink / raw) To: linux-arm-kernel On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > Hi Eduardo, Sascha, > > On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: >> >> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: >> > Eduardo, >> > >> > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: >> > > Hi Eduardo, >> > > >> > > > >> > > > That should remove the policy of computing the maximum from this driver. >> > > > Please have a look on the work being done [1] to add grouping and >> > > > aggregation of thermal zones. With that in place, you should be a matter >> > > > of configuring the grouping and selecting max as the aggregation function, >> > > > from the thermal core, instead in the driver. Which should give the >> > > > system engineer, more flexibility to compose whatever policy based on >> > > > the exposed sensors. >> > > >> > > I think the aggregation of thermal zones is quite useful when it comes >> > > to putting different chips together to a system. I am not so sure how >> > > useful it is to expose different thermal zones of a single SoC to the >> > > device tree. >> > > Currently the only control knob we have is the CPU frequency. When any >> > > of the sensors on the SoC gets too hot then the only thing we can do is >> > > to decrease the CPU frequency. This does not leave much space for >> > > configuration in the device tree. >> > > What I need to be able is to attach multiple sensors to one thermal >> > > zone. The aggregation patch series only partly solves that and I think >> > > is inconsistent, but I commented on the series directly. >> > >> > Any input on this? I really like to get this driver upstream as it is >> > currently blocking other Mediatek drivers. >> > >> >> Hi Eduardo, >> >> Do you have any comment about Sascha's response ? We really hope get >> your comment since Mediatek thermal driver already reviewed in public >> over half years, and we have other patches [0] [1] depend on thermal >> driver. >> >> [0]: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html >> [1]: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > Friendly ping on the Mediatek thermal driver. > The "EFUSE" dependency has now landed in v4.5-rc4. Actually, it landed in char-misc-next, not v4.5-rc4. > So, AFAICT, the only thing left that may be blocking landing Mediatek > thermal driver is resolution of this discussion about thermal zones. > Can we kindly resolve this soon so we have a chance to land it in v4.6. > > Thanks, > -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-15 2:14 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-02-15 2:14 UTC (permalink / raw) To: Eddie Huang Cc: Eduardo Valentin, Sascha Hauer, linux-pm, linux-kernel, linux-mediatek, kernel, Matthias Brugger, Zhang Rui, linux-arm-kernel On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > Hi Eduardo, Sascha, > > On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: >> >> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: >> > Eduardo, >> > >> > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: >> > > Hi Eduardo, >> > > >> > > > >> > > > That should remove the policy of computing the maximum from this driver. >> > > > Please have a look on the work being done [1] to add grouping and >> > > > aggregation of thermal zones. With that in place, you should be a matter >> > > > of configuring the grouping and selecting max as the aggregation function, >> > > > from the thermal core, instead in the driver. Which should give the >> > > > system engineer, more flexibility to compose whatever policy based on >> > > > the exposed sensors. >> > > >> > > I think the aggregation of thermal zones is quite useful when it comes >> > > to putting different chips together to a system. I am not so sure how >> > > useful it is to expose different thermal zones of a single SoC to the >> > > device tree. >> > > Currently the only control knob we have is the CPU frequency. When any >> > > of the sensors on the SoC gets too hot then the only thing we can do is >> > > to decrease the CPU frequency. This does not leave much space for >> > > configuration in the device tree. >> > > What I need to be able is to attach multiple sensors to one thermal >> > > zone. The aggregation patch series only partly solves that and I think >> > > is inconsistent, but I commented on the series directly. >> > >> > Any input on this? I really like to get this driver upstream as it is >> > currently blocking other Mediatek drivers. >> > >> >> Hi Eduardo, >> >> Do you have any comment about Sascha's response ? We really hope get >> your comment since Mediatek thermal driver already reviewed in public >> over half years, and we have other patches [0] [1] depend on thermal >> driver. >> >> [0]: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html >> [1]: >> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > Friendly ping on the Mediatek thermal driver. > The "EFUSE" dependency has now landed in v4.5-rc4. Actually, it landed in char-misc-next, not v4.5-rc4. > So, AFAICT, the only thing left that may be blocking landing Mediatek > thermal driver is resolution of this discussion about thermal zones. > Can we kindly resolve this soon so we have a chance to land it in v4.6. > > Thanks, > -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-15 2:14 ` Daniel Kurtz (?) @ 2016-02-17 17:05 ` Matthias Brugger -1 siblings, 0 replies; 139+ messages in thread From: Matthias Brugger @ 2016-02-17 17:05 UTC (permalink / raw) To: Daniel Kurtz, Eddie Huang Cc: Eduardo Valentin, Sascha Hauer, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel On 15/02/16 03:14, Daniel Kurtz wrote: > On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: >> Hi Eduardo, Sascha, >> >> On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: >>> >>> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: >>>> Eduardo, >>>> >>>> On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: >>>>> Hi Eduardo, >>>>> >>>>>> >>>>>> That should remove the policy of computing the maximum from this driver. >>>>>> Please have a look on the work being done [1] to add grouping and >>>>>> aggregation of thermal zones. With that in place, you should be a matter >>>>>> of configuring the grouping and selecting max as the aggregation function, >>>>>> from the thermal core, instead in the driver. Which should give the >>>>>> system engineer, more flexibility to compose whatever policy based on >>>>>> the exposed sensors. >>>>> >>>>> I think the aggregation of thermal zones is quite useful when it comes >>>>> to putting different chips together to a system. I am not so sure how >>>>> useful it is to expose different thermal zones of a single SoC to the >>>>> device tree. >>>>> Currently the only control knob we have is the CPU frequency. When any >>>>> of the sensors on the SoC gets too hot then the only thing we can do is >>>>> to decrease the CPU frequency. This does not leave much space for >>>>> configuration in the device tree. >>>>> What I need to be able is to attach multiple sensors to one thermal >>>>> zone. The aggregation patch series only partly solves that and I think >>>>> is inconsistent, but I commented on the series directly. >>>> >>>> Any input on this? I really like to get this driver upstream as it is >>>> currently blocking other Mediatek drivers. >>>> >>> >>> Hi Eduardo, >>> >>> Do you have any comment about Sascha's response ? We really hope get >>> your comment since Mediatek thermal driver already reviewed in public >>> over half years, and we have other patches [0] [1] depend on thermal >>> driver. >>> >>> [0]: >>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html >>> [1]: >>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html >> >> Friendly ping on the Mediatek thermal driver. >> The "EFUSE" dependency has now landed in v4.5-rc4. > > Actually, it landed in char-misc-next, not v4.5-rc4. > >> So, AFAICT, the only thing left that may be blocking landing Mediatek >> thermal driver is resolution of this discussion about thermal zones. >> Can we kindly resolve this soon so we have a chance to land it in v4.6. >> I think the problem is, that Eduardo wants to see the hierachical thermal zones being used. But there is still a discussion ongoing [1]. [1] https://patchwork.kernel.org/patch/7699971/ ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-17 17:05 ` Matthias Brugger 0 siblings, 0 replies; 139+ messages in thread From: Matthias Brugger @ 2016-02-17 17:05 UTC (permalink / raw) To: linux-arm-kernel On 15/02/16 03:14, Daniel Kurtz wrote: > On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: >> Hi Eduardo, Sascha, >> >> On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: >>> >>> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: >>>> Eduardo, >>>> >>>> On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: >>>>> Hi Eduardo, >>>>> >>>>>> >>>>>> That should remove the policy of computing the maximum from this driver. >>>>>> Please have a look on the work being done [1] to add grouping and >>>>>> aggregation of thermal zones. With that in place, you should be a matter >>>>>> of configuring the grouping and selecting max as the aggregation function, >>>>>> from the thermal core, instead in the driver. Which should give the >>>>>> system engineer, more flexibility to compose whatever policy based on >>>>>> the exposed sensors. >>>>> >>>>> I think the aggregation of thermal zones is quite useful when it comes >>>>> to putting different chips together to a system. I am not so sure how >>>>> useful it is to expose different thermal zones of a single SoC to the >>>>> device tree. >>>>> Currently the only control knob we have is the CPU frequency. When any >>>>> of the sensors on the SoC gets too hot then the only thing we can do is >>>>> to decrease the CPU frequency. This does not leave much space for >>>>> configuration in the device tree. >>>>> What I need to be able is to attach multiple sensors to one thermal >>>>> zone. The aggregation patch series only partly solves that and I think >>>>> is inconsistent, but I commented on the series directly. >>>> >>>> Any input on this? I really like to get this driver upstream as it is >>>> currently blocking other Mediatek drivers. >>>> >>> >>> Hi Eduardo, >>> >>> Do you have any comment about Sascha's response ? We really hope get >>> your comment since Mediatek thermal driver already reviewed in public >>> over half years, and we have other patches [0] [1] depend on thermal >>> driver. >>> >>> [0]: >>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html >>> [1]: >>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html >> >> Friendly ping on the Mediatek thermal driver. >> The "EFUSE" dependency has now landed in v4.5-rc4. > > Actually, it landed in char-misc-next, not v4.5-rc4. > >> So, AFAICT, the only thing left that may be blocking landing Mediatek >> thermal driver is resolution of this discussion about thermal zones. >> Can we kindly resolve this soon so we have a chance to land it in v4.6. >> I think the problem is, that Eduardo wants to see the hierachical thermal zones being used. But there is still a discussion ongoing [1]. [1] https://patchwork.kernel.org/patch/7699971/ ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-17 17:05 ` Matthias Brugger 0 siblings, 0 replies; 139+ messages in thread From: Matthias Brugger @ 2016-02-17 17:05 UTC (permalink / raw) To: Daniel Kurtz, Eddie Huang Cc: Eduardo Valentin, Sascha Hauer, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel On 15/02/16 03:14, Daniel Kurtz wrote: > On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: >> Hi Eduardo, Sascha, >> >> On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.huang@mediatek.com> wrote: >>> >>> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote: >>>> Eduardo, >>>> >>>> On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote: >>>>> Hi Eduardo, >>>>> >>>>>> >>>>>> That should remove the policy of computing the maximum from this driver. >>>>>> Please have a look on the work being done [1] to add grouping and >>>>>> aggregation of thermal zones. With that in place, you should be a matter >>>>>> of configuring the grouping and selecting max as the aggregation function, >>>>>> from the thermal core, instead in the driver. Which should give the >>>>>> system engineer, more flexibility to compose whatever policy based on >>>>>> the exposed sensors. >>>>> >>>>> I think the aggregation of thermal zones is quite useful when it comes >>>>> to putting different chips together to a system. I am not so sure how >>>>> useful it is to expose different thermal zones of a single SoC to the >>>>> device tree. >>>>> Currently the only control knob we have is the CPU frequency. When any >>>>> of the sensors on the SoC gets too hot then the only thing we can do is >>>>> to decrease the CPU frequency. This does not leave much space for >>>>> configuration in the device tree. >>>>> What I need to be able is to attach multiple sensors to one thermal >>>>> zone. The aggregation patch series only partly solves that and I think >>>>> is inconsistent, but I commented on the series directly. >>>> >>>> Any input on this? I really like to get this driver upstream as it is >>>> currently blocking other Mediatek drivers. >>>> >>> >>> Hi Eduardo, >>> >>> Do you have any comment about Sascha's response ? We really hope get >>> your comment since Mediatek thermal driver already reviewed in public >>> over half years, and we have other patches [0] [1] depend on thermal >>> driver. >>> >>> [0]: >>> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html >>> [1]: >>> http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html >> >> Friendly ping on the Mediatek thermal driver. >> The "EFUSE" dependency has now landed in v4.5-rc4. > > Actually, it landed in char-misc-next, not v4.5-rc4. > >> So, AFAICT, the only thing left that may be blocking landing Mediatek >> thermal driver is resolution of this discussion about thermal zones. >> Can we kindly resolve this soon so we have a chance to land it in v4.6. >> I think the problem is, that Eduardo wants to see the hierachical thermal zones being used. But there is still a discussion ongoing [1]. [1] https://patchwork.kernel.org/patch/7699971/ ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-17 17:05 ` Matthias Brugger (?) @ 2016-02-18 10:56 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-02-18 10:56 UTC (permalink / raw) To: Matthias Brugger Cc: Daniel Kurtz, Eddie Huang, Eduardo Valentin, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > > On 15/02/16 03:14, Daniel Kurtz wrote: > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > >>Hi Eduardo, Sascha, > >> > >>>>Any input on this? I really like to get this driver upstream as it is > >>>>currently blocking other Mediatek drivers. > >>>> > >>> > >>>Hi Eduardo, > >>> > >>>Do you have any comment about Sascha's response ? We really hope get > >>>your comment since Mediatek thermal driver already reviewed in public > >>>over half years, and we have other patches [0] [1] depend on thermal > >>>driver. > >>> > >>>[0]: > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > >>>[1]: > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > >> > >>Friendly ping on the Mediatek thermal driver. > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > >>thermal driver is resolution of this discussion about thermal zones. > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > >> > > > I think the problem is, that Eduardo wants to see the hierachical thermal > zones being used. But there is still a discussion ongoing [1]. It seems the original Author lost interest in the hierarchical thermal zones. I am not convinced that we need hierarchical thermal zones for the Mediatek driver since from the five sensors we only need the maximum temperature (If this ever changes we could still rework it). Given the current speed of communication I am not willing to add another, possibly controversal, dependency to an otherwise simple driver. I am even less willing when concerns like these come after *v12* of this series. Eduardo, it would really help to get a word from you. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-18 10:56 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-02-18 10:56 UTC (permalink / raw) To: linux-arm-kernel On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > > On 15/02/16 03:14, Daniel Kurtz wrote: > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > >>Hi Eduardo, Sascha, > >> > >>>>Any input on this? I really like to get this driver upstream as it is > >>>>currently blocking other Mediatek drivers. > >>>> > >>> > >>>Hi Eduardo, > >>> > >>>Do you have any comment about Sascha's response ? We really hope get > >>>your comment since Mediatek thermal driver already reviewed in public > >>>over half years, and we have other patches [0] [1] depend on thermal > >>>driver. > >>> > >>>[0]: > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > >>>[1]: > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > >> > >>Friendly ping on the Mediatek thermal driver. > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > >>thermal driver is resolution of this discussion about thermal zones. > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > >> > > > I think the problem is, that Eduardo wants to see the hierachical thermal > zones being used. But there is still a discussion ongoing [1]. It seems the original Author lost interest in the hierarchical thermal zones. I am not convinced that we need hierarchical thermal zones for the Mediatek driver since from the five sensors we only need the maximum temperature (If this ever changes we could still rework it). Given the current speed of communication I am not willing to add another, possibly controversal, dependency to an otherwise simple driver. I am even less willing when concerns like these come after *v12* of this series. Eduardo, it would really help to get a word from you. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-18 10:56 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-02-18 10:56 UTC (permalink / raw) To: Matthias Brugger Cc: Daniel Kurtz, Eddie Huang, Eduardo Valentin, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > > On 15/02/16 03:14, Daniel Kurtz wrote: > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > >>Hi Eduardo, Sascha, > >> > >>>>Any input on this? I really like to get this driver upstream as it is > >>>>currently blocking other Mediatek drivers. > >>>> > >>> > >>>Hi Eduardo, > >>> > >>>Do you have any comment about Sascha's response ? We really hope get > >>>your comment since Mediatek thermal driver already reviewed in public > >>>over half years, and we have other patches [0] [1] depend on thermal > >>>driver. > >>> > >>>[0]: > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > >>>[1]: > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > >> > >>Friendly ping on the Mediatek thermal driver. > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > >>thermal driver is resolution of this discussion about thermal zones. > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > >> > > > I think the problem is, that Eduardo wants to see the hierachical thermal > zones being used. But there is still a discussion ongoing [1]. It seems the original Author lost interest in the hierarchical thermal zones. I am not convinced that we need hierarchical thermal zones for the Mediatek driver since from the five sensors we only need the maximum temperature (If this ever changes we could still rework it). Given the current speed of communication I am not willing to add another, possibly controversal, dependency to an otherwise simple driver. I am even less willing when concerns like these come after *v12* of this series. Eduardo, it would really help to get a word from you. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-18 10:56 ` Sascha Hauer (?) @ 2016-02-18 14:28 ` Javi Merino -1 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2016-02-18 14:28 UTC (permalink / raw) To: Sascha Hauer Cc: Matthias Brugger, linux-pm, linux-kernel, Daniel Kurtz, Eduardo Valentin, linux-mediatek, kernel, Zhang Rui, Eddie Huang, linux-arm-kernel Hi Sascha, On Thu, Feb 18, 2016 at 11:56:03AM +0100, Sascha Hauer wrote: > On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > On 15/02/16 03:14, Daniel Kurtz wrote: > > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > >>Hi Eduardo, Sascha, > > >> > > >>>>Any input on this? I really like to get this driver upstream as it is > > >>>>currently blocking other Mediatek drivers. > > >>>> > > >>> > > >>>Hi Eduardo, > > >>> > > >>>Do you have any comment about Sascha's response ? We really hope get > > >>>your comment since Mediatek thermal driver already reviewed in public > > >>>over half years, and we have other patches [0] [1] depend on thermal > > >>>driver. > > >>> > > >>>[0]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > > >>>[1]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > >> > > >>Friendly ping on the Mediatek thermal driver. > > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > > >>thermal driver is resolution of this discussion about thermal zones. > > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > > >> > > > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > zones being used. But there is still a discussion ongoing [1]. > > It seems the original Author lost interest in the hierarchical thermal > zones. I am not convinced that we need hierarchical thermal zones for > the Mediatek driver since from the five sensors we only need the maximum > temperature (If this ever changes we could still rework it). I guess that "the original Author" refers to me. I haven't lost interest in the hierarchical thermal zones, I just don't have time to work on it currently. I'd like to address your review at some point in the future and continue working on it. > Given the current speed of communication I am not willing to add > another, possibly controversal, dependency to an otherwise simple > driver. I am even less willing when concerns like these come after *v12* > of this series. I agree. I don't think we should make this driver depend on the hierarchical thermal zones series. When hierarchical thermal zones get merged we can consider to change the driver to use them but there's no point in waiting for that to happen. Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-18 14:28 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2016-02-18 14:28 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, On Thu, Feb 18, 2016 at 11:56:03AM +0100, Sascha Hauer wrote: > On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > On 15/02/16 03:14, Daniel Kurtz wrote: > > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > >>Hi Eduardo, Sascha, > > >> > > >>>>Any input on this? I really like to get this driver upstream as it is > > >>>>currently blocking other Mediatek drivers. > > >>>> > > >>> > > >>>Hi Eduardo, > > >>> > > >>>Do you have any comment about Sascha's response ? We really hope get > > >>>your comment since Mediatek thermal driver already reviewed in public > > >>>over half years, and we have other patches [0] [1] depend on thermal > > >>>driver. > > >>> > > >>>[0]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > > >>>[1]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > >> > > >>Friendly ping on the Mediatek thermal driver. > > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > > >>thermal driver is resolution of this discussion about thermal zones. > > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > > >> > > > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > zones being used. But there is still a discussion ongoing [1]. > > It seems the original Author lost interest in the hierarchical thermal > zones. I am not convinced that we need hierarchical thermal zones for > the Mediatek driver since from the five sensors we only need the maximum > temperature (If this ever changes we could still rework it). I guess that "the original Author" refers to me. I haven't lost interest in the hierarchical thermal zones, I just don't have time to work on it currently. I'd like to address your review at some point in the future and continue working on it. > Given the current speed of communication I am not willing to add > another, possibly controversal, dependency to an otherwise simple > driver. I am even less willing when concerns like these come after *v12* > of this series. I agree. I don't think we should make this driver depend on the hierarchical thermal zones series. When hierarchical thermal zones get merged we can consider to change the driver to use them but there's no point in waiting for that to happen. Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-18 14:28 ` Javi Merino 0 siblings, 0 replies; 139+ messages in thread From: Javi Merino @ 2016-02-18 14:28 UTC (permalink / raw) To: Sascha Hauer Cc: Matthias Brugger, linux-pm, linux-kernel, Daniel Kurtz, Eduardo Valentin, linux-mediatek, kernel, Zhang Rui, Eddie Huang, linux-arm-kernel Hi Sascha, On Thu, Feb 18, 2016 at 11:56:03AM +0100, Sascha Hauer wrote: > On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > On 15/02/16 03:14, Daniel Kurtz wrote: > > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > >>Hi Eduardo, Sascha, > > >> > > >>>>Any input on this? I really like to get this driver upstream as it is > > >>>>currently blocking other Mediatek drivers. > > >>>> > > >>> > > >>>Hi Eduardo, > > >>> > > >>>Do you have any comment about Sascha's response ? We really hope get > > >>>your comment since Mediatek thermal driver already reviewed in public > > >>>over half years, and we have other patches [0] [1] depend on thermal > > >>>driver. > > >>> > > >>>[0]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > > >>>[1]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > >> > > >>Friendly ping on the Mediatek thermal driver. > > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > > >>thermal driver is resolution of this discussion about thermal zones. > > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > > >> > > > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > zones being used. But there is still a discussion ongoing [1]. > > It seems the original Author lost interest in the hierarchical thermal > zones. I am not convinced that we need hierarchical thermal zones for > the Mediatek driver since from the five sensors we only need the maximum > temperature (If this ever changes we could still rework it). I guess that "the original Author" refers to me. I haven't lost interest in the hierarchical thermal zones, I just don't have time to work on it currently. I'd like to address your review at some point in the future and continue working on it. > Given the current speed of communication I am not willing to add > another, possibly controversal, dependency to an otherwise simple > driver. I am even less willing when concerns like these come after *v12* > of this series. I agree. I don't think we should make this driver depend on the hierarchical thermal zones series. When hierarchical thermal zones get merged we can consider to change the driver to use them but there's no point in waiting for that to happen. Cheers, Javi ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-18 10:56 ` Sascha Hauer (?) @ 2016-02-18 15:15 ` Eduardo Valentin -1 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2016-02-18 15:15 UTC (permalink / raw) To: Sascha Hauer Cc: Matthias Brugger, Daniel Kurtz, Eddie Huang, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel Folks, On Thu, Feb 18, 2016 at 11:56:03AM +0100, Sascha Hauer wrote: > On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > > > > > On 15/02/16 03:14, Daniel Kurtz wrote: > > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > >>Hi Eduardo, Sascha, > > >> > > >>>>Any input on this? I really like to get this driver upstream as it is > > >>>>currently blocking other Mediatek drivers. > > >>>> > > >>> > > >>>Hi Eduardo, > > >>> > > >>>Do you have any comment about Sascha's response ? We really hope get > > >>>your comment since Mediatek thermal driver already reviewed in public > > >>>over half years, and we have other patches [0] [1] depend on thermal > > >>>driver. > > >>> > > >>>[0]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > > >>>[1]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > >> > > >>Friendly ping on the Mediatek thermal driver. > > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > > >>thermal driver is resolution of this discussion about thermal zones. > > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > > >> > > > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > zones being used. But there is still a discussion ongoing [1]. > > It seems the original Author lost interest in the hierarchical thermal > zones. I am not convinced that we need hierarchical thermal zones for > the Mediatek driver since from the five sensors we only need the maximum > temperature (If this ever changes we could still rework it). > > Given the current speed of communication I am not willing to add > another, possibly controversal, dependency to an otherwise simple > driver. I am even less willing when concerns like these come after *v12* > of this series. > > Eduardo, it would really help to get a word from you. Apologize for the long delays here. In fact I want the hierarchical support on this driver. But given that it is not really a strong dependency and the hierarchical support is still an ongoing development, I don't see why we should not merge this driver. I also have had the chance to try it out in a board, and seams to work for me. I am adding to my tree. Thanks for the perseverance. :-) > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-18 15:15 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2016-02-18 15:15 UTC (permalink / raw) To: linux-arm-kernel Folks, On Thu, Feb 18, 2016 at 11:56:03AM +0100, Sascha Hauer wrote: > On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > > > > > On 15/02/16 03:14, Daniel Kurtz wrote: > > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > >>Hi Eduardo, Sascha, > > >> > > >>>>Any input on this? I really like to get this driver upstream as it is > > >>>>currently blocking other Mediatek drivers. > > >>>> > > >>> > > >>>Hi Eduardo, > > >>> > > >>>Do you have any comment about Sascha's response ? We really hope get > > >>>your comment since Mediatek thermal driver already reviewed in public > > >>>over half years, and we have other patches [0] [1] depend on thermal > > >>>driver. > > >>> > > >>>[0]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > > >>>[1]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > >> > > >>Friendly ping on the Mediatek thermal driver. > > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > > >>thermal driver is resolution of this discussion about thermal zones. > > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > > >> > > > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > zones being used. But there is still a discussion ongoing [1]. > > It seems the original Author lost interest in the hierarchical thermal > zones. I am not convinced that we need hierarchical thermal zones for > the Mediatek driver since from the five sensors we only need the maximum > temperature (If this ever changes we could still rework it). > > Given the current speed of communication I am not willing to add > another, possibly controversal, dependency to an otherwise simple > driver. I am even less willing when concerns like these come after *v12* > of this series. > > Eduardo, it would really help to get a word from you. Apologize for the long delays here. In fact I want the hierarchical support on this driver. But given that it is not really a strong dependency and the hierarchical support is still an ongoing development, I don't see why we should not merge this driver. I also have had the chance to try it out in a board, and seams to work for me. I am adding to my tree. Thanks for the perseverance. :-) > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-18 15:15 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2016-02-18 15:15 UTC (permalink / raw) To: Sascha Hauer Cc: Matthias Brugger, Daniel Kurtz, Eddie Huang, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel Folks, On Thu, Feb 18, 2016 at 11:56:03AM +0100, Sascha Hauer wrote: > On Wed, Feb 17, 2016 at 06:05:57PM +0100, Matthias Brugger wrote: > > > > > > On 15/02/16 03:14, Daniel Kurtz wrote: > > >On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > >>Hi Eduardo, Sascha, > > >> > > >>>>Any input on this? I really like to get this driver upstream as it is > > >>>>currently blocking other Mediatek drivers. > > >>>> > > >>> > > >>>Hi Eduardo, > > >>> > > >>>Do you have any comment about Sascha's response ? We really hope get > > >>>your comment since Mediatek thermal driver already reviewed in public > > >>>over half years, and we have other patches [0] [1] depend on thermal > > >>>driver. > > >>> > > >>>[0]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394084.html > > >>>[1]: > > >>>http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401055.html > > >> > > >>Friendly ping on the Mediatek thermal driver. > > >>The "EFUSE" dependency has now landed in v4.5-rc4. > > > > > >Actually, it landed in char-misc-next, not v4.5-rc4. > > > > > >>So, AFAICT, the only thing left that may be blocking landing Mediatek > > >>thermal driver is resolution of this discussion about thermal zones. > > >>Can we kindly resolve this soon so we have a chance to land it in v4.6. > > >> > > > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > zones being used. But there is still a discussion ongoing [1]. > > It seems the original Author lost interest in the hierarchical thermal > zones. I am not convinced that we need hierarchical thermal zones for > the Mediatek driver since from the five sensors we only need the maximum > temperature (If this ever changes we could still rework it). > > Given the current speed of communication I am not willing to add > another, possibly controversal, dependency to an otherwise simple > driver. I am even less willing when concerns like these come after *v12* > of this series. > > Eduardo, it would really help to get a word from you. Apologize for the long delays here. In fact I want the hierarchical support on this driver. But given that it is not really a strong dependency and the hierarchical support is still an ongoing development, I don't see why we should not merge this driver. I also have had the chance to try it out in a board, and seams to work for me. I am adding to my tree. Thanks for the perseverance. :-) > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-02-18 15:15 ` Eduardo Valentin (?) @ 2016-02-19 7:21 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-02-19 7:21 UTC (permalink / raw) To: Eduardo Valentin Cc: Matthias Brugger, Daniel Kurtz, Eddie Huang, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel On Thu, Feb 18, 2016 at 07:15:54AM -0800, Eduardo Valentin wrote: > Folks, > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > > zones being used. But there is still a discussion ongoing [1]. > > > > It seems the original Author lost interest in the hierarchical thermal > > zones. I am not convinced that we need hierarchical thermal zones for > > the Mediatek driver since from the five sensors we only need the maximum > > temperature (If this ever changes we could still rework it). > > > > Given the current speed of communication I am not willing to add > > another, possibly controversal, dependency to an otherwise simple > > driver. I am even less willing when concerns like these come after *v12* > > of this series. > > > > Eduardo, it would really help to get a word from you. > > Apologize for the long delays here. In fact I want the hierarchical > support on this driver. But given that it is not really a strong > dependency and the hierarchical support is still an ongoing development, > I don't see why we should not merge this driver. > > I also have had the chance to try it out in a board, and seams to work > for me. I am adding to my tree. Thanks for applying :) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-19 7:21 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-02-19 7:21 UTC (permalink / raw) To: linux-arm-kernel On Thu, Feb 18, 2016 at 07:15:54AM -0800, Eduardo Valentin wrote: > Folks, > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > > zones being used. But there is still a discussion ongoing [1]. > > > > It seems the original Author lost interest in the hierarchical thermal > > zones. I am not convinced that we need hierarchical thermal zones for > > the Mediatek driver since from the five sensors we only need the maximum > > temperature (If this ever changes we could still rework it). > > > > Given the current speed of communication I am not willing to add > > another, possibly controversal, dependency to an otherwise simple > > driver. I am even less willing when concerns like these come after *v12* > > of this series. > > > > Eduardo, it would really help to get a word from you. > > Apologize for the long delays here. In fact I want the hierarchical > support on this driver. But given that it is not really a strong > dependency and the hierarchical support is still an ongoing development, > I don't see why we should not merge this driver. > > I also have had the chance to try it out in a board, and seams to work > for me. I am adding to my tree. Thanks for applying :) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-02-19 7:21 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-02-19 7:21 UTC (permalink / raw) To: Eduardo Valentin Cc: Matthias Brugger, Daniel Kurtz, Eddie Huang, linux-pm, linux-kernel, linux-mediatek, kernel, Zhang Rui, linux-arm-kernel On Thu, Feb 18, 2016 at 07:15:54AM -0800, Eduardo Valentin wrote: > Folks, > > > > I think the problem is, that Eduardo wants to see the hierachical thermal > > > zones being used. But there is still a discussion ongoing [1]. > > > > It seems the original Author lost interest in the hierarchical thermal > > zones. I am not convinced that we need hierarchical thermal zones for > > the Mediatek driver since from the five sensors we only need the maximum > > temperature (If this ever changes we could still rework it). > > > > Given the current speed of communication I am not willing to add > > another, possibly controversal, dependency to an otherwise simple > > driver. I am even less willing when concerns like these come after *v12* > > of this series. > > > > Eduardo, it would really help to get a word from you. > > Apologize for the long delays here. In fact I want the hierarchical > support on this driver. But given that it is not really a strong > dependency and the hierarchical support is still an ongoing development, > I don't see why we should not merge this driver. > > I also have had the chance to try it out in a board, and seams to work > for me. I am adding to my tree. Thanks for applying :) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-30 11:42 ` Sascha Hauer (?) @ 2015-12-21 4:07 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-12-21 4:07 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger Hi Sascha, One nit below that can be fixed up later, or now if you don't plan to spin this driver to address Eduardo's feedback... On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [snip] > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret = 0; > + > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) It is useful to know why the thermal driver is being probe defered, so I suggest here: dev_warn(dev, "Waiting for calibration data.\n"); > + return PTR_ERR(cell); > + return 0; > + } Thanks, -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-12-21 4:07 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-12-21 4:07 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, One nit below that can be fixed up later, or now if you don't plan to spin this driver to address Eduardo's feedback... On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [snip] > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret = 0; > + > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) It is useful to know why the thermal driver is being probe defered, so I suggest here: dev_warn(dev, "Waiting for calibration data.\n"); > + return PTR_ERR(cell); > + return 0; > + } Thanks, -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-12-21 4:07 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-12-21 4:07 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger Hi Sascha, One nit below that can be fixed up later, or now if you don't plan to spin this driver to address Eduardo's feedback... On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [snip] > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret = 0; > + > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) It is useful to know why the thermal driver is being probe defered, so I suggest here: dev_warn(dev, "Waiting for calibration data.\n"); > + return PTR_ERR(cell); > + return 0; > + } Thanks, -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-12-21 4:07 ` Daniel Kurtz (?) @ 2016-01-04 14:31 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-04 14:31 UTC (permalink / raw) To: Daniel Kurtz Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger On Mon, Dec 21, 2015 at 12:07:58PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > One nit below that can be fixed up later, or now if you don't plan to > spin this driver to > address Eduardo's feedback... > > On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > [snip] > > > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > > +{ > > + struct nvmem_cell *cell; > > + u32 *buf; > > + size_t len; > > + int i, ret = 0; > > + > > + /* Start with default values */ > > + mt->adc_ge = 512; > > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > > + mt->vts[i] = 260; > > + mt->degc_cali = 40; > > + mt->o_slope = 0; > > + > > + cell = nvmem_cell_get(dev, "calibration-data"); > > + if (IS_ERR(cell)) { > > + if (PTR_ERR(cell) == -EPROBE_DEFER) > > It is useful to know why the thermal driver is being probe defered, so > I suggest here: > dev_warn(dev, "Waiting for calibration data.\n"); The problem with that is that this message is not shown once but possibly many times and may not even show a problem because in the end the device may be probed successfully. In this case the last thing you see from the device is "Waiting for calibration data." and get annoyed by all this useless noise from the driver. Of course I agree that this information may be useful in the case you wonder why your device doesn't show up... Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-01-04 14:31 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-04 14:31 UTC (permalink / raw) To: linux-arm-kernel On Mon, Dec 21, 2015 at 12:07:58PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > One nit below that can be fixed up later, or now if you don't plan to > spin this driver to > address Eduardo's feedback... > > On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > [snip] > > > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > > +{ > > + struct nvmem_cell *cell; > > + u32 *buf; > > + size_t len; > > + int i, ret = 0; > > + > > + /* Start with default values */ > > + mt->adc_ge = 512; > > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > > + mt->vts[i] = 260; > > + mt->degc_cali = 40; > > + mt->o_slope = 0; > > + > > + cell = nvmem_cell_get(dev, "calibration-data"); > > + if (IS_ERR(cell)) { > > + if (PTR_ERR(cell) == -EPROBE_DEFER) > > It is useful to know why the thermal driver is being probe defered, so > I suggest here: > dev_warn(dev, "Waiting for calibration data.\n"); The problem with that is that this message is not shown once but possibly many times and may not even show a problem because in the end the device may be probed successfully. In this case the last thing you see from the device is "Waiting for calibration data." and get annoyed by all this useless noise from the driver. Of course I agree that this information may be useful in the case you wonder why your device doesn't show up... Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-01-04 14:31 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2016-01-04 14:31 UTC (permalink / raw) To: Daniel Kurtz Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger On Mon, Dec 21, 2015 at 12:07:58PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > One nit below that can be fixed up later, or now if you don't plan to > spin this driver to > address Eduardo's feedback... > > On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > [snip] > > > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > > +{ > > + struct nvmem_cell *cell; > > + u32 *buf; > > + size_t len; > > + int i, ret = 0; > > + > > + /* Start with default values */ > > + mt->adc_ge = 512; > > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > > + mt->vts[i] = 260; > > + mt->degc_cali = 40; > > + mt->o_slope = 0; > > + > > + cell = nvmem_cell_get(dev, "calibration-data"); > > + if (IS_ERR(cell)) { > > + if (PTR_ERR(cell) == -EPROBE_DEFER) > > It is useful to know why the thermal driver is being probe defered, so > I suggest here: > dev_warn(dev, "Waiting for calibration data.\n"); The problem with that is that this message is not shown once but possibly many times and may not even show a problem because in the end the device may be probed successfully. In this case the last thing you see from the device is "Waiting for calibration data." and get annoyed by all this useless noise from the driver. Of course I agree that this information may be useful in the case you wonder why your device doesn't show up... Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2016-01-04 14:31 ` Sascha Hauer (?) @ 2016-01-04 15:43 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-01-04 15:43 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, moderated list:ARM/Mediatek SoC support, linux-arm-kernel, Matthias Brugger On Mon, Jan 4, 2016 at 10:31 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Mon, Dec 21, 2015 at 12:07:58PM +0800, Daniel Kurtz wrote: >> Hi Sascha, >> >> One nit below that can be fixed up later, or now if you don't plan to >> spin this driver to >> address Eduardo's feedback... >> >> On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: >> > This adds support for the Mediatek thermal controller found on MT8173 >> > and likely other SoCs. >> > The controller is a bit special. It does not have its own ADC, instead >> > it controls the on-SoC AUXADC via AHB bus accesses. For this reason >> > we need the physical address of the AUXADC. Also it controls a mux >> > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. >> > >> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> >> >> [snip] >> >> > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) >> > +{ >> > + struct nvmem_cell *cell; >> > + u32 *buf; >> > + size_t len; >> > + int i, ret = 0; >> > + >> > + /* Start with default values */ >> > + mt->adc_ge = 512; >> > + for (i = 0; i < MT8173_NUM_SENSORS; i++) >> > + mt->vts[i] = 260; >> > + mt->degc_cali = 40; >> > + mt->o_slope = 0; >> > + >> > + cell = nvmem_cell_get(dev, "calibration-data"); >> > + if (IS_ERR(cell)) { >> > + if (PTR_ERR(cell) == -EPROBE_DEFER) >> >> It is useful to know why the thermal driver is being probe defered, so >> I suggest here: >> dev_warn(dev, "Waiting for calibration data.\n"); > > The problem with that is that this message is not shown once but > possibly many times and may not even show a problem because in the end > the device may be probed successfully. In this case the last thing you > see from the device is "Waiting for calibration data." and get annoyed > by all this useless noise from the driver. > > Of course I agree that this information may be useful in the case you > wonder why your device doesn't show up... The solution for this, then, is: dev_dbg() ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-01-04 15:43 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-01-04 15:43 UTC (permalink / raw) To: linux-arm-kernel On Mon, Jan 4, 2016 at 10:31 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Mon, Dec 21, 2015 at 12:07:58PM +0800, Daniel Kurtz wrote: >> Hi Sascha, >> >> One nit below that can be fixed up later, or now if you don't plan to >> spin this driver to >> address Eduardo's feedback... >> >> On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: >> > This adds support for the Mediatek thermal controller found on MT8173 >> > and likely other SoCs. >> > The controller is a bit special. It does not have its own ADC, instead >> > it controls the on-SoC AUXADC via AHB bus accesses. For this reason >> > we need the physical address of the AUXADC. Also it controls a mux >> > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. >> > >> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> >> >> [snip] >> >> > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) >> > +{ >> > + struct nvmem_cell *cell; >> > + u32 *buf; >> > + size_t len; >> > + int i, ret = 0; >> > + >> > + /* Start with default values */ >> > + mt->adc_ge = 512; >> > + for (i = 0; i < MT8173_NUM_SENSORS; i++) >> > + mt->vts[i] = 260; >> > + mt->degc_cali = 40; >> > + mt->o_slope = 0; >> > + >> > + cell = nvmem_cell_get(dev, "calibration-data"); >> > + if (IS_ERR(cell)) { >> > + if (PTR_ERR(cell) == -EPROBE_DEFER) >> >> It is useful to know why the thermal driver is being probe defered, so >> I suggest here: >> dev_warn(dev, "Waiting for calibration data.\n"); > > The problem with that is that this message is not shown once but > possibly many times and may not even show a problem because in the end > the device may be probed successfully. In this case the last thing you > see from the device is "Waiting for calibration data." and get annoyed > by all this useless noise from the driver. > > Of course I agree that this information may be useful in the case you > wonder why your device doesn't show up... The solution for this, then, is: dev_dbg() ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2016-01-04 15:43 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2016-01-04 15:43 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, moderated list:ARM/Mediatek SoC support, linux-arm-kernel, Matthias Brugger On Mon, Jan 4, 2016 at 10:31 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > On Mon, Dec 21, 2015 at 12:07:58PM +0800, Daniel Kurtz wrote: >> Hi Sascha, >> >> One nit below that can be fixed up later, or now if you don't plan to >> spin this driver to >> address Eduardo's feedback... >> >> On Mon, Nov 30, 2015 at 7:42 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: >> > This adds support for the Mediatek thermal controller found on MT8173 >> > and likely other SoCs. >> > The controller is a bit special. It does not have its own ADC, instead >> > it controls the on-SoC AUXADC via AHB bus accesses. For this reason >> > we need the physical address of the AUXADC. Also it controls a mux >> > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. >> > >> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> >> >> [snip] >> >> > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) >> > +{ >> > + struct nvmem_cell *cell; >> > + u32 *buf; >> > + size_t len; >> > + int i, ret = 0; >> > + >> > + /* Start with default values */ >> > + mt->adc_ge = 512; >> > + for (i = 0; i < MT8173_NUM_SENSORS; i++) >> > + mt->vts[i] = 260; >> > + mt->degc_cali = 40; >> > + mt->o_slope = 0; >> > + >> > + cell = nvmem_cell_get(dev, "calibration-data"); >> > + if (IS_ERR(cell)) { >> > + if (PTR_ERR(cell) == -EPROBE_DEFER) >> >> It is useful to know why the thermal driver is being probe defered, so >> I suggest here: >> dev_warn(dev, "Waiting for calibration data.\n"); > > The problem with that is that this message is not shown once but > possibly many times and may not even show a problem because in the end > the device may be probed successfully. In this case the last thing you > see from the device is "Waiting for calibration data." and get annoyed > by all this useless noise from the driver. > > Of course I agree that this information may be useful in the case you > wonder why your device doesn't show up... The solution for this, then, is: dev_dbg() ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v11] Add Mediatek thermal support @ 2015-11-18 8:24 Sascha Hauer 2015-11-18 8:24 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:24 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Sascha changes since v10: - Some style cleanup - Add comment to make clear why we use the sensors in banks even if we currently only use the maximum of all banks changes since v9: - rebase on v4.3 - Add support for reading the calibration values from nvmem fuses - Only register a single thermal zone instead of four as it seems that's everything needed changes since v8: - Add commit description to binding patch - rebase on v4.3-rc2 changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency ------------- fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJWQHCkAAoJEPFlmONMx+ezneEP/265kyAMT71c7/HewE7kA1aZ 3/ah5w7gtOjBlY0y3VNaVCs0u0gJEUqa/JFIBRvXm61mNoDt/uKH1hP5IroHVFHa uW9wc1nOgr8G185IZRYszIePwchoKE0lBLTpt1DplK8NwUv6k9NXdAlXlDrLkejQ fDnvGbIq0Ok5OLntjp81hGUxOYcyfoQrqHTLUWohzsovRwVegVOMOh08gwnWNJuI DKMaKlv4XpUiX8roeUEgQdrVnTLsddR85mvPonLcjIwpCMNooLygNKDmlTHf3C4g VFpdoUH04cc1XdxtxJ6oAetCq+/C6z9BA22nVWm+tRecN8VU+ywjB9xo2qUR+xjv aqEhKZMq8eTWNKWYUIhBh/LBPtoqZb5rYoS+Z76xFD/e+/umviscoh/QhavuohvZ bEMGIY4jziUMccFzklzZGyfxPPcVx9yIwB0+q4IgkWxGYznFyXcuNi4+J3xcxtid xYq1B6kcbca7G2UgEtt+JMSl9ukZYSeOAXGgYGQWsP0VyZWohvm+bH7FX455eHyX FLd+b3CpUEyxT3yL7ZpuJeiwzpnpsOgbqSu5Djzd5KpgUNnl4QCRAFAv4L9BqKZM L1ugFAhFJFcBIhjhgthws5WLhAY/hEI2gDaesYq2Wu5GgXiqZNIJyp7D1EA9RRpO RQjaXpX7u47O5HgQpfBA =4rKu -----END PGP SIGNATURE----- commit 53fcb89e372f49218e33889286a1812595e38cf3 Author: Sascha Hauer <s.hauer@pengutronix.de> Date: Tue May 12 09:22:29 2015 +0200 ARM64: dts: mt8173: Add thermal/auxadc device nodes This adds the thermal controller and auxadc nodes to the Mediatek MT8173 dtsi file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 06a1564..e2ddd03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -277,6 +277,11 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", "mediatek,mt6577-uart"; @@ -487,6 +492,18 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; }; }; -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJWTDT9AAoJEPFlmONMx+ez3RMQAKgHbBxQNJGKeINIetHYbKjS chdOWL5OWtRwgi/vQbwq0b35qdvRhPMS5Ufgipjf4xO1BVSu5EOKWFuzgMQ6wh0r xdFVe1VR188TcEDgc5YfJNMwiJ/eYreATE7EWF5uufXVVk9TAQLKl6b4o/Si2KtU 4Zy2uGQT6ZkwlMn8R1XDRoy0sSW3mnzs4it43YI/dJXYTw8S/OJlPFkUNT8jSFKU LyIAhnU/Zux9Ueh4YNmRu/csiwuKI+Wpkbyu6fFb224SOmfE9Nz3hAQTmIIMV/FS WwZ7V3CKCmh4xG7fRmjUu/naHnmWx6esVvdXPPKwr2qRDNX9ELRhq88R5Cue/wrX gJgFTch6cBDRuNyAfCk1T29FebR0Y9BCuWLpUXGUj1/Rh+wSj/q7q6wNeKwW9TJ5 hIDdMio0fcR1ahmqIwG1NU3zJXpLNDnimD0MVtz/vfE85qBtahnClC9+4kcN0W3r I6n0qQ/YxFp/xNJuHiBKRfw15RuTKyJBT6VtI+/lNd8YejPwdtqESrEJhL3yN9JM bJ5sEZeGSOSi0KCXgC2bUq/aYEiedKhEsT0EoqnuIZu4wxk7/DL5Fb+F8py5gllZ 9haA2ryZYDEGLcZbhb8z0wHJD5MDLNFv5MRQw+TpG3oP75Jj5/Ejp+jjmBV9nBZM PkyZGMUNPcEmvuXPqTR/ =Lp5z -----END PGP SIGNATURE----- commit 54d2d3b91b271f0edba2d8dbdf34eb76e37286c7 Author: Sascha Hauer <s.hauer@pengutronix.de> Date: Tue May 12 09:22:29 2015 +0200 ARM64: dts: mt8173: Add thermal/auxadc device nodes This adds the thermal controller and auxadc nodes to the Mediatek MT8173 dtsi file. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 06a1564..e2ddd03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -277,6 +277,11 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", "mediatek,mt6577-uart"; @@ -487,6 +492,18 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <0>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; }; }; ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-18 8:24 [PATCH v11] Add Mediatek thermal support Sascha Hauer @ 2015-11-18 8:24 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:24 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 632 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..0bdf38d --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + * + * The thermal core only gets the maximum temperature of all banks, so + * the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data, and this indeed needs the temperatures of the individual banks + * for making better decisions. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + mtk_thermal_get_bank(bank); + + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); + + mtk_thermal_put_bank(bank); + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.2 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-18 8:24 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-18 8:24 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 632 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 5aabc4b..503448a 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" depends on ARCH_HAS_BANDGAP || COMPILE_TEST source "drivers/thermal/ti-soc-thermal/Kconfig" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..0bdf38d --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * Sascha Hauer <s.hauer@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/nvmem-consumer.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/types.h> +#include <linux/nvmem-consumer.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +/* Layout of the fuses providing the calibration data */ +#define MT8173_CALIB_BUF0_VALID (1 << 0) +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 degc_cali; + s32 o_slope; + s32 vts[MT8173_NUM_SENSORS]; + + struct thermal_zone_device *tzd; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + * + * The thermal core only gets the maximum temperature of all banks, so + * the bank concept wouldn't be necessary here. However, the SVS (Smart + * Voltage Scaling) unit makes its decisions based on the same bank + * data, and this indeed needs the temperatures of the individual banks + * for making better decisions. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) +{ + s32 tmp; + + raw &= 0xfff; + + tmp = 203450520 << 3; + tmp /= 165 + mt->o_slope; + tmp /= 10000 + mt->adc_ge; + tmp *= raw - mt->vts[sensno] - 3350; + tmp >>= 3; + + return mt->degc_cali * 500 - tmp; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temperature) +{ + struct mtk_thermal *mt = data; + int i; + int tempmax = INT_MIN; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + mtk_thermal_get_bank(bank); + + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); + + mtk_thermal_put_bank(bank); + } + + *temperature = tempmax; + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) +{ + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, ret; + + /* Start with default values */ + mt->adc_ge = 512; + for (i = 0; i < MT8173_NUM_SENSORS; i++) + mt->vts[i] = 260; + mt->degc_cali = 40; + mt->o_slope = 0; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + if (PTR_ERR(cell) == -EPROBE_DEFER) + return PTR_ERR(cell); + return 0; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + ret = -EINVAL; + goto out; + } + + if (buf[0] & MT8173_CALIB_BUF0_VALID) { + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); + } else { + dev_info(dev, "Device not calibrated, using default calibration values\n"); + } + +out: + kfree(buf); + + return ret; +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); + if (ret) + return ret; + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + + of_node_put(auxadc); + + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + + of_node_put(apmixedsys); + + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, + &mtk_thermal_ops); + if (IS_ERR(mt->tzd)) + goto err_register; + + return 0; + +err_register: + clk_disable_unprepare(mt->clk_peri_therm); + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer at pengutronix.de"); +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.6.2 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-18 8:24 ` Sascha Hauer (?) @ 2015-11-24 6:06 ` dawei chien -1 siblings, 0 replies; 139+ messages in thread From: dawei chien @ 2015-11-24 6:06 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel Hi Sascha, On Wed, 2015-11-18 at 09:24 +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 632 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 5aabc4b..503448a 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs"Why does ret value didn't set to 0 during this function. This function of return value would be not 0 with valid calibration data. > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..0bdf38d > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,623 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * Sascha Hauer <s.hauer@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090Hi Sascha, > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + * > + * The thermal core only gets the maximum temperature of all banks, so > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > + * Voltage Scaling) unit makes its decisions based on the same bank > + * data, and this indeed needs the temperatures of the individual banks > + * for making better decisions. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + mtk_thermal_get_bank(bank); > + > + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); > + > + mtk_thermal_put_bank(bank); > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret; > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) > + return PTR_ERR(cell); > + return 0; > + } > + > + buf = (u32 *)nvmem_cell_read(cell, &len); > + > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + if (len < 3 * sizeof(u32)) { > + dev_warn(dev, "invalid calibration data\n"); > + ret = -EINVAL; > + goto out; > + } ret would not be assigned if the length of calibration data is correct. Otherwise, Tested-by: Dawei Chien <dawei.chien@mediatek.com> Thanks. > + if (buf[0] & MT8173_CALIB_BUF0_VALID) { > + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); > + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); > + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); > + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); > + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); > + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); > + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); > + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); > + } else { > + dev_info(dev, "Device not calibrated, using default calibration values\n"); > + } > + > +out: > + kfree(buf); > + > + return ret; > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); > + if (ret) > + return ret; > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + > + of_node_put(auxadc); > + > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + > + of_node_put(apmixedsys); > + > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, > + &mtk_thermal_ops); > + if (IS_ERR(mt->tzd)) > + goto err_register; > + > + return 0; > + > +err_register: > + clk_disable_unprepare(mt->clk_peri_therm); > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-24 6:06 ` dawei chien 0 siblings, 0 replies; 139+ messages in thread From: dawei chien @ 2015-11-24 6:06 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, On Wed, 2015-11-18 at 09:24 +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 632 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 5aabc4b..503448a 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs"Why does ret value didn't set to 0 during this function. This function of return value would be not 0 with valid calibration data. > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..0bdf38d > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,623 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * Sascha Hauer <s.hauer@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090Hi Sascha, > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + * > + * The thermal core only gets the maximum temperature of all banks, so > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > + * Voltage Scaling) unit makes its decisions based on the same bank > + * data, and this indeed needs the temperatures of the individual banks > + * for making better decisions. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + mtk_thermal_get_bank(bank); > + > + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); > + > + mtk_thermal_put_bank(bank); > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret; > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) > + return PTR_ERR(cell); > + return 0; > + } > + > + buf = (u32 *)nvmem_cell_read(cell, &len); > + > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + if (len < 3 * sizeof(u32)) { > + dev_warn(dev, "invalid calibration data\n"); > + ret = -EINVAL; > + goto out; > + } ret would not be assigned if the length of calibration data is correct. Otherwise, Tested-by: Dawei Chien <dawei.chien@mediatek.com> Thanks. > + if (buf[0] & MT8173_CALIB_BUF0_VALID) { > + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); > + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); > + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); > + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); > + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); > + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); > + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); > + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); > + } else { > + dev_info(dev, "Device not calibrated, using default calibration values\n"); > + } > + > +out: > + kfree(buf); > + > + return ret; > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); > + if (ret) > + return ret; > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + > + of_node_put(auxadc); > + > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + > + of_node_put(apmixedsys); > + > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, > + &mtk_thermal_ops); > + if (IS_ERR(mt->tzd)) > + goto err_register; > + > + return 0; > + > +err_register: > + clk_disable_unprepare(mt->clk_peri_therm); > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-24 6:06 ` dawei chien 0 siblings, 0 replies; 139+ messages in thread From: dawei chien @ 2015-11-24 6:06 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel Hi Sascha, On Wed, 2015-11-18 at 09:24 +0100, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 623 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 632 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 5aabc4b..503448a 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs"Why does ret value didn't set to 0 during this function. This function of return value would be not 0 with valid calibration data. > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > depends on ARCH_HAS_BANDGAP || COMPILE_TEST > source "drivers/thermal/ti-soc-thermal/Kconfig" > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..0bdf38d > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,623 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * Sascha Hauer <s.hauer@pengutronix.de> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/io.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/types.h> > +#include <linux/nvmem-consumer.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090Hi Sascha, > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +/* Layout of the fuses providing the calibration data */ > +#define MT8173_CALIB_BUF0_VALID (1 << 0) > +#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22 ) & 0x3ff) > +#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8 ) & 0x1ff) > +#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23 ) & 0x1ff) > +#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14 ) & 0x1ff) > +#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1 ) & 0x3f) > +#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26 ) & 0x3f) > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 degc_cali; > + s32 o_slope; > + s32 vts[MT8173_NUM_SENSORS]; > + > + struct thermal_zone_device *tzd; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + * > + * The thermal core only gets the maximum temperature of all banks, so > + * the bank concept wouldn't be necessary here. However, the SVS (Smart > + * Voltage Scaling) unit makes its decisions based on the same bank > + * data, and this indeed needs the temperatures of the individual banks > + * for making better decisions. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) > +{ > + s32 tmp; > + > + raw &= 0xfff; > + > + tmp = 203450520 << 3; > + tmp /= 165 + mt->o_slope; > + tmp /= 10000 + mt->adc_ge; > + tmp *= raw - mt->vts[sensno] - 3350; > + tmp >>= 3; > + > + return mt->degc_cali * 500 - tmp; > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temperature) > +{ > + struct mtk_thermal *mt = data; > + int i; > + int tempmax = INT_MIN; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + mtk_thermal_get_bank(bank); > + > + tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); > + > + mtk_thermal_put_bank(bank); > + } > + > + *temperature = tempmax; > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x0, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > +{ > + struct nvmem_cell *cell; > + u32 *buf; > + size_t len; > + int i, ret; > + /* Start with default values */ > + mt->adc_ge = 512; > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > + mt->vts[i] = 260; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + if (PTR_ERR(cell) == -EPROBE_DEFER) > + return PTR_ERR(cell); > + return 0; > + } > + > + buf = (u32 *)nvmem_cell_read(cell, &len); > + > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + if (len < 3 * sizeof(u32)) { > + dev_warn(dev, "invalid calibration data\n"); > + ret = -EINVAL; > + goto out; > + } ret would not be assigned if the length of calibration data is correct. Otherwise, Tested-by: Dawei Chien <dawei.chien@mediatek.com> Thanks. > + if (buf[0] & MT8173_CALIB_BUF0_VALID) { > + mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); > + mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); > + mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); > + mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); > + mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); > + mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); > + mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); > + mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); > + } else { > + dev_info(dev, "Device not calibrated, using default calibration values\n"); > + } > + > +out: > + kfree(buf); > + > + return ret; > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); > + if (ret) > + return ret; > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + > + of_node_put(auxadc); > + > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + > + of_node_put(apmixedsys); > + > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt, > + &mtk_thermal_ops); > + if (IS_ERR(mt->tzd)) > + goto err_register; > + > + return 0; > + > +err_register: > + clk_disable_unprepare(mt->clk_peri_therm); > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + > + thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd); > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-11-24 6:06 ` dawei chien @ 2015-11-24 7:53 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-24 7:53 UTC (permalink / raw) To: dawei chien Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, kernel, Matthias Brugger, linux-arm-kernel On Tue, Nov 24, 2015 at 02:06:09PM +0800, dawei chien wrote: > Hi Sascha, > > > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > > +{ > > + struct nvmem_cell *cell; > > + u32 *buf; > > + size_t len; > > + int i, ret; > > + /* Start with default values */ > > + mt->adc_ge = 512; > > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > > + mt->vts[i] = 260; > > + mt->degc_cali = 40; > > + mt->o_slope = 0; > > + > > + cell = nvmem_cell_get(dev, "calibration-data"); > > + if (IS_ERR(cell)) { > > + if (PTR_ERR(cell) == -EPROBE_DEFER) > > + return PTR_ERR(cell); > > + return 0; > > + } > > + > > + buf = (u32 *)nvmem_cell_read(cell, &len); > > + > > + nvmem_cell_put(cell); > > + > > + if (IS_ERR(buf)) > > + return PTR_ERR(buf); > > + > > + if (len < 3 * sizeof(u32)) { > > + dev_warn(dev, "invalid calibration data\n"); > > + ret = -EINVAL; > > + goto out; > > + } > > ret would not be assigned if the length of calibration data is correct. > Otherwise, gcc does a increasingly bad job when it comes to warn about uninitialized variables :( Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-11-24 7:53 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-11-24 7:53 UTC (permalink / raw) To: linux-arm-kernel On Tue, Nov 24, 2015 at 02:06:09PM +0800, dawei chien wrote: > Hi Sascha, > > > +static int mtk_thermal_get_calibration_data(struct device *dev, struct mtk_thermal *mt) > > +{ > > + struct nvmem_cell *cell; > > + u32 *buf; > > + size_t len; > > + int i, ret; > > + /* Start with default values */ > > + mt->adc_ge = 512; > > + for (i = 0; i < MT8173_NUM_SENSORS; i++) > > + mt->vts[i] = 260; > > + mt->degc_cali = 40; > > + mt->o_slope = 0; > > + > > + cell = nvmem_cell_get(dev, "calibration-data"); > > + if (IS_ERR(cell)) { > > + if (PTR_ERR(cell) == -EPROBE_DEFER) > > + return PTR_ERR(cell); > > + return 0; > > + } > > + > > + buf = (u32 *)nvmem_cell_read(cell, &len); > > + > > + nvmem_cell_put(cell); > > + > > + if (IS_ERR(buf)) > > + return PTR_ERR(buf); > > + > > + if (len < 3 * sizeof(u32)) { > > + dev_warn(dev, "invalid calibration data\n"); > > + ret = -EINVAL; > > + goto out; > > + } > > ret would not be assigned if the length of calibration data is correct. > Otherwise, gcc does a increasingly bad job when it comes to warn about uninitialized variables :( Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v9] Add Mediatek thermal support @ 2015-09-23 13:37 Sascha Hauer 2015-09-23 13:37 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-09-23 13:37 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. changes since v8: - Add commit description to binding patch - rebase on v4.3-rc2 changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJWAqrzAAoJEPFlmONMx+ezud4QAK3BODYyBYKDPHRF3M6bwcRR Hc5gO9RuA3asA9eyxS+BCIyo9kuJW1Usb1xAE/YL8ryrXlMHMAGBxJH6jnlkuDTS hNZRXdjIfCSLypWOxOLotDuH8RlRQVW4faNHjGYFxflXSL3YNGQlNPjxS2LLAKdU flLSvwg9aWvtdeIwOyIL/tWbpMgF3sluLIz1K2iElqGKDFSDzwBfYEMlf27d6CKw B3PoqDI0rRR6iDiMBoZFJLYzjyyNSKz9Xqqe9y6osOfPnlC7SRmwbBQ19df/Sqxl +Cd4VsuWedqDmP5WD1MCr5SzYqocUnM54t7aarz5TmVf1Ehd3Z+hBW8ItGJsFPDp Itn75HHiIDxm2GrIIkVs82dr3dUpw3v1vThEke3JqfrOvOi2H0bZ2C5jXCqbFr6M bLKVADmyNDHfP/av+v224zMffmJVqRIedfnBKMV6nDLbTzzjlKVf2n1KeBKjwntS PfEY/E4Qg/PM95E/G1qZCuInAN7w53dNZCGMnm+KCNVAcdkMsEwpNWT1lf8+18ng brXWYXcDCniwr1Ye31NuakGdkWLzSolbpmWS5ValUtA/K9flfZBcnqJ5obF8ooD1 cMnyq4FMpYozhgRYoPVD3pooIBl+yqKNmNtphBftyozZKgPfdOjhPkoCx0hlpBuH 270RN+jva0dOJWk+FXGR =bcx6 -----END PGP SIGNATURE----- commit de42d22304311e6d5d711b85e66a281fe1035ba2 Author: Sascha Hauer <s.hauer@pengutronix.de> Date: Tue May 12 09:22:29 2015 +0200 ARM64: dts: mt8173: Add thermal/auxadc device nodes Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d18ee42..3b18f37 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -277,6 +277,11 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + auxadc: auxadc@11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", "mediatek,mt6577-uart"; @@ -487,6 +492,18 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + thermal: thermal@1100b000 { + #thermal-sensor-cells = <1>; + compatible = "mediatek,mt8173-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; }; }; ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-23 13:37 [PATCH v9] Add Mediatek thermal support Sascha Hauer @ 2015-09-23 13:37 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-23 13:37 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 0390044..dadd1eb 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..6be1a6c --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> +#include <dt-bindings/thermal/mt8173.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + [MT8173_THERMAL_ZONE_CA53] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, + + [MT8173_THERMAL_ZONE_CA57] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, + + [MT8173_THERMAL_ZONE_GPU] = { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, + + [MT8173_THERMAL_ZONE_CORE] = { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-23 13:37 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-23 13:37 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 0390044..dadd1eb 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL Thermal reporting device will provide temperature reading, programmable trip points and other information. +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 26f1608..5f979e7 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..6be1a6c --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> +#include <dt-bindings/thermal/mt8173.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + [MT8173_THERMAL_ZONE_CA53] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, + + [MT8173_THERMAL_ZONE_CA57] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, + + [MT8173_THERMAL_ZONE_GPU] = { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, + + [MT8173_THERMAL_ZONE_CORE] = { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.1 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-23 18:31 ` Vladimir Zapolskiy 0 siblings, 0 replies; 139+ messages in thread From: Vladimir Zapolskiy @ 2015-09-23 18:31 UTC (permalink / raw) To: Sascha Hauer, Eduardo Valentin Cc: linux-pm, Zhang Rui, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt Hi Sascha, On 23.09.2015 16:37, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > [snip] > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); in case of OF_DYNAMIC enabled of_parse_phandle() requires of_node_put(), which is fine to place right here. > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + [snip] > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); I would propose to add return value checks here, otherwise there might be an oops in mtk_thermal_remove(), if something goes wrong. -- With best wishes, Vladimir ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-23 18:31 ` Vladimir Zapolskiy 0 siblings, 0 replies; 139+ messages in thread From: Vladimir Zapolskiy @ 2015-09-23 18:31 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, On 23.09.2015 16:37, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > [snip] > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); in case of OF_DYNAMIC enabled of_parse_phandle() requires of_node_put(), which is fine to place right here. > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + [snip] > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); I would propose to add return value checks here, otherwise there might be an oops in mtk_thermal_remove(), if something goes wrong. -- With best wishes, Vladimir ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-23 18:31 ` Vladimir Zapolskiy 0 siblings, 0 replies; 139+ messages in thread From: Vladimir Zapolskiy @ 2015-09-23 18:31 UTC (permalink / raw) To: Sascha Hauer, Eduardo Valentin Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Matthias Brugger, Zhang Rui, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Sascha, On 23.09.2015 16:37, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> > Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > [snip] > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); in case of OF_DYNAMIC enabled of_parse_phandle() requires of_node_put(), which is fine to place right here. > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + [snip] > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); I would propose to add return value checks here, otherwise there might be an oops in mtk_thermal_remove(), if something goes wrong. -- With best wishes, Vladimir ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-23 18:31 ` Vladimir Zapolskiy @ 2015-09-30 6:14 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-30 6:14 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: Eduardo Valentin, linux-pm, Zhang Rui, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt Hi Vladimir, On Wed, Sep 23, 2015 at 09:31:12PM +0300, Vladimir Zapolskiy wrote: > Hi Sascha, > > in case of OF_DYNAMIC enabled of_parse_phandle() requires of_node_put(), > which is fine to place right here. > > > + if (auxadc_phys_base == OF_BAD_ADDR) { > > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > > + return -EINVAL; > > + } > > + > > [snip] > > > + > > + /* > > + * These calibration values should finally be provided by the > > + * firmware or fuses. For now use default values. > > + */ > > + mt->calib_slope = -123; > > + mt->calib_offset = 465124; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) > > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > > + > > + platform_set_drvdata(pdev, mt); > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + > > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > > + &mtk_thermal_ops); > > I would propose to add return value checks here, otherwise there might > be an oops in mtk_thermal_remove(), if something goes wrong. Thanks for the input. I'll fix that in the next round. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 6:14 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-30 6:14 UTC (permalink / raw) To: linux-arm-kernel Hi Vladimir, On Wed, Sep 23, 2015 at 09:31:12PM +0300, Vladimir Zapolskiy wrote: > Hi Sascha, > > in case of OF_DYNAMIC enabled of_parse_phandle() requires of_node_put(), > which is fine to place right here. > > > + if (auxadc_phys_base == OF_BAD_ADDR) { > > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > > + return -EINVAL; > > + } > > + > > [snip] > > > + > > + /* > > + * These calibration values should finally be provided by the > > + * firmware or fuses. For now use default values. > > + */ > > + mt->calib_slope = -123; > > + mt->calib_offset = 465124; > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) > > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > > + > > + platform_set_drvdata(pdev, mt); > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + > > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > > + &mtk_thermal_ops); > > I would propose to add return value checks here, otherwise there might > be an oops in mtk_thermal_remove(), if something goes wrong. Thanks for the input. I'll fix that in the next round. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-29 23:04 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-09-29 23:04 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt On Wed, Sep 23, 2015 at 03:37:42PM +0200, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 0390044..dadd1eb 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..6be1a6c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,537 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> You dont seam to be using this header. Can you please clean up to have only the headers you need? > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > +#include <dt-bindings/thermal/mt8173.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + [MT8173_THERMAL_ZONE_CA53] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, > + > + [MT8173_THERMAL_ZONE_CA57] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, > + > + [MT8173_THERMAL_ZONE_GPU] = { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, > + > + [MT8173_THERMAL_ZONE_CORE] = { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) Ok... How about after the first read? is > 200000 a valid (supported) value range? Just trying to understand if the cap can be kept on all cases. > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); of_put? > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; I would still prefer that this driver would not have these hardcoded values. Specially considering the fact that we could map it in DT for instance. What is the impact of using this? Does it work across all chip distribution? Should we wait until you have the code to read the fuses before merging this? > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); You need to error handle this. > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.5.1 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-29 23:04 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-09-29 23:04 UTC (permalink / raw) To: linux-arm-kernel On Wed, Sep 23, 2015 at 03:37:42PM +0200, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 0390044..dadd1eb 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..6be1a6c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,537 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> You dont seam to be using this header. Can you please clean up to have only the headers you need? > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > +#include <dt-bindings/thermal/mt8173.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + [MT8173_THERMAL_ZONE_CA53] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, > + > + [MT8173_THERMAL_ZONE_CA57] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, > + > + [MT8173_THERMAL_ZONE_GPU] = { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, > + > + [MT8173_THERMAL_ZONE_CORE] = { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) Ok... How about after the first read? is > 200000 a valid (supported) value range? Just trying to understand if the cap can be kept on all cases. > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); of_put? > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; I would still prefer that this driver would not have these hardcoded values. Specially considering the fact that we could map it in DT for instance. What is the impact of using this? Does it work across all chip distribution? Should we wait until you have the code to read the fuses before merging this? > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); You need to error handle this. > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.5.1 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-29 23:04 ` Eduardo Valentin 0 siblings, 0 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-09-29 23:04 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger, devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A On Wed, Sep 23, 2015 at 03:37:42PM +0200, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> > Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 0390044..dadd1eb 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..6be1a6c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,537 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> You dont seam to be using this header. Can you please clean up to have only the headers you need? > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > +#include <dt-bindings/thermal/mt8173.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + [MT8173_THERMAL_ZONE_CA53] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, > + > + [MT8173_THERMAL_ZONE_CA57] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, > + > + [MT8173_THERMAL_ZONE_GPU] = { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, > + > + [MT8173_THERMAL_ZONE_CORE] = { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) Ok... How about after the first read? is > 200000 a valid (supported) value range? Just trying to understand if the cap can be kept on all cases. > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, int *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); of_put? > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; I would still prefer that this driver would not have these hardcoded values. Specially considering the fact that we could map it in DT for instance. What is the impact of using this? Does it work across all chip distribution? Should we wait until you have the code to read the fuses before merging this? > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); You need to error handle this. > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.5.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-29 23:04 ` Eduardo Valentin @ 2015-09-30 6:13 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-30 6:13 UTC (permalink / raw) To: Eduardo Valentin Cc: linux-pm, Zhang Rui, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt Hi Eduardo, On Tue, Sep 29, 2015 at 04:04:40PM -0700, Eduardo Valentin wrote: > On Wed, Sep 23, 2015 at 03:37:42PM +0200, Sascha Hauer wrote: > > +#include <linux/clk.h> > > +#include <linux/delay.h> > > +#include <linux/interrupt.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/of_irq.h> > > You dont seam to be using this header. Can you please clean up to have > only the headers you need? Ok, did that. > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > Ok... How about after the first read? is > 200000 a valid (supported) value range? No, temperatures over 200°C are not supported for this SoC. > > + > > + mt->dev = &pdev->dev; > > + > > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > of_put? added > > + if (!auxadc) { > > + dev_err(&pdev->dev, "missing auxadc node\n"); > > + return -ENODEV; > > + } > > + > > + auxadc_phys_base = of_get_phys_base(auxadc); > > + if (auxadc_phys_base == OF_BAD_ADDR) { > > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > > + return -EINVAL; > > + } > > + > > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > > + if (!apmixedsys) { > > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > > + return -ENODEV; > > + } For this one aswell. > > + /* > > + * These calibration values should finally be provided by the > > + * firmware or fuses. For now use default values. > > + */ > > + mt->calib_slope = -123; > > + mt->calib_offset = 465124; > > I would still prefer that this driver would not have these hardcoded > values. Specially considering the fact that we could map it in DT for > instance. What is the impact of using this? Does it work across all chip > distribution? I think yes, but not that accurate. > > Should we wait until you have the code to read the fuses before merging > this? I'd say we should merge this. It makes the life easier for the guys writing the cpufreq driver. Adding a dependency on a not yet written driver IMO only adds unnecessary delays. > > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) > > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > > + > > + platform_set_drvdata(pdev, mt); > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + > > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > > + &mtk_thermal_ops); > > You need to error handle this. Errors here are pretty much expected. This is due to the behaviour of thermal_zone_of_sensor_register which errors out when no user for a sensor is found. Normally I would expect that I can register a sensor regardless if it is used or not, but that's not how thermal_zone_of_sensor_register is written. I could catch -EPROBE_DEFER here, but currently I see no case where this can actually be returned from thermal_zone_of_sensor_register. What I can and should do though is to call thermal_zone_of_sensor_unregister only for sensors that are successfully registered. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 6:13 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-30 6:13 UTC (permalink / raw) To: linux-arm-kernel Hi Eduardo, On Tue, Sep 29, 2015 at 04:04:40PM -0700, Eduardo Valentin wrote: > On Wed, Sep 23, 2015 at 03:37:42PM +0200, Sascha Hauer wrote: > > +#include <linux/clk.h> > > +#include <linux/delay.h> > > +#include <linux/interrupt.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/of_irq.h> > > You dont seam to be using this header. Can you please clean up to have > only the headers you need? Ok, did that. > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > Ok... How about after the first read? is > 200000 a valid (supported) value range? No, temperatures over 200?C are not supported for this SoC. > > + > > + mt->dev = &pdev->dev; > > + > > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > of_put? added > > + if (!auxadc) { > > + dev_err(&pdev->dev, "missing auxadc node\n"); > > + return -ENODEV; > > + } > > + > > + auxadc_phys_base = of_get_phys_base(auxadc); > > + if (auxadc_phys_base == OF_BAD_ADDR) { > > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > > + return -EINVAL; > > + } > > + > > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > > + if (!apmixedsys) { > > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > > + return -ENODEV; > > + } For this one aswell. > > + /* > > + * These calibration values should finally be provided by the > > + * firmware or fuses. For now use default values. > > + */ > > + mt->calib_slope = -123; > > + mt->calib_offset = 465124; > > I would still prefer that this driver would not have these hardcoded > values. Specially considering the fact that we could map it in DT for > instance. What is the impact of using this? Does it work across all chip > distribution? I think yes, but not that accurate. > > Should we wait until you have the code to read the fuses before merging > this? I'd say we should merge this. It makes the life easier for the guys writing the cpufreq driver. Adding a dependency on a not yet written driver IMO only adds unnecessary delays. > > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) > > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > > + > > + platform_set_drvdata(pdev, mt); > > + > > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + > > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > > + &mtk_thermal_ops); > > You need to error handle this. Errors here are pretty much expected. This is due to the behaviour of thermal_zone_of_sensor_register which errors out when no user for a sensor is found. Normally I would expect that I can register a sensor regardless if it is used or not, but that's not how thermal_zone_of_sensor_register is written. I could catch -EPROBE_DEFER here, but currently I see no case where this can actually be returned from thermal_zone_of_sensor_register. What I can and should do though is to call thermal_zone_of_sensor_unregister only for sensors that are successfully registered. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 9:36 ` Punit Agrawal 0 siblings, 0 replies; 139+ messages in thread From: Punit Agrawal @ 2015-09-30 9:36 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt Hi Sascha, Re-posting a comment from v7. Perhaps you missed it... Sascha Hauer <s.hauer@pengutronix.de> writes: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 0390044..dadd1eb 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..6be1a6c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,537 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > +#include <dt-bindings/thermal/mt8173.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + [MT8173_THERMAL_ZONE_CA53] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, > + > + [MT8173_THERMAL_ZONE_CA57] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, > + > + [MT8173_THERMAL_ZONE_GPU] = { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, > + > + [MT8173_THERMAL_ZONE_CORE] = { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + If the bogus value is only the first time the sensor is read, instead of filtering here, you could call mtk_thermal_bank_temperature at probe time when you are initialising the banks and ignore the returned value. Thanks, Punit > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + [...] ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 9:36 ` Punit Agrawal 0 siblings, 0 replies; 139+ messages in thread From: Punit Agrawal @ 2015-09-30 9:36 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, Re-posting a comment from v7. Perhaps you missed it... Sascha Hauer <s.hauer@pengutronix.de> writes: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 0390044..dadd1eb 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..6be1a6c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,537 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > +#include <dt-bindings/thermal/mt8173.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + [MT8173_THERMAL_ZONE_CA53] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, > + > + [MT8173_THERMAL_ZONE_CA57] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, > + > + [MT8173_THERMAL_ZONE_GPU] = { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, > + > + [MT8173_THERMAL_ZONE_CORE] = { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + If the bogus value is only the first time the sensor is read, instead of filtering here, you could call mtk_thermal_bank_temperature at probe time when you are initialising the banks and ignore the returned value. Thanks, Punit > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + [...] ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 9:36 ` Punit Agrawal 0 siblings, 0 replies; 139+ messages in thread From: Punit Agrawal @ 2015-09-30 9:36 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, Eduardo Valentin, linux-kernel-u79uwXL29TY76Z2rM5mHXA, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Matthias Brugger, devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A Hi Sascha, Re-posting a comment from v7. Perhaps you missed it... Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> writes: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> > Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 546 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 0390044..dadd1eb 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -348,6 +348,14 @@ config INTEL_PCH_THERMAL > Thermal reporting device will provide temperature reading, > programmable trip points and other information. > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 26f1608..5f979e7 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -45,3 +45,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..6be1a6c > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,537 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > +#include <dt-bindings/thermal/mt8173.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + [MT8173_THERMAL_ZONE_CA53] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, > + > + [MT8173_THERMAL_ZONE_CA57] = { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, > + > + [MT8173_THERMAL_ZONE_GPU] = { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, > + > + [MT8173_THERMAL_ZONE_CORE] = { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + If the bogus value is only the first time the sensor is read, instead of filtering here, you could call mtk_thermal_bank_temperature at probe time when you are initialising the banks and ignore the returned value. Thanks, Punit > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + [...] -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-30 9:36 ` Punit Agrawal @ 2015-09-30 10:37 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-30 10:37 UTC (permalink / raw) To: Punit Agrawal Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt Hi Punit, On Wed, Sep 30, 2015 at 10:36:14AM +0100, Punit Agrawal wrote: > Hi Sascha, > > Re-posting a comment from v7. Perhaps you missed it... Uh, sorry. In fact I didn't miss it and I thought I have answered it. Appearantly I haven't. > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > If the bogus value is only the first time the sensor is read, instead of > filtering here, you could call mtk_thermal_bank_temperature at probe > time when you are initialising the banks and ignore the returned value. It seems that after initialization the hardware needs some time to settle before correct values can be read. Doing what you suggest would mean we have to delay the boot by several 100ms. I'd rather not do that. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 10:37 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-30 10:37 UTC (permalink / raw) To: linux-arm-kernel Hi Punit, On Wed, Sep 30, 2015 at 10:36:14AM +0100, Punit Agrawal wrote: > Hi Sascha, > > Re-posting a comment from v7. Perhaps you missed it... Uh, sorry. In fact I didn't miss it and I thought I have answered it. Appearantly I haven't. > > + struct mtk_thermal *mt = bank->mt; > > + int temp, i, max; > > + u32 raw; > > + > > + temp = max = INT_MIN; > > + > > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > > + raw = readl(mt->thermal_base + sensing_points[i].msr); > > + > > + temp = raw_to_mcelsius(mt, raw); > > + > > + /* > > + * The first read of a sensor often contains very high bogus > > + * temperature value. Filter these out so that the system does > > + * not immediately shut down. > > + */ > > + if (temp > 200000) > > + temp = 0; > > + > > If the bogus value is only the first time the sensor is read, instead of > filtering here, you could call mtk_thermal_bank_temperature at probe > time when you are initialising the banks and ignore the returned value. It seems that after initialization the hardware needs some time to settle before correct values can be read. Doing what you suggest would mean we have to delay the boot by several 100ms. I'd rather not do that. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-30 10:37 ` Sascha Hauer @ 2015-09-30 11:07 ` Punit Agrawal -1 siblings, 0 replies; 139+ messages in thread From: Punit Agrawal @ 2015-09-30 11:07 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt Sascha Hauer <s.hauer@pengutronix.de> writes: > Hi Punit, > > On Wed, Sep 30, 2015 at 10:36:14AM +0100, Punit Agrawal wrote: >> Hi Sascha, >> >> Re-posting a comment from v7. Perhaps you missed it... > > Uh, sorry. In fact I didn't miss it and I thought I have answered it. > Appearantly I haven't. > >> > + struct mtk_thermal *mt = bank->mt; >> > + int temp, i, max; >> > + u32 raw; >> > + >> > + temp = max = INT_MIN; >> > + >> > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { >> > + raw = readl(mt->thermal_base + sensing_points[i].msr); >> > + >> > + temp = raw_to_mcelsius(mt, raw); >> > + >> > + /* >> > + * The first read of a sensor often contains very high bogus >> > + * temperature value. Filter these out so that the system does >> > + * not immediately shut down. >> > + */ >> > + if (temp > 200000) >> > + temp = 0; >> > + >> >> If the bogus value is only the first time the sensor is read, instead of >> filtering here, you could call mtk_thermal_bank_temperature at probe >> time when you are initialising the banks and ignore the returned value. > > It seems that after initialization the hardware needs some time to > settle before correct values can be read. Doing what you suggest would > mean we have to delay the boot by several 100ms. I'd rather not do that. Fair enough. Thanks for clarifying. > > Sascha ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-30 11:07 ` Punit Agrawal 0 siblings, 0 replies; 139+ messages in thread From: Punit Agrawal @ 2015-09-30 11:07 UTC (permalink / raw) To: linux-arm-kernel Sascha Hauer <s.hauer@pengutronix.de> writes: > Hi Punit, > > On Wed, Sep 30, 2015 at 10:36:14AM +0100, Punit Agrawal wrote: >> Hi Sascha, >> >> Re-posting a comment from v7. Perhaps you missed it... > > Uh, sorry. In fact I didn't miss it and I thought I have answered it. > Appearantly I haven't. > >> > + struct mtk_thermal *mt = bank->mt; >> > + int temp, i, max; >> > + u32 raw; >> > + >> > + temp = max = INT_MIN; >> > + >> > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { >> > + raw = readl(mt->thermal_base + sensing_points[i].msr); >> > + >> > + temp = raw_to_mcelsius(mt, raw); >> > + >> > + /* >> > + * The first read of a sensor often contains very high bogus >> > + * temperature value. Filter these out so that the system does >> > + * not immediately shut down. >> > + */ >> > + if (temp > 200000) >> > + temp = 0; >> > + >> >> If the bogus value is only the first time the sensor is read, instead of >> filtering here, you could call mtk_thermal_bank_temperature at probe >> time when you are initialising the banks and ignore the returned value. > > It seems that after initialization the hardware needs some time to > settle before correct values can be read. Doing what you suggest would > mean we have to delay the boot by several 100ms. I'd rather not do that. Fair enough. Thanks for clarifying. > > Sascha ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v8] Add Mediatek thermal support @ 2015-08-31 7:34 Sascha Hauer 2015-08-31 7:34 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-31 7:34 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. changes since v7: - re-add some used defines removed in v5 - Use MT8173_THERMAL_ZONE_* defines as array indices in static initializers changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-08-31 7:34 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-31 7:34 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, devicetree, mark.rutland, robh+dt, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..229d8a7 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> +#include <dt-bindings/thermal/mt8173.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + [MT8173_THERMAL_ZONE_CA53] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, + + [MT8173_THERMAL_ZONE_CA57] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, + + [MT8173_THERMAL_ZONE_GPU] = { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, + + [MT8173_THERMAL_ZONE_CORE] = { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.0 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-08-31 7:34 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-31 7:34 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..229d8a7 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> +#include <dt-bindings/thermal/mt8173.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + [MT8173_THERMAL_ZONE_CA53] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, + + [MT8173_THERMAL_ZONE_CA57] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, + + [MT8173_THERMAL_ZONE_GPU] = { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, + + [MT8173_THERMAL_ZONE_CORE] = { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.0 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-08-31 7:34 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-31 7:34 UTC (permalink / raw) To: linux-pm-u79uwXL29TY76Z2rM5mHXA, Zhang Rui, Eduardo Valentin Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA, Sascha Hauer, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Matthias Brugger, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 537 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..229d8a7 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> +#include <dt-bindings/thermal/mt8173.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + [MT8173_THERMAL_ZONE_CA53] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, + + [MT8173_THERMAL_ZONE_CA57] = { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, + + [MT8173_THERMAL_ZONE_GPU] = { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, + + [MT8173_THERMAL_ZONE_CORE] = { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.0 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-31 7:34 ` Sascha Hauer (?) @ 2015-09-14 7:32 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-09-14 7:32 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, Mark Rutland, open list:OPEN FIRMWARE AND..., linux-kernel, Rob Herring, linux-mediatek, Sasha Hauer, Matthias Brugger, linux-arm-kernel Hi Sascha, On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> [snip...] > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, On v4.3-rc1, this now causes a compile warning, since the prototype for get_temp was changed to: int (*get_temp)(void *, int *); by: commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a thermal: consistently use int for temperatures -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-14 7:32 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-09-14 7:32 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> [snip...] > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, On v4.3-rc1, this now causes a compile warning, since the prototype for get_temp was changed to: int (*get_temp)(void *, int *); by: commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a thermal: consistently use int for temperatures -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-14 7:32 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-09-14 7:32 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, Mark Rutland, open list:OPEN FIRMWARE AND..., linux-kernel, Rob Herring, linux-mediatek, Sasha Hauer, Matthias Brugger, linux-arm-kernel Hi Sascha, On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> [snip...] > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, On v4.3-rc1, this now causes a compile warning, since the prototype for get_temp was changed to: int (*get_temp)(void *, int *); by: commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a thermal: consistently use int for temperatures -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-14 7:32 ` Daniel Kurtz (?) @ 2015-09-22 7:30 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-09-22 7:30 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, Mark Rutland, open list:OPEN FIRMWARE AND..., linux-kernel, Rob Herring, linux-mediatek, Sasha Hauer, Matthias Brugger, linux-arm-kernel On Mon, Sep 14, 2015 at 3:32 PM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > Hi Sascha, > > On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > > [snip...] > > > +static int mtk_read_temp(void *data, long *temp) > > +{ > > + struct mtk_thermal_bank *bank = data; > > + > > + mtk_thermal_get_bank(bank); > > + > > + *temp = mtk_thermal_bank_temperature(bank); > > + > > + mtk_thermal_put_bank(bank); > > + > > + return 0; > > +} > > + > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > + .get_temp = mtk_read_temp, > > On v4.3-rc1, this now causes a compile warning, since the prototype > for get_temp was changed to: > > int (*get_temp)(void *, int *); > > by: > commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a > thermal: consistently use int for temperatures It is actually a little worse than a warning. This actually causes a crash on boot. Sascha, can you send out a rebased patch set on v4.3-rc1? Thanks, -Dan > > > -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-22 7:30 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-09-22 7:30 UTC (permalink / raw) To: linux-arm-kernel On Mon, Sep 14, 2015 at 3:32 PM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > Hi Sascha, > > On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > > [snip...] > > > +static int mtk_read_temp(void *data, long *temp) > > +{ > > + struct mtk_thermal_bank *bank = data; > > + > > + mtk_thermal_get_bank(bank); > > + > > + *temp = mtk_thermal_bank_temperature(bank); > > + > > + mtk_thermal_put_bank(bank); > > + > > + return 0; > > +} > > + > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > + .get_temp = mtk_read_temp, > > On v4.3-rc1, this now causes a compile warning, since the prototype > for get_temp was changed to: > > int (*get_temp)(void *, int *); > > by: > commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a > thermal: consistently use int for temperatures It is actually a little worse than a warning. This actually causes a crash on boot. Sascha, can you send out a rebased patch set on v4.3-rc1? Thanks, -Dan > > > -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-22 7:30 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-09-22 7:30 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, Mark Rutland, open list:OPEN FIRMWARE AND..., linux-kernel, Rob Herring, linux-mediatek, Sasha Hauer, Matthias Brugger, linux-arm-kernel On Mon, Sep 14, 2015 at 3:32 PM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > Hi Sascha, > > On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > This adds support for the Mediatek thermal controller found on MT8173 > > and likely other SoCs. > > The controller is a bit special. It does not have its own ADC, instead > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > we need the physical address of the AUXADC. Also it controls a mux > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > > [snip...] > > > +static int mtk_read_temp(void *data, long *temp) > > +{ > > + struct mtk_thermal_bank *bank = data; > > + > > + mtk_thermal_get_bank(bank); > > + > > + *temp = mtk_thermal_bank_temperature(bank); > > + > > + mtk_thermal_put_bank(bank); > > + > > + return 0; > > +} > > + > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > + .get_temp = mtk_read_temp, > > On v4.3-rc1, this now causes a compile warning, since the prototype > for get_temp was changed to: > > int (*get_temp)(void *, int *); > > by: > commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a > thermal: consistently use int for temperatures It is actually a little worse than a warning. This actually causes a crash on boot. Sascha, can you send out a rebased patch set on v4.3-rc1? Thanks, -Dan > > > -Dan ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-09-22 7:30 ` Daniel Kurtz (?) @ 2015-09-22 8:30 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-22 8:30 UTC (permalink / raw) To: Daniel Kurtz Cc: linux-pm, Zhang Rui, Eduardo Valentin, Mark Rutland, open list:OPEN FIRMWARE AND..., linux-kernel, Rob Herring, linux-mediatek, Sasha Hauer, Matthias Brugger, linux-arm-kernel On Tue, Sep 22, 2015 at 03:30:47PM +0800, Daniel Kurtz wrote: > On Mon, Sep 14, 2015 at 3:32 PM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > > > Hi Sascha, > > > > On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > This adds support for the Mediatek thermal controller found on MT8173 > > > and likely other SoCs. > > > The controller is a bit special. It does not have its own ADC, instead > > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > > we need the physical address of the AUXADC. Also it controls a mux > > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > > > > [snip...] > > > > > +static int mtk_read_temp(void *data, long *temp) > > > +{ > > > + struct mtk_thermal_bank *bank = data; > > > + > > > + mtk_thermal_get_bank(bank); > > > + > > > + *temp = mtk_thermal_bank_temperature(bank); > > > + > > > + mtk_thermal_put_bank(bank); > > > + > > > + return 0; > > > +} > > > + > > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > > + .get_temp = mtk_read_temp, > > > > On v4.3-rc1, this now causes a compile warning, since the prototype > > for get_temp was changed to: > > > > int (*get_temp)(void *, int *); > > > > by: > > commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a > > thermal: consistently use int for temperatures > > It is actually a little worse than a warning. This actually causes a > crash on boot. > Sascha, can you send out a rebased patch set on v4.3-rc1? Yes, I'll send out a new version tomorrow. I am currently quite busy with another project. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-22 8:30 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-22 8:30 UTC (permalink / raw) To: linux-arm-kernel On Tue, Sep 22, 2015 at 03:30:47PM +0800, Daniel Kurtz wrote: > On Mon, Sep 14, 2015 at 3:32 PM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > > > Hi Sascha, > > > > On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > This adds support for the Mediatek thermal controller found on MT8173 > > > and likely other SoCs. > > > The controller is a bit special. It does not have its own ADC, instead > > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > > we need the physical address of the AUXADC. Also it controls a mux > > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > > > > [snip...] > > > > > +static int mtk_read_temp(void *data, long *temp) > > > +{ > > > + struct mtk_thermal_bank *bank = data; > > > + > > > + mtk_thermal_get_bank(bank); > > > + > > > + *temp = mtk_thermal_bank_temperature(bank); > > > + > > > + mtk_thermal_put_bank(bank); > > > + > > > + return 0; > > > +} > > > + > > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > > + .get_temp = mtk_read_temp, > > > > On v4.3-rc1, this now causes a compile warning, since the prototype > > for get_temp was changed to: > > > > int (*get_temp)(void *, int *); > > > > by: > > commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a > > thermal: consistently use int for temperatures > > It is actually a little worse than a warning. This actually causes a > crash on boot. > Sascha, can you send out a rebased patch set on v4.3-rc1? Yes, I'll send out a new version tomorrow. I am currently quite busy with another project. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-09-22 8:30 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-09-22 8:30 UTC (permalink / raw) To: Daniel Kurtz Cc: linux-pm, Zhang Rui, Eduardo Valentin, Mark Rutland, open list:OPEN FIRMWARE AND..., linux-kernel, Rob Herring, linux-mediatek, Sasha Hauer, Matthias Brugger, linux-arm-kernel On Tue, Sep 22, 2015 at 03:30:47PM +0800, Daniel Kurtz wrote: > On Mon, Sep 14, 2015 at 3:32 PM, Daniel Kurtz <djkurtz@chromium.org> wrote: > > > > Hi Sascha, > > > > On Mon, Aug 31, 2015 at 3:34 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > This adds support for the Mediatek thermal controller found on MT8173 > > > and likely other SoCs. > > > The controller is a bit special. It does not have its own ADC, instead > > > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > > > we need the physical address of the AUXADC. Also it controls a mux > > > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > > > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > > > > [snip...] > > > > > +static int mtk_read_temp(void *data, long *temp) > > > +{ > > > + struct mtk_thermal_bank *bank = data; > > > + > > > + mtk_thermal_get_bank(bank); > > > + > > > + *temp = mtk_thermal_bank_temperature(bank); > > > + > > > + mtk_thermal_put_bank(bank); > > > + > > > + return 0; > > > +} > > > + > > > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > > > + .get_temp = mtk_read_temp, > > > > On v4.3-rc1, this now causes a compile warning, since the prototype > > for get_temp was changed to: > > > > int (*get_temp)(void *, int *); > > > > by: > > commit 17e8351a77397e8a83727eb17e3a3e9b8ab5257a > > thermal: consistently use int for temperatures > > It is actually a little worse than a warning. This actually causes a > crash on boot. > Sascha, can you send out a rebased patch set on v4.3-rc1? Yes, I'll send out a new version tomorrow. I am currently quite busy with another project. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v7] Add Mediatek thermal support @ 2015-08-27 6:41 Sascha Hauer 2015-08-27 6:41 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-27 6:41 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. changes since v6: - remove dot in Hanyi Wus name changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-27 6:41 [PATCH v7] Add Mediatek thermal support Sascha Hauer @ 2015-08-27 6:41 ` Sascha Hauer 2015-08-27 11:50 ` Punit Agrawal 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-27 6:41 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 528 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 537 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..4f8cd34 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,528 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.0 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-27 6:41 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer @ 2015-08-27 11:50 ` Punit Agrawal 0 siblings, 0 replies; 139+ messages in thread From: Punit Agrawal @ 2015-08-27 11:50 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger Hi Sascha, One comment below - Sascha Hauer <s.hauer@pengutronix.de> writes: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 528 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 537 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..4f8cd34 > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,528 @@ > +/* > + * Copyright (c) 2015 MediaTek Inc. > + * Author: Hanyi Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_SPARE0 0x0f0 > + > +#define PTPCORESEL 0x400 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + If the bogus value is one time, Instead of filtering here, you could sanitise the sensor values at probe time when you are initialising the banks. Thanks, Punit > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v6] Add Mediatek thermal support @ 2015-08-26 13:58 Sascha Hauer 2015-08-26 13:58 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-26 13:58 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. changes since v5: - update copyright - remove unused defines Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-26 13:58 [PATCH v6] Add Mediatek thermal support Sascha Hauer @ 2015-08-26 13:58 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-26 13:58 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 528 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 537 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..8029698 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,528 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MSRCTL0 0x038 +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_SPARE0 0x0f0 + +#define PTPCORESEL 0x400 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.5.0 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH v5] Add Mediatek thermal support @ 2015-08-20 8:05 Sascha Hauer 2015-08-20 8:06 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-20 8:05 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. Changes since v4: - give calibration constants more meaningful names (offset, slope) - Use define instead of 0x00c for register access. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ---------------------------------------------------------------- Sascha Hauer (3): dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: Add Mediatek thermal controller support ARM64: dts: mt8173: Add thermal/auxadc device nodes .../bindings/thermal/mediatek-thermal.txt | 38 ++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 17 + drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 582 +++++++++++++++++++++ include/dt-bindings/thermal/mt8173.h | 13 + 6 files changed, 659 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt create mode 100644 drivers/thermal/mtk_thermal.c create mode 100644 include/dt-bindings/thermal/mt8173.h ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 8:05 [PATCH v5] Add Mediatek thermal support Sascha Hauer @ 2015-08-20 8:06 ` Sascha Hauer 2015-08-20 22:20 ` Eduardo Valentin ` (2 more replies) 0 siblings, 3 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-20 8:06 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 582 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 591 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..06d52ef --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,582 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONINT 0x00c +#define TEMP_MONINTSTS 0x010 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MONIDET2 0x01c +#define TEMP_H2NTHRE 0x024 +#define TEMP_HTHRE 0x028 +#define TEMP_CTHRE 0x02c +#define TEMP_OFFSETH 0x030 +#define TEMP_OFFSETL 0x034 +#define TEMP_MSRCTL0 0x038 +#define TEMP_MSRCTL1 0x03c +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEXT 0x058 +#define TEMP_ADCEXT1 0x05c +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCEXTADDR 0x06c +#define TEMP_ADCEXT1ADDR 0x070 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_IMMD0 0x0a0 +#define TEMP_IMMD1 0x0a4 +#define TEMP_IMMD2 0x0a8 + +#define TEMP_PROTCTL 0x0c0 +#define TEMP_PROTTA 0x0c4 +#define TEMP_PROTTB 0x0c8 +#define TEMP_PROTTC 0x0cc + +#define TEMP_SPARE0 0x0f0 +#define TEMP_SPARE1 0x0f4 +#define TEMP_SPARE2 0x0f8 +#define TEMP_SPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) +#define TEMP_MONINT_TIMEOUT BIT(15) +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMP_PROTCTL_AVERAGE (0 << 16) +#define TEMP_PROTCTL_MAXIMUM (1 << 16) +#define TEMP_PROTCTL_SELECTED (2 << 16) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_slope; + int calib_offset; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, + mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_slope = -123; + mt->calib_offset = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.4.6 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 8:06 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer @ 2015-08-20 22:20 ` Eduardo Valentin 2015-08-20 22:29 ` Daniel Lezcano 2015-08-21 5:06 ` Sascha Hauer 2015-08-20 23:12 ` Daniel Lezcano 2015-08-25 17:41 ` Daniel Kurtz 2 siblings, 2 replies; 139+ messages in thread From: Eduardo Valentin @ 2015-08-20 22:20 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger On Thu, Aug 20, 2015 at 10:06:01AM +0200, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 582 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 591 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..06d52ef > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,582 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONINT 0x00c > +#define TEMP_MONINTSTS 0x010 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MONIDET2 0x01c > +#define TEMP_H2NTHRE 0x024 > +#define TEMP_HTHRE 0x028 > +#define TEMP_CTHRE 0x02c > +#define TEMP_OFFSETH 0x030 > +#define TEMP_OFFSETL 0x034 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_MSRCTL1 0x03c > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEXT 0x058 > +#define TEMP_ADCEXT1 0x05c > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCEXTADDR 0x06c > +#define TEMP_ADCEXT1ADDR 0x070 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_IMMD0 0x0a0 > +#define TEMP_IMMD1 0x0a4 > +#define TEMP_IMMD2 0x0a8 > + > +#define TEMP_PROTCTL 0x0c0 > +#define TEMP_PROTTA 0x0c4 > +#define TEMP_PROTTB 0x0c8 > +#define TEMP_PROTTC 0x0cc > + > +#define TEMP_SPARE0 0x0f0 > +#define TEMP_SPARE1 0x0f4 > +#define TEMP_SPARE2 0x0f8 > +#define TEMP_SPARE3 0x0fc > + > +#define PTPCORESEL 0x400 > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) > +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) > +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) > +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) > +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) > +#define TEMP_MONINT_TIMEOUT BIT(15) > +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) > +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define TEMP_PROTCTL_AVERAGE (0 << 16) > +#define TEMP_PROTCTL_MAXIMUM (1 << 16) > +#define TEMP_PROTCTL_SELECTED (2 << 16) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_slope; > + int calib_offset; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_offset + mt->calib_slope * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + AUXADC_CON1_CLR_V, > + mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_slope = -123; > + mt->calib_offset = 465124; Would it make sense to use the coefficients device tree property to describe the sensor slope and offset? > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.4.6 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 22:20 ` Eduardo Valentin @ 2015-08-20 22:29 ` Daniel Lezcano 2015-08-21 5:06 ` Sascha Hauer 1 sibling, 0 replies; 139+ messages in thread From: Daniel Lezcano @ 2015-08-20 22:29 UTC (permalink / raw) To: Eduardo Valentin, Sascha Hauer Cc: linux-pm, Zhang Rui, linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger On 08/21/2015 12:20 AM, Eduardo Valentin wrote: > On Thu, Aug 20, 2015 at 10:06:01AM +0200, Sascha Hauer wrote: >> This adds support for the Mediatek thermal controller found on MT8173 >> and likely other SoCs. >> The controller is a bit special. It does not have its own ADC, instead >> it controls the on-SoC AUXADC via AHB bus accesses. For this reason >> we need the physical address of the AUXADC. Also it controls a mux >> using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. >> >> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> >> --- [ ... ] >> + /* >> + * These calibration values should finally be provided by the >> + * firmware or fuses. For now use default values. >> + */ >> + mt->calib_slope = -123; >> + mt->calib_offset = 465124; > > Would it make sense to use the coefficients device tree property to > describe the sensor slope and offset? Trim the mail when possible please. -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 22:20 ` Eduardo Valentin 2015-08-20 22:29 ` Daniel Lezcano @ 2015-08-21 5:06 ` Sascha Hauer 1 sibling, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-21 5:06 UTC (permalink / raw) To: Eduardo Valentin Cc: linux-pm, Zhang Rui, linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger On Thu, Aug 20, 2015 at 03:20:52PM -0700, Eduardo Valentin wrote: > On Thu, Aug 20, 2015 at 10:06:01AM +0200, Sascha Hauer wrote: > > + > > + /* > > + * These calibration values should finally be provided by the > > + * firmware or fuses. For now use default values. > > + */ > > + mt->calib_slope = -123; > > + mt->calib_offset = 465124; > > Would it make sense to use the coefficients device tree property to > describe the sensor slope and offset? > The values shall ultimately be stored in fuses in the SoC. The current bootloader cannot convert these values into device tree properties. Also there is the new nvmem framework landing. This will allow us to put a description into the device tree where in the fuses the calibration values are found, rather than putting the calibration values themselves into the device tree. This all needs some discussion and work, so I left this topic for later. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 8:06 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-20 22:20 ` Eduardo Valentin @ 2015-08-20 23:12 ` Daniel Lezcano 2015-08-26 13:54 ` Sascha Hauer 2015-08-25 17:41 ` Daniel Kurtz 2 siblings, 1 reply; 139+ messages in thread From: Daniel Lezcano @ 2015-08-20 23:12 UTC (permalink / raw) To: Sascha Hauer, linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger On 08/20/2015 10:06 AM, Sascha Hauer wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- [ ... ] > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..06d52ef > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,582 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. 2015 ? > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> Hanyi Wu ? [ ... ] --> > +#define TEMP_MONINTSTS 0x010 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MONIDET2 0x01c > +#define TEMP_H2NTHRE 0x024 > +#define TEMP_HTHRE 0x028 > +#define TEMP_CTHRE 0x02c > +#define TEMP_OFFSETH 0x030 > +#define TEMP_OFFSETL 0x034 > +#define TEMP_MSRCTL1 0x03c > +#define TEMP_ADCEXT 0x058 > +#define TEMP_ADCEXT1 0x05c > +#define TEMP_ADCEXTADDR 0x06c > +#define TEMP_ADCEXT1ADDR 0x070 > +#define TEMP_IMMD0 0x0a0 > +#define TEMP_IMMD1 0x0a4 > +#define TEMP_IMMD2 0x0a8 > +#define TEMP_PROTCTL 0x0c0 > +#define TEMP_PROTTA 0x0c4 > +#define TEMP_PROTTB 0x0c8 > +#define TEMP_PROTTC 0x0cc > +#define TEMP_SPARE1 0x0f4 > +#define TEMP_SPARE2 0x0f8 > +#define TEMP_SPARE3 0x0fc > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) > +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) > +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) > +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) > +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) > +#define TEMP_MONINT_TIMEOUT BIT(15) > +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) > +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) > +#define TEMP_PROTCTL_AVERAGE (0 << 16) > +#define TEMP_PROTCTL_MAXIMUM (1 << 16) > +#define TEMP_PROTCTL_SELECTED (2 << 16) <-- Not used. -- Daniel -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 23:12 ` Daniel Lezcano @ 2015-08-26 13:54 ` Sascha Hauer 2015-08-26 14:02 ` Daniel Lezcano 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-26 13:54 UTC (permalink / raw) To: Daniel Lezcano Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger On Fri, Aug 21, 2015 at 01:12:23AM +0200, Daniel Lezcano wrote: > On 08/20/2015 10:06 AM, Sascha Hauer wrote: > >This adds support for the Mediatek thermal controller found on MT8173 > >and likely other SoCs. > >The controller is a bit special. It does not have its own ADC, instead > >it controls the on-SoC AUXADC via AHB bus accesses. For this reason > >we need the physical address of the AUXADC. Also it controls a mux > >using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > > >Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > >--- > > [ ... ] > > >diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > >new file mode 100644 > >index 0000000..06d52ef > >--- /dev/null > >+++ b/drivers/thermal/mtk_thermal.c > >@@ -0,0 +1,582 @@ > >+/* > >+ * Copyright (c) 2014 MediaTek Inc. > > 2015 ? Can change to 2015 > > >+ * Author: Hanyi.Wu <hanyi.wu@mediatek.com> > > Hanyi Wu ? It's the original author of this code. > >+#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) > >+#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) > >+#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) > >+#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) > >+#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) > >+#define TEMP_MONINT_TIMEOUT BIT(15) > >+#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) > >+#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) > >+#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) > >+#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) > >+#define TEMP_PROTCTL_AVERAGE (0 << 16) > >+#define TEMP_PROTCTL_MAXIMUM (1 << 16) > >+#define TEMP_PROTCTL_SELECTED (2 << 16) > > <-- Not used. Will remove. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-26 13:54 ` Sascha Hauer @ 2015-08-26 14:02 ` Daniel Lezcano 0 siblings, 0 replies; 139+ messages in thread From: Daniel Lezcano @ 2015-08-26 14:02 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger On 08/26/2015 03:54 PM, Sascha Hauer wrote: > On Fri, Aug 21, 2015 at 01:12:23AM +0200, Daniel Lezcano wrote: >> On 08/20/2015 10:06 AM, Sascha Hauer wrote: >>> This adds support for the Mediatek thermal controller found on MT8173 >>> and likely other SoCs. >>> The controller is a bit special. It does not have its own ADC, instead >>> it controls the on-SoC AUXADC via AHB bus accesses. For this reason >>> we need the physical address of the AUXADC. Also it controls a mux >>> using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. >>> >>> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> >>> --- >> >> [ ... ] >> >>> diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c >>> new file mode 100644 >>> index 0000000..06d52ef >>> --- /dev/null >>> +++ b/drivers/thermal/mtk_thermal.c >>> @@ -0,0 +1,582 @@ >>> +/* >>> + * Copyright (c) 2014 MediaTek Inc. >> >> 2015 ? > > Can change to 2015 > >> >>> + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> >> >> Hanyi Wu ? > > It's the original author of this code. Sorry I wasn't clear. I was suggesting to remove the dot between Hanyi and Wu. >>> +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) >>> +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) >>> +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) >>> +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) >>> +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) >>> +#define TEMP_MONINT_TIMEOUT BIT(15) >>> +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) >>> +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) >>> +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) >>> +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) >>> +#define TEMP_PROTCTL_AVERAGE (0 << 16) >>> +#define TEMP_PROTCTL_MAXIMUM (1 << 16) >>> +#define TEMP_PROTCTL_SELECTED (2 << 16) >> >> <-- Not used. > > Will remove. > > Sascha > > -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-20 8:06 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-20 22:20 ` Eduardo Valentin 2015-08-20 23:12 ` Daniel Lezcano @ 2015-08-25 17:41 ` Daniel Kurtz 2 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-08-25 17:41 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Sasha Hauer, Matthias Brugger Hi Sascha, On Thu, Aug 20, 2015 at 4:06 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Please respond to Daniel Lezcano's comments too. But beyond that, all three patches in this set are: Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v4] Add Mediatek thermal support @ 2015-08-07 13:55 Sascha Hauer 2015-08-07 13:55 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-07 13:55 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. Changes since v3: - add include/dt-bindings/thermal/mt8173.h for to be able to use sensor names in dts files - fix disabling wrong clock in error path - remove now unused reset-names property from binding document - rename MT8173_NUM_BANKS -> MT8173_NUM_ZONES - rename MT8173_NUM_SENSING_POINTS -> MT8173_NUM_SENSORS_PER_ZONE - rename struct thermal_zone_device *tz -> struct thermal_zone_device *tzd Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-07 13:55 [PATCH v4] Add Mediatek thermal support Sascha Hauer @ 2015-08-07 13:55 ` Sascha Hauer 2015-08-11 7:03 ` Daniel Kurtz 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-07 13:55 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 581 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 590 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..1a3829a --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONINT 0x00c +#define TEMP_MONINTSTS 0x010 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MONIDET2 0x01c +#define TEMP_H2NTHRE 0x024 +#define TEMP_HTHRE 0x028 +#define TEMP_CTHRE 0x02c +#define TEMP_OFFSETH 0x030 +#define TEMP_OFFSETL 0x034 +#define TEMP_MSRCTL0 0x038 +#define TEMP_MSRCTL1 0x03c +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEXT 0x058 +#define TEMP_ADCEXT1 0x05c +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCEXTADDR 0x06c +#define TEMP_ADCEXT1ADDR 0x070 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_IMMD0 0x0a0 +#define TEMP_IMMD1 0x0a4 +#define TEMP_IMMD2 0x0a8 + +#define TEMP_PROTCTL 0x0c0 +#define TEMP_PROTTA 0x0c4 +#define TEMP_PROTTB 0x0c8 +#define TEMP_PROTTC 0x0cc + +#define TEMP_SPARE0 0x0f0 +#define TEMP_SPARE1 0x0f4 +#define TEMP_SPARE2 0x0f8 +#define TEMP_SPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) +#define TEMP_MONINT_TIMEOUT BIT(15) +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMP_PROTCTL_AVERAGE (0 << 16) +#define TEMP_PROTCTL_MAXIMUM (1 << 16) +#define TEMP_PROTCTL_SELECTED (2 << 16) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_ZONES 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSORS_PER_ZONE 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tzd; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; + + struct mutex lock; + + /* Calibration values */ + int calib_a; + int calib_b; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_b + mt->calib_a * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + 0x00c, mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + goto err_disable_clk_auxadc; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_a = -123; + mt->calib_b = 465124; + + for (i = 0; i < MT8173_NUM_ZONES; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_auxadc); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_ZONES; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.4.6 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-07 13:55 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer @ 2015-08-11 7:03 ` Daniel Kurtz 2015-08-20 7:57 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Daniel Kurtz @ 2015-08-11 7:03 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Sasha Hauer, Matthias Brugger Hi Sascha, I think this patch looks very good now, just some very tiny things inline... On Fri, Aug 7, 2015 at 9:55 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 581 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 590 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..1a3829a > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,581 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONINT 0x00c > +#define TEMP_MONINTSTS 0x010 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MONIDET2 0x01c > +#define TEMP_H2NTHRE 0x024 > +#define TEMP_HTHRE 0x028 > +#define TEMP_CTHRE 0x02c > +#define TEMP_OFFSETH 0x030 > +#define TEMP_OFFSETL 0x034 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_MSRCTL1 0x03c > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEXT 0x058 > +#define TEMP_ADCEXT1 0x05c > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCEXTADDR 0x06c > +#define TEMP_ADCEXT1ADDR 0x070 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_IMMD0 0x0a0 > +#define TEMP_IMMD1 0x0a4 > +#define TEMP_IMMD2 0x0a8 > + > +#define TEMP_PROTCTL 0x0c0 > +#define TEMP_PROTTA 0x0c4 > +#define TEMP_PROTTB 0x0c8 > +#define TEMP_PROTTC 0x0cc > + > +#define TEMP_SPARE0 0x0f0 > +#define TEMP_SPARE1 0x0f4 > +#define TEMP_SPARE2 0x0f8 > +#define TEMP_SPARE3 0x0fc > + > +#define PTPCORESEL 0x400 > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) > +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) > +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) > +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) > +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) > +#define TEMP_MONINT_TIMEOUT BIT(15) > +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) > +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define TEMP_PROTCTL_AVERAGE (0 << 16) > +#define TEMP_PROTCTL_MAXIMUM (1 << 16) > +#define TEMP_PROTCTL_SELECTED (2 << 16) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSORS_PER_ZONE 4 Aw well... since you left "bank" in all of the comments, variable names and function names, I now regret suggesting you change these macro names. For consistency, I think we should change the macro names back to: MT8173_NUM_BANKS and MT8173_NUM_SENSORS_PER_BANK since you only changed the names for these constants, perhaps > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tzd; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_a; > + int calib_b; Rather than "a" and "b", these should probably names something like "offset" and "slope". Since these are properties of the hardware (board? SoC?), perhaps it makes sense to allow setting them in devicetree? > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_b + mt->calib_a * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + 0x00c, mt->thermal_base + TEMP_ADCMUXADDR); Can you define a AUXADC_ constant for this "0x00c"? > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } Seems like the temp sensor and ADC will always be on and clocked, even if not used. Does it make sense to give this driver runtime_pm support to disable the sensor and its clocks between temperature readings? (Doesn't need to be added in this patch, of course. That's it! Thanks for spinning (and re-spinning, ...) the patches! -Dan > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_a = -123; > + mt->calib_b = 465124; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tzd = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_ZONES; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tzd); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.4.6 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-11 7:03 ` Daniel Kurtz @ 2015-08-20 7:57 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-20 7:57 UTC (permalink / raw) To: Daniel Kurtz Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Sasha Hauer, Matthias Brugger On Tue, Aug 11, 2015 at 03:03:53PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > I think this patch looks very good now, just some very tiny things inline... > > > + > > +struct mtk_thermal { > > + struct device *dev; > > + void __iomem *thermal_base; > > + > > + struct clk *clk_peri_therm; > > + struct clk *clk_auxadc; > > + > > + struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; > > + > > + struct mutex lock; > > + > > + /* Calibration values */ > > + int calib_a; > > + int calib_b; > > Rather than "a" and "b", these should probably names something like > "offset" and "slope". Ok. > > Since these are properties of the hardware (board? SoC?), perhaps it > makes sense to allow setting them in devicetree? It seems there are some fuses in the SoC which shall store the calibration values ultimately. The current bootloader cannot convert these values into device tree properties and I'm not sure the format in which they are stored is clear now (I hope not, since then we would have five calibration values to describe a line). Also the new nvmem framework seems to make it possible to describe the place for the constants in the device tree rather than having to put the values themselves into the device tree. To cut a long story short I left this for a future exercise. > > + /* > > + * The MT8173 thermal controller does not have its own ADC. Instead it > > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > > + * controller has to be programmed with the physical addresses of the > > + * AUXADC registers and with the various bit positions in the AUXADC. > > + * Also the thermal controller controls a mux in the APMIXEDSYS register > > + * space. > > + */ > > + > > + /* > > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > > + * automatically by hw > > + */ > > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > > + > > + /* AHB address for auxadc mux selection */ > > + writel(auxadc_phys_base + 0x00c, mt->thermal_base + TEMP_ADCMUXADDR); > > Can you define a AUXADC_ constant for this "0x00c"? Ok. Sorry, missed that in the last review. > > + > > + ret = clk_prepare_enable(mt->clk_peri_therm); > > + if (ret) { > > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > > + goto err_disable_clk_auxadc; > > + } > > Seems like the temp sensor and ADC will always be on and clocked, even > if not used. > Does it make sense to give this driver runtime_pm support to disable > the sensor and its clocks between temperature readings? (Doesn't need > to be added in this patch, of course. In the longer run I would rather implement interrupt support so that we get interrupted on critical conditions. Then we probably have to keep the clock enabled anyway. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v3] Add Mediatek thermal support @ 2015-08-05 12:25 Sascha Hauer 2015-08-05 12:25 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-05 12:25 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. Changes since v2: - sort #includes alphabetically - Add prefix to register defines - drop some members from struct mtk_thermal - simplify raw_to_mcelsius() - add and use more register bit defines - use device_reset() instead of devm_reset_control_get()/reset_control_reset() - misc other stuff Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-05 12:25 [PATCH v3] Add Mediatek thermal support Sascha Hauer @ 2015-08-05 12:25 ` Sascha Hauer 2015-08-05 18:02 ` Daniel Kurtz 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-08-05 12:25 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, linux-mediatek, Daniel Kurtz, kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 581 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 590 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..0f859b9 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/thermal.h> +#include <linux/reset.h> +#include <linux/time.h> +#include <linux/types.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) BIT(x) + +#define APMIXED_SYS_TS_CON1 0x604 + +/* Thermal Controller Registers */ +#define TEMP_MONCTL0 0x000 +#define TEMP_MONCTL1 0x004 +#define TEMP_MONCTL2 0x008 +#define TEMP_MONINT 0x00c +#define TEMP_MONINTSTS 0x010 +#define TEMP_MONIDET0 0x014 +#define TEMP_MONIDET1 0x018 +#define TEMP_MONIDET2 0x01c +#define TEMP_H2NTHRE 0x024 +#define TEMP_HTHRE 0x028 +#define TEMP_CTHRE 0x02c +#define TEMP_OFFSETH 0x030 +#define TEMP_OFFSETL 0x034 +#define TEMP_MSRCTL0 0x038 +#define TEMP_MSRCTL1 0x03c +#define TEMP_AHBPOLL 0x040 +#define TEMP_AHBTO 0x044 +#define TEMP_ADCPNP0 0x048 +#define TEMP_ADCPNP1 0x04c +#define TEMP_ADCPNP2 0x050 +#define TEMP_ADCPNP3 0x0b4 + +#define TEMP_ADCMUX 0x054 +#define TEMP_ADCEXT 0x058 +#define TEMP_ADCEXT1 0x05c +#define TEMP_ADCEN 0x060 +#define TEMP_PNPMUXADDR 0x064 +#define TEMP_ADCMUXADDR 0x068 +#define TEMP_ADCEXTADDR 0x06c +#define TEMP_ADCEXT1ADDR 0x070 +#define TEMP_ADCENADDR 0x074 +#define TEMP_ADCVALIDADDR 0x078 +#define TEMP_ADCVOLTADDR 0x07c +#define TEMP_RDCTRL 0x080 +#define TEMP_ADCVALIDMASK 0x084 +#define TEMP_ADCVOLTAGESHIFT 0x088 +#define TEMP_ADCWRITECTRL 0x08c +#define TEMP_MSR0 0x090 +#define TEMP_MSR1 0x094 +#define TEMP_MSR2 0x098 +#define TEMP_MSR3 0x0B8 + +#define TEMP_IMMD0 0x0a0 +#define TEMP_IMMD1 0x0a4 +#define TEMP_IMMD2 0x0a8 + +#define TEMP_PROTCTL 0x0c0 +#define TEMP_PROTTA 0x0c4 +#define TEMP_PROTTB 0x0c8 +#define TEMP_PROTTC 0x0cc + +#define TEMP_SPARE0 0x0f0 +#define TEMP_SPARE1 0x0f4 +#define TEMP_SPARE2 0x0f8 +#define TEMP_SPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) + +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) + +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) + +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) +#define TEMP_MONINT_TIMEOUT BIT(15) +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) + +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) + +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMP_PROTCTL_AVERAGE (0 << 16) +#define TEMP_PROTCTL_MAXIMUM (1 << 16) +#define TEMP_PROTCTL_SELECTED (2 << 16) + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_BANKS 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSING_POINTS 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tz; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; + + struct mutex lock; + + /* Calibration values */ + int calib_a; + int calib_b; +}; + +struct mtk_thermal_bank_cfg { + unsigned int num_sensors; + unsigned int sensors[MT8173_NUM_SENSING_POINTS]; +}; + +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static const struct mtk_thermal_bank_cfg bank_data[] = { + { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .num_sensors = 2, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .num_sensors = 3, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .num_sensors = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +struct mtk_thermal_sense_point { + int msr; + int adcpnp; +}; + +static const struct mtk_thermal_sense_point + sensing_points[MT8173_NUM_SENSING_POINTS] = { + { + .msr = TEMP_MSR0, + .adcpnp = TEMP_ADCPNP0, + }, { + .msr = TEMP_MSR1, + .adcpnp = TEMP_ADCPNP1, + }, { + .msr = TEMP_MSR2, + .adcpnp = TEMP_ADCPNP2, + }, { + .msr = TEMP_MSR3, + .adcpnp = TEMP_ADCPNP3, + }, +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + return mt->calib_b + mt->calib_a * (raw & 0xfff); +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = INT_MIN; + + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { + raw = readl(mt->thermal_base + sensing_points[i].msr); + + temp = raw_to_mcelsius(mt, raw); + + /* + * The first read of a sensor often contains very high bogus + * temperature value. Filter these out so that the system does + * not immediately shut down. + */ + if (temp > 200000) + temp = 0; + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, + u32 apmixed_phys_base, u32 auxadc_phys_base) +{ + struct mtk_thermal_bank *bank = &mt->banks[num]; + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; + int i; + + bank->id = num; + bank->mt = mt; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | + TEMP_MONCTL2_SENSOR_INTERVAL(429), + mt->thermal_base + TEMP_MONCTL2); + + /* poll is set to 10u */ + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), + mt->thermal_base + TEMP_AHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMP_MONIDET0); + writel(0x0, mt->thermal_base + TEMP_MONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) + * automatically by hw + */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); + + /* AHB address for auxadc mux selection */ + writel(auxadc_phys_base + 0x00c, mt->thermal_base + TEMP_ADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, + mt->thermal_base + TEMP_PNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMP_ADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMP_ADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMP_RDCTRL); + + /* indicate where the valid bit is */ + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMP_ADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + for (i = 0; i < cfg->num_sensors; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + sensing_points[i].adcpnp); + + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); + + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMP_ADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + u64 auxadc_phys_base, apmixed_phys_base; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + auxadc_phys_base = of_get_phys_base(auxadc); + if (auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + apmixed_phys_base = of_get_phys_base(apmixedsys); + if (apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + ret = device_reset(&pdev->dev); + if (ret) + return ret; + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_disable_clk_auxadc; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->calib_a = -123; + mt->calib_b = 465124; + + for (i = 0; i < MT8173_NUM_BANKS; i++) + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_disable_clk_auxadc: + clk_disable_unprepare(mt->clk_peri_therm); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.4.6 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-05 12:25 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer @ 2015-08-05 18:02 ` Daniel Kurtz 2015-08-06 8:10 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Daniel Kurtz @ 2015-08-05 18:02 UTC (permalink / raw) To: Sascha Hauer Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Sasha Hauer, Matthias Brugger On Wed, Aug 5, 2015 at 8:25 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 581 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 590 insertions(+) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..0f859b9 > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,581 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/interrupt.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/thermal.h> > +#include <linux/reset.h> > +#include <linux/time.h> > +#include <linux/types.h> > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) BIT(x) > + > +#define APMIXED_SYS_TS_CON1 0x604 > + > +/* Thermal Controller Registers */ > +#define TEMP_MONCTL0 0x000 > +#define TEMP_MONCTL1 0x004 > +#define TEMP_MONCTL2 0x008 > +#define TEMP_MONINT 0x00c > +#define TEMP_MONINTSTS 0x010 > +#define TEMP_MONIDET0 0x014 > +#define TEMP_MONIDET1 0x018 > +#define TEMP_MONIDET2 0x01c > +#define TEMP_H2NTHRE 0x024 > +#define TEMP_HTHRE 0x028 > +#define TEMP_CTHRE 0x02c > +#define TEMP_OFFSETH 0x030 > +#define TEMP_OFFSETL 0x034 > +#define TEMP_MSRCTL0 0x038 > +#define TEMP_MSRCTL1 0x03c > +#define TEMP_AHBPOLL 0x040 > +#define TEMP_AHBTO 0x044 > +#define TEMP_ADCPNP0 0x048 > +#define TEMP_ADCPNP1 0x04c > +#define TEMP_ADCPNP2 0x050 > +#define TEMP_ADCPNP3 0x0b4 > + > +#define TEMP_ADCMUX 0x054 > +#define TEMP_ADCEXT 0x058 > +#define TEMP_ADCEXT1 0x05c > +#define TEMP_ADCEN 0x060 > +#define TEMP_PNPMUXADDR 0x064 > +#define TEMP_ADCMUXADDR 0x068 > +#define TEMP_ADCEXTADDR 0x06c > +#define TEMP_ADCEXT1ADDR 0x070 > +#define TEMP_ADCENADDR 0x074 > +#define TEMP_ADCVALIDADDR 0x078 > +#define TEMP_ADCVOLTADDR 0x07c > +#define TEMP_RDCTRL 0x080 > +#define TEMP_ADCVALIDMASK 0x084 > +#define TEMP_ADCVOLTAGESHIFT 0x088 > +#define TEMP_ADCWRITECTRL 0x08c > +#define TEMP_MSR0 0x090 > +#define TEMP_MSR1 0x094 > +#define TEMP_MSR2 0x098 > +#define TEMP_MSR3 0x0B8 > + > +#define TEMP_IMMD0 0x0a0 > +#define TEMP_IMMD1 0x0a4 > +#define TEMP_IMMD2 0x0a8 > + > +#define TEMP_PROTCTL 0x0c0 > +#define TEMP_PROTTA 0x0c4 > +#define TEMP_PROTTB 0x0c8 > +#define TEMP_PROTTC 0x0cc > + > +#define TEMP_SPARE0 0x0f0 > +#define TEMP_SPARE1 0x0f4 > +#define TEMP_SPARE2 0x0f8 > +#define TEMP_SPARE3 0x0fc > + > +#define PTPCORESEL 0x400 > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > + > +#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) > + > +#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff)) << 16 > +#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) > + > +#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) > + > +#define TEMP_MONINT_COLD(sp) (BIT(0) << ((sp) * 5)) > +#define TEMP_MONINT_HOT(sp) (BIT(1) << ((sp) * 5)) > +#define TEMP_MONINT_LOW_OFS(sp) (BIT(2) << ((sp) * 5)) > +#define TEMP_MONINT_HIGH_OFS(sp) (BIT(3) << ((sp) * 5)) > +#define TEMP_MONINT_HOT_TO_NORM(sp) (BIT(4) << ((sp) * 5)) > +#define TEMP_MONINT_TIMEOUT BIT(15) > +#define TEMP_MONINT_IMMEDIATE_SENSE(sp) BIT(16 + (sp)) > +#define TEMP_MONINT_FILTER_SENSE(sp) BIT(19 + (sp)) > + > +#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) > +#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA_WRITE BIT(2) > +#define TEMP_ADCWRITECTRL_ADC_EXTRA1_WRITE BIT(3) > + > +#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) > +#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define TEMP_PROTCTL_AVERAGE (0 << 16) > +#define TEMP_PROTCTL_MAXIMUM (1 << 16) > +#define TEMP_PROTCTL_SELECTED (2 << 16) > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_BANKS 4 I think there is a 1:1 between "banks" and thermal_zones, so, perhaps let's simplify things, and just use: #define MT8173_NUM_ZONES 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSING_POINTS 4 The use of "sensor" and "sensing_point" is a bit confusing. So, perhaps: #define MT8173_NUM_SENSOR_PER_ZONE 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tz; A better name for this field is "tzd" - that is what is used in drivers/thermal/of-thermal.c. > + int id; nit: we don't need both *mt and id, since "id" here is always just the index into the mtk_thermal->banks[] array, given either mt or id and our bank pointer, we can derive the other. I think something like this would work: static inline struct mtk_thermal *to_mtk_thermal(struct mtk_thermal_bank* bank) { struct mtk_thermal_bank *banks = bank - bank->id; return container_of(banks, struct mtk_thermal_bank, banks); } or: static inline int mtk_thermal_bank_id(struct mtk_thermal_bank* bank) { return bank - bank->mt->banks; } > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; > + > + struct mutex lock; > + > + /* Calibration values */ > + int calib_a; > + int calib_b; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int num_sensors; > + unsigned int sensors[MT8173_NUM_SENSING_POINTS]; > +}; > + > +static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static const struct mtk_thermal_bank_cfg bank_data[] = { > + { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .num_sensors = 2, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .num_sensors = 3, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .num_sensors = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +struct mtk_thermal_sense_point { > + int msr; > + int adcpnp; > +}; > + > +static const struct mtk_thermal_sense_point > + sensing_points[MT8173_NUM_SENSING_POINTS] = { This is a bit confusing - perhaps add a comment that this array contains register offsets for accessing the 4 sensors in a zone. > + { > + .msr = TEMP_MSR0, > + .adcpnp = TEMP_ADCPNP0, > + }, { > + .msr = TEMP_MSR1, > + .adcpnp = TEMP_ADCPNP1, > + }, { > + .msr = TEMP_MSR2, > + .adcpnp = TEMP_ADCPNP2, > + }, { > + .msr = TEMP_MSR3, > + .adcpnp = TEMP_ADCPNP3, > + }, > +}; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + return mt->calib_b + mt->calib_a * (raw & 0xfff); > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = INT_MIN; > + > + for (i = 0; i < bank_data[bank->id].num_sensors; i++) { > + raw = readl(mt->thermal_base + sensing_points[i].msr); > + > + temp = raw_to_mcelsius(mt, raw); > + > + /* > + * The first read of a sensor often contains very high bogus > + * temperature value. Filter these out so that the system does > + * not immediately shut down. > + */ > + if (temp > 200000) > + temp = 0; > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > + u32 apmixed_phys_base, u32 auxadc_phys_base) > +{ > + struct mtk_thermal_bank *bank = &mt->banks[num]; > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > + int i; > + > + bank->id = num; > + bank->mt = mt; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > + The only things that look zone specific here are the following: mtk_thermal_get_bank(bank); for (i = 0; i < cfg->num_sensors; i++) writel(sensor_mux_values[cfg->sensors[i]], mt->thermal_base + sensing_points[i].adcpnp); writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); mtk_thermal_put_bank(bank); The rest is just rewriting the same constants to the same fixed register addresses. But maybe that get/put zone thing does some magic shadow register selecting? > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | > + TEMP_MONCTL2_SENSOR_INTERVAL(429), > + mt->thermal_base + TEMP_MONCTL2); > + > + /* poll is set to 10u */ > + writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), > + mt->thermal_base + TEMP_AHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMP_MSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMP_MONIDET0); > + writel(0x0, mt->thermal_base + TEMP_MONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) > + * automatically by hw > + */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(auxadc_phys_base + 0x00c, mt->thermal_base + TEMP_ADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, > + mt->thermal_base + TEMP_PNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMP_ADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMP_ADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMP_RDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMP_ADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + for (i = 0; i < cfg->num_sensors; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + sensing_points[i].adcpnp); > + > + writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > + > + writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMP_ADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + u64 auxadc_phys_base, apmixed_phys_base; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + auxadc_phys_base = of_get_phys_base(auxadc); > + if (auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + ret = device_reset(&pdev->dev); > + if (ret) > + return ret; goto err_disable_clk_auxadc; > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->calib_a = -123; > + mt->calib_b = 465124; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); Hmm.. the 'i' passed here to thermal_zone_of_sensor_register is the id that a .dts thermal-zone will use to select one of the sensors provided by our "mediatek,mt8173-thermal" compatible thermal node. So, I think it is really ABI and should be some label defined in a header file as part of the of binding for the sensor node. Each label would then be encoded somehow in mtk_thermal_bank_cfg[] (or perhaps used as the index when initializing the array, like you did for scpsys in: static const struct scp_domain_data scp_domain_data[] __initconst [MT8173_POWER_DOMAIN_VDEC] = { > + } > + > + return 0; > + > +err_disable_clk_auxadc: > + clk_disable_unprepare(mt->clk_peri_therm); This should be: clk_disable_unprepare(mt->clk_auxadc); > + > + return ret; > +} In general, it looks a lot better now, though! -Dan > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.4.6 > ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-08-05 18:02 ` Daniel Kurtz @ 2015-08-06 8:10 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-06 8:10 UTC (permalink / raw) To: Daniel Kurtz Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, linux-mediatek, Sasha Hauer, Matthias Brugger On Thu, Aug 06, 2015 at 02:02:30AM +0800, Daniel Kurtz wrote: > > > + > > +#define THERMAL_NAME "mtk-thermal" > > + > > +struct mtk_thermal; > > + > > +struct mtk_thermal_bank { > > + struct mtk_thermal *mt; > > + struct thermal_zone_device *tz; > > A better name for this field is "tzd" - that is what is used in > drivers/thermal/of-thermal.c. > > > + int id; > > nit: we don't need both *mt and id, since "id" here is always just the > index into the mtk_thermal->banks[] array, given either mt or id and > our bank pointer, we can derive the other. > > I think something like this would work: > > static inline struct mtk_thermal *to_mtk_thermal(struct mtk_thermal_bank* bank) > { > struct mtk_thermal_bank *banks = bank - bank->id; > return container_of(banks, struct mtk_thermal_bank, banks); > } > > or: > > static inline int mtk_thermal_bank_id(struct mtk_thermal_bank* bank) > { > return bank - bank->mt->banks; > } Yes, probably both work. I don't think though that any of these makes the code clearer. > > +static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, > > + u32 apmixed_phys_base, u32 auxadc_phys_base) > > +{ > > + struct mtk_thermal_bank *bank = &mt->banks[num]; > > + const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; > > + int i; > > + > > + bank->id = num; > > + bank->mt = mt; > > + > > + mtk_thermal_get_bank(bank); > > + > > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > > + writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); > > + > > The only things that look zone specific here are the following: > > mtk_thermal_get_bank(bank); > for (i = 0; i < cfg->num_sensors; i++) > writel(sensor_mux_values[cfg->sensors[i]], mt->thermal_base + > sensing_points[i].adcpnp); > writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); > mtk_thermal_put_bank(bank); > > The rest is just rewriting the same constants to the same fixed > register addresses. > > But maybe that get/put zone thing does some magic shadow register selecting? Yes. The comment above mtk_thermal_get_bank() explains that. > > + > > + ret = clk_prepare_enable(mt->clk_peri_therm); > > + if (ret) { > > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > > + goto err_disable_clk_auxadc; > > + } > > + > > + /* > > + * These calibration values should finally be provided by the > > + * firmware or fuses. For now use default values. > > + */ > > + mt->calib_a = -123; > > + mt->calib_b = 465124; > > + > > + for (i = 0; i < MT8173_NUM_BANKS; i++) > > + mtk_thermal_init_bank(mt, i, apmixed_phys_base, auxadc_phys_base); > > + > > + platform_set_drvdata(pdev, mt); > > + > > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > > + struct mtk_thermal_bank *bank = &mt->banks[i]; > > + > > + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > > + &mtk_thermal_ops); > > Hmm.. the 'i' passed here to thermal_zone_of_sensor_register is the > id that a .dts thermal-zone will use to select one of the sensors > provided by our "mediatek,mt8173-thermal" compatible thermal node. > So, I think it is really ABI and should be some label defined in a > header file as part of the of binding for the sensor node. Each label > would then be encoded somehow in mtk_thermal_bank_cfg[] (or perhaps > used as the index when initializing the array, like you did for scpsys > in Makes sense. I'll add that for the next version. Thanks for reviewing, Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH v2] Add Mediatek thermal support @ 2015-07-21 7:59 Sascha Hauer 2015-07-21 7:59 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-07-21 7:59 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. Changes since v1: - Use "mediatek," prefix for custom properties - Drop "thermal: consistently use int for temperatures" dependency Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ---------------------------------------------------------------- Sascha Hauer (3): dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: Add Mediatek thermal controller support ARM64: dts: mt8173: Add thermal/auxadc device nodes .../bindings/thermal/mediatek-thermal.txt | 38 ++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 + drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ 5 files changed, 667 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt create mode 100644 drivers/thermal/mtk_thermal.c ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-07-21 7:59 [PATCH v2] Add Mediatek thermal support Sascha Hauer @ 2015-07-21 7:59 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-07-21 7:59 UTC (permalink / raw) To: linux-pm, Zhang Rui, Eduardo Valentin Cc: linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- .../bindings/thermal/mediatek-thermal.txt | 8 +- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ 4 files changed, 615 insertions(+), 4 deletions(-) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index d90e4dc..c425a0f 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -18,8 +18,8 @@ Required properties: - resets, reset-names: Reference to the reset controller controlling the thermal controller. Required reset-names: "therm": The main reset line -- auxadc: A phandle to the AUXADC which the thermal controller uses -- apmixedsys: A phandle to the APMIXEDSYS controller. +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description Example: @@ -33,6 +33,6 @@ Example: clock-names = "therm", "auxadc"; resets = <&pericfg MT8173_PERI_THERM_SW_RST>; reset-names = "therm"; - auxadc = <&auxadc>; - apmixedsys = <&apmixedsys>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; }; diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..2f177b5 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/dmi.h> +#include <linux/thermal.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/interrupt.h> +#include <linux/reset.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) + +/* Thermal Controller Registers */ +#define TEMPMONCTL0 0x000 +#define TEMPMONCTL1 0x004 +#define TEMPMONCTL2 0x008 +#define TEMPMONINT 0x00c +#define TEMPMONINTSTS 0x010 +#define TEMPMONIDET0 0x014 +#define TEMPMONIDET1 0x018 +#define TEMPMONIDET2 0x01c +#define TEMPH2NTHRE 0x024 +#define TEMPHTHRE 0x028 +#define TEMPCTHRE 0x02c +#define TEMPOFFSETH 0x030 +#define TEMPOFFSETL 0x034 +#define TEMPMSRCTL0 0x038 +#define TEMPMSRCTL1 0x03c +#define TEMPAHBPOLL 0x040 +#define TEMPAHBTO 0x044 +#define TEMPADCPNP0 0x048 +#define TEMPADCPNP1 0x04c +#define TEMPADCPNP2 0x050 +#define TEMPADCPNP3 0x0b4 + +#define TEMPADCMUX 0x054 +#define TEMPADCEXT 0x058 +#define TEMPADCEXT1 0x05c +#define TEMPADCEN 0x060 +#define TEMPPNPMUXADDR 0x064 +#define TEMPADCMUXADDR 0x068 +#define TEMPADCEXTADDR 0x06c +#define TEMPADCEXT1ADDR 0x070 +#define TEMPADCENADDR 0x074 +#define TEMPADCVALIDADDR 0x078 +#define TEMPADCVOLTADDR 0x07c +#define TEMPRDCTRL 0x080 +#define TEMPADCVALIDMASK 0x084 +#define TEMPADCVOLTAGESHIFT 0x088 +#define TEMPADCWRITECTRL 0x08c +#define TEMPMSR0 0x090 +#define TEMPMSR1 0x094 +#define TEMPMSR2 0x098 +#define TEMPMSR3 0x0B8 + +#define TEMPIMMD0 0x0a0 +#define TEMPIMMD1 0x0a4 +#define TEMPIMMD2 0x0a8 + +#define TEMPPROTCTL 0x0c0 +#define TEMPPROTTA 0x0c4 +#define TEMPPROTTB 0x0c8 +#define TEMPPROTTC 0x0cc + +#define TEMPSPARE0 0x0f0 +#define TEMPSPARE1 0x0f4 +#define TEMPSPARE2 0x0f8 +#define TEMPSPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) +#define TEMPMONINT_TIMEOUT (1 << 15) +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) + +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) + +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMPPROTCTL_AVERAGE (0 << 16) +#define TEMPPROTCTL_MAXIMUM (1 << 16) +#define TEMPPROTCTL_SELECTED (2 << 16) + +#define MT8173_THERMAL_ZONE_CA57 0 +#define MT8173_THERMAL_ZONE_CA53 1 +#define MT8173_THERMAL_ZONE_GPU 2 +#define MT8173_THERMAL_ZONE_CORE 3 + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_BANKS 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSING_POINTS 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tz; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + void __iomem *auxadc_base; + + u64 auxadc_phys_base; + u64 apmixed_phys_base; + struct reset_control *reset; + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 adc_oe; + s32 degc_cali; + s32 o_slope; + s32 vts; +}; + +struct mtk_thermal_bank_cfg { + unsigned int enable_mask; + unsigned int sensors[4]; +}; + +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static struct mtk_thermal_bank_cfg bank_data[] = { + { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .enable_mask = 7, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .enable_mask = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 +}; + +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + s32 format_1, format_2, format_3, format_4; + s32 xtoomt; + s32 gain; + + raw &= 0xfff; + + gain = (10000 + mt->adc_ge); + + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / + gain; + + format_1 = ((mt->degc_cali * 10) >> 1); + format_2 = (raw - mt->adc_oe); + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; + format_3 = format_3 * 15 / 18; + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); + format_4 = format_4 - (format_4 << 1); + + return (format_1 + format_4) * 100; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = -INT_MAX; + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { + int sensno; + + if (!(bank_data[bank->id].enable_mask & (1 << i))) + continue; + + raw = readl(mt->thermal_base + tempmsr_ofs[i]); + + sensno = bank_data[bank->id].sensors[i]; + temp = raw_to_mcelsius(mt, raw); + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + /* + * The first read of a sensor often contains very high bogus temperature + * value. Filter these out so that the system does not immediately shut + * down. + */ + if (*temp > 200000) + *temp = 0; + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; + int i; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); + + /* poll is set to 10u */ + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMPMONIDET0); + writel(0x0, mt->thermal_base + TEMPMONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) + * automatically by hw + */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); + + /* AHB address for auxadc mux selection */ + writel(mt->auxadc_phys_base + 0x00c, + mt->thermal_base + TEMPADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(mt->apmixed_phys_base + 0x0604, + mt->thermal_base + TEMPPNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMPADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMPRDCTRL); + + /* indicate where the valid bit is */ + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMPADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + tempadcpnp_ofs[i]); + + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); + + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); + if (IS_ERR(mt->reset)) { + ret = PTR_ERR(mt->reset); + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); + return ret; + } + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + mt->auxadc_phys_base = of_get_phys_base(auxadc); + if (mt->auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); + if (mt->apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + reset_control_reset(mt->reset); + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_enable_clk; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->adc_ge = ((512 - 512) * 10000) / 4096; + mt->adc_oe = 512 - 512; + mt->degc_cali = 40; + mt->o_slope = 0; + mt->vts = 260; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->id = i; + bank->mt = mt; + mtk_thermal_init_bank(&mt->banks[i]); + } + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_enable_clk: + clk_disable_unprepare(mt->clk_peri_therm); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + if (!IS_ERR(bank)) + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.1.4 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-07-21 7:59 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-07-21 7:59 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- .../bindings/thermal/mediatek-thermal.txt | 8 +- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ 4 files changed, 615 insertions(+), 4 deletions(-) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index d90e4dc..c425a0f 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -18,8 +18,8 @@ Required properties: - resets, reset-names: Reference to the reset controller controlling the thermal controller. Required reset-names: "therm": The main reset line -- auxadc: A phandle to the AUXADC which the thermal controller uses -- apmixedsys: A phandle to the APMIXEDSYS controller. +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description Example: @@ -33,6 +33,6 @@ Example: clock-names = "therm", "auxadc"; resets = <&pericfg MT8173_PERI_THERM_SW_RST>; reset-names = "therm"; - auxadc = <&auxadc>; - apmixedsys = <&apmixedsys>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; }; diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..2f177b5 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/dmi.h> +#include <linux/thermal.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/interrupt.h> +#include <linux/reset.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) + +/* Thermal Controller Registers */ +#define TEMPMONCTL0 0x000 +#define TEMPMONCTL1 0x004 +#define TEMPMONCTL2 0x008 +#define TEMPMONINT 0x00c +#define TEMPMONINTSTS 0x010 +#define TEMPMONIDET0 0x014 +#define TEMPMONIDET1 0x018 +#define TEMPMONIDET2 0x01c +#define TEMPH2NTHRE 0x024 +#define TEMPHTHRE 0x028 +#define TEMPCTHRE 0x02c +#define TEMPOFFSETH 0x030 +#define TEMPOFFSETL 0x034 +#define TEMPMSRCTL0 0x038 +#define TEMPMSRCTL1 0x03c +#define TEMPAHBPOLL 0x040 +#define TEMPAHBTO 0x044 +#define TEMPADCPNP0 0x048 +#define TEMPADCPNP1 0x04c +#define TEMPADCPNP2 0x050 +#define TEMPADCPNP3 0x0b4 + +#define TEMPADCMUX 0x054 +#define TEMPADCEXT 0x058 +#define TEMPADCEXT1 0x05c +#define TEMPADCEN 0x060 +#define TEMPPNPMUXADDR 0x064 +#define TEMPADCMUXADDR 0x068 +#define TEMPADCEXTADDR 0x06c +#define TEMPADCEXT1ADDR 0x070 +#define TEMPADCENADDR 0x074 +#define TEMPADCVALIDADDR 0x078 +#define TEMPADCVOLTADDR 0x07c +#define TEMPRDCTRL 0x080 +#define TEMPADCVALIDMASK 0x084 +#define TEMPADCVOLTAGESHIFT 0x088 +#define TEMPADCWRITECTRL 0x08c +#define TEMPMSR0 0x090 +#define TEMPMSR1 0x094 +#define TEMPMSR2 0x098 +#define TEMPMSR3 0x0B8 + +#define TEMPIMMD0 0x0a0 +#define TEMPIMMD1 0x0a4 +#define TEMPIMMD2 0x0a8 + +#define TEMPPROTCTL 0x0c0 +#define TEMPPROTTA 0x0c4 +#define TEMPPROTTB 0x0c8 +#define TEMPPROTTC 0x0cc + +#define TEMPSPARE0 0x0f0 +#define TEMPSPARE1 0x0f4 +#define TEMPSPARE2 0x0f8 +#define TEMPSPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) +#define TEMPMONINT_TIMEOUT (1 << 15) +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) + +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) + +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMPPROTCTL_AVERAGE (0 << 16) +#define TEMPPROTCTL_MAXIMUM (1 << 16) +#define TEMPPROTCTL_SELECTED (2 << 16) + +#define MT8173_THERMAL_ZONE_CA57 0 +#define MT8173_THERMAL_ZONE_CA53 1 +#define MT8173_THERMAL_ZONE_GPU 2 +#define MT8173_THERMAL_ZONE_CORE 3 + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_BANKS 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSING_POINTS 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tz; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + void __iomem *auxadc_base; + + u64 auxadc_phys_base; + u64 apmixed_phys_base; + struct reset_control *reset; + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 adc_oe; + s32 degc_cali; + s32 o_slope; + s32 vts; +}; + +struct mtk_thermal_bank_cfg { + unsigned int enable_mask; + unsigned int sensors[4]; +}; + +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static struct mtk_thermal_bank_cfg bank_data[] = { + { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .enable_mask = 7, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .enable_mask = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 +}; + +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + s32 format_1, format_2, format_3, format_4; + s32 xtoomt; + s32 gain; + + raw &= 0xfff; + + gain = (10000 + mt->adc_ge); + + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / + gain; + + format_1 = ((mt->degc_cali * 10) >> 1); + format_2 = (raw - mt->adc_oe); + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; + format_3 = format_3 * 15 / 18; + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); + format_4 = format_4 - (format_4 << 1); + + return (format_1 + format_4) * 100; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = -INT_MAX; + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { + int sensno; + + if (!(bank_data[bank->id].enable_mask & (1 << i))) + continue; + + raw = readl(mt->thermal_base + tempmsr_ofs[i]); + + sensno = bank_data[bank->id].sensors[i]; + temp = raw_to_mcelsius(mt, raw); + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, long *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + /* + * The first read of a sensor often contains very high bogus temperature + * value. Filter these out so that the system does not immediately shut + * down. + */ + if (*temp > 200000) + *temp = 0; + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; + int i; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); + + /* poll is set to 10u */ + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMPMONIDET0); + writel(0x0, mt->thermal_base + TEMPMONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) + * automatically by hw + */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); + + /* AHB address for auxadc mux selection */ + writel(mt->auxadc_phys_base + 0x00c, + mt->thermal_base + TEMPADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(mt->apmixed_phys_base + 0x0604, + mt->thermal_base + TEMPPNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMPADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMPRDCTRL); + + /* indicate where the valid bit is */ + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMPADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + tempadcpnp_ofs[i]); + + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); + + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); + if (IS_ERR(mt->reset)) { + ret = PTR_ERR(mt->reset); + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); + return ret; + } + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + mt->auxadc_phys_base = of_get_phys_base(auxadc); + if (mt->auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); + if (mt->apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + reset_control_reset(mt->reset); + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_enable_clk; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->adc_ge = ((512 - 512) * 10000) / 4096; + mt->adc_oe = 512 - 512; + mt->degc_cali = 40; + mt->o_slope = 0; + mt->vts = 260; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->id = i; + bank->mt = mt; + mtk_thermal_init_bank(&mt->banks[i]); + } + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_enable_clk: + clk_disable_unprepare(mt->clk_peri_therm); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + if (!IS_ERR(bank)) + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.1.4 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-07-21 7:59 ` Sascha Hauer (?) @ 2015-07-21 15:13 ` Daniel Kurtz -1 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-07-21 15:13 UTC (permalink / raw) To: Sascha Hauer, Hanyi.Wu Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger Hi Sascha, Review comments inline... On Tue, Jul 21, 2015 at 3:59 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../bindings/thermal/mediatek-thermal.txt | 8 +- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ > 4 files changed, 615 insertions(+), 4 deletions(-) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > index d90e4dc..c425a0f 100644 > --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > @@ -18,8 +18,8 @@ Required properties: > - resets, reset-names: Reference to the reset controller controlling the thermal > controller. Required reset-names: > "therm": The main reset line > -- auxadc: A phandle to the AUXADC which the thermal controller uses > -- apmixedsys: A phandle to the APMIXEDSYS controller. > +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses > +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. > - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description I think you meant to squash these Documentation hunks into patch 1. > > Example: > @@ -33,6 +33,6 @@ Example: > clock-names = "therm", "auxadc"; > resets = <&pericfg MT8173_PERI_THERM_SW_RST>; > reset-names = "therm"; > - auxadc = <&auxadc>; > - apmixedsys = <&apmixedsys>; > + mediatek,auxadc = <&auxadc>; > + mediatek,apmixedsys = <&apmixedsys>; > }; > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..2f177b5 > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,602 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> Should this patch be SOB by Hanyi.Wu <hanyi.wu@mediatek.com> ? > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/dmi.h> > +#include <linux/thermal.h> > +#include <linux/platform_device.h> > +#include <linux/types.h> > +#include <linux/delay.h> > +#include <linux/slab.h> > +#include <linux/clk.h> > +#include <linux/time.h> > +#include <linux/of.h> > +#include <linux/of_irq.h> > +#include <linux/of_address.h> > +#include <linux/interrupt.h> > +#include <linux/reset.h> nit: some folks like to see #includes alphabetized. > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) Or just use BIT() ? > + > +/* Thermal Controller Registers */ > +#define TEMPMONCTL0 0x000 nit: "TEMP_" might makes these register names a bit more readable. > +#define TEMPMONCTL1 0x004 > +#define TEMPMONCTL2 0x008 > +#define TEMPMONINT 0x00c > +#define TEMPMONINTSTS 0x010 > +#define TEMPMONIDET0 0x014 > +#define TEMPMONIDET1 0x018 > +#define TEMPMONIDET2 0x01c > +#define TEMPH2NTHRE 0x024 > +#define TEMPHTHRE 0x028 > +#define TEMPCTHRE 0x02c > +#define TEMPOFFSETH 0x030 > +#define TEMPOFFSETL 0x034 > +#define TEMPMSRCTL0 0x038 > +#define TEMPMSRCTL1 0x03c > +#define TEMPAHBPOLL 0x040 > +#define TEMPAHBTO 0x044 > +#define TEMPADCPNP0 0x048 > +#define TEMPADCPNP1 0x04c > +#define TEMPADCPNP2 0x050 > +#define TEMPADCPNP3 0x0b4 > + > +#define TEMPADCMUX 0x054 > +#define TEMPADCEXT 0x058 > +#define TEMPADCEXT1 0x05c > +#define TEMPADCEN 0x060 > +#define TEMPPNPMUXADDR 0x064 > +#define TEMPADCMUXADDR 0x068 > +#define TEMPADCEXTADDR 0x06c > +#define TEMPADCEXT1ADDR 0x070 > +#define TEMPADCENADDR 0x074 > +#define TEMPADCVALIDADDR 0x078 > +#define TEMPADCVOLTADDR 0x07c > +#define TEMPRDCTRL 0x080 > +#define TEMPADCVALIDMASK 0x084 > +#define TEMPADCVOLTAGESHIFT 0x088 > +#define TEMPADCWRITECTRL 0x08c > +#define TEMPMSR0 0x090 > +#define TEMPMSR1 0x094 > +#define TEMPMSR2 0x098 > +#define TEMPMSR3 0x0B8 > + > +#define TEMPIMMD0 0x0a0 > +#define TEMPIMMD1 0x0a4 > +#define TEMPIMMD2 0x0a8 > + > +#define TEMPPROTCTL 0x0c0 > +#define TEMPPROTTA 0x0c4 > +#define TEMPPROTTB 0x0c8 > +#define TEMPPROTTC 0x0cc > + > +#define TEMPSPARE0 0x0f0 > +#define TEMPSPARE1 0x0f4 > +#define TEMPSPARE2 0x0f8 > +#define TEMPSPARE3 0x0fc > + > +#define PTPCORESEL 0x400 > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > + > +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) > +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) > +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) > +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) > +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) > +#define TEMPMONINT_TIMEOUT (1 << 15) > +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) > +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) Some clever use of BIT() could clean these up. > + > +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) > +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) > +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) > +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) BIT() > + > +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) > +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define TEMPPROTCTL_AVERAGE (0 << 16) > +#define TEMPPROTCTL_MAXIMUM (1 << 16) > +#define TEMPPROTCTL_SELECTED (2 << 16) > + > +#define MT8173_THERMAL_ZONE_CA57 0 > +#define MT8173_THERMAL_ZONE_CA53 1 > +#define MT8173_THERMAL_ZONE_GPU 2 > +#define MT8173_THERMAL_ZONE_CORE 3 These 4 MT8173_THERMAL_ZONE_* defines are not used. Do they refer to the same zones as "MT8173_TS1", etc? If so, I actually like them better, since they are more descriptive. > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_BANKS 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSING_POINTS 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tz; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + void __iomem *auxadc_base; auxadc_base is never used. > + > + u64 auxadc_phys_base; > + u64 apmixed_phys_base; > + struct reset_control *reset; these three are only used during probe->bank_init(), so don't store them in struct mtk_thermal. > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 adc_oe; > + s32 degc_cali; > + s32 o_slope; > + s32 vts; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int enable_mask; A simple sensor count would be more clear than enable_mask. > + unsigned int sensors[4]; MT8173_NUM_SENSING_POINTS perhaps? > +}; > + > +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static struct mtk_thermal_bank_cfg bank_data[] = { static const struct > + { > + .enable_mask = 3, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .enable_mask = 3, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .enable_mask = 7, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .enable_mask = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { const > + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 > +}; > + > +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { const > + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 > +}; These two arrays are tightly coupled, so perhaps it would be useful to create a struct to represent a sense point: struct mtk_thermal_sense_point { int msr; int adcpnp; }; static const struct mtk_thermal_sense_point[MT8173_NUM_SENSING_POINTS] = { { TEMP_MSR0, TEMP_ADCPNP0 }, { TEMP_MSR1, TEMP_ADCPNP1 }, { TEMP_MSR2, TEMP_ADCPNP2 }, { TEMP_MSR3, TEMP_ADCPNP3 }, }; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + s32 format_1, format_2, format_3, format_4; The formula would be easier to follow with better variable names than "format_X". > + s32 xtoomt; What does "xtoomt" mean? > + s32 gain; > + > + raw &= 0xfff; > + > + gain = (10000 + mt->adc_ge); no outer () > + > + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / > + gain; > + > + format_1 = ((mt->degc_cali * 10) >> 1); When doing computations, I think "A / 2" is preferred over "A >> 1". Also, no outer (). > + format_2 = (raw - mt->adc_oe); > + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; This is just: format_3 = ((((raw - mt->vts - 3350) * 10000) / 4096) * 10000) / gain; No wonder mt->adc_oe = 512-512 = 0... it just cancels itself out here, anyway. > + format_3 = format_3 * 15 / 18; Of course we should multiply by 15/18! What is going on here? Why this magic 5/6 ratio? > + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); no outer () > + format_4 = format_4 - (format_4 << 1); Hmm... A = X - 2*X; otherwise known as: A = -X; > + return (format_1 + format_4) * 100; Or just: return (format_1 - format_4) * 100; > + > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = -INT_MAX; nit: INT_MIN? > + > + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { If enable_mask became sensor_count, this would become: for (i = 0; i < bank_data[bank->id].sensor_count; i++) { > + int sensno; > + > + if (!(bank_data[bank->id].enable_mask & (1 << i))) > + continue; > + > + raw = readl(mt->thermal_base + tempmsr_ofs[i]); > + > + sensno = bank_data[bank->id].sensors[i]; sensno is set but not used. > + temp = raw_to_mcelsius(mt, raw); > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + /* > + * The first read of a sensor often contains very high bogus temperature > + * value. Filter these out so that the system does not immediately shut > + * down. > + */ > + if (*temp > 200000) > + *temp = 0; Why not just put this limiter in mtk_thermal_bank_temperature(), and discard bogus sense points? Since mtk_thermal_bank_temperature() returns the max of all sense points, any one bogus sense point will cause a bogus temperature. > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; > + int i; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); Please create some #defines for the register bits that are written in this function. > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); > + > + /* poll is set to 10u */ > + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMPMONIDET0); > + writel(0x0, mt->thermal_base + TEMPMONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) > + * automatically by hw > + */ > + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(mt->auxadc_phys_base + 0x00c, Is this "0x00c" : AUXADC_CON1_CLR_V ? Since auxadc_phys_base is only used during probe()->init_bank(), don't store it in mt. > + mt->thermal_base + TEMPADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(mt->apmixed_phys_base + 0x0604, What is the name of the APMIXED register with offset "0x0604"? Since apmixed_phys_base is only used during probe()->init_bank(), don't store it in mt. > + mt->thermal_base + TEMPPNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMPADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMPADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMPADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMPRDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMPADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMPADCWRITECTRL); > + > + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + tempadcpnp_ofs[i]); Not all banks use MT8173_NUM_SENSING_POINTS sensors. If enable_mask became sensor_count, this could avoid writing unnecessary registers: for (i = 0; i < cfg->sensor_count; i++) > + > + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); And computing enable_mask from sensor_count is trivial: GENMASK(cfg->sensor_count - 1, 0); > + > + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMPADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->reset)) { > + ret = PTR_ERR(mt->reset); > + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); > + return ret; > + } > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + mt->auxadc_phys_base = of_get_phys_base(auxadc); > + if (mt->auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (mt->apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + reset_control_reset(mt->reset); > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_enable_clk; I think labels are usually named by what they do, rather than what causes the goto. So, perhaps: goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->adc_ge = ((512 - 512) * 10000) / 4096; > + mt->adc_oe = 512 - 512; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + mt->vts = 260; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->id = i; > + bank->mt = mt; > + mtk_thermal_init_bank(&mt->banks[i]); I think this would work better as just: mtk_thermal_init_bank(mt, i, apmixedsys_phys_base, auxadc_phys_base); Setting "id" and "mt" out here doesn't add much value. > + } > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); > + } > + > + return 0; > + > +err_enable_clk: > + clk_disable_unprepare(mt->clk_peri_therm); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + if (!IS_ERR(bank)) How could this be true? ok... enough for now :-) Thanks, -Dan > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.1.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-07-21 15:13 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-07-21 15:13 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, Review comments inline... On Tue, Jul 21, 2015 at 3:59 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../bindings/thermal/mediatek-thermal.txt | 8 +- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ > 4 files changed, 615 insertions(+), 4 deletions(-) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > index d90e4dc..c425a0f 100644 > --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > @@ -18,8 +18,8 @@ Required properties: > - resets, reset-names: Reference to the reset controller controlling the thermal > controller. Required reset-names: > "therm": The main reset line > -- auxadc: A phandle to the AUXADC which the thermal controller uses > -- apmixedsys: A phandle to the APMIXEDSYS controller. > +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses > +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. > - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description I think you meant to squash these Documentation hunks into patch 1. > > Example: > @@ -33,6 +33,6 @@ Example: > clock-names = "therm", "auxadc"; > resets = <&pericfg MT8173_PERI_THERM_SW_RST>; > reset-names = "therm"; > - auxadc = <&auxadc>; > - apmixedsys = <&apmixedsys>; > + mediatek,auxadc = <&auxadc>; > + mediatek,apmixedsys = <&apmixedsys>; > }; > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..2f177b5 > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,602 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> Should this patch be SOB by Hanyi.Wu <hanyi.wu@mediatek.com> ? > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/dmi.h> > +#include <linux/thermal.h> > +#include <linux/platform_device.h> > +#include <linux/types.h> > +#include <linux/delay.h> > +#include <linux/slab.h> > +#include <linux/clk.h> > +#include <linux/time.h> > +#include <linux/of.h> > +#include <linux/of_irq.h> > +#include <linux/of_address.h> > +#include <linux/interrupt.h> > +#include <linux/reset.h> nit: some folks like to see #includes alphabetized. > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) Or just use BIT() ? > + > +/* Thermal Controller Registers */ > +#define TEMPMONCTL0 0x000 nit: "TEMP_" might makes these register names a bit more readable. > +#define TEMPMONCTL1 0x004 > +#define TEMPMONCTL2 0x008 > +#define TEMPMONINT 0x00c > +#define TEMPMONINTSTS 0x010 > +#define TEMPMONIDET0 0x014 > +#define TEMPMONIDET1 0x018 > +#define TEMPMONIDET2 0x01c > +#define TEMPH2NTHRE 0x024 > +#define TEMPHTHRE 0x028 > +#define TEMPCTHRE 0x02c > +#define TEMPOFFSETH 0x030 > +#define TEMPOFFSETL 0x034 > +#define TEMPMSRCTL0 0x038 > +#define TEMPMSRCTL1 0x03c > +#define TEMPAHBPOLL 0x040 > +#define TEMPAHBTO 0x044 > +#define TEMPADCPNP0 0x048 > +#define TEMPADCPNP1 0x04c > +#define TEMPADCPNP2 0x050 > +#define TEMPADCPNP3 0x0b4 > + > +#define TEMPADCMUX 0x054 > +#define TEMPADCEXT 0x058 > +#define TEMPADCEXT1 0x05c > +#define TEMPADCEN 0x060 > +#define TEMPPNPMUXADDR 0x064 > +#define TEMPADCMUXADDR 0x068 > +#define TEMPADCEXTADDR 0x06c > +#define TEMPADCEXT1ADDR 0x070 > +#define TEMPADCENADDR 0x074 > +#define TEMPADCVALIDADDR 0x078 > +#define TEMPADCVOLTADDR 0x07c > +#define TEMPRDCTRL 0x080 > +#define TEMPADCVALIDMASK 0x084 > +#define TEMPADCVOLTAGESHIFT 0x088 > +#define TEMPADCWRITECTRL 0x08c > +#define TEMPMSR0 0x090 > +#define TEMPMSR1 0x094 > +#define TEMPMSR2 0x098 > +#define TEMPMSR3 0x0B8 > + > +#define TEMPIMMD0 0x0a0 > +#define TEMPIMMD1 0x0a4 > +#define TEMPIMMD2 0x0a8 > + > +#define TEMPPROTCTL 0x0c0 > +#define TEMPPROTTA 0x0c4 > +#define TEMPPROTTB 0x0c8 > +#define TEMPPROTTC 0x0cc > + > +#define TEMPSPARE0 0x0f0 > +#define TEMPSPARE1 0x0f4 > +#define TEMPSPARE2 0x0f8 > +#define TEMPSPARE3 0x0fc > + > +#define PTPCORESEL 0x400 > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > + > +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) > +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) > +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) > +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) > +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) > +#define TEMPMONINT_TIMEOUT (1 << 15) > +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) > +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) Some clever use of BIT() could clean these up. > + > +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) > +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) > +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) > +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) BIT() > + > +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) > +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define TEMPPROTCTL_AVERAGE (0 << 16) > +#define TEMPPROTCTL_MAXIMUM (1 << 16) > +#define TEMPPROTCTL_SELECTED (2 << 16) > + > +#define MT8173_THERMAL_ZONE_CA57 0 > +#define MT8173_THERMAL_ZONE_CA53 1 > +#define MT8173_THERMAL_ZONE_GPU 2 > +#define MT8173_THERMAL_ZONE_CORE 3 These 4 MT8173_THERMAL_ZONE_* defines are not used. Do they refer to the same zones as "MT8173_TS1", etc? If so, I actually like them better, since they are more descriptive. > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_BANKS 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSING_POINTS 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tz; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + void __iomem *auxadc_base; auxadc_base is never used. > + > + u64 auxadc_phys_base; > + u64 apmixed_phys_base; > + struct reset_control *reset; these three are only used during probe->bank_init(), so don't store them in struct mtk_thermal. > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 adc_oe; > + s32 degc_cali; > + s32 o_slope; > + s32 vts; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int enable_mask; A simple sensor count would be more clear than enable_mask. > + unsigned int sensors[4]; MT8173_NUM_SENSING_POINTS perhaps? > +}; > + > +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static struct mtk_thermal_bank_cfg bank_data[] = { static const struct > + { > + .enable_mask = 3, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .enable_mask = 3, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .enable_mask = 7, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .enable_mask = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { const > + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 > +}; > + > +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { const > + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 > +}; These two arrays are tightly coupled, so perhaps it would be useful to create a struct to represent a sense point: struct mtk_thermal_sense_point { int msr; int adcpnp; }; static const struct mtk_thermal_sense_point[MT8173_NUM_SENSING_POINTS] = { { TEMP_MSR0, TEMP_ADCPNP0 }, { TEMP_MSR1, TEMP_ADCPNP1 }, { TEMP_MSR2, TEMP_ADCPNP2 }, { TEMP_MSR3, TEMP_ADCPNP3 }, }; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + s32 format_1, format_2, format_3, format_4; The formula would be easier to follow with better variable names than "format_X". > + s32 xtoomt; What does "xtoomt" mean? > + s32 gain; > + > + raw &= 0xfff; > + > + gain = (10000 + mt->adc_ge); no outer () > + > + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / > + gain; > + > + format_1 = ((mt->degc_cali * 10) >> 1); When doing computations, I think "A / 2" is preferred over "A >> 1". Also, no outer (). > + format_2 = (raw - mt->adc_oe); > + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; This is just: format_3 = ((((raw - mt->vts - 3350) * 10000) / 4096) * 10000) / gain; No wonder mt->adc_oe = 512-512 = 0... it just cancels itself out here, anyway. > + format_3 = format_3 * 15 / 18; Of course we should multiply by 15/18! What is going on here? Why this magic 5/6 ratio? > + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); no outer () > + format_4 = format_4 - (format_4 << 1); Hmm... A = X - 2*X; otherwise known as: A = -X; > + return (format_1 + format_4) * 100; Or just: return (format_1 - format_4) * 100; > + > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = -INT_MAX; nit: INT_MIN? > + > + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { If enable_mask became sensor_count, this would become: for (i = 0; i < bank_data[bank->id].sensor_count; i++) { > + int sensno; > + > + if (!(bank_data[bank->id].enable_mask & (1 << i))) > + continue; > + > + raw = readl(mt->thermal_base + tempmsr_ofs[i]); > + > + sensno = bank_data[bank->id].sensors[i]; sensno is set but not used. > + temp = raw_to_mcelsius(mt, raw); > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + /* > + * The first read of a sensor often contains very high bogus temperature > + * value. Filter these out so that the system does not immediately shut > + * down. > + */ > + if (*temp > 200000) > + *temp = 0; Why not just put this limiter in mtk_thermal_bank_temperature(), and discard bogus sense points? Since mtk_thermal_bank_temperature() returns the max of all sense points, any one bogus sense point will cause a bogus temperature. > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; > + int i; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); Please create some #defines for the register bits that are written in this function. > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); > + > + /* poll is set to 10u */ > + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMPMONIDET0); > + writel(0x0, mt->thermal_base + TEMPMONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) > + * automatically by hw > + */ > + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(mt->auxadc_phys_base + 0x00c, Is this "0x00c" : AUXADC_CON1_CLR_V ? Since auxadc_phys_base is only used during probe()->init_bank(), don't store it in mt. > + mt->thermal_base + TEMPADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(mt->apmixed_phys_base + 0x0604, What is the name of the APMIXED register with offset "0x0604"? Since apmixed_phys_base is only used during probe()->init_bank(), don't store it in mt. > + mt->thermal_base + TEMPPNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMPADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMPADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMPADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMPRDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMPADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMPADCWRITECTRL); > + > + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + tempadcpnp_ofs[i]); Not all banks use MT8173_NUM_SENSING_POINTS sensors. If enable_mask became sensor_count, this could avoid writing unnecessary registers: for (i = 0; i < cfg->sensor_count; i++) > + > + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); And computing enable_mask from sensor_count is trivial: GENMASK(cfg->sensor_count - 1, 0); > + > + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMPADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->reset)) { > + ret = PTR_ERR(mt->reset); > + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); > + return ret; > + } > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + mt->auxadc_phys_base = of_get_phys_base(auxadc); > + if (mt->auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (mt->apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + reset_control_reset(mt->reset); > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_enable_clk; I think labels are usually named by what they do, rather than what causes the goto. So, perhaps: goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->adc_ge = ((512 - 512) * 10000) / 4096; > + mt->adc_oe = 512 - 512; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + mt->vts = 260; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->id = i; > + bank->mt = mt; > + mtk_thermal_init_bank(&mt->banks[i]); I think this would work better as just: mtk_thermal_init_bank(mt, i, apmixedsys_phys_base, auxadc_phys_base); Setting "id" and "mt" out here doesn't add much value. > + } > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); > + } > + > + return 0; > + > +err_enable_clk: > + clk_disable_unprepare(mt->clk_peri_therm); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + if (!IS_ERR(bank)) How could this be true? ok... enough for now :-) Thanks, -Dan > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.1.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-07-21 15:13 ` Daniel Kurtz 0 siblings, 0 replies; 139+ messages in thread From: Daniel Kurtz @ 2015-07-21 15:13 UTC (permalink / raw) To: Sascha Hauer, Hanyi.Wu Cc: linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger Hi Sascha, Review comments inline... On Tue, Jul 21, 2015 at 3:59 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote: > This adds support for the Mediatek thermal controller found on MT8173 > and likely other SoCs. > The controller is a bit special. It does not have its own ADC, instead > it controls the on-SoC AUXADC via AHB bus accesses. For this reason > we need the physical address of the AUXADC. Also it controls a mux > using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../bindings/thermal/mediatek-thermal.txt | 8 +- > drivers/thermal/Kconfig | 8 + > drivers/thermal/Makefile | 1 + > drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ > 4 files changed, 615 insertions(+), 4 deletions(-) > create mode 100644 drivers/thermal/mtk_thermal.c > > diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > index d90e4dc..c425a0f 100644 > --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt > @@ -18,8 +18,8 @@ Required properties: > - resets, reset-names: Reference to the reset controller controlling the thermal > controller. Required reset-names: > "therm": The main reset line > -- auxadc: A phandle to the AUXADC which the thermal controller uses > -- apmixedsys: A phandle to the APMIXEDSYS controller. > +- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses > +- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. > - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description I think you meant to squash these Documentation hunks into patch 1. > > Example: > @@ -33,6 +33,6 @@ Example: > clock-names = "therm", "auxadc"; > resets = <&pericfg MT8173_PERI_THERM_SW_RST>; > reset-names = "therm"; > - auxadc = <&auxadc>; > - apmixedsys = <&apmixedsys>; > + mediatek,auxadc = <&auxadc>; > + mediatek,apmixedsys = <&apmixedsys>; > }; > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig > index 118938e..07ad114 100644 > --- a/drivers/thermal/Kconfig > +++ b/drivers/thermal/Kconfig > @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL > tristate > depends on ACPI > > +config MTK_THERMAL > + tristate "Temperature sensor driver for mediatek SoCs" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + default y > + help > + Enable this option if you want to have support for thermal management > + controller present in Mediatek SoCs > + > menu "Texas Instruments thermal drivers" > source "drivers/thermal/ti-soc-thermal/Kconfig" > endmenu > diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile > index 535dfee..cc1cab3 100644 > --- a/drivers/thermal/Makefile > +++ b/drivers/thermal/Makefile > @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ > obj-$(CONFIG_ST_THERMAL) += st/ > obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o > obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o > +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o > diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c > new file mode 100644 > index 0000000..2f177b5 > --- /dev/null > +++ b/drivers/thermal/mtk_thermal.c > @@ -0,0 +1,602 @@ > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> Should this patch be SOB by Hanyi.Wu <hanyi.wu@mediatek.com> ? > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/dmi.h> > +#include <linux/thermal.h> > +#include <linux/platform_device.h> > +#include <linux/types.h> > +#include <linux/delay.h> > +#include <linux/slab.h> > +#include <linux/clk.h> > +#include <linux/time.h> > +#include <linux/of.h> > +#include <linux/of_irq.h> > +#include <linux/of_address.h> > +#include <linux/interrupt.h> > +#include <linux/reset.h> nit: some folks like to see #includes alphabetized. > + > +/* AUXADC Registers */ > +#define AUXADC_CON0_V 0x000 > +#define AUXADC_CON1_V 0x004 > +#define AUXADC_CON1_SET_V 0x008 > +#define AUXADC_CON1_CLR_V 0x00c > +#define AUXADC_CON2_V 0x010 > +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) > +#define AUXADC_MISC_V 0x094 > + > +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) Or just use BIT() ? > + > +/* Thermal Controller Registers */ > +#define TEMPMONCTL0 0x000 nit: "TEMP_" might makes these register names a bit more readable. > +#define TEMPMONCTL1 0x004 > +#define TEMPMONCTL2 0x008 > +#define TEMPMONINT 0x00c > +#define TEMPMONINTSTS 0x010 > +#define TEMPMONIDET0 0x014 > +#define TEMPMONIDET1 0x018 > +#define TEMPMONIDET2 0x01c > +#define TEMPH2NTHRE 0x024 > +#define TEMPHTHRE 0x028 > +#define TEMPCTHRE 0x02c > +#define TEMPOFFSETH 0x030 > +#define TEMPOFFSETL 0x034 > +#define TEMPMSRCTL0 0x038 > +#define TEMPMSRCTL1 0x03c > +#define TEMPAHBPOLL 0x040 > +#define TEMPAHBTO 0x044 > +#define TEMPADCPNP0 0x048 > +#define TEMPADCPNP1 0x04c > +#define TEMPADCPNP2 0x050 > +#define TEMPADCPNP3 0x0b4 > + > +#define TEMPADCMUX 0x054 > +#define TEMPADCEXT 0x058 > +#define TEMPADCEXT1 0x05c > +#define TEMPADCEN 0x060 > +#define TEMPPNPMUXADDR 0x064 > +#define TEMPADCMUXADDR 0x068 > +#define TEMPADCEXTADDR 0x06c > +#define TEMPADCEXT1ADDR 0x070 > +#define TEMPADCENADDR 0x074 > +#define TEMPADCVALIDADDR 0x078 > +#define TEMPADCVOLTADDR 0x07c > +#define TEMPRDCTRL 0x080 > +#define TEMPADCVALIDMASK 0x084 > +#define TEMPADCVOLTAGESHIFT 0x088 > +#define TEMPADCWRITECTRL 0x08c > +#define TEMPMSR0 0x090 > +#define TEMPMSR1 0x094 > +#define TEMPMSR2 0x098 > +#define TEMPMSR3 0x0B8 > + > +#define TEMPIMMD0 0x0a0 > +#define TEMPIMMD1 0x0a4 > +#define TEMPIMMD2 0x0a8 > + > +#define TEMPPROTCTL 0x0c0 > +#define TEMPPROTTA 0x0c4 > +#define TEMPPROTTB 0x0c8 > +#define TEMPPROTTC 0x0cc > + > +#define TEMPSPARE0 0x0f0 > +#define TEMPSPARE1 0x0f4 > +#define TEMPSPARE2 0x0f8 > +#define TEMPSPARE3 0x0fc > + > +#define PTPCORESEL 0x400 > +#define THERMINTST 0x404 > +#define PTPODINTST 0x408 > +#define THSTAGE0ST 0x40c > +#define THSTAGE1ST 0x410 > +#define THSTAGE2ST 0x414 > +#define THAHBST0 0x418 > +#define THAHBST1 0x41c /* Only for DE debug */ > +#define PTPSPARE0 0x420 > +#define PTPSPARE1 0x424 > +#define PTPSPARE2 0x428 > +#define PTPSPARE3 0x42c > +#define THSLPEVEB 0x430 > + > +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) > +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) > +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) > +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) > +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) > +#define TEMPMONINT_TIMEOUT (1 << 15) > +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) > +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) Some clever use of BIT() could clean these up. > + > +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) > +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) > +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) > +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) BIT() > + > +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) > +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) > + > +#define TEMPPROTCTL_AVERAGE (0 << 16) > +#define TEMPPROTCTL_MAXIMUM (1 << 16) > +#define TEMPPROTCTL_SELECTED (2 << 16) > + > +#define MT8173_THERMAL_ZONE_CA57 0 > +#define MT8173_THERMAL_ZONE_CA53 1 > +#define MT8173_THERMAL_ZONE_GPU 2 > +#define MT8173_THERMAL_ZONE_CORE 3 These 4 MT8173_THERMAL_ZONE_* defines are not used. Do they refer to the same zones as "MT8173_TS1", etc? If so, I actually like them better, since they are more descriptive. > + > +#define MT8173_TS1 0 > +#define MT8173_TS2 1 > +#define MT8173_TS3 2 > +#define MT8173_TS4 3 > +#define MT8173_TSABB 4 > + > +/* AUXADC channel 11 is used for the temperature sensors */ > +#define MT8173_TEMP_AUXADC_CHANNEL 11 > + > +/* The total number of temperature sensors in the MT8173 */ > +#define MT8173_NUM_SENSORS 5 > + > +/* The number of banks in the MT8173 */ > +#define MT8173_NUM_BANKS 4 > + > +/* The number of sensing points per bank */ > +#define MT8173_NUM_SENSING_POINTS 4 > + > +#define THERMAL_NAME "mtk-thermal" > + > +struct mtk_thermal; > + > +struct mtk_thermal_bank { > + struct mtk_thermal *mt; > + struct thermal_zone_device *tz; > + int id; > +}; > + > +struct mtk_thermal { > + struct device *dev; > + void __iomem *thermal_base; > + void __iomem *auxadc_base; auxadc_base is never used. > + > + u64 auxadc_phys_base; > + u64 apmixed_phys_base; > + struct reset_control *reset; these three are only used during probe->bank_init(), so don't store them in struct mtk_thermal. > + struct clk *clk_peri_therm; > + struct clk *clk_auxadc; > + > + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; > + > + struct mutex lock; > + > + /* Calibration values */ > + s32 adc_ge; > + s32 adc_oe; > + s32 degc_cali; > + s32 o_slope; > + s32 vts; > +}; > + > +struct mtk_thermal_bank_cfg { > + unsigned int enable_mask; A simple sensor count would be more clear than enable_mask. > + unsigned int sensors[4]; MT8173_NUM_SENSING_POINTS perhaps? > +}; > + > +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; > + > +/* > + * The MT8173 thermal controller has four banks. Each bank can read up to > + * four temperature sensors simultaneously. The MT8173 has a total of 5 > + * temperature sensors. We use each bank to measure a certain area of the > + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple > + * areas, hence is used in different banks. > + */ > +static struct mtk_thermal_bank_cfg bank_data[] = { static const struct > + { > + .enable_mask = 3, > + .sensors = { MT8173_TS2, MT8173_TS3 }, > + }, { > + .enable_mask = 3, > + .sensors = { MT8173_TS2, MT8173_TS4 }, > + }, { > + .enable_mask = 7, > + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, > + }, { > + .enable_mask = 1, > + .sensors = { MT8173_TS2 }, > + }, > +}; > + > +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { const > + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 > +}; > + > +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { const > + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 > +}; These two arrays are tightly coupled, so perhaps it would be useful to create a struct to represent a sense point: struct mtk_thermal_sense_point { int msr; int adcpnp; }; static const struct mtk_thermal_sense_point[MT8173_NUM_SENSING_POINTS] = { { TEMP_MSR0, TEMP_ADCPNP0 }, { TEMP_MSR1, TEMP_ADCPNP1 }, { TEMP_MSR2, TEMP_ADCPNP2 }, { TEMP_MSR3, TEMP_ADCPNP3 }, }; > + > +/** > + * raw_to_mcelsius - convert a raw ADC value to mcelsius > + * @mt: The thermal controller > + * @raw: raw ADC value > + * > + * This converts the raw ADC value to mcelsius using the SoC specific > + * calibration constants > + */ > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > +{ > + s32 format_1, format_2, format_3, format_4; The formula would be easier to follow with better variable names than "format_X". > + s32 xtoomt; What does "xtoomt" mean? > + s32 gain; > + > + raw &= 0xfff; > + > + gain = (10000 + mt->adc_ge); no outer () > + > + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / > + gain; > + > + format_1 = ((mt->degc_cali * 10) >> 1); When doing computations, I think "A / 2" is preferred over "A >> 1". Also, no outer (). > + format_2 = (raw - mt->adc_oe); > + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; This is just: format_3 = ((((raw - mt->vts - 3350) * 10000) / 4096) * 10000) / gain; No wonder mt->adc_oe = 512-512 = 0... it just cancels itself out here, anyway. > + format_3 = format_3 * 15 / 18; Of course we should multiply by 15/18! What is going on here? Why this magic 5/6 ratio? > + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); no outer () > + format_4 = format_4 - (format_4 << 1); Hmm... A = X - 2*X; otherwise known as: A = -X; > + return (format_1 + format_4) * 100; Or just: return (format_1 - format_4) * 100; > + > +} > + > +/** > + * mtk_thermal_get_bank - get bank > + * @bank: The bank > + * > + * The bank registers are banked, we have to select a bank in the > + * PTPCORESEL register to access it. > + */ > +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + u32 val; > + > + mutex_lock(&mt->lock); > + > + val = readl(mt->thermal_base + PTPCORESEL); > + val &= ~0xf; > + val |= bank->id; > + writel(val, mt->thermal_base + PTPCORESEL); > +} > + > +/** > + * mtk_thermal_put_bank - release bank > + * @bank: The bank > + * > + * release a bank previously taken with mtk_thermal_get_bank, > + */ > +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + > + mutex_unlock(&mt->lock); > +} > + > +/** > + * mtk_thermal_bank_temperature - get the temperature of a bank > + * @bank: The bank > + * > + * The temperature of a bank is considered the maximum temperature of > + * the sensors associated to the bank. > + */ > +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + int temp, i, max; > + u32 raw; > + > + temp = max = -INT_MAX; nit: INT_MIN? > + > + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { If enable_mask became sensor_count, this would become: for (i = 0; i < bank_data[bank->id].sensor_count; i++) { > + int sensno; > + > + if (!(bank_data[bank->id].enable_mask & (1 << i))) > + continue; > + > + raw = readl(mt->thermal_base + tempmsr_ofs[i]); > + > + sensno = bank_data[bank->id].sensors[i]; sensno is set but not used. > + temp = raw_to_mcelsius(mt, raw); > + > + if (temp > max) > + max = temp; > + } > + > + return max; > +} > + > +static int mtk_read_temp(void *data, long *temp) > +{ > + struct mtk_thermal_bank *bank = data; > + > + mtk_thermal_get_bank(bank); > + > + *temp = mtk_thermal_bank_temperature(bank); > + > + /* > + * The first read of a sensor often contains very high bogus temperature > + * value. Filter these out so that the system does not immediately shut > + * down. > + */ > + if (*temp > 200000) > + *temp = 0; Why not just put this limiter in mtk_thermal_bank_temperature(), and discard bogus sense points? Since mtk_thermal_bank_temperature() returns the max of all sense points, any one bogus sense point will cause a bogus temperature. > + > + mtk_thermal_put_bank(bank); > + > + return 0; > +} > + > +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { > + .get_temp = mtk_read_temp, > +}; > + > +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) > +{ > + struct mtk_thermal *mt = bank->mt; > + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; > + int i; > + > + mtk_thermal_get_bank(bank); > + > + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ > + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); Please create some #defines for the register bits that are written in this function. > + > + /* > + * filt interval is 1 * 46.540us = 46.54us, > + * sen interval is 429 * 46.540us = 19.96ms > + */ > + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); > + > + /* poll is set to 10u */ > + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); > + > + /* temperature sampling control, 1 sample */ > + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); > + > + /* exceed this polling time, IRQ would be inserted */ > + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); > + > + /* number of interrupts per event, 1 is enough */ > + writel(0x0, mt->thermal_base + TEMPMONIDET0); > + writel(0x0, mt->thermal_base + TEMPMONIDET1); > + > + /* > + * The MT8173 thermal controller does not have its own ADC. Instead it > + * uses AHB bus accesses to control the AUXADC. To do this the thermal > + * controller has to be programmed with the physical addresses of the > + * AUXADC registers and with the various bit positions in the AUXADC. > + * Also the thermal controller controls a mux in the APMIXEDSYS register > + * space. > + */ > + > + /* > + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) > + * automatically by hw > + */ > + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); > + > + /* AHB address for auxadc mux selection */ > + writel(mt->auxadc_phys_base + 0x00c, Is this "0x00c" : AUXADC_CON1_CLR_V ? Since auxadc_phys_base is only used during probe()->init_bank(), don't store it in mt. > + mt->thermal_base + TEMPADCMUXADDR); > + > + /* AHB address for pnp sensor mux selection */ > + writel(mt->apmixed_phys_base + 0x0604, What is the name of the APMIXED register with offset "0x0604"? Since apmixed_phys_base is only used during probe()->init_bank(), don't store it in mt. > + mt->thermal_base + TEMPPNPMUXADDR); > + > + /* AHB value for auxadc enable */ > + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); > + > + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ > + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, > + mt->thermal_base + TEMPADCENADDR); > + > + /* AHB address for auxadc valid bit */ > + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMPADCVALIDADDR); > + > + /* AHB address for auxadc voltage output */ > + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), > + mt->thermal_base + TEMPADCVOLTADDR); > + > + /* read valid & voltage are at the same register */ > + writel(0x0, mt->thermal_base + TEMPRDCTRL); > + > + /* indicate where the valid bit is */ > + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), > + mt->thermal_base + TEMPADCVALIDMASK); > + > + /* no shift */ > + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); > + > + /* enable auxadc mux write transaction */ > + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMPADCWRITECTRL); > + > + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) > + writel(sensor_mux_values[cfg->sensors[i]], > + mt->thermal_base + tempadcpnp_ofs[i]); Not all banks use MT8173_NUM_SENSING_POINTS sensors. If enable_mask became sensor_count, this could avoid writing unnecessary registers: for (i = 0; i < cfg->sensor_count; i++) > + > + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); And computing enable_mask from sensor_count is trivial: GENMASK(cfg->sensor_count - 1, 0); > + > + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, > + mt->thermal_base + TEMPADCWRITECTRL); > + > + mtk_thermal_put_bank(bank); > +} > + > +static u64 of_get_phys_base(struct device_node *np) > +{ > + u64 size64; > + const __be32 *regaddr_p; > + > + regaddr_p = of_get_address(np, 0, &size64, NULL); > + if (!regaddr_p) > + return OF_BAD_ADDR; > + > + return of_translate_address(np, regaddr_p); > +} > + > +static int mtk_thermal_probe(struct platform_device *pdev) > +{ > + int ret, i; > + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; > + struct mtk_thermal *mt; > + struct resource *res; > + > + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); > + if (!mt) > + return -ENOMEM; > + > + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->clk_peri_therm)) > + return PTR_ERR(mt->clk_peri_therm); > + > + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); > + if (IS_ERR(mt->clk_auxadc)) > + return PTR_ERR(mt->clk_auxadc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(mt->thermal_base)) > + return PTR_ERR(mt->thermal_base); > + > + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); > + if (IS_ERR(mt->reset)) { > + ret = PTR_ERR(mt->reset); > + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); > + return ret; > + } > + > + mutex_init(&mt->lock); > + > + mt->dev = &pdev->dev; > + > + auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); > + if (!auxadc) { > + dev_err(&pdev->dev, "missing auxadc node\n"); > + return -ENODEV; > + } > + > + mt->auxadc_phys_base = of_get_phys_base(auxadc); > + if (mt->auxadc_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); > + if (!apmixedsys) { > + dev_err(&pdev->dev, "missing apmixedsys node\n"); > + return -ENODEV; > + } > + > + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); > + if (mt->apmixed_phys_base == OF_BAD_ADDR) { > + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); > + return -EINVAL; > + } > + > + ret = clk_prepare_enable(mt->clk_auxadc); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); > + return ret; > + } > + > + reset_control_reset(mt->reset); > + > + ret = clk_prepare_enable(mt->clk_peri_therm); > + if (ret) { > + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); > + goto err_enable_clk; I think labels are usually named by what they do, rather than what causes the goto. So, perhaps: goto err_disable_clk_auxadc; > + } > + > + /* > + * These calibration values should finally be provided by the > + * firmware or fuses. For now use default values. > + */ > + mt->adc_ge = ((512 - 512) * 10000) / 4096; > + mt->adc_oe = 512 - 512; > + mt->degc_cali = 40; > + mt->o_slope = 0; > + mt->vts = 260; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->id = i; > + bank->mt = mt; > + mtk_thermal_init_bank(&mt->banks[i]); I think this would work better as just: mtk_thermal_init_bank(mt, i, apmixedsys_phys_base, auxadc_phys_base); Setting "id" and "mt" out here doesn't add much value. > + } > + > + platform_set_drvdata(pdev, mt); > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, > + &mtk_thermal_ops); > + } > + > + return 0; > + > +err_enable_clk: > + clk_disable_unprepare(mt->clk_peri_therm); > + > + return ret; > +} > + > +static int mtk_thermal_remove(struct platform_device *pdev) > +{ > + struct mtk_thermal *mt = platform_get_drvdata(pdev); > + int i; > + > + for (i = 0; i < MT8173_NUM_BANKS; i++) { > + struct mtk_thermal_bank *bank = &mt->banks[i]; > + > + if (!IS_ERR(bank)) How could this be true? ok... enough for now :-) Thanks, -Dan > + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); > + } > + > + clk_disable_unprepare(mt->clk_peri_therm); > + clk_disable_unprepare(mt->clk_auxadc); > + > + return 0; > +} > + > +static const struct of_device_id mtk_thermal_of_match[] = { > + { > + .compatible = "mediatek,mt8173-thermal", > + }, { > + }, > +}; > + > +static struct platform_driver mtk_thermal_driver = { > + .probe = mtk_thermal_probe, > + .remove = mtk_thermal_remove, > + .driver = { > + .name = THERMAL_NAME, > + .of_match_table = mtk_thermal_of_match, > + }, > +}; > + > +module_platform_driver(mtk_thermal_driver); > + > +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); > +MODULE_DESCRIPTION("Mediatek thermal driver"); > +MODULE_LICENSE("GPL v2"); > -- > 2.1.4 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-07-21 15:13 ` Daniel Kurtz (?) @ 2015-08-05 10:20 ` Sascha Hauer -1 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-05 10:20 UTC (permalink / raw) To: Daniel Kurtz Cc: Hanyi.Wu, linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger On Tue, Jul 21, 2015 at 11:13:22PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > Review comments inline... > > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > > +{ > > + s32 format_1, format_2, format_3, format_4; > > The formula would be easier to follow with better variable names than > "format_X". > > > + s32 xtoomt; > > What does "xtoomt" mean? > > > + s32 gain; > > + > > + raw &= 0xfff; > > + > > + gain = (10000 + mt->adc_ge); > > no outer () > > > + > > + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / > > + gain; > > + > > + format_1 = ((mt->degc_cali * 10) >> 1); > > When doing computations, I think "A / 2" is preferred over "A >> 1". > Also, no outer (). > > > + format_2 = (raw - mt->adc_oe); > > + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; > > This is just: > format_3 = ((((raw - mt->vts - 3350) * 10000) / 4096) * 10000) / gain; > > No wonder mt->adc_oe = 512-512 = 0... it just cancels itself out here, anyway. > > > + format_3 = format_3 * 15 / 18; > > Of course we should multiply by 15/18! > What is going on here? Why this magic 5/6 ratio? > > > + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); > > no outer () > > > + format_4 = format_4 - (format_4 << 1); > > Hmm... > A = X - 2*X; > otherwise known as: > A = -X; > > > + return (format_1 + format_4) * 100; > > Or just: > return (format_1 - format_4) * 100; I must admit I took this calculation from the original driver and never looked at it. Simplifying this further this goes down to: static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) { return mt->calib_b + mt->calib_a * (raw & 0xfff); } with calib_a = -123 and calib_b = 465124. I'll address this and the other comments in v2. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-08-05 10:20 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-05 10:20 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 21, 2015 at 11:13:22PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > Review comments inline... > > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > > +{ > > + s32 format_1, format_2, format_3, format_4; > > The formula would be easier to follow with better variable names than > "format_X". > > > + s32 xtoomt; > > What does "xtoomt" mean? > > > + s32 gain; > > + > > + raw &= 0xfff; > > + > > + gain = (10000 + mt->adc_ge); > > no outer () > > > + > > + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / > > + gain; > > + > > + format_1 = ((mt->degc_cali * 10) >> 1); > > When doing computations, I think "A / 2" is preferred over "A >> 1". > Also, no outer (). > > > + format_2 = (raw - mt->adc_oe); > > + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; > > This is just: > format_3 = ((((raw - mt->vts - 3350) * 10000) / 4096) * 10000) / gain; > > No wonder mt->adc_oe = 512-512 = 0... it just cancels itself out here, anyway. > > > + format_3 = format_3 * 15 / 18; > > Of course we should multiply by 15/18! > What is going on here? Why this magic 5/6 ratio? > > > + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); > > no outer () > > > + format_4 = format_4 - (format_4 << 1); > > Hmm... > A = X - 2*X; > otherwise known as: > A = -X; > > > + return (format_1 + format_4) * 100; > > Or just: > return (format_1 - format_4) * 100; I must admit I took this calculation from the original driver and never looked at it. Simplifying this further this goes down to: static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) { return mt->calib_b + mt->calib_a * (raw & 0xfff); } with calib_a = -123 and calib_b = 465124. I'll address this and the other comments in v2. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* Re: [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-08-05 10:20 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-08-05 10:20 UTC (permalink / raw) To: Daniel Kurtz Cc: Hanyi.Wu, linux-pm, Zhang Rui, Eduardo Valentin, linux-kernel, Sasha Hauer, linux-mediatek, linux-arm-kernel, Matthias Brugger On Tue, Jul 21, 2015 at 11:13:22PM +0800, Daniel Kurtz wrote: > Hi Sascha, > > Review comments inline... > > > + * > > + * This converts the raw ADC value to mcelsius using the SoC specific > > + * calibration constants > > + */ > > +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) > > +{ > > + s32 format_1, format_2, format_3, format_4; > > The formula would be easier to follow with better variable names than > "format_X". > > > + s32 xtoomt; > > What does "xtoomt" mean? > > > + s32 gain; > > + > > + raw &= 0xfff; > > + > > + gain = (10000 + mt->adc_ge); > > no outer () > > > + > > + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / > > + gain; > > + > > + format_1 = ((mt->degc_cali * 10) >> 1); > > When doing computations, I think "A / 2" is preferred over "A >> 1". > Also, no outer (). > > > + format_2 = (raw - mt->adc_oe); > > + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; > > This is just: > format_3 = ((((raw - mt->vts - 3350) * 10000) / 4096) * 10000) / gain; > > No wonder mt->adc_oe = 512-512 = 0... it just cancels itself out here, anyway. > > > + format_3 = format_3 * 15 / 18; > > Of course we should multiply by 15/18! > What is going on here? Why this magic 5/6 ratio? > > > + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); > > no outer () > > > + format_4 = format_4 - (format_4 << 1); > > Hmm... > A = X - 2*X; > otherwise known as: > A = -X; > > > + return (format_1 + format_4) * 100; > > Or just: > return (format_1 - format_4) * 100; I must admit I took this calculation from the original driver and never looked at it. Simplifying this further this goes down to: static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) { return mt->calib_b + mt->calib_a * (raw & 0xfff); } with calib_a = -123 and calib_b = 465124. I'll address this and the other comments in v2. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH] thermal: Add Mediatek thermal support @ 2015-07-13 10:34 Sascha Hauer 2015-07-13 10:34 ` Sascha Hauer 0 siblings, 1 reply; 139+ messages in thread From: Sascha Hauer @ 2015-07-13 10:34 UTC (permalink / raw) To: linux-pm Cc: Zhang Rui, Eduardo Valentin, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger This series adds support for the thermal sensors included in the MT8173 SoC. Currently only basic temperature reading is supported without any interrupt support. The cpufreq driver for MT8173 is currently under review, so there's no real cooling device available in mainline. Until this is available the thermal driver can be tested with the following dts snippet. It creates a fake gpio fan and a fake trip point which is so low that it can easily be reached with a "cat /dev/zero > /dev/null" on the command line. Please review and let me know what's missing to be included in mainline. Sascha fan: gpio_fan { compatible = "gpio-fan"; gpios = <&pio 24 0>; gpio-fan,speed-map = <0 0 4500 1>; #cooling-cells = <2>; }; thermal-zones { cpu_thermal: cpu_thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&thermal 0>; trips { cpu_passive: cpu_passive { temperature = <47000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "passive"; }; cpu_crit { temperature = <90000>; /* millicelsius */ hysteresis = <2000>; /* millicelsius */ type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu_passive>; cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; }; ---------------------------------------------------------------- Sascha Hauer (3): dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: Add Mediatek thermal controller support ARM64: dts: mt8173: Add thermal/auxadc device nodes .../bindings/thermal/mediatek-thermal.txt | 38 ++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 + drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 602 +++++++++++++++++++++ 5 files changed, 667 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek-thermal.txt create mode 100644 drivers/thermal/mtk_thermal.c ^ permalink raw reply [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support 2015-07-13 10:34 [PATCH] thermal: Add Mediatek thermal support Sascha Hauer @ 2015-07-13 10:34 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-07-13 10:34 UTC (permalink / raw) To: linux-pm Cc: Zhang Rui, Eduardo Valentin, linux-kernel, kernel, linux-mediatek, linux-arm-kernel, Matthias Brugger, Sascha Hauer This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 602 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 611 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..538e438 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/dmi.h> +#include <linux/thermal.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/interrupt.h> +#include <linux/reset.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) + +/* Thermal Controller Registers */ +#define TEMPMONCTL0 0x000 +#define TEMPMONCTL1 0x004 +#define TEMPMONCTL2 0x008 +#define TEMPMONINT 0x00c +#define TEMPMONINTSTS 0x010 +#define TEMPMONIDET0 0x014 +#define TEMPMONIDET1 0x018 +#define TEMPMONIDET2 0x01c +#define TEMPH2NTHRE 0x024 +#define TEMPHTHRE 0x028 +#define TEMPCTHRE 0x02c +#define TEMPOFFSETH 0x030 +#define TEMPOFFSETL 0x034 +#define TEMPMSRCTL0 0x038 +#define TEMPMSRCTL1 0x03c +#define TEMPAHBPOLL 0x040 +#define TEMPAHBTO 0x044 +#define TEMPADCPNP0 0x048 +#define TEMPADCPNP1 0x04c +#define TEMPADCPNP2 0x050 +#define TEMPADCPNP3 0x0b4 + +#define TEMPADCMUX 0x054 +#define TEMPADCEXT 0x058 +#define TEMPADCEXT1 0x05c +#define TEMPADCEN 0x060 +#define TEMPPNPMUXADDR 0x064 +#define TEMPADCMUXADDR 0x068 +#define TEMPADCEXTADDR 0x06c +#define TEMPADCEXT1ADDR 0x070 +#define TEMPADCENADDR 0x074 +#define TEMPADCVALIDADDR 0x078 +#define TEMPADCVOLTADDR 0x07c +#define TEMPRDCTRL 0x080 +#define TEMPADCVALIDMASK 0x084 +#define TEMPADCVOLTAGESHIFT 0x088 +#define TEMPADCWRITECTRL 0x08c +#define TEMPMSR0 0x090 +#define TEMPMSR1 0x094 +#define TEMPMSR2 0x098 +#define TEMPMSR3 0x0B8 + +#define TEMPIMMD0 0x0a0 +#define TEMPIMMD1 0x0a4 +#define TEMPIMMD2 0x0a8 + +#define TEMPPROTCTL 0x0c0 +#define TEMPPROTTA 0x0c4 +#define TEMPPROTTB 0x0c8 +#define TEMPPROTTC 0x0cc + +#define TEMPSPARE0 0x0f0 +#define TEMPSPARE1 0x0f4 +#define TEMPSPARE2 0x0f8 +#define TEMPSPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) +#define TEMPMONINT_TIMEOUT (1 << 15) +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) + +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) + +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMPPROTCTL_AVERAGE (0 << 16) +#define TEMPPROTCTL_MAXIMUM (1 << 16) +#define TEMPPROTCTL_SELECTED (2 << 16) + +#define MT8173_THERMAL_ZONE_CA57 0 +#define MT8173_THERMAL_ZONE_CA53 1 +#define MT8173_THERMAL_ZONE_GPU 2 +#define MT8173_THERMAL_ZONE_CORE 3 + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_BANKS 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSING_POINTS 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tz; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + void __iomem *auxadc_base; + + u64 auxadc_phys_base; + u64 apmixed_phys_base; + struct reset_control *reset; + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 adc_oe; + s32 degc_cali; + s32 o_slope; + s32 vts; +}; + +struct mtk_thermal_bank_cfg { + unsigned int enable_mask; + unsigned int sensors[4]; +}; + +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static struct mtk_thermal_bank_cfg bank_data[] = { + { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .enable_mask = 7, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .enable_mask = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 +}; + +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + s32 format_1, format_2, format_3, format_4; + s32 xtoomt; + s32 gain; + + raw &= 0xfff; + + gain = (10000 + mt->adc_ge); + + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / + gain; + + format_1 = ((mt->degc_cali * 10) >> 1); + format_2 = (raw - mt->adc_oe); + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; + format_3 = format_3 * 15 / 18; + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); + format_4 = format_4 - (format_4 << 1); + + return (format_1 + format_4) * 100; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = -INT_MAX; + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { + int sensno; + + if (!(bank_data[bank->id].enable_mask & (1 << i))) + continue; + + raw = readl(mt->thermal_base + tempmsr_ofs[i]); + + sensno = bank_data[bank->id].sensors[i]; + temp = raw_to_mcelsius(mt, raw); + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + /* + * The first read of a sensor often contains very high bogus temperature + * value. Filter these out so that the system does not immediately shut + * down. + */ + if (*temp > 200000) + *temp = 0; + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; + int i; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); + + /* poll is set to 10u */ + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMPMONIDET0); + writel(0x0, mt->thermal_base + TEMPMONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) + * automatically by hw + */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); + + /* AHB address for auxadc mux selection */ + writel(mt->auxadc_phys_base + 0x00c, + mt->thermal_base + TEMPADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(mt->apmixed_phys_base + 0x0604, + mt->thermal_base + TEMPPNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMPADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMPRDCTRL); + + /* indicate where the valid bit is */ + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMPADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + tempadcpnp_ofs[i]); + + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); + + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); + if (IS_ERR(mt->reset)) { + ret = PTR_ERR(mt->reset); + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); + return ret; + } + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + mt->auxadc_phys_base = of_get_phys_base(auxadc); + if (mt->auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); + if (mt->apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + reset_control_reset(mt->reset); + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_enable_clk; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->adc_ge = ((512 - 512) * 10000) / 4096; + mt->adc_oe = 512 - 512; + mt->degc_cali = 40; + mt->o_slope = 0; + mt->vts = 260; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->id = i; + bank->mt = mt; + mtk_thermal_init_bank(&mt->banks[i]); + } + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_enable_clk: + clk_disable_unprepare(mt->clk_peri_therm); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + if (!IS_ERR(bank)) + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.1.4 ^ permalink raw reply related [flat|nested] 139+ messages in thread
* [PATCH 2/3] thermal: Add Mediatek thermal controller support @ 2015-07-13 10:34 ` Sascha Hauer 0 siblings, 0 replies; 139+ messages in thread From: Sascha Hauer @ 2015-07-13 10:34 UTC (permalink / raw) To: linux-arm-kernel This adds support for the Mediatek thermal controller found on MT8173 and likely other SoCs. The controller is a bit special. It does not have its own ADC, instead it controls the on-SoC AUXADC via AHB bus accesses. For this reason we need the physical address of the AUXADC. Also it controls a mux using AHB bus accesses, so we need the APMIXEDSYS physical address aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/thermal/Kconfig | 8 + drivers/thermal/Makefile | 1 + drivers/thermal/mtk_thermal.c | 602 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 611 insertions(+) create mode 100644 drivers/thermal/mtk_thermal.c diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 118938e..07ad114 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -340,6 +340,14 @@ config ACPI_THERMAL_REL tristate depends on ACPI +config MTK_THERMAL + tristate "Temperature sensor driver for mediatek SoCs" + depends on ARCH_MEDIATEK || COMPILE_TEST + default y + help + Enable this option if you want to have support for thermal management + controller present in Mediatek SoCs + menu "Texas Instruments thermal drivers" source "drivers/thermal/ti-soc-thermal/Kconfig" endmenu diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index 535dfee..cc1cab3 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/ obj-$(CONFIG_ST_THERMAL) += st/ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c new file mode 100644 index 0000000..538e438 --- /dev/null +++ b/drivers/thermal/mtk_thermal.c @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Hanyi.Wu <hanyi.wu@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/dmi.h> +#include <linux/thermal.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/time.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/interrupt.h> +#include <linux/reset.h> + +/* AUXADC Registers */ +#define AUXADC_CON0_V 0x000 +#define AUXADC_CON1_V 0x004 +#define AUXADC_CON1_SET_V 0x008 +#define AUXADC_CON1_CLR_V 0x00c +#define AUXADC_CON2_V 0x010 +#define AUXADC_DATA(channel) (0x14 + (channel) * 4) +#define AUXADC_MISC_V 0x094 + +#define AUXADC_CON1_CHANNEL(x) (1 << (x)) + +/* Thermal Controller Registers */ +#define TEMPMONCTL0 0x000 +#define TEMPMONCTL1 0x004 +#define TEMPMONCTL2 0x008 +#define TEMPMONINT 0x00c +#define TEMPMONINTSTS 0x010 +#define TEMPMONIDET0 0x014 +#define TEMPMONIDET1 0x018 +#define TEMPMONIDET2 0x01c +#define TEMPH2NTHRE 0x024 +#define TEMPHTHRE 0x028 +#define TEMPCTHRE 0x02c +#define TEMPOFFSETH 0x030 +#define TEMPOFFSETL 0x034 +#define TEMPMSRCTL0 0x038 +#define TEMPMSRCTL1 0x03c +#define TEMPAHBPOLL 0x040 +#define TEMPAHBTO 0x044 +#define TEMPADCPNP0 0x048 +#define TEMPADCPNP1 0x04c +#define TEMPADCPNP2 0x050 +#define TEMPADCPNP3 0x0b4 + +#define TEMPADCMUX 0x054 +#define TEMPADCEXT 0x058 +#define TEMPADCEXT1 0x05c +#define TEMPADCEN 0x060 +#define TEMPPNPMUXADDR 0x064 +#define TEMPADCMUXADDR 0x068 +#define TEMPADCEXTADDR 0x06c +#define TEMPADCEXT1ADDR 0x070 +#define TEMPADCENADDR 0x074 +#define TEMPADCVALIDADDR 0x078 +#define TEMPADCVOLTADDR 0x07c +#define TEMPRDCTRL 0x080 +#define TEMPADCVALIDMASK 0x084 +#define TEMPADCVOLTAGESHIFT 0x088 +#define TEMPADCWRITECTRL 0x08c +#define TEMPMSR0 0x090 +#define TEMPMSR1 0x094 +#define TEMPMSR2 0x098 +#define TEMPMSR3 0x0B8 + +#define TEMPIMMD0 0x0a0 +#define TEMPIMMD1 0x0a4 +#define TEMPIMMD2 0x0a8 + +#define TEMPPROTCTL 0x0c0 +#define TEMPPROTTA 0x0c4 +#define TEMPPROTTB 0x0c8 +#define TEMPPROTTC 0x0cc + +#define TEMPSPARE0 0x0f0 +#define TEMPSPARE1 0x0f4 +#define TEMPSPARE2 0x0f8 +#define TEMPSPARE3 0x0fc + +#define PTPCORESEL 0x400 +#define THERMINTST 0x404 +#define PTPODINTST 0x408 +#define THSTAGE0ST 0x40c +#define THSTAGE1ST 0x410 +#define THSTAGE2ST 0x414 +#define THAHBST0 0x418 +#define THAHBST1 0x41c /* Only for DE debug */ +#define PTPSPARE0 0x420 +#define PTPSPARE1 0x424 +#define PTPSPARE2 0x428 +#define PTPSPARE3 0x42c +#define THSLPEVEB 0x430 + +#define TEMPMONINT_COLD(sp) ((1 << 0) << ((sp) * 5)) +#define TEMPMONINT_HOT(sp) ((1 << 1) << ((sp) * 5)) +#define TEMPMONINT_LOW_OFS(sp) ((1 << 2) << ((sp) * 5)) +#define TEMPMONINT_HIGH_OFS(sp) ((1 << 3) << ((sp) * 5)) +#define TEMPMONINT_HOT_TO_NORM(sp) ((1 << 4) << ((sp) * 5)) +#define TEMPMONINT_TIMEOUT (1 << 15) +#define TEMPMONINT_IMMEDIATE_SENSE(sp) (1 << (16 + (sp))) +#define TEMPMONINT_FILTER_SENSE(sp) (1 << (19 + (sp))) + +#define TEMPADCWRITECTRL_ADC_PNP_WRITE (1 << 0) +#define TEMPADCWRITECTRL_ADC_MUX_WRITE (1 << 1) +#define TEMPADCWRITECTRL_ADC_EXTRA_WRITE (1 << 2) +#define TEMPADCWRITECTRL_ADC_EXTRA1_WRITE (1 << 3) + +#define TEMPADCVALIDMASK_VALID_HIGH (1 << 5) +#define TEMPADCVALIDMASK_VALID_POS(bit) (bit) + +#define TEMPPROTCTL_AVERAGE (0 << 16) +#define TEMPPROTCTL_MAXIMUM (1 << 16) +#define TEMPPROTCTL_SELECTED (2 << 16) + +#define MT8173_THERMAL_ZONE_CA57 0 +#define MT8173_THERMAL_ZONE_CA53 1 +#define MT8173_THERMAL_ZONE_GPU 2 +#define MT8173_THERMAL_ZONE_CORE 3 + +#define MT8173_TS1 0 +#define MT8173_TS2 1 +#define MT8173_TS3 2 +#define MT8173_TS4 3 +#define MT8173_TSABB 4 + +/* AUXADC channel 11 is used for the temperature sensors */ +#define MT8173_TEMP_AUXADC_CHANNEL 11 + +/* The total number of temperature sensors in the MT8173 */ +#define MT8173_NUM_SENSORS 5 + +/* The number of banks in the MT8173 */ +#define MT8173_NUM_BANKS 4 + +/* The number of sensing points per bank */ +#define MT8173_NUM_SENSING_POINTS 4 + +#define THERMAL_NAME "mtk-thermal" + +struct mtk_thermal; + +struct mtk_thermal_bank { + struct mtk_thermal *mt; + struct thermal_zone_device *tz; + int id; +}; + +struct mtk_thermal { + struct device *dev; + void __iomem *thermal_base; + void __iomem *auxadc_base; + + u64 auxadc_phys_base; + u64 apmixed_phys_base; + struct reset_control *reset; + struct clk *clk_peri_therm; + struct clk *clk_auxadc; + + struct mtk_thermal_bank banks[MT8173_NUM_BANKS]; + + struct mutex lock; + + /* Calibration values */ + s32 adc_ge; + s32 adc_oe; + s32 degc_cali; + s32 o_slope; + s32 vts; +}; + +struct mtk_thermal_bank_cfg { + unsigned int enable_mask; + unsigned int sensors[4]; +}; + +static int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; + +/* + * The MT8173 thermal controller has four banks. Each bank can read up to + * four temperature sensors simultaneously. The MT8173 has a total of 5 + * temperature sensors. We use each bank to measure a certain area of the + * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple + * areas, hence is used in different banks. + */ +static struct mtk_thermal_bank_cfg bank_data[] = { + { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS3 }, + }, { + .enable_mask = 3, + .sensors = { MT8173_TS2, MT8173_TS4 }, + }, { + .enable_mask = 7, + .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, + }, { + .enable_mask = 1, + .sensors = { MT8173_TS2 }, + }, +}; + +static int tempmsr_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPMSR0, TEMPMSR1, TEMPMSR2, TEMPMSR3 +}; + +static int tempadcpnp_ofs[MT8173_NUM_SENSING_POINTS] = { + TEMPADCPNP0, TEMPADCPNP1, TEMPADCPNP2, TEMPADCPNP3 +}; + +/** + * raw_to_mcelsius - convert a raw ADC value to mcelsius + * @mt: The thermal controller + * @raw: raw ADC value + * + * This converts the raw ADC value to mcelsius using the SoC specific + * calibration constants + */ +static int raw_to_mcelsius(struct mtk_thermal *mt, u32 raw) +{ + s32 format_1, format_2, format_3, format_4; + s32 xtoomt; + s32 gain; + + raw &= 0xfff; + + gain = (10000 + mt->adc_ge); + + xtoomt = ((((mt->vts + 3350 - mt->adc_oe) * 10000) / 4096) * 10000) / + gain; + + format_1 = ((mt->degc_cali * 10) >> 1); + format_2 = (raw - mt->adc_oe); + format_3 = (((((format_2) * 10000) >> 12) * 10000) / gain) - xtoomt; + format_3 = format_3 * 15 / 18; + format_4 = ((format_3 * 100) / (165 + mt->o_slope)); + format_4 = format_4 - (format_4 << 1); + + return (format_1 + format_4) * 100; +} + +/** + * mtk_thermal_get_bank - get bank + * @bank: The bank + * + * The bank registers are banked, we have to select a bank in the + * PTPCORESEL register to access it. + */ +static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + u32 val; + + mutex_lock(&mt->lock); + + val = readl(mt->thermal_base + PTPCORESEL); + val &= ~0xf; + val |= bank->id; + writel(val, mt->thermal_base + PTPCORESEL); +} + +/** + * mtk_thermal_put_bank - release bank + * @bank: The bank + * + * release a bank previously taken with mtk_thermal_get_bank, + */ +static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + + mutex_unlock(&mt->lock); +} + +/** + * mtk_thermal_bank_temperature - get the temperature of a bank + * @bank: The bank + * + * The temperature of a bank is considered the maximum temperature of + * the sensors associated to the bank. + */ +static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + int temp, i, max; + u32 raw; + + temp = max = -INT_MAX; + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) { + int sensno; + + if (!(bank_data[bank->id].enable_mask & (1 << i))) + continue; + + raw = readl(mt->thermal_base + tempmsr_ofs[i]); + + sensno = bank_data[bank->id].sensors[i]; + temp = raw_to_mcelsius(mt, raw); + + if (temp > max) + max = temp; + } + + return max; +} + +static int mtk_read_temp(void *data, int *temp) +{ + struct mtk_thermal_bank *bank = data; + + mtk_thermal_get_bank(bank); + + *temp = mtk_thermal_bank_temperature(bank); + + /* + * The first read of a sensor often contains very high bogus temperature + * value. Filter these out so that the system does not immediately shut + * down. + */ + if (*temp > 200000) + *temp = 0; + + mtk_thermal_put_bank(bank); + + return 0; +} + +static const struct thermal_zone_of_device_ops mtk_thermal_ops = { + .get_temp = mtk_read_temp, +}; + +static void mtk_thermal_init_bank(struct mtk_thermal_bank *bank) +{ + struct mtk_thermal *mt = bank->mt; + struct mtk_thermal_bank_cfg *cfg = &bank_data[bank->id]; + int i; + + mtk_thermal_get_bank(bank); + + /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ + writel(0x0000000c, mt->thermal_base + TEMPMONCTL1); + + /* + * filt interval is 1 * 46.540us = 46.54us, + * sen interval is 429 * 46.540us = 19.96ms + */ + writel(0x000101ad, mt->thermal_base + TEMPMONCTL2); + + /* poll is set to 10u */ + writel(0x00000300, mt->thermal_base + TEMPAHBPOLL); + + /* temperature sampling control, 1 sample */ + writel(0x00000000, mt->thermal_base + TEMPMSRCTL0); + + /* exceed this polling time, IRQ would be inserted */ + writel(0xffffffff, mt->thermal_base + TEMPAHBTO); + + /* number of interrupts per event, 1 is enough */ + writel(0x0, mt->thermal_base + TEMPMONIDET0); + writel(0x0, mt->thermal_base + TEMPMONIDET1); + + /* + * The MT8173 thermal controller does not have its own ADC. Instead it + * uses AHB bus accesses to control the AUXADC. To do this the thermal + * controller has to be programmed with the physical addresses of the + * AUXADC registers and with the various bit positions in the AUXADC. + * Also the thermal controller controls a mux in the APMIXEDSYS register + * space. + */ + + /* + * this value will be stored to TEMPPNPMUXADDR (TEMPSPARE0) + * automatically by hw + */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCMUX); + + /* AHB address for auxadc mux selection */ + writel(mt->auxadc_phys_base + 0x00c, + mt->thermal_base + TEMPADCMUXADDR); + + /* AHB address for pnp sensor mux selection */ + writel(mt->apmixed_phys_base + 0x0604, + mt->thermal_base + TEMPPNPMUXADDR); + + /* AHB value for auxadc enable */ + writel(1 << MT8173_TEMP_AUXADC_CHANNEL, mt->thermal_base + TEMPADCEN); + + /* AHB address for auxadc enable (channel 0 immediate mode selected) */ + writel(mt->auxadc_phys_base + AUXADC_CON1_SET_V, + mt->thermal_base + TEMPADCENADDR); + + /* AHB address for auxadc valid bit */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVALIDADDR); + + /* AHB address for auxadc voltage output */ + writel(mt->auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), + mt->thermal_base + TEMPADCVOLTADDR); + + /* read valid & voltage are at the same register */ + writel(0x0, mt->thermal_base + TEMPRDCTRL); + + /* indicate where the valid bit is */ + writel(TEMPADCVALIDMASK_VALID_HIGH | TEMPADCVALIDMASK_VALID_POS(12), + mt->thermal_base + TEMPADCVALIDMASK); + + /* no shift */ + writel(0x0, mt->thermal_base + TEMPADCVOLTAGESHIFT); + + /* enable auxadc mux write transaction */ + writel(TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + for (i = 0; i < MT8173_NUM_SENSING_POINTS; i++) + writel(sensor_mux_values[cfg->sensors[i]], + mt->thermal_base + tempadcpnp_ofs[i]); + + writel(cfg->enable_mask, mt->thermal_base + TEMPMONCTL0); + + writel(TEMPADCWRITECTRL_ADC_PNP_WRITE | TEMPADCWRITECTRL_ADC_MUX_WRITE, + mt->thermal_base + TEMPADCWRITECTRL); + + mtk_thermal_put_bank(bank); +} + +static u64 of_get_phys_base(struct device_node *np) +{ + u64 size64; + const __be32 *regaddr_p; + + regaddr_p = of_get_address(np, 0, &size64, NULL); + if (!regaddr_p) + return OF_BAD_ADDR; + + return of_translate_address(np, regaddr_p); +} + +static int mtk_thermal_probe(struct platform_device *pdev) +{ + int ret, i; + struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; + struct mtk_thermal *mt; + struct resource *res; + + mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); + if (!mt) + return -ENOMEM; + + mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); + if (IS_ERR(mt->clk_peri_therm)) + return PTR_ERR(mt->clk_peri_therm); + + mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); + if (IS_ERR(mt->clk_auxadc)) + return PTR_ERR(mt->clk_auxadc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(mt->thermal_base)) + return PTR_ERR(mt->thermal_base); + + mt->reset = devm_reset_control_get(&pdev->dev, "therm"); + if (IS_ERR(mt->reset)) { + ret = PTR_ERR(mt->reset); + dev_err(&pdev->dev, "cannot get reset: %d\n", ret); + return ret; + } + + mutex_init(&mt->lock); + + mt->dev = &pdev->dev; + + auxadc = of_parse_phandle(np, "auxadc", 0); + if (!auxadc) { + dev_err(&pdev->dev, "missing auxadc node\n"); + return -ENODEV; + } + + mt->auxadc_phys_base = of_get_phys_base(auxadc); + if (mt->auxadc_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + apmixedsys = of_parse_phandle(np, "apmixedsys", 0); + if (!apmixedsys) { + dev_err(&pdev->dev, "missing apmixedsys node\n"); + return -ENODEV; + } + + mt->apmixed_phys_base = of_get_phys_base(apmixedsys); + if (mt->apmixed_phys_base == OF_BAD_ADDR) { + dev_err(&pdev->dev, "Can't get auxadc phys address\n"); + return -EINVAL; + } + + ret = clk_prepare_enable(mt->clk_auxadc); + if (ret) { + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); + return ret; + } + + reset_control_reset(mt->reset); + + ret = clk_prepare_enable(mt->clk_peri_therm); + if (ret) { + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); + goto err_enable_clk; + } + + /* + * These calibration values should finally be provided by the + * firmware or fuses. For now use default values. + */ + mt->adc_ge = ((512 - 512) * 10000) / 4096; + mt->adc_oe = 512 - 512; + mt->degc_cali = 40; + mt->o_slope = 0; + mt->vts = 260; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->id = i; + bank->mt = mt; + mtk_thermal_init_bank(&mt->banks[i]); + } + + platform_set_drvdata(pdev, mt); + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + bank->tz = thermal_zone_of_sensor_register(&pdev->dev, i, bank, + &mtk_thermal_ops); + } + + return 0; + +err_enable_clk: + clk_disable_unprepare(mt->clk_peri_therm); + + return ret; +} + +static int mtk_thermal_remove(struct platform_device *pdev) +{ + struct mtk_thermal *mt = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < MT8173_NUM_BANKS; i++) { + struct mtk_thermal_bank *bank = &mt->banks[i]; + + if (!IS_ERR(bank)) + thermal_zone_of_sensor_unregister(&pdev->dev, bank->tz); + } + + clk_disable_unprepare(mt->clk_peri_therm); + clk_disable_unprepare(mt->clk_auxadc); + + return 0; +} + +static const struct of_device_id mtk_thermal_of_match[] = { + { + .compatible = "mediatek,mt8173-thermal", + }, { + }, +}; + +static struct platform_driver mtk_thermal_driver = { + .probe = mtk_thermal_probe, + .remove = mtk_thermal_remove, + .driver = { + .name = THERMAL_NAME, + .of_match_table = mtk_thermal_of_match, + }, +}; + +module_platform_driver(mtk_thermal_driver); + +MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de"); +MODULE_DESCRIPTION("Mediatek thermal driver"); +MODULE_LICENSE("GPL v2"); -- 2.1.4 ^ permalink raw reply related [flat|nested] 139+ messages in thread
end of thread, other threads:[~2016-02-19 7:21 UTC | newest] Thread overview: 139+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-11-09 10:13 [PATCH v10] Add Mediatek thermal support Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer 2015-11-09 10:13 ` [PATCH 1/3] dt-bindings: thermal: Add binding document for Mediatek thermal controller Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer 2015-11-09 15:59 ` Rob Herring 2015-11-09 15:59 ` Rob Herring 2015-11-09 10:13 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer 2015-11-09 14:39 ` Andy Shevchenko 2015-11-09 14:39 ` Andy Shevchenko 2015-11-18 8:11 ` Sascha Hauer 2015-11-18 8:11 ` Sascha Hauer 2015-11-18 8:11 ` Sascha Hauer 2015-11-10 12:05 ` Javi Merino 2015-11-10 12:05 ` Javi Merino 2015-11-10 18:26 ` Eduardo Valentin 2015-11-10 18:26 ` Eduardo Valentin 2015-11-11 7:27 ` Sascha Hauer 2015-11-11 7:27 ` Sascha Hauer 2015-11-11 9:40 ` Javi Merino 2015-11-11 9:40 ` Javi Merino 2015-11-11 9:40 ` Javi Merino 2015-11-13 10:09 ` Sascha Hauer 2015-11-13 10:09 ` Sascha Hauer 2015-11-13 11:26 ` Javi Merino 2015-11-13 11:26 ` Javi Merino 2015-11-18 8:18 ` Sascha Hauer 2015-11-18 8:18 ` Sascha Hauer 2015-11-09 10:13 ` [PATCH 3/3] ARM64: dts: mt8173: Add thermal/auxadc device nodes Sascha Hauer 2015-11-09 10:13 ` Sascha Hauer -- strict thread matches above, loose matches on Subject: below -- 2015-11-30 11:42 [PATCH v12] Add Mediatek thermal support Sascha Hauer 2015-11-30 11:42 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-11-30 11:42 ` Sascha Hauer 2015-12-17 19:33 ` Eduardo Valentin 2015-12-17 19:33 ` Eduardo Valentin 2016-01-04 14:19 ` Sascha Hauer 2016-01-04 14:19 ` Sascha Hauer 2016-01-19 7:29 ` Sascha Hauer 2016-01-19 7:29 ` Sascha Hauer 2016-02-01 2:54 ` Eddie Huang 2016-02-01 2:54 ` Eddie Huang 2016-02-01 2:54 ` Eddie Huang 2016-02-15 2:11 ` Daniel Kurtz 2016-02-15 2:11 ` Daniel Kurtz 2016-02-15 2:11 ` Daniel Kurtz 2016-02-15 2:14 ` Daniel Kurtz 2016-02-15 2:14 ` Daniel Kurtz 2016-02-15 2:14 ` Daniel Kurtz 2016-02-17 17:05 ` Matthias Brugger 2016-02-17 17:05 ` Matthias Brugger 2016-02-17 17:05 ` Matthias Brugger 2016-02-18 10:56 ` Sascha Hauer 2016-02-18 10:56 ` Sascha Hauer 2016-02-18 10:56 ` Sascha Hauer 2016-02-18 14:28 ` Javi Merino 2016-02-18 14:28 ` Javi Merino 2016-02-18 14:28 ` Javi Merino 2016-02-18 15:15 ` Eduardo Valentin 2016-02-18 15:15 ` Eduardo Valentin 2016-02-18 15:15 ` Eduardo Valentin 2016-02-19 7:21 ` Sascha Hauer 2016-02-19 7:21 ` Sascha Hauer 2016-02-19 7:21 ` Sascha Hauer 2015-12-21 4:07 ` Daniel Kurtz 2015-12-21 4:07 ` Daniel Kurtz 2015-12-21 4:07 ` Daniel Kurtz 2016-01-04 14:31 ` Sascha Hauer 2016-01-04 14:31 ` Sascha Hauer 2016-01-04 14:31 ` Sascha Hauer 2016-01-04 15:43 ` Daniel Kurtz 2016-01-04 15:43 ` Daniel Kurtz 2016-01-04 15:43 ` Daniel Kurtz 2015-11-18 8:24 [PATCH v11] Add Mediatek thermal support Sascha Hauer 2015-11-18 8:24 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-11-18 8:24 ` Sascha Hauer 2015-11-24 6:06 ` dawei chien 2015-11-24 6:06 ` dawei chien 2015-11-24 6:06 ` dawei chien 2015-11-24 7:53 ` Sascha Hauer 2015-11-24 7:53 ` Sascha Hauer 2015-09-23 13:37 [PATCH v9] Add Mediatek thermal support Sascha Hauer 2015-09-23 13:37 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-09-23 13:37 ` Sascha Hauer 2015-09-23 18:31 ` Vladimir Zapolskiy 2015-09-23 18:31 ` Vladimir Zapolskiy 2015-09-23 18:31 ` Vladimir Zapolskiy 2015-09-30 6:14 ` Sascha Hauer 2015-09-30 6:14 ` Sascha Hauer 2015-09-29 23:04 ` Eduardo Valentin 2015-09-29 23:04 ` Eduardo Valentin 2015-09-29 23:04 ` Eduardo Valentin 2015-09-30 6:13 ` Sascha Hauer 2015-09-30 6:13 ` Sascha Hauer 2015-09-30 9:36 ` Punit Agrawal 2015-09-30 9:36 ` Punit Agrawal 2015-09-30 9:36 ` Punit Agrawal 2015-09-30 10:37 ` Sascha Hauer 2015-09-30 10:37 ` Sascha Hauer 2015-09-30 11:07 ` Punit Agrawal 2015-09-30 11:07 ` Punit Agrawal 2015-08-31 7:34 [PATCH v8] Add Mediatek thermal support Sascha Hauer 2015-08-31 7:34 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-31 7:34 ` Sascha Hauer 2015-08-31 7:34 ` Sascha Hauer 2015-09-14 7:32 ` Daniel Kurtz 2015-09-14 7:32 ` Daniel Kurtz 2015-09-14 7:32 ` Daniel Kurtz 2015-09-22 7:30 ` Daniel Kurtz 2015-09-22 7:30 ` Daniel Kurtz 2015-09-22 7:30 ` Daniel Kurtz 2015-09-22 8:30 ` Sascha Hauer 2015-09-22 8:30 ` Sascha Hauer 2015-09-22 8:30 ` Sascha Hauer 2015-08-27 6:41 [PATCH v7] Add Mediatek thermal support Sascha Hauer 2015-08-27 6:41 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-27 11:50 ` Punit Agrawal 2015-08-26 13:58 [PATCH v6] Add Mediatek thermal support Sascha Hauer 2015-08-26 13:58 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-20 8:05 [PATCH v5] Add Mediatek thermal support Sascha Hauer 2015-08-20 8:06 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-20 22:20 ` Eduardo Valentin 2015-08-20 22:29 ` Daniel Lezcano 2015-08-21 5:06 ` Sascha Hauer 2015-08-20 23:12 ` Daniel Lezcano 2015-08-26 13:54 ` Sascha Hauer 2015-08-26 14:02 ` Daniel Lezcano 2015-08-25 17:41 ` Daniel Kurtz 2015-08-07 13:55 [PATCH v4] Add Mediatek thermal support Sascha Hauer 2015-08-07 13:55 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-11 7:03 ` Daniel Kurtz 2015-08-20 7:57 ` Sascha Hauer 2015-08-05 12:25 [PATCH v3] Add Mediatek thermal support Sascha Hauer 2015-08-05 12:25 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-08-05 18:02 ` Daniel Kurtz 2015-08-06 8:10 ` Sascha Hauer 2015-07-21 7:59 [PATCH v2] Add Mediatek thermal support Sascha Hauer 2015-07-21 7:59 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-07-21 7:59 ` Sascha Hauer 2015-07-21 15:13 ` Daniel Kurtz 2015-07-21 15:13 ` Daniel Kurtz 2015-07-21 15:13 ` Daniel Kurtz 2015-08-05 10:20 ` Sascha Hauer 2015-08-05 10:20 ` Sascha Hauer 2015-08-05 10:20 ` Sascha Hauer 2015-07-13 10:34 [PATCH] thermal: Add Mediatek thermal support Sascha Hauer 2015-07-13 10:34 ` [PATCH 2/3] thermal: Add Mediatek thermal controller support Sascha Hauer 2015-07-13 10:34 ` Sascha Hauer
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