All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jon Hunter <jonathanh@nvidia.com>
To: Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Jiang Liu <jiang.liu@linux.intel.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>
Cc: Kevin Hilman <khilman@kernel.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Grygorii Strashko <grygorii.strashko@ti.com>,
	Lars-Peter Clausen <lars@metafoo.de>,
	Linus Walleij <linus.walleij@linaro.org>,
	Soren Brinkmann <soren.brinkmann@xilinx.com>,
	linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
	Jon Hunter <jonathanh@nvidia.com>
Subject: [RFC PATCH V2 5/8] irqchip/gic: Return an error if GIC initialisation fails
Date: Thu, 17 Dec 2015 10:48:26 +0000	[thread overview]
Message-ID: <1450349309-8107-6-git-send-email-jonathanh@nvidia.com> (raw)
In-Reply-To: <1450349309-8107-1-git-send-email-jonathanh@nvidia.com>

If the GIC initialisation fails, then currently we do not return an error
or clean-up afterwards. Although for root controllers, this failure may be
fatal anyway, for secondary controllers, it may not be fatal and so return
an error on failure and clean-up.

Also for non-banked GIC controllers, make sure that we free any memory
allocated if we fail to initialise the IRQ domain.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/irqchip/irq-gic.c | 56 +++++++++++++++++++++++++++++++++--------------
 1 file changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 561a5cb5b8bc..5d1f1d4396c2 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1032,30 +1032,30 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
 	.unmap = gic_irq_domain_unmap,
 };
 
-static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
+static int __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 			   void __iomem *dist_base, void __iomem *cpu_base,
 			   u32 percpu_offset, struct fwnode_handle *handle)
 {
 	irq_hw_number_t hwirq_base;
 	struct gic_chip_data *gic;
-	int gic_irqs, irq_base, i;
+	int gic_irqs, irq_base, i, ret;
 
 	BUG_ON(gic_nr >= MAX_GIC_NR);
 
 	gic_check_cpu_features();
 
 	gic = &gic_data[gic_nr];
-#ifdef CONFIG_GIC_NON_BANKED
-	if (percpu_offset) { /* Frankein-GIC without banked registers... */
+
+	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) {
+		/* Frankein-GIC without banked registers... */
 		unsigned int cpu;
 
 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
 		if (WARN_ON(!gic->dist_base.percpu_base ||
 			    !gic->cpu_base.percpu_base)) {
-			free_percpu(gic->dist_base.percpu_base);
-			free_percpu(gic->cpu_base.percpu_base);
-			return;
+			ret = -ENOMEM;
+			goto err;
 		}
 
 		for_each_possible_cpu(cpu) {
@@ -1067,9 +1067,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 		}
 
 		gic_set_base_accessor(gic, gic_get_percpu_base);
-	} else
-#endif
-	{			/* Normal, sane GIC... */
+	} else {
+		/* Normal, sane GIC... */
 		WARN(percpu_offset,
 		     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
 		     percpu_offset);
@@ -1119,8 +1118,10 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 					hwirq_base, &gic_irq_domain_ops, gic);
 	}
 
-	if (WARN_ON(!gic->domain))
-		return;
+	if (WARN_ON(!gic->domain)) {
+		ret = -ENODEV;
+		goto err;
+	}
 
 	if (gic_nr == 0) {
 		/*
@@ -1142,6 +1143,16 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic_dist_init(gic);
 	gic_cpu_init(gic);
 	gic_pm_init(gic);
+
+	return 0;
+
+err:
+	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) {
+		free_percpu(gic->dist_base.percpu_base);
+		free_percpu(gic->cpu_base.percpu_base);
+	}
+
+	return ret;
 }
 
 void __init gic_init(unsigned int gic_nr, int irq_start,
@@ -1202,7 +1213,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	void __iomem *cpu_base;
 	void __iomem *dist_base;
 	u32 percpu_offset;
-	int irq;
+	int irq, ret;
 
 	if (WARN_ON(!node))
 		return -ENODEV;
@@ -1227,8 +1238,14 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
 		percpu_offset = 0;
 
-	__gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
+	ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
 			 &node->fwnode);
+	if (ret) {
+		iounmap(dist_base);
+		iounmap(cpu_base);
+		return ret;
+	}
+
 	if (!gic_cnt)
 		gic_init_physaddr(node);
 
@@ -1317,7 +1334,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
 	struct acpi_madt_generic_distributor *dist;
 	void __iomem *cpu_base, *dist_base;
 	struct fwnode_handle *domain_handle;
-	int count;
+	int count, ret;
 
 	/* Collect CPU base addresses */
 	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
@@ -1360,7 +1377,14 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
 		return -ENOMEM;
 	}
 
-	__gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
+	ret = __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
+	if (ret) {
+		pr_err("Failed to initialise GIC\n");
+		irq_domain_free_fwnode(domain_handle);
+		iounmap(cpu_base);
+		iounmap(dist_base);
+		return ret;
+	}
 
 	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
 	return 0;
-- 
2.1.4

WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com>
To: Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Jiang Liu <jiang.liu@linux.intel.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>
Cc: Kevin Hilman <khilman@kernel.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Grygorii Strashko <grygorii.strashko@ti.com>,
	Lars-Peter Clausen <lars@metafoo.de>,
	Linus Walleij <linus.walleij@linaro.org>,
	Soren Brinkmann <soren.brinkmann@xilinx.com>,
	linux-kernel@vger.kernel.org, <linux-tegra@vger.kernel.org>,
	Jon Hunter <jonathanh@nvidia.com>
Subject: [RFC PATCH V2 5/8] irqchip/gic: Return an error if GIC initialisation fails
Date: Thu, 17 Dec 2015 10:48:26 +0000	[thread overview]
Message-ID: <1450349309-8107-6-git-send-email-jonathanh@nvidia.com> (raw)
In-Reply-To: <1450349309-8107-1-git-send-email-jonathanh@nvidia.com>

If the GIC initialisation fails, then currently we do not return an error
or clean-up afterwards. Although for root controllers, this failure may be
fatal anyway, for secondary controllers, it may not be fatal and so return
an error on failure and clean-up.

Also for non-banked GIC controllers, make sure that we free any memory
allocated if we fail to initialise the IRQ domain.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/irqchip/irq-gic.c | 56 +++++++++++++++++++++++++++++++++--------------
 1 file changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 561a5cb5b8bc..5d1f1d4396c2 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1032,30 +1032,30 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
 	.unmap = gic_irq_domain_unmap,
 };
 
-static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
+static int __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 			   void __iomem *dist_base, void __iomem *cpu_base,
 			   u32 percpu_offset, struct fwnode_handle *handle)
 {
 	irq_hw_number_t hwirq_base;
 	struct gic_chip_data *gic;
-	int gic_irqs, irq_base, i;
+	int gic_irqs, irq_base, i, ret;
 
 	BUG_ON(gic_nr >= MAX_GIC_NR);
 
 	gic_check_cpu_features();
 
 	gic = &gic_data[gic_nr];
-#ifdef CONFIG_GIC_NON_BANKED
-	if (percpu_offset) { /* Frankein-GIC without banked registers... */
+
+	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) {
+		/* Frankein-GIC without banked registers... */
 		unsigned int cpu;
 
 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
 		if (WARN_ON(!gic->dist_base.percpu_base ||
 			    !gic->cpu_base.percpu_base)) {
-			free_percpu(gic->dist_base.percpu_base);
-			free_percpu(gic->cpu_base.percpu_base);
-			return;
+			ret = -ENOMEM;
+			goto err;
 		}
 
 		for_each_possible_cpu(cpu) {
@@ -1067,9 +1067,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 		}
 
 		gic_set_base_accessor(gic, gic_get_percpu_base);
-	} else
-#endif
-	{			/* Normal, sane GIC... */
+	} else {
+		/* Normal, sane GIC... */
 		WARN(percpu_offset,
 		     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
 		     percpu_offset);
@@ -1119,8 +1118,10 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 					hwirq_base, &gic_irq_domain_ops, gic);
 	}
 
-	if (WARN_ON(!gic->domain))
-		return;
+	if (WARN_ON(!gic->domain)) {
+		ret = -ENODEV;
+		goto err;
+	}
 
 	if (gic_nr == 0) {
 		/*
@@ -1142,6 +1143,16 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic_dist_init(gic);
 	gic_cpu_init(gic);
 	gic_pm_init(gic);
+
+	return 0;
+
+err:
+	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) {
+		free_percpu(gic->dist_base.percpu_base);
+		free_percpu(gic->cpu_base.percpu_base);
+	}
+
+	return ret;
 }
 
 void __init gic_init(unsigned int gic_nr, int irq_start,
@@ -1202,7 +1213,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	void __iomem *cpu_base;
 	void __iomem *dist_base;
 	u32 percpu_offset;
-	int irq;
+	int irq, ret;
 
 	if (WARN_ON(!node))
 		return -ENODEV;
@@ -1227,8 +1238,14 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
 		percpu_offset = 0;
 
-	__gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
+	ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
 			 &node->fwnode);
+	if (ret) {
+		iounmap(dist_base);
+		iounmap(cpu_base);
+		return ret;
+	}
+
 	if (!gic_cnt)
 		gic_init_physaddr(node);
 
@@ -1317,7 +1334,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
 	struct acpi_madt_generic_distributor *dist;
 	void __iomem *cpu_base, *dist_base;
 	struct fwnode_handle *domain_handle;
-	int count;
+	int count, ret;
 
 	/* Collect CPU base addresses */
 	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
@@ -1360,7 +1377,14 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
 		return -ENOMEM;
 	}
 
-	__gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
+	ret = __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
+	if (ret) {
+		pr_err("Failed to initialise GIC\n");
+		irq_domain_free_fwnode(domain_handle);
+		iounmap(cpu_base);
+		iounmap(dist_base);
+		return ret;
+	}
 
 	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
 	return 0;
-- 
2.1.4


  parent reply	other threads:[~2015-12-17 10:48 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-17 10:48 [RFC PATCH V2 0/8] Add support for Tegra210 AGIC Jon Hunter
2015-12-17 10:48 ` Jon Hunter
2015-12-17 10:48 ` [RFC PATCH V2 1/8] irqdomain: Ensure type settings match for an existing mapping Jon Hunter
2015-12-17 10:48   ` Jon Hunter
2015-12-17 13:16   ` Linus Walleij
     [not found]     ` <CACRpkdYPvMfqou7t9K_5=Ojx3U_sc8B2Zkxgeu=1JXxCUU_E2Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-12-18 10:10       ` Jon Hunter
2015-12-18 10:10         ` Jon Hunter
2015-12-22  9:58         ` Linus Walleij
     [not found]           ` <CACRpkdbjRiW8gcZcifHLELjBukpsCKyTQ+NpP51+v3kYLDcPHA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-12-22 10:00             ` Linus Walleij
2015-12-22 10:00               ` Linus Walleij
     [not found]               ` <CACRpkdasLeVyE7MXyJ=LQHSYxUDE77VttX_TdqMV6afgk_NqrQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-12-22 11:27                 ` Jon Hunter
2015-12-22 11:27                   ` Jon Hunter
2015-12-22 11:31                 ` Grygorii Strashko
2015-12-22 11:31                   ` Grygorii Strashko
     [not found] ` <1450349309-8107-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-17 10:48   ` [RFC PATCH V2 2/8] irqdomain: Don't set type when mapping an IRQ Jon Hunter
2015-12-17 10:48     ` Jon Hunter
     [not found]     ` <1450349309-8107-3-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-17 12:18       ` Linus Walleij
2015-12-17 12:18         ` Linus Walleij
2015-12-22 11:18       ` Grygorii Strashko
2015-12-22 11:18         ` Grygorii Strashko
     [not found]         ` <56793191.30502-l0cyMroinI0@public.gmane.org>
2015-12-22 11:56           ` Jon Hunter
2015-12-22 11:56             ` Jon Hunter
     [not found]             ` <56793A5B.4040302-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-03-18  9:16               ` Geert Uytterhoeven
2016-03-18  9:16                 ` Geert Uytterhoeven
2015-12-17 10:48   ` [RFC PATCH V2 3/8] genirq: Add runtime power management support for IRQ chips Jon Hunter
2015-12-17 10:48     ` Jon Hunter
2015-12-17 13:19     ` Linus Walleij
2015-12-18 10:20       ` Jon Hunter
2016-01-12 18:40     ` Grygorii Strashko
2016-01-12 18:40       ` Grygorii Strashko
2016-01-12 21:43       ` Sören Brinkmann
2016-01-12 21:43         ` Sören Brinkmann
     [not found]     ` <1450349309-8107-4-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-01-18 14:47       ` Ulf Hansson
2016-01-18 14:47         ` Ulf Hansson
2016-01-19 10:43         ` Jon Hunter
2016-01-20 15:30           ` Thomas Gleixner
2016-01-21  8:38             ` Jon Hunter
2016-01-21  8:38               ` Jon Hunter
2016-01-21 12:40             ` Ulf Hansson
2016-01-21 12:40               ` Ulf Hansson
2016-01-21 12:40               ` Ulf Hansson
2016-01-21 19:51               ` Thomas Gleixner
2016-01-22 11:08                 ` Ulf Hansson
2016-01-22 11:08                   ` Ulf Hansson
2016-01-26 17:17                   ` Thomas Gleixner
2016-02-05 14:37                 ` Linus Walleij
2016-02-05 14:37                   ` Linus Walleij
     [not found]                   ` <CACRpkdbE-Ny585yK+DBkNENpWyk8rSEvdRdvLgMTCBp13grp4w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-03-18 13:57                     ` Grygorii Strashko
2016-03-18 13:57                       ` Grygorii Strashko
2015-12-17 10:48 ` [RFC PATCH V2 4/8] irqchip/gic: Don't initialise chip if mapping IO space fails Jon Hunter
2015-12-17 10:48   ` Jon Hunter
     [not found]   ` <1450349309-8107-5-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-17 13:21     ` Linus Walleij
2015-12-17 13:21       ` Linus Walleij
2015-12-17 10:48 ` Jon Hunter [this message]
2015-12-17 10:48   ` [RFC PATCH V2 5/8] irqchip/gic: Return an error if GIC initialisation fails Jon Hunter
     [not found]   ` <1450349309-8107-6-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-17 13:26     ` Linus Walleij
2015-12-17 13:26       ` Linus Walleij
     [not found]       ` <CACRpkdaw+DM5ddi27UpJEg-+3A3ffS7k_Qnm4i-w2rLhpxp+8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-12-18 10:24         ` Jon Hunter
2015-12-18 10:24           ` Jon Hunter
2015-12-17 10:48 ` [RFC PATCH V2 6/8] irqchip/gic: Assign irqchip dynamically Jon Hunter
2015-12-17 10:48   ` Jon Hunter
     [not found]   ` <1450349309-8107-7-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-17 11:00     ` Marc Zyngier
2015-12-17 11:00       ` Marc Zyngier
     [not found]       ` <567295B5.8050900-5wv7dgnIgG8@public.gmane.org>
2015-12-18 10:26         ` Jon Hunter
2015-12-18 10:26           ` Jon Hunter
2015-12-17 10:48 ` [RFC PATCH V2 7/8] irqchip/gic: Prepare for adding platform driver Jon Hunter
2015-12-17 10:48   ` Jon Hunter
2015-12-17 10:48 ` [RFC PATCH V2 8/8] irqchip/gic: Add support for tegra AGIC interrupt controller Jon Hunter
2015-12-17 10:48   ` Jon Hunter
2015-12-17 10:58   ` Jon Hunter
2015-12-17 10:58     ` Jon Hunter
     [not found]   ` <1450349309-8107-9-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-17 13:32     ` Linus Walleij
2015-12-17 13:32       ` Linus Walleij
2015-12-18 10:44       ` Jon Hunter
     [not found]         ` <5673E38B.7060702-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-12-22 10:03           ` Linus Walleij
2015-12-22 10:03             ` Linus Walleij

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1450349309-8107-6-git-send-email-jonathanh@nvidia.com \
    --to=jonathanh@nvidia.com \
    --cc=geert@linux-m68k.org \
    --cc=grygorii.strashko@ti.com \
    --cc=jason@lakedaemon.net \
    --cc=jiang.liu@linux.intel.com \
    --cc=khilman@kernel.org \
    --cc=lars@metafoo.de \
    --cc=linus.walleij@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=soren.brinkmann@xilinx.com \
    --cc=swarren@wwwdotorg.org \
    --cc=tglx@linutronix.de \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.