From: Jon Hunter <jonathanh@nvidia.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com>, Jiang Liu <jiang.liu@linux.intel.com>, Stephen Warren <swarren@wwwdotorg.org>, Thierry Reding <thierry.reding@gmail.com> Cc: Kevin Hilman <khilman@kernel.org>, Geert Uytterhoeven <geert@linux-m68k.org>, Grygorii Strashko <grygorii.strashko@ti.com>, Lars-Peter Clausen <lars@metafoo.de>, Linus Walleij <linus.walleij@linaro.org>, Soren Brinkmann <soren.brinkmann@xilinx.com>, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [RFC PATCH V2 8/8] irqchip/gic: Add support for tegra AGIC interrupt controller Date: Thu, 17 Dec 2015 10:58:52 +0000 [thread overview] Message-ID: <5672956C.5010904@nvidia.com> (raw) In-Reply-To: <1450349309-8107-9-git-send-email-jonathanh@nvidia.com> On 17/12/15 10:48, Jon Hunter wrote: > Add a driver for the Tegra-AGIC interrupt controller which is compatible > with the ARM GIC-400 interrupt controller. > > The Tegra AGIC (Audio GIC) is part of the Audio Processing Engine (APE) on > Tegra210 and can route interrupts to either the GIC for the CPU subsystem > or the Audio DSP (ADSP) within the APE. The AGIC uses CPU interface 0 to > route interrupts to the CPU GIC and CPU interface 1 to route interrupts to > the ADSP. > > The APE is located within its own power domain on the chip and so the > AGIC needs to manage both the power domain and its clocks. Commit > afbbd2338176 ("irqchip/gic: Document optional Clock and Power Domain > properties") adding clock and power-domain properties to the GIC binding > and so the aim would be to make use of these to handle power management > (however, this is very much dependent upon adding support for generic > PM domains for Tegra which is still a work-in-progress). > > With the AGIC being located in a different power domain to the main CPU > cluster this means that: > 1. The interrupt controller cannot be registered via IRQCHIP_DECLARE() > because it needs to be registered as a platform device so that the > generic PM domain core will ensure that the power domain is available > before probing. > 2. The interrupt controller cannot be suspended/restored based upon > changes in the CPU power state and needs to use runtime-pm instead. > > This is very much a work-in-progress and there are still a few items that > need to be resolved. These items are: > 1. Currently the GIC platform driver only supports non-root GICs. The > platform driver performs a save and restore of PPI interrupts for > non-root GICs, which is probably not necessary and so could be changed. > At a minimum we need to re-enable the CPU interface during the device > resume but we could skip the restoration of the PPIs. In general we > could update the driver to only save and restore PPIs for the root > controller, if that makes sense. > 2. Currently routing of interrupts to the ADSP for Tegra210 is not > supported by this driver. Although the ADSP on Tegra210 could also setup > the AGIC distributor having two independent subsystems configure the > distributor does not seem like a good idea. Given that the ADSP is a > slave and would be under the control of the kernel via its own driver, > it would seem best that only the kernel configures the distributors > routing of the interrupts. This could be achieved by adding a new genirq > API to migrate the interrupt. The GIC driver already has an API to > migrate all interrupts from one CPU interface to another (which I > understand is for a different reason), but having an generic API to > migrate an interrupt to another device could be useful (unless something > already exists that I have overlooked). > > Please let me know if you have any thoughts/opinions on the above. > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > --- > drivers/irqchip/irq-gic.c | 330 +++++++++++++++++++++++++++++++++++----------- > 1 file changed, 253 insertions(+), 77 deletions(-) [snip] > +#ifdef CONFIG_PM_SLEEP > +static int gic_resume(struct device *dev) > +{ > + int ret; > + > + ret = gic_runtime_resume(dev); > + if (ret < 0) > + return ret; > + > + pm_runtime_enable(dev); > + > + return 0; > +} > + > +static int gic_suspend(struct device *dev) > +{ > + pm_runtime_disable(dev); > + if (!pm_runtime_status_suspended(dev)) > + return gic_runtime_suspend(dev); > + > + return 0; > +} > +#endif > + > +static const struct dev_pm_ops gic_pm_ops = { > + SET_RUNTIME_PM_OPS(gic_runtime_suspend, > + gic_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(gic_suspend, gic_resume) > +}; I believe these need to be the noirq variants. Will fix. Jon
WARNING: multiple messages have this Message-ID (diff)
From: Jon Hunter <jonathanh@nvidia.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com>, Jiang Liu <jiang.liu@linux.intel.com>, Stephen Warren <swarren@wwwdotorg.org>, Thierry Reding <thierry.reding@gmail.com> Cc: Kevin Hilman <khilman@kernel.org>, Geert Uytterhoeven <geert@linux-m68k.org>, Grygorii Strashko <grygorii.strashko@ti.com>, Lars-Peter Clausen <lars@metafoo.de>, Linus Walleij <linus.walleij@linaro.org>, Soren Brinkmann <soren.brinkmann@xilinx.com>, <linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org> Subject: Re: [RFC PATCH V2 8/8] irqchip/gic: Add support for tegra AGIC interrupt controller Date: Thu, 17 Dec 2015 10:58:52 +0000 [thread overview] Message-ID: <5672956C.5010904@nvidia.com> (raw) In-Reply-To: <1450349309-8107-9-git-send-email-jonathanh@nvidia.com> On 17/12/15 10:48, Jon Hunter wrote: > Add a driver for the Tegra-AGIC interrupt controller which is compatible > with the ARM GIC-400 interrupt controller. > > The Tegra AGIC (Audio GIC) is part of the Audio Processing Engine (APE) on > Tegra210 and can route interrupts to either the GIC for the CPU subsystem > or the Audio DSP (ADSP) within the APE. The AGIC uses CPU interface 0 to > route interrupts to the CPU GIC and CPU interface 1 to route interrupts to > the ADSP. > > The APE is located within its own power domain on the chip and so the > AGIC needs to manage both the power domain and its clocks. Commit > afbbd2338176 ("irqchip/gic: Document optional Clock and Power Domain > properties") adding clock and power-domain properties to the GIC binding > and so the aim would be to make use of these to handle power management > (however, this is very much dependent upon adding support for generic > PM domains for Tegra which is still a work-in-progress). > > With the AGIC being located in a different power domain to the main CPU > cluster this means that: > 1. The interrupt controller cannot be registered via IRQCHIP_DECLARE() > because it needs to be registered as a platform device so that the > generic PM domain core will ensure that the power domain is available > before probing. > 2. The interrupt controller cannot be suspended/restored based upon > changes in the CPU power state and needs to use runtime-pm instead. > > This is very much a work-in-progress and there are still a few items that > need to be resolved. These items are: > 1. Currently the GIC platform driver only supports non-root GICs. The > platform driver performs a save and restore of PPI interrupts for > non-root GICs, which is probably not necessary and so could be changed. > At a minimum we need to re-enable the CPU interface during the device > resume but we could skip the restoration of the PPIs. In general we > could update the driver to only save and restore PPIs for the root > controller, if that makes sense. > 2. Currently routing of interrupts to the ADSP for Tegra210 is not > supported by this driver. Although the ADSP on Tegra210 could also setup > the AGIC distributor having two independent subsystems configure the > distributor does not seem like a good idea. Given that the ADSP is a > slave and would be under the control of the kernel via its own driver, > it would seem best that only the kernel configures the distributors > routing of the interrupts. This could be achieved by adding a new genirq > API to migrate the interrupt. The GIC driver already has an API to > migrate all interrupts from one CPU interface to another (which I > understand is for a different reason), but having an generic API to > migrate an interrupt to another device could be useful (unless something > already exists that I have overlooked). > > Please let me know if you have any thoughts/opinions on the above. > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > --- > drivers/irqchip/irq-gic.c | 330 +++++++++++++++++++++++++++++++++++----------- > 1 file changed, 253 insertions(+), 77 deletions(-) [snip] > +#ifdef CONFIG_PM_SLEEP > +static int gic_resume(struct device *dev) > +{ > + int ret; > + > + ret = gic_runtime_resume(dev); > + if (ret < 0) > + return ret; > + > + pm_runtime_enable(dev); > + > + return 0; > +} > + > +static int gic_suspend(struct device *dev) > +{ > + pm_runtime_disable(dev); > + if (!pm_runtime_status_suspended(dev)) > + return gic_runtime_suspend(dev); > + > + return 0; > +} > +#endif > + > +static const struct dev_pm_ops gic_pm_ops = { > + SET_RUNTIME_PM_OPS(gic_runtime_suspend, > + gic_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(gic_suspend, gic_resume) > +}; I believe these need to be the noirq variants. Will fix. Jon
next prev parent reply other threads:[~2015-12-17 10:58 UTC|newest] Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-12-17 10:48 [RFC PATCH V2 0/8] Add support for Tegra210 AGIC Jon Hunter 2015-12-17 10:48 ` Jon Hunter 2015-12-17 10:48 ` [RFC PATCH V2 1/8] irqdomain: Ensure type settings match for an existing mapping Jon Hunter 2015-12-17 10:48 ` Jon Hunter 2015-12-17 13:16 ` Linus Walleij [not found] ` <CACRpkdYPvMfqou7t9K_5=Ojx3U_sc8B2Zkxgeu=1JXxCUU_E2Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-12-18 10:10 ` Jon Hunter 2015-12-18 10:10 ` Jon Hunter 2015-12-22 9:58 ` Linus Walleij [not found] ` <CACRpkdbjRiW8gcZcifHLELjBukpsCKyTQ+NpP51+v3kYLDcPHA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-12-22 10:00 ` Linus Walleij 2015-12-22 10:00 ` Linus Walleij [not found] ` <CACRpkdasLeVyE7MXyJ=LQHSYxUDE77VttX_TdqMV6afgk_NqrQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-12-22 11:27 ` Jon Hunter 2015-12-22 11:27 ` Jon Hunter 2015-12-22 11:31 ` Grygorii Strashko 2015-12-22 11:31 ` Grygorii Strashko [not found] ` <1450349309-8107-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-17 10:48 ` [RFC PATCH V2 2/8] irqdomain: Don't set type when mapping an IRQ Jon Hunter 2015-12-17 10:48 ` Jon Hunter [not found] ` <1450349309-8107-3-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-17 12:18 ` Linus Walleij 2015-12-17 12:18 ` Linus Walleij 2015-12-22 11:18 ` Grygorii Strashko 2015-12-22 11:18 ` Grygorii Strashko [not found] ` <56793191.30502-l0cyMroinI0@public.gmane.org> 2015-12-22 11:56 ` Jon Hunter 2015-12-22 11:56 ` Jon Hunter [not found] ` <56793A5B.4040302-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-03-18 9:16 ` Geert Uytterhoeven 2016-03-18 9:16 ` Geert Uytterhoeven 2015-12-17 10:48 ` [RFC PATCH V2 3/8] genirq: Add runtime power management support for IRQ chips Jon Hunter 2015-12-17 10:48 ` Jon Hunter 2015-12-17 13:19 ` Linus Walleij 2015-12-18 10:20 ` Jon Hunter 2016-01-12 18:40 ` Grygorii Strashko 2016-01-12 18:40 ` Grygorii Strashko 2016-01-12 21:43 ` Sören Brinkmann 2016-01-12 21:43 ` Sören Brinkmann [not found] ` <1450349309-8107-4-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-01-18 14:47 ` Ulf Hansson 2016-01-18 14:47 ` Ulf Hansson 2016-01-19 10:43 ` Jon Hunter 2016-01-20 15:30 ` Thomas Gleixner 2016-01-21 8:38 ` Jon Hunter 2016-01-21 8:38 ` Jon Hunter 2016-01-21 12:40 ` Ulf Hansson 2016-01-21 12:40 ` Ulf Hansson 2016-01-21 12:40 ` Ulf Hansson 2016-01-21 19:51 ` Thomas Gleixner 2016-01-22 11:08 ` Ulf Hansson 2016-01-22 11:08 ` Ulf Hansson 2016-01-26 17:17 ` Thomas Gleixner 2016-02-05 14:37 ` Linus Walleij 2016-02-05 14:37 ` Linus Walleij [not found] ` <CACRpkdbE-Ny585yK+DBkNENpWyk8rSEvdRdvLgMTCBp13grp4w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-03-18 13:57 ` Grygorii Strashko 2016-03-18 13:57 ` Grygorii Strashko 2015-12-17 10:48 ` [RFC PATCH V2 4/8] irqchip/gic: Don't initialise chip if mapping IO space fails Jon Hunter 2015-12-17 10:48 ` Jon Hunter [not found] ` <1450349309-8107-5-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-17 13:21 ` Linus Walleij 2015-12-17 13:21 ` Linus Walleij 2015-12-17 10:48 ` [RFC PATCH V2 5/8] irqchip/gic: Return an error if GIC initialisation fails Jon Hunter 2015-12-17 10:48 ` Jon Hunter [not found] ` <1450349309-8107-6-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-17 13:26 ` Linus Walleij 2015-12-17 13:26 ` Linus Walleij [not found] ` <CACRpkdaw+DM5ddi27UpJEg-+3A3ffS7k_Qnm4i-w2rLhpxp+8g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2015-12-18 10:24 ` Jon Hunter 2015-12-18 10:24 ` Jon Hunter 2015-12-17 10:48 ` [RFC PATCH V2 6/8] irqchip/gic: Assign irqchip dynamically Jon Hunter 2015-12-17 10:48 ` Jon Hunter [not found] ` <1450349309-8107-7-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-17 11:00 ` Marc Zyngier 2015-12-17 11:00 ` Marc Zyngier [not found] ` <567295B5.8050900-5wv7dgnIgG8@public.gmane.org> 2015-12-18 10:26 ` Jon Hunter 2015-12-18 10:26 ` Jon Hunter 2015-12-17 10:48 ` [RFC PATCH V2 7/8] irqchip/gic: Prepare for adding platform driver Jon Hunter 2015-12-17 10:48 ` Jon Hunter 2015-12-17 10:48 ` [RFC PATCH V2 8/8] irqchip/gic: Add support for tegra AGIC interrupt controller Jon Hunter 2015-12-17 10:48 ` Jon Hunter 2015-12-17 10:58 ` Jon Hunter [this message] 2015-12-17 10:58 ` Jon Hunter [not found] ` <1450349309-8107-9-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-17 13:32 ` Linus Walleij 2015-12-17 13:32 ` Linus Walleij 2015-12-18 10:44 ` Jon Hunter [not found] ` <5673E38B.7060702-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2015-12-22 10:03 ` Linus Walleij 2015-12-22 10:03 ` Linus Walleij
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