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From: "Cédric Le Goater" <clg@fr.ibm.com>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: Thomas Huth <thuth@redhat.com>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs
Date: Mon, 14 Mar 2016 17:56:25 +0100	[thread overview]
Message-ID: <1457974600-13828-3-git-send-email-clg@fr.ibm.com> (raw)
In-Reply-To: <1457974600-13828-1-git-send-email-clg@fr.ibm.com>

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

The current set of spr_register_* macros only take the user and
supervisor function pointers. To make the transition easy, we
don't change that but we add "_hv" variants that can be used to
register all 3 sets.

To simplify the transition, users of the "old" macro will set the
hypervisor callback to be the same as the supervisor one. The new
registration function only needs to be used for registers that are
either hypervisor only or behave differently in HV mode.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target-ppc/translate.c      | 26 ++++++++++++++++----------
 target-ppc/translate_init.c | 35 +++++++++++++++++++++++++++++++----
 2 files changed, 47 insertions(+), 14 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e402ff920314..327f3259b4be 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4282,14 +4282,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
     void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
     uint32_t sprn = SPR(ctx->opcode);
 
-#if !defined(CONFIG_USER_ONLY)
-    if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+    read_cb = ctx->spr_cb[sprn].uea_read;
+#else
+    if (ctx->pr) {
+        read_cb = ctx->spr_cb[sprn].uea_read;
+    } else if (ctx->hv) {
         read_cb = ctx->spr_cb[sprn].hea_read;
-    else if (!ctx->pr)
+    } else if (!ctx->pr) {
         read_cb = ctx->spr_cb[sprn].oea_read;
-    else
+    }
 #endif
-        read_cb = ctx->spr_cb[sprn].uea_read;
     if (likely(read_cb != NULL)) {
         if (likely(read_cb != SPR_NOACCESS)) {
             (*read_cb)(ctx, rD(ctx->opcode), sprn);
@@ -4437,14 +4440,17 @@ static void gen_mtspr(DisasContext *ctx)
     void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
     uint32_t sprn = SPR(ctx->opcode);
 
-#if !defined(CONFIG_USER_ONLY)
-    if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+    write_cb = ctx->spr_cb[sprn].uea_write;
+#else
+    if (ctx->pr) {
+        write_cb = ctx->spr_cb[sprn].uea_write;
+    } else if (ctx->hv) {
         write_cb = ctx->spr_cb[sprn].hea_write;
-    else if (!ctx->pr)
+    } else {
         write_cb = ctx->spr_cb[sprn].oea_write;
-    else
+    }
 #endif
-        write_cb = ctx->spr_cb[sprn].uea_write;
     if (likely(write_cb != NULL)) {
         if (likely(write_cb != SPR_NOACCESS)) {
             (*write_cb)(ctx, sprn, rS(ctx->opcode));
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index fb206aff29ad..6a11b41206e5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -579,17 +579,33 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
 #define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
                          oea_read, oea_write, one_reg_id, initial_value)       \
     _spr_register(env, num, name, uea_read, uea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
+                            oea_read, oea_write, hea_read, hea_write,          \
+                            one_reg_id, initial_value)                         \
+    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 #else
 #if !defined(CONFIG_KVM)
 #define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
-                         oea_read, oea_write, one_reg_id, initial_value) \
+                         oea_read, oea_write, one_reg_id, initial_value)       \
+    _spr_register(env, num, name, uea_read, uea_write,                         \
+                  oea_read, oea_write, oea_read, oea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
+                            oea_read, oea_write, hea_read, hea_write,          \
+                            one_reg_id, initial_value)                         \
     _spr_register(env, num, name, uea_read, uea_write,                         \
-                  oea_read, oea_write, initial_value)
+                  oea_read, oea_write, hea_read, hea_write, initial_value)
 #else
 #define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
-                         oea_read, oea_write, one_reg_id, initial_value) \
+                         oea_read, oea_write, one_reg_id, initial_value)       \
+    _spr_register(env, num, name, uea_read, uea_write,                         \
+                  oea_read, oea_write, oea_read, oea_write,                    \
+                  one_reg_id, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
+                            oea_read, oea_write, hea_read, hea_write,          \
+                            one_reg_id, initial_value)                         \
     _spr_register(env, num, name, uea_read, uea_write,                         \
-                  oea_read, oea_write, one_reg_id, initial_value)
+                  oea_read, oea_write, hea_read, hea_write,                    \
+                  one_reg_id, initial_value)
 #endif
 #endif
 
@@ -598,6 +614,13 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
     spr_register_kvm(env, num, name, uea_read, uea_write,                      \
                      oea_read, oea_write, 0, initial_value)
 
+#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
+                        oea_read, oea_write, hea_read, hea_write,              \
+                        initial_value)                                         \
+    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
+                        oea_read, oea_write, hea_read, hea_write,              \
+                        0, initial_value)
+
 static inline void _spr_register(CPUPPCState *env, int num,
                                  const char *name,
                                  void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
@@ -606,6 +629,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
 
                                  void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
                                  void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
+                                 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
+                                 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
 #endif
 #if defined(CONFIG_KVM)
                                  uint64_t one_reg_id,
@@ -633,6 +658,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
 #if !defined(CONFIG_USER_ONLY)
     spr->oea_read = oea_read;
     spr->oea_write = oea_write;
+    spr->hea_read = hea_read;
+    spr->hea_write = hea_write;
 #endif
 #if defined(CONFIG_KVM)
     spr->one_reg_id = one_reg_id,
-- 
2.1.4

  parent reply	other threads:[~2016-03-14 16:57 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
2016-03-14 18:34   ` Thomas Huth
2016-03-14 16:56 ` Cédric Le Goater [this message]
2016-03-14 18:50   ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
2016-03-14 19:14   ` Thomas Huth
2016-03-15  9:43     ` David Gibson
2016-03-15 10:49       ` Thomas Huth
2016-03-15 17:04         ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-03-16  1:04         ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
2016-03-14 19:20   ` Thomas Huth
2016-03-15  8:06     ` Cédric Le Goater
2016-03-15  8:21     ` Bharata B Rao
2016-03-15  9:45   ` David Gibson
2016-03-15 21:11     ` Benjamin Herrenschmidt
2016-03-16  0:41       ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
2016-03-14 19:29   ` Thomas Huth
2016-03-15  9:47     ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
2016-03-17  2:34   ` David Gibson
2016-03-17 12:33     ` Cédric Le Goater
2016-03-17 22:03       ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
2016-03-16  1:05   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
2016-03-14 19:32   ` Thomas Huth
2016-03-16  1:06   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
2016-03-14 19:37   ` Thomas Huth
2016-03-16  1:07     ` David Gibson
2016-03-16  1:07   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
2016-03-14 19:40   ` Thomas Huth
2016-03-16  1:08   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
2016-03-14 20:13   ` Thomas Huth
2016-03-16  1:09   ` David Gibson
2016-03-17  2:36   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
2016-03-14 20:26   ` Thomas Huth
2016-03-15  8:05     ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
2016-03-14 20:36   ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
2016-03-14 20:54   ` Thomas Huth
2016-03-14 21:07     ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-03-16  1:12   ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
2016-03-16  1:14   ` David Gibson
2016-03-16  6:17     ` Thomas Huth
2016-03-16  9:24       ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
2016-03-14 20:00   ` Thomas Huth
2016-03-16  1:14   ` David Gibson
2016-03-16  6:24     ` Thomas Huth
2016-03-16 22:28       ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
2016-03-14 20:08   ` Thomas Huth
2016-03-16  1:15   ` David Gibson
2016-03-15  0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
2016-03-15  8:11   ` Cédric Le Goater
2016-03-16  1:19     ` David Gibson
2016-03-16  9:08       ` Cédric Le Goater
2016-03-17  2:45         ` David Gibson
2016-03-17 14:28           ` Cédric Le Goater
2016-03-21  0:59             ` David Gibson

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