Re: [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions

[Thomas Huth <thuth@redhat.com>]

On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> Add definitions for additional SPR numbers and SPR bit definitions
> that will be relevant for subsequent improvements to POWER8 emulation
> 
> Also fix the definition of LPIDR which was incorrect (and is different
> for server and embedded).
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>  target-ppc/cpu.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++-------
>  1 file changed, 47 insertions(+), 7 deletions(-)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 8d90d862de17..9ce301f18922 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -474,9 +474,17 @@ struct ppc_slb_t {
>  #define MSR_RI   1  /* Recoverable interrupt                        1        */
>  #define MSR_LE   0  /* Little-endian mode                           1 hflags */
>  
> -#define LPCR_ILE (1 << (63-38))
> -#define LPCR_AIL_SHIFT (63-40)      /* Alternate interrupt location */
> -#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
> +/* LPCR bits */
> +#define LPCR_VPM0         (1ull << (63 - 0))
> +#define LPCR_VPM1         (1ull << (63 - 1))
> +#define LPCR_ISL          (1ull << (63 - 2))
> +#define LPCR_KBV          (1ull << (63 - 3))
> +#define LPCR_ILE          (1ull << (63 - 38))
> +#define LPCR_MER          (1ull << (63 - 52))
> +#define LPCR_LPES0        (1ull << (63 - 60))
> +#define LPCR_LPES1        (1ull << (63 - 61))
> +#define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
> +#define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
>  
>  #define msr_sf   ((env->msr >> MSR_SF)   & 1)
>  #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
> @@ -1381,6 +1389,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_MPC_ICTRL         (0x09E)
>  #define SPR_MPC_BAR           (0x09F)
>  #define SPR_PSPB              (0x09F)
> +#define SPR_DAWR              (0x0B4)
> +#define SPR_RPR               (0x0BA)
> +#define SPR_DAWRX             (0x0BC)
> +#define SPR_HFSCR             (0x0BE)
>  #define SPR_VRSAVE            (0x100)
>  #define SPR_USPRG0            (0x100)
>  #define SPR_USPRG1            (0x101)
> @@ -1435,19 +1447,25 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_HSRR1             (0x13B)
>  #define SPR_BOOKE_IAC4        (0x13B)
>  #define SPR_BOOKE_DAC1        (0x13C)
> -#define SPR_LPIDR             (0x13D)
> +#define SPR_MMCRH             (0x13C)
>  #define SPR_DABR2             (0x13D)
>  #define SPR_BOOKE_DAC2        (0x13D)
> +#define SPR_TFMR              (0x13D)
>  #define SPR_BOOKE_DVC1        (0x13E)
>  #define SPR_LPCR              (0x13E)
>  #define SPR_BOOKE_DVC2        (0x13F)
> +#define SPR_LPIDR             (0x13F)
>  #define SPR_BOOKE_TSR         (0x150)
> +#define SPR_HMER              (0x150)
> +#define SPR_HMEER             (0x151)
>  #define SPR_PCR               (0x152)
> +#define SPR_BOOKE_LPIDR       (0x152)
>  #define SPR_BOOKE_TCR         (0x154)
>  #define SPR_BOOKE_TLB0PS      (0x158)
>  #define SPR_BOOKE_TLB1PS      (0x159)
>  #define SPR_BOOKE_TLB2PS      (0x15A)
>  #define SPR_BOOKE_TLB3PS      (0x15B)
> +#define SPR_AMOR              (0x15D)
>  #define SPR_BOOKE_MAS7_MAS3   (0x174)
>  #define SPR_BOOKE_IVOR0       (0x190)
>  #define SPR_BOOKE_IVOR1       (0x191)
> @@ -1667,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_RCPU_L2U_RA3      (0x32B)
>  #define SPR_TAR               (0x32F)
>  #define SPR_VTB               (0x351)
> +#define SPR_MMCRC             (0x353)
>  #define SPR_440_INV0          (0x370)
>  #define SPR_440_INV1          (0x371)
>  #define SPR_440_INV2          (0x372)
> @@ -1705,6 +1724,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_440_DVLIM         (0x398)
>  #define SPR_750_WPAR          (0x399)
>  #define SPR_440_IVLIM         (0x399)
> +#define SPR_TSCR              (0x399)
>  #define SPR_750_DMAU          (0x39A)
>  #define SPR_750_DMAL          (0x39B)
>  #define SPR_440_RSTCFG        (0x39B)
> @@ -1879,9 +1899,10 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
>  
>  /* HID0 bits */
> -#define HID0_DEEPNAP        (1 << 24)
> -#define HID0_DOZE           (1 << 23)
> -#define HID0_NAP            (1 << 22)
> +#define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
> +#define HID0_DOZE           (1 << 23)           /* pre-2.06 */
> +#define HID0_NAP            (1 << 22)           /* pre-2.06 */
> +#define HID0_HILE           (1ull << (63 - 19)) /* POWER8 */
>  
>  /*****************************************************************************/
>  /* PowerPC Instructions types definitions                                    */
> @@ -2230,6 +2251,25 @@ enum {
>      PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
>  };
>  
> +/* HMER/HMEER */
> +enum {
> +    HMER_MALFUNCTION_ALERT      = 1ull << (63 - 0),
> +    HMER_PROC_RECV_DONE         = 1ull << (63 - 2),
> +    HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
> +    HMER_TFAC_ERROR             = 1ull << (63 - 4),
> +    HMER_TFMR_PARITY_ERROR      = 1ull << (63 - 5),
> +    HMER_XSCOM_FAIL             = 1ull << (63 - 8),
> +    HMER_XSCOM_DONE             = 1ull << (63 - 9),
> +    HMER_PROC_RECV_AGAIN        = 1ull << (63 - 11),
> +    HMER_WARN_RISE              = 1ull << (63 - 14),
> +    HMER_WARN_FALL              = 1ull << (63 - 15),
> +    HMER_SCOM_FIR_HMI           = 1ull << (63 - 16),
> +    HMER_TRIG_FIR_HMI           = 1ull << (63 - 17),
> +    HMER_HYP_RESOURCE_ERR       = 1ull << (63 - 20),
> +    HMER_XSCOM_STATUS_MASK      = 7ull << (63 - 23),
> +    HMER_XSCOM_STATUS_LSH       = (63 - 23),
> +};
> +
>  /*****************************************************************************/
>  
>  static inline target_ulong cpu_read_xer(CPUPPCState *env)
> 

Some of the definitions (MMCRH, MMCRC, TFMR, TSCR, HID0_HILE and most of
the HMER bits) are unfortunately not listed in the PowerISA spec, but
the definitions here match the definitions from the Linux kernel and/or
skiboot, so I assume they are OK. So:

Reviewed-by: Thomas Huth <thuth@redhat.com>