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From: Thomas Huth <thuth@redhat.com>
To: "Cédric Le Goater" <clg@fr.ibm.com>,
	"David Gibson" <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs
Date: Mon, 14 Mar 2016 21:08:06 +0100	[thread overview]
Message-ID: <56E71A26.6020702@redhat.com> (raw)
In-Reply-To: <1457974600-13828-18-git-send-email-clg@fr.ibm.com>

On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> ---
>  target-ppc/cpu.h            |  3 +++
>  target-ppc/translate_init.c | 12 ++++++++++++
>  2 files changed, 15 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 9e1ef10b7dc6..9ed406cf111b 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1359,7 +1359,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_SRR1              (0x01B)
>  #define SPR_CFAR              (0x01C)
>  #define SPR_AMR               (0x01D)
> +#define SPR_ACOP              (0x01F)
>  #define SPR_BOOKE_PID         (0x030)
> +#define SPR_BOOKS_PID         (0x030)
>  #define SPR_BOOKE_DECAR       (0x036)
>  #define SPR_BOOKE_CSRR0       (0x03A)
>  #define SPR_BOOKE_CSRR1       (0x03B)
> @@ -1713,6 +1715,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
>  #define SPR_POWER_SPMC1       (0x37C)
>  #define SPR_POWER_SPMC2       (0x37D)
>  #define SPR_POWER_MMCRS       (0x37E)
> +#define SPR_WORT              (0x37F)
>  #define SPR_PPR               (0x380)
>  #define SPR_750_GQR0          (0x390)
>  #define SPR_440_DNV0          (0x390)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index f88bdf7b3cd1..22afeef2731a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8175,6 +8175,18 @@ static void gen_spr_power8_book4(CPUPPCState *env)
>                      &spr_read_generic, SPR_NOACCESS,
>                      &spr_read_generic, &spr_write_generic,
>                      0);
> +    spr_register_kvm(env, SPR_ACOP, "ACOP",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_ACOP, 0);
> +    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_PID, 0);
> +    spr_register_kvm(env, SPR_WORT, "WORT",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_WORT, 0);
>  #endif
>  }

Register numbers match the ones from the header
arch/powerpc/include/asm/reg.h in the linux kernel sources, so I assume
the SPR numbers are correct. So:

Reviewed-by: Thomas Huth <thuth@redhat.com>

  reply	other threads:[~2016-03-14 20:08 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-14 16:56 [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 01/17] ppc: Update SPR definitions Cédric Le Goater
2016-03-14 18:34   ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 02/17] ppc: Add macros to register hypervisor mode SPRs Cédric Le Goater
2016-03-14 18:50   ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 03/17] ppc: Add a bunch of hypervisor SPRs to Book3s Cédric Le Goater
2016-03-14 19:14   ` Thomas Huth
2016-03-15  9:43     ` David Gibson
2016-03-15 10:49       ` Thomas Huth
2016-03-15 17:04         ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2016-03-16  1:04         ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition Cédric Le Goater
2016-03-14 19:20   ` Thomas Huth
2016-03-15  8:06     ` Cédric Le Goater
2016-03-15  8:21     ` Bharata B Rao
2016-03-15  9:45   ` David Gibson
2016-03-15 21:11     ` Benjamin Herrenschmidt
2016-03-16  0:41       ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 05/17] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV Cédric Le Goater
2016-03-14 19:29   ` Thomas Huth
2016-03-15  9:47     ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 06/17] ppc: Create cpu_ppc_set_papr() helper Cédric Le Goater
2016-03-17  2:34   ` David Gibson
2016-03-17 12:33     ` Cédric Le Goater
2016-03-17 22:03       ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 07/17] ppc: Better figure out if processor has HV mode Cédric Le Goater
2016-03-16  1:05   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 08/17] ppc: Add placeholder SPRs for DPDES and DHDES on P8 Cédric Le Goater
2016-03-14 19:32   ` Thomas Huth
2016-03-16  1:06   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 09/17] ppc: SPURR & PURR are HV writeable and privileged Cédric Le Goater
2016-03-14 19:37   ` Thomas Huth
2016-03-16  1:07     ` David Gibson
2016-03-16  1:07   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 10/17] ppc: Add dummy SPR_IC for POWER8 Cédric Le Goater
2016-03-14 19:40   ` Thomas Huth
2016-03-16  1:08   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 11/17] ppc: Initialize AMOR in PAPR mode Cédric Le Goater
2016-03-14 20:13   ` Thomas Huth
2016-03-16  1:09   ` David Gibson
2016-03-17  2:36   ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 12/17] ppc: Fix writing to AMR/UAMOR Cédric Le Goater
2016-03-14 20:26   ` Thomas Huth
2016-03-15  8:05     ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 13/17] ppc: Add POWER8 IAMR register Cédric Le Goater
2016-03-14 20:36   ` Thomas Huth
2016-03-14 16:56 ` [Qemu-devel] [PATCH 14/17] ppc: Add dummy write to VTB Cédric Le Goater
2016-03-14 20:54   ` Thomas Huth
2016-03-14 21:07     ` [Qemu-devel] [Qemu-ppc] " Benjamin Herrenschmidt
2016-03-16  1:12   ` [Qemu-devel] " David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 15/17] ppc: Add dummy POWER8 MPPR register Cédric Le Goater
2016-03-16  1:14   ` David Gibson
2016-03-16  6:17     ` Thomas Huth
2016-03-16  9:24       ` Cédric Le Goater
2016-03-14 16:56 ` [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR Cédric Le Goater
2016-03-14 20:00   ` Thomas Huth
2016-03-16  1:14   ` David Gibson
2016-03-16  6:24     ` Thomas Huth
2016-03-16 22:28       ` David Gibson
2016-03-14 16:56 ` [Qemu-devel] [PATCH 17/17] ppc: A couple more dummy POWER8 Book4 regs Cédric Le Goater
2016-03-14 20:08   ` Thomas Huth [this message]
2016-03-16  1:15   ` David Gibson
2016-03-15  0:39 ` [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing David Gibson
2016-03-15  8:11   ` Cédric Le Goater
2016-03-16  1:19     ` David Gibson
2016-03-16  9:08       ` Cédric Le Goater
2016-03-17  2:45         ` David Gibson
2016-03-17 14:28           ` Cédric Le Goater
2016-03-21  0:59             ` David Gibson

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