* [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings
@ 2016-05-08 22:55 Simon Glass
2016-05-08 22:55 ` [U-Boot] [PATCH v2 1/6] errno: Add copyright header and header guard Simon Glass
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw)
To: u-boot
The original tegra20 display driver was written before Linux had device tree
bindings for display. Since then Linux has developed a robust set of bindings
covering various aspects of enabling a display.
This series moves closer to those bindings by using the panel and backlight
as separate drivers. The device tree files for seaboard, ventana and harmony
thereby become almost the same as Linux.
Unfortunately this breaks the other boards, which will need a similar sync.
So I'm not sure how easy it will be to accept this series. Still, it seems
worth sending it out in the hope that board maintainers can help. I have
kept this series separate so that it can progress separately.
Changes in v2:
- Add new patch to add a copyright header and header guard to errno.h
- Add new patch to allow errno_str() to be used without CONFIG_ERRNO_STR
- Rebase to master
- Update harmony and ventana also
- Don't enable CONFIG_ERRNO_STR for each board
Simon Glass (6):
errno: Add copyright header and header guard
errno: Allow errno_str() to be used without CONFIG_ERRNO_STR
tegra: dts: Sync tegra20 device tree files with Linux
video: tegra: Move to using simple-panel and pwm-backlight
tegra: video: Always use write-through cache on LCD
fdt: Drop some unused compatible strings
arch/arm/dts/tegra20-harmony.dts | 751 ++++++++++++++++++++++++++++--
arch/arm/dts/tegra20-seaboard.dts | 934 ++++++++++++++++++++++++++++++++++----
arch/arm/dts/tegra20-ventana.dts | 685 ++++++++++++++++++++++++++--
configs/colibri_t20_defconfig | 3 +
configs/harmony_defconfig | 3 +
configs/medcom-wide_defconfig | 3 +
configs/paz00_defconfig | 3 +
configs/seaboard_defconfig | 3 +
configs/tec_defconfig | 3 +
configs/ventana_defconfig | 3 +
drivers/video/tegra.c | 333 +++-----------
include/errno.h | 12 +
include/fdtdec.h | 4 -
lib/fdtdec.c | 4 -
14 files changed, 2312 insertions(+), 432 deletions(-)
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply [flat|nested] 12+ messages in thread* [U-Boot] [PATCH v2 1/6] errno: Add copyright header and header guard 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass @ 2016-05-08 22:55 ` Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 2/6] errno: Allow errno_str() to be used without CONFIG_ERRNO_STR Simon Glass ` (5 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw) To: u-boot Bring in a copyright for this file from cmd/pmic.c since this file was submitted by the same author at around the same time. Also fix the missing header guard. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Add new patch to add a copyright header and header guard to errno.h include/errno.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/errno.h b/include/errno.h index 14ac3cb..3942681 100644 --- a/include/errno.h +++ b/include/errno.h @@ -1,4 +1,11 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak <p.marczak@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ #ifndef _ERRNO_H +#define _ERRNO_H #include <asm-generic/errno.h> -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 2/6] errno: Allow errno_str() to be used without CONFIG_ERRNO_STR 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 1/6] errno: Add copyright header and header guard Simon Glass @ 2016-05-08 22:55 ` Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux Simon Glass ` (4 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw) To: u-boot The pmic framework uses errno_str() and this requires board that use it to enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build error. This will show as "(null)" when U-Boot prints it. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Add new patch to allow errno_str() to be used without CONFIG_ERRNO_STR include/errno.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/errno.h b/include/errno.h index 3942681..15ece2f 100644 --- a/include/errno.h +++ b/include/errno.h @@ -15,5 +15,10 @@ extern int errno; #ifdef CONFIG_ERRNO_STR const char *errno_str(int errno); +#else +static inline const char *errno_str(int errno) +{ + return 0; +} #endif #endif /* _ERRNO_H */ -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 1/6] errno: Add copyright header and header guard Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 2/6] errno: Allow errno_str() to be used without CONFIG_ERRNO_STR Simon Glass @ 2016-05-08 22:55 ` Simon Glass 2016-05-09 17:09 ` Stephen Warren 2016-05-08 22:55 ` [U-Boot] [PATCH v2 4/6] video: tegra: Move to using simple-panel and pwm-backlight Simon Glass ` (3 subsequent siblings) 6 siblings, 1 reply; 12+ messages in thread From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw) To: u-boot Sync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Rebase to master - Update harmony and ventana also arch/arm/dts/tegra20-harmony.dts | 703 +++++++++++++++++++++++++++++- arch/arm/dts/tegra20-seaboard.dts | 889 +++++++++++++++++++++++++++++++++++--- arch/arm/dts/tegra20-ventana.dts | 635 ++++++++++++++++++++++++++- 3 files changed, 2154 insertions(+), 73 deletions(-) diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index 623eb90..a8540d4 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { @@ -11,6 +12,9 @@ }; aliases { + rtc0 = "/i2c at 7000d000/tps6586x at 34"; + rtc1 = "/rtc at 7000e000"; + serial0 = &uartd; usb0 = "/usb at c5008000"; usb1 = "/usb at c5004000"; sdhci0 = "/sdhci at c8000600"; @@ -30,12 +34,276 @@ nvidia,panel = <&lcd_panel>; }; }; + + hdmi at 54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux at 70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + }; + }; + }; + + i2s at 70002800 { + status = "okay"; }; serial at 70006300 { + status = "okay"; clock-frequency = < 216000000 >; }; + pwm: pwm at 7000a000 { + status = "okay"; + }; + + i2c at 7000c000 { + status = "okay"; + clock-frequency = <400000>; + + wm8903: wm8903 at 1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + }; + nand-controller at 70008000 { nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; nvidia,width = <8>; @@ -46,15 +314,319 @@ }; }; + hdmi_ddc: i2c at 7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c at 7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c at 7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x at 34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + pci_clk_reg: ldo0 { + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor at 4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + kbc at 7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <2>; + nvidia,repeat-delay-ms = <160>; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) + MATRIX_KEY(0x00, 0x03, KEY_S) + MATRIX_KEY(0x00, 0x04, KEY_A) + MATRIX_KEY(0x00, 0x05, KEY_Z) + MATRIX_KEY(0x00, 0x07, KEY_FN) + MATRIX_KEY(0x01, 0x07, KEY_MENU) + MATRIX_KEY(0x02, 0x06, KEY_LEFTALT) + MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT) + MATRIX_KEY(0x03, 0x00, KEY_5) + MATRIX_KEY(0x03, 0x01, KEY_4) + MATRIX_KEY(0x03, 0x02, KEY_R) + MATRIX_KEY(0x03, 0x03, KEY_E) + MATRIX_KEY(0x03, 0x04, KEY_F) + MATRIX_KEY(0x03, 0x05, KEY_D) + MATRIX_KEY(0x03, 0x06, KEY_X) + MATRIX_KEY(0x04, 0x00, KEY_7) + MATRIX_KEY(0x04, 0x01, KEY_6) + MATRIX_KEY(0x04, 0x02, KEY_T) + MATRIX_KEY(0x04, 0x03, KEY_H) + MATRIX_KEY(0x04, 0x04, KEY_G) + MATRIX_KEY(0x04, 0x05, KEY_V) + MATRIX_KEY(0x04, 0x06, KEY_C) + MATRIX_KEY(0x04, 0x07, KEY_SPACE) + MATRIX_KEY(0x05, 0x00, KEY_9) + MATRIX_KEY(0x05, 0x01, KEY_8) + MATRIX_KEY(0x05, 0x02, KEY_U) + MATRIX_KEY(0x05, 0x03, KEY_Y) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x05, 0x05, KEY_N) + MATRIX_KEY(0x05, 0x06, KEY_B) + MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) + MATRIX_KEY(0x06, 0x00, KEY_MINUS) + MATRIX_KEY(0x06, 0x01, KEY_0) + MATRIX_KEY(0x06, 0x02, KEY_O) + MATRIX_KEY(0x06, 0x03, KEY_I) + MATRIX_KEY(0x06, 0x04, KEY_L) + MATRIX_KEY(0x06, 0x05, KEY_K) + MATRIX_KEY(0x06, 0x06, KEY_COMMA) + MATRIX_KEY(0x06, 0x07, KEY_M) + MATRIX_KEY(0x07, 0x01, KEY_EQUAL) + MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) + MATRIX_KEY(0x07, 0x03, KEY_ENTER) + MATRIX_KEY(0x07, 0x07, KEY_MENU) + MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT) + MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT) + MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL) + MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL) + MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) + MATRIX_KEY(0x0B, 0x01, KEY_P) + MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) + MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) + MATRIX_KEY(0x0B, 0x04, KEY_SLASH) + MATRIX_KEY(0x0B, 0x05, KEY_DOT) + MATRIX_KEY(0x0C, 0x00, KEY_F10) + MATRIX_KEY(0x0C, 0x01, KEY_F9) + MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) + MATRIX_KEY(0x0C, 0x03, KEY_3) + MATRIX_KEY(0x0C, 0x04, KEY_2) + MATRIX_KEY(0x0C, 0x05, KEY_UP) + MATRIX_KEY(0x0C, 0x06, KEY_PRINT) + MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) + MATRIX_KEY(0x0D, 0x00, KEY_INSERT) + MATRIX_KEY(0x0D, 0x01, KEY_DELETE) + MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) + MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) + MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) + MATRIX_KEY(0x0D, 0x06, KEY_DOWN) + MATRIX_KEY(0x0D, 0x07, KEY_LEFT) + MATRIX_KEY(0x0E, 0x00, KEY_F11) + MATRIX_KEY(0x0E, 0x01, KEY_F12) + MATRIX_KEY(0x0E, 0x02, KEY_F8) + MATRIX_KEY(0x0E, 0x03, KEY_Q) + MATRIX_KEY(0x0E, 0x04, KEY_F4) + MATRIX_KEY(0x0E, 0x05, KEY_F3) + MATRIX_KEY(0x0E, 0x06, KEY_1) + MATRIX_KEY(0x0E, 0x07, KEY_F7) + MATRIX_KEY(0x0F, 0x00, KEY_ESC) + MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) + MATRIX_KEY(0x0F, 0x02, KEY_F5) + MATRIX_KEY(0x0F, 0x03, KEY_TAB) + MATRIX_KEY(0x0F, 0x04, KEY_F1) + MATRIX_KEY(0x0F, 0x05, KEY_F2) + MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) + MATRIX_KEY(0x0F, 0x07, KEY_F6) + MATRIX_KEY(0x14, 0x00, KEY_KP7) + MATRIX_KEY(0x15, 0x00, KEY_KP9) + MATRIX_KEY(0x15, 0x01, KEY_KP8) + MATRIX_KEY(0x15, 0x02, KEY_KP4) + MATRIX_KEY(0x15, 0x04, KEY_KP1) + MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) + MATRIX_KEY(0x16, 0x02, KEY_KP6) + MATRIX_KEY(0x16, 0x03, KEY_KP5) + MATRIX_KEY(0x16, 0x04, KEY_KP3) + MATRIX_KEY(0x16, 0x05, KEY_KP2) + MATRIX_KEY(0x16, 0x07, KEY_KP0) + MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) + MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) + MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) + MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) + MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) + MATRIX_KEY(0x1D, 0x03, KEY_HOME) + MATRIX_KEY(0x1D, 0x04, KEY_END) + MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) + MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) + MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) + MATRIX_KEY(0x1E, 0x02, KEY_MUTE) + MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>; + }; + + pmc at 7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + }; + + pcie-controller at 80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + pci at 1,0 { + status = "okay"; + }; + + pci at 2,0 { + status = "okay"; + }; + }; + + usb at c5000000 { + status = "okay"; + }; + + usb-phy at c5000000 { + status = "okay"; + }; + usb at c5004000 { - statuc = "okay"; + status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; }; + usb-phy at c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + usb at c5008000 { status = "okay"; }; + usb-phy at c5008000 { + status = "okay"; + }; + sdhci at c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -71,6 +643,17 @@ bus-width = <8>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -84,8 +667,15 @@ }; }; - pwm: pwm at 7000a000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; }; lcd_panel: panel { @@ -112,4 +702,111 @@ GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <0 0 200 0 0>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pci_vdd_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_pnl_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator at 5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_hdmi: regulator at 6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-harmony", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Harmony"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 5893d2a..6169094 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -1,19 +1,12 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { model = "NVIDIA Seaboard"; compatible = "nvidia,seaboard", "nvidia,tegra20"; - chosen { - bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; - }; - - chosen { - stdout-path = &uartd; - }; - aliases { /* This defines the order of our ports */ usb0 = "/usb at c5008000"; @@ -22,13 +15,23 @@ i2c1 = "/i2c at 7000c000"; i2c2 = "/i2c at 7000c400"; i2c3 = "/i2c at 7000c500"; + rtc0 = "/i2c at 7000d000/tps6586x at 34"; + rtc1 = "/rtc at 7000e000"; + serial0 = &uartd; sdhci0 = "/sdhci at c8000600"; sdhci1 = "/sdhci at c8000400"; }; + chosen { + bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; + }; + + chosen { + stdout-path = &uartd; + }; + memory { - device_type = "memory"; - reg = < 0x00000000 0x40000000 >; + reg = <0x00000000 0x40000000>; }; host1x at 50000000 { @@ -37,31 +40,305 @@ status = "okay"; rgb { status = "okay"; - nvidia,panel = <&lcd_panel>; + + nvidia,panel = <&panel>; }; }; + + hdmi at 54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; }; - /* This is not used in U-Boot, but is expected to be in kernel .dts */ - i2c at 7000d000 { - status = "okay"; - clock-frequency = <100000>; - pmic at 34 { - compatible = "ti,tps6586x"; - reg = <0x34>; + pinmux at 70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", + "lsck", "lsda"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap2", + "dap4", "ddc", "dtf", "gma", "gmc", "gmd", + "gme", "gpu", "gpu7", "i2cp", "irrx", + "irtx", "pta", "rm", "sdc", "sdd", + "slxd", "slxk", "spdi", "spdo", "uac", + "uad", "uca", "ucb", "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ate { + nvidia,pins = "ate", "csus", "dap3", + "gpv", "owc", "slxc", "spib", "spid", + "spie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spia", + "spig", "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_dte { + nvidia,pins = "dte", "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "spic", "uaa", + "uab"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc", "sdb"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; - clk_32k: clock { - compatible = "fixed-clock"; - /* - * leave out for now due to CPP: - * #clock-cells = <0>; - */ - clock-frequency = <32768>; + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; }; }; }; + i2s at 70002800 { + status = "okay"; + }; + serial at 70006300 { + status = "okay"; clock-frequency = < 216000000 >; }; @@ -75,56 +352,376 @@ }; }; + pwm: pwm at 7000a000 { + status = "okay"; + }; + i2c at 7000c000 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; + + wm8903: wm8903 at 1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + /* ALS and proximity sensor */ + isl29018 at 44 { + compatible = "isil,isl29018"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; + }; + + gyrometer at 68 { + compatible = "invn,mpu3050"; + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; + }; }; i2c at 7000c400 { status = "okay"; + clock-frequency = <100000>; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c at 0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c at 1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery at b { + compatible = "ti,bq20z75", "smart-battery-1.1"; + reg = <0xb>; + ti,i2c-retry-count = <2>; + ti,poll-retry-count = <10>; + }; + }; }; i2c at 7000c500 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; + }; + + i2c at 7000d000 { + status = "okay"; + clock-frequency = <400000>; + + magnetometer at c { + compatible = "asahi-kasei,ak8975"; + reg = <0xc>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; + }; + + pmic: tps6586x at 34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor at 4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; }; kbc at 7000e200 { status = "okay"; - linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c - 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006 - 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020 - 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023 - 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a - 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031 - 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018 - 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032 - 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036 - 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019 - 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044 - 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067 - 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068 - 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057 - 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d - 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f - 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040 - 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f - 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050 - 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053 - 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072 - 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071 - 0x1f04008a>; - linux,fn-keymap = <0x05040002>; - }; - - emc at 7000f400 { - #address-cells = <1>; - #size-cells = <0>; + nvidia,debounce-delay-ms = <32>; + nvidia,repeat-delay-ms = <160>; + nvidia,ghost-filter; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) + MATRIX_KEY(0x00, 0x03, KEY_S) + MATRIX_KEY(0x00, 0x04, KEY_A) + MATRIX_KEY(0x00, 0x05, KEY_Z) + MATRIX_KEY(0x00, 0x07, KEY_FN) + + MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA) + MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT) + MATRIX_KEY(0x02, 0x07, KEY_LEFTALT) + + MATRIX_KEY(0x03, 0x00, KEY_5) + MATRIX_KEY(0x03, 0x01, KEY_4) + MATRIX_KEY(0x03, 0x02, KEY_R) + MATRIX_KEY(0x03, 0x03, KEY_E) + MATRIX_KEY(0x03, 0x04, KEY_F) + MATRIX_KEY(0x03, 0x05, KEY_D) + MATRIX_KEY(0x03, 0x06, KEY_X) + + MATRIX_KEY(0x04, 0x00, KEY_7) + MATRIX_KEY(0x04, 0x01, KEY_6) + MATRIX_KEY(0x04, 0x02, KEY_T) + MATRIX_KEY(0x04, 0x03, KEY_H) + MATRIX_KEY(0x04, 0x04, KEY_G) + MATRIX_KEY(0x04, 0x05, KEY_V) + MATRIX_KEY(0x04, 0x06, KEY_C) + MATRIX_KEY(0x04, 0x07, KEY_SPACE) + + MATRIX_KEY(0x05, 0x00, KEY_9) + MATRIX_KEY(0x05, 0x01, KEY_8) + MATRIX_KEY(0x05, 0x02, KEY_U) + MATRIX_KEY(0x05, 0x03, KEY_Y) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x05, 0x05, KEY_N) + MATRIX_KEY(0x05, 0x06, KEY_B) + MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) + + MATRIX_KEY(0x06, 0x00, KEY_MINUS) + MATRIX_KEY(0x06, 0x01, KEY_0) + MATRIX_KEY(0x06, 0x02, KEY_O) + MATRIX_KEY(0x06, 0x03, KEY_I) + MATRIX_KEY(0x06, 0x04, KEY_L) + MATRIX_KEY(0x06, 0x05, KEY_K) + MATRIX_KEY(0x06, 0x06, KEY_COMMA) + MATRIX_KEY(0x06, 0x07, KEY_M) + + MATRIX_KEY(0x07, 0x01, KEY_EQUAL) + MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) + MATRIX_KEY(0x07, 0x03, KEY_ENTER) + MATRIX_KEY(0x07, 0x07, KEY_MENU) + + MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT) + MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT) + + MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL) + MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL) + + MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) + MATRIX_KEY(0x0B, 0x01, KEY_P) + MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) + MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) + MATRIX_KEY(0x0B, 0x04, KEY_SLASH) + MATRIX_KEY(0x0B, 0x05, KEY_DOT) + + MATRIX_KEY(0x0C, 0x00, KEY_F10) + MATRIX_KEY(0x0C, 0x01, KEY_F9) + MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) + MATRIX_KEY(0x0C, 0x03, KEY_3) + MATRIX_KEY(0x0C, 0x04, KEY_2) + MATRIX_KEY(0x0C, 0x05, KEY_UP) + MATRIX_KEY(0x0C, 0x06, KEY_PRINT) + MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) + + MATRIX_KEY(0x0D, 0x00, KEY_INSERT) + MATRIX_KEY(0x0D, 0x01, KEY_DELETE) + MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) + MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) + MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) + MATRIX_KEY(0x0D, 0x06, KEY_DOWN) + MATRIX_KEY(0x0D, 0x07, KEY_LEFT) + + MATRIX_KEY(0x0E, 0x00, KEY_F11) + MATRIX_KEY(0x0E, 0x01, KEY_F12) + MATRIX_KEY(0x0E, 0x02, KEY_F8) + MATRIX_KEY(0x0E, 0x03, KEY_Q) + MATRIX_KEY(0x0E, 0x04, KEY_F4) + MATRIX_KEY(0x0E, 0x05, KEY_F3) + MATRIX_KEY(0x0E, 0x06, KEY_1) + MATRIX_KEY(0x0E, 0x07, KEY_F7) + + MATRIX_KEY(0x0F, 0x00, KEY_ESC) + MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) + MATRIX_KEY(0x0F, 0x02, KEY_F5) + MATRIX_KEY(0x0F, 0x03, KEY_TAB) + MATRIX_KEY(0x0F, 0x04, KEY_F1) + MATRIX_KEY(0x0F, 0x05, KEY_F2) + MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) + MATRIX_KEY(0x0F, 0x07, KEY_F6) + + /* Software Handled Function Keys */ + MATRIX_KEY(0x14, 0x00, KEY_KP7) + + MATRIX_KEY(0x15, 0x00, KEY_KP9) + MATRIX_KEY(0x15, 0x01, KEY_KP8) + MATRIX_KEY(0x15, 0x02, KEY_KP4) + MATRIX_KEY(0x15, 0x04, KEY_KP1) + + MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) + MATRIX_KEY(0x16, 0x02, KEY_KP6) + MATRIX_KEY(0x16, 0x03, KEY_KP5) + MATRIX_KEY(0x16, 0x04, KEY_KP3) + MATRIX_KEY(0x16, 0x05, KEY_KP2) + MATRIX_KEY(0x16, 0x07, KEY_KP0) + + MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) + MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) + MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) + MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) + + MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) + + MATRIX_KEY(0x1D, 0x03, KEY_HOME) + MATRIX_KEY(0x1D, 0x04, KEY_END) + MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) + MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) + + MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) + MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) + MATRIX_KEY(0x1E, 0x02, KEY_MUTE) + + MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; + }; + + pmc at 7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + }; + + memory-controller at 7000f400 { emc-table at 190000 { - reg = < 190000 >; + reg = <190000>; compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 190000 >; - nvidia,emc-registers = < 0x0000000c 0x00000026 + clock-frequency = <190000>; + nvidia,emc-registers = <0x0000000c 0x00000026 0x00000009 0x00000003 0x00000004 0x00000004 0x00000002 0x0000000c 0x00000003 0x00000003 0x00000002 0x00000001 0x00000004 0x00000005 @@ -135,13 +732,14 @@ 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0xa06204ae 0x007dc010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 >; + 0x00000000 0x00000000 0x00000000 0x00000000>; }; + emc-table at 380000 { - reg = < 380000 >; + reg = <380000>; compatible = "nvidia,tegra20-emc-table"; - clock-frequency = < 380000 >; - nvidia,emc-registers = < 0x00000017 0x0000004b + clock-frequency = <380000>; + nvidia,emc-registers = <0x00000017 0x0000004b 0x00000012 0x00000006 0x00000004 0x00000005 0x00000003 0x0000000c 0x00000006 0x00000006 0x00000003 0x00000001 0x00000004 0x00000005 @@ -152,7 +750,7 @@ 0x00000002 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000083 0xe044048b 0x007d8010 0x00000000 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000 >; + 0x00000000 0x00000000 0x00000000 0x00000000>; }; }; @@ -162,14 +760,39 @@ dr_mode = "otg"; }; + usb-phy at c5000000 { + status = "okay"; + vbus-supply = <&vbus_reg>; + dr_mode = "otg"; + }; + usb at c5004000 { status = "disabled"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy at c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb at c5008000 { status = "okay"; }; + usb-phy at c5008000 { + status = "okay"; + }; + + sdhci at c8000000 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + sdhci at c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -181,6 +804,18 @@ sdhci at c8000600 { status = "okay"; bus-width = <8>; + non-removable; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; }; clocks { @@ -196,11 +831,27 @@ }; }; - pwm: pwm at 7000a000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; }; - lcd_panel: panel { + panel: panel { /* Seaboard has 1366x768 */ clock = <70600000>; xres = <1366>; @@ -224,4 +875,108 @@ GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <400 4 203 17 15>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_vbus_wup1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(D, 0) 0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator at 5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_hdmi: regulator at 6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-seaboard", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Seaboard"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1R", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 851e0ed..0ce46ae 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / { @@ -11,6 +12,9 @@ }; aliases { + rtc0 = "/i2c at 7000d000/tps6586x at 34"; + rtc1 = "/rtc at 7000e000"; + serial0 = &uartd; usb0 = "/usb at c5008000"; sdhci0 = "/sdhci at c8000600"; sdhci1 = "/sdhci at c8000400"; @@ -29,16 +33,537 @@ nvidia,panel = <&lcd_panel>; }; }; + + hdmi at 54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux at 70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap2", + "dap4", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "i2cp", "irrx", + "irtx", "pta", "rm", "sdc", "sdd", + "slxc", "slxd", "slxk", "spdi", "spdo", + "uac", "uad", "uca", "ucb", "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ate { + nvidia,pins = "ate", "csus", "dap3", "gmd", + "gpv", "owc", "spia", "spib", "spic", + "spid", "spie", "spig"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_dte { + nvidia,pins = "dte", "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + }; + + i2s at 70002800 { + status = "okay"; }; serial at 70006300 { - clock-frequency = < 216000000 >; + status = "okay"; + clock-frequency = < 216000000 >; }; + + pwm: pwm at 7000a000 { + status = "okay"; + }; + + i2c at 7000c000 { + status = "okay"; + clock-frequency = <400000>; + + wm8903: wm8903 at 1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + + /* ALS and proximity sensor */ + isl29018 at 44 { + compatible = "isil,isl29018"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + i2c at 7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c at 0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c at 1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c at 7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c at 7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x at 34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor at 4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + }; + }; + + pmc at 7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + }; + + usb at c5000000 { + status = "okay"; + }; + + usb-phy at c5000000 { + status = "okay"; + }; + + usb at c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + + usb-phy at c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb at c5008000 { status = "okay"; }; + usb-phy at c5008000 { + status = "okay"; + }; + + sdhci at c8000000 { + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + keep-power-in-suspend; + }; + sdhci at c8000400 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -50,6 +575,18 @@ sdhci at c8000600 { status = "okay"; bus-width = <8>; + non-removable; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; }; clocks { @@ -65,8 +602,69 @@ }; }; - pwm: pwm at 7000a000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_pnl_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; lcd_panel: panel { @@ -93,4 +691,35 @@ GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <0 0 200 0 0>; }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-ventana", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Ventana"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; }; -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux 2016-05-08 22:55 ` [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux Simon Glass @ 2016-05-09 17:09 ` Stephen Warren 2016-05-09 19:26 ` Simon Glass 0 siblings, 1 reply; 12+ messages in thread From: Stephen Warren @ 2016-05-09 17:09 UTC (permalink / raw) To: u-boot On 05/08/2016 04:55 PM, Simon Glass wrote: > Sync everything except the display panel, which will come in a future patch. > One USB port is left disabled since we don't want to support it in U-Boot. I'd rather be a bit more careful here, and only import the DT nodes directly related to display output. This change brings in a slew of other nodes that aren't used by U-Boot (something we've historically explicitly avoided) such as pinctrl, audio, Tegra KBC, I2C mux, & regulators. It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C, and I think USB for all boards), and at least Harmony's USB nodes don't seem to match what's in the kernel so I'm not sure where the DT content came from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer rather than GPIO_ACTIVE_LOW, which is present in at least the most recent kernel release (v4.5). Splitting this up a bit or limiting it to just display-related nodes would make it easier to debug any issues that crop up with the sync. Also, have we made an explicit decision to change the policy of only including DT nodes that U-Boot actually uses, rather than simply copying the entire kernel DT into U-Boot? I'm pretty sure that some board(s) have deliberate differences in areas other than display, e.g. since U-Boot doesn't (or at least didn't) support pinctrl-based I2C muxed which are used on some Tegra20 boards in the kernel at least, and hence U-Boot likely either disabled those I2C ports or picked an explicit pinmux configuration to hard-code to. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux 2016-05-09 17:09 ` Stephen Warren @ 2016-05-09 19:26 ` Simon Glass 2016-05-10 17:45 ` Stephen Warren 0 siblings, 1 reply; 12+ messages in thread From: Simon Glass @ 2016-05-09 19:26 UTC (permalink / raw) To: u-boot Hi Stephen, On 9 May 2016 at 11:09, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 05/08/2016 04:55 PM, Simon Glass wrote: >> >> Sync everything except the display panel, which will come in a future >> patch. >> One USB port is left disabled since we don't want to support it in U-Boot. > > > I'd rather be a bit more careful here, and only import the DT nodes directly > related to display output. > > This change brings in a slew of other nodes that aren't used by U-Boot > (something we've historically explicitly avoided) such as pinctrl, audio, > Tegra KBC, I2C mux, & regulators. I believe that audio, KBC and regulators are used. > > It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C, > and I think USB for all boards), and at least Harmony's USB nodes don't seem > to match what's in the kernel so I'm not sure where the DT content came > from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer > rather than GPIO_ACTIVE_LOW, which is present in at least the most recent > kernel release (v4.5). This was against v4.4, but I may have messed up the merge in some cases. since I had to change the addresses from 64 bit. > > Splitting this up a bit or limiting it to just display-related nodes would > make it easier to debug any issues that crop up with the sync. Also, have we > made an explicit decision to change the policy of only including DT nodes > that U-Boot actually uses, rather than simply copying the entire kernel DT > into U-Boot? I'm pretty sure that some board(s) have deliberate differences > in areas other than display, e.g. since U-Boot doesn't (or at least didn't) > support pinctrl-based I2C muxed which are used on some Tegra20 boards in the > kernel at least, and hence U-Boot likely either disabled those I2C ports or > picked an explicit pinmux configuration to hard-code to. I think I know what you mean, and I don't believe that actually affects any I2C ports that are used in U-Boot. Do you have any example? I'd rather have the DT completely in sync, so far as can be done. We have this merge window to find problems. I don't see a big benefit to leaving stuff out...at least with other boards we've defaulted to just bringing everything in. Are we mostly talking about the pinmux stuff? Regards, Simon ^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux 2016-05-09 19:26 ` Simon Glass @ 2016-05-10 17:45 ` Stephen Warren 2016-05-13 3:11 ` Simon Glass 0 siblings, 1 reply; 12+ messages in thread From: Stephen Warren @ 2016-05-10 17:45 UTC (permalink / raw) To: u-boot On 05/09/2016 01:26 PM, Simon Glass wrote: > Hi Stephen, > > On 9 May 2016 at 11:09, Stephen Warren <swarren@wwwdotorg.org> wrote: >> On 05/08/2016 04:55 PM, Simon Glass wrote: >>> >>> Sync everything except the display panel, which will come in a future >>> patch. >>> One USB port is left disabled since we don't want to support it in U-Boot. >> >> >> I'd rather be a bit more careful here, and only import the DT nodes directly >> related to display output. >> >> This change brings in a slew of other nodes that aren't used by U-Boot >> (something we've historically explicitly avoided) such as pinctrl, audio, >> Tegra KBC, I2C mux, & regulators. > > I believe that audio, KBC and regulators are used. Audio and regulators certainly aren't used by mainline U-Boot; we don't have any audio drivers and IIRC we don't have any regulators instantiated in the DTs currently in U-Boot for Tegra devices. >> It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C, >> and I think USB for all boards), and at least Harmony's USB nodes don't seem >> to match what's in the kernel so I'm not sure where the DT content came >> from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer >> rather than GPIO_ACTIVE_LOW, which is present in at least the most recent >> kernel release (v4.5). > > This was against v4.4, but I may have messed up the merge in some > cases. since I had to change the addresses from 64 bit. It looks like that particular change was made in v3.11 in the kernel. >> Splitting this up a bit or limiting it to just display-related nodes would >> make it easier to debug any issues that crop up with the sync. Also, have we >> made an explicit decision to change the policy of only including DT nodes >> that U-Boot actually uses, rather than simply copying the entire kernel DT >> into U-Boot? I'm pretty sure that some board(s) have deliberate differences >> in areas other than display, e.g. since U-Boot doesn't (or at least didn't) >> support pinctrl-based I2C muxed which are used on some Tegra20 boards in the >> kernel at least, and hence U-Boot likely either disabled those I2C ports or >> picked an explicit pinmux configuration to hard-code to. > > I think I know what you mean, and I don't believe that actually > affects any I2C ports that are used in U-Boot. Do you have any > example? In tegra20-seaboard.dts, the kernel DT has a pinctrl-based I2C mux on controller /i2c at 7000c400, whereas U-Boot has that I2C controller routed to some fixed pinctrl setting, and is currently enabled. Thinking more about this, since the i2c-mux-pinctrl node won't currently be processed by U-Boot in any way, since there is no driver for it, that mux node shouldn't affect the I2C controller's operation any way in U-Boot, so everything should work out fine. tegra20-ventana.dts has an i2c-mux-pinctrl node in the kernel DT, but the I2C controller isn't enabled in U-Boot, so there should be no possibility of regression. tegra20-tamonten.dtsi already has the i2c-mux-pinctrl node in the U-Boot DT without issue. > I'd rather have the DT completely in sync, so far as can be done. We > have this merge window to find problems. I don't see a big benefit to > leaving stuff out...at least with other boards we've defaulted to just > bringing everything in. > > Are we mostly talking about the pinmux stuff? I guess keeping the DT completely in sync, or as close as possible, will simply future comparisons. However, I have the following concerns, especially just doing it all at once: 1) This likely enables a lot more devices. In particular, there are certainly I2C controllers enabled in some kernel DTs that aren't enabled in U-Boot DTs yet, since we simply haven't needed them. Likewise, we don't instantiate complete regulator drivers (at least for Tegra) in (m)any cases in U-Boot. In theory, this will not cause any issue. However, there might be bugs such as: * The clock driver doesn't correctly support/implement certain clocks/resets we haven't yet happened to use. This is quite likely. * I2C controller driver is broken and doesn't call the clock driver with the correct parameters to enable clock and release reset for some controllers we haven't used yet. This is less likely. * pinmux may not be set up correctly for controllers we haven't used yet. This is especially likely on older boards where U-Boot only partially programs the pinmux for controllers known to be used, rather than programming the entire thing at once to the final configuration. Hopefully this won't cause any issues, but in the worst case it could cause some individual controller to malfunction, which just perhaps could impact some other part of the system. * Hopefully any regulator driver doesn't touch the HW unless explicitly requested to by some client, so hopefully we don't end up with rails being explicitly disabled at boot, this preventing HW from operating when it worked fine without the driver. 2) There are some bindings that are different between U-Boot and the kernel. One obvious example is the Tegra USB controller, which has a single "usb" node in U-Boot but separate "usb" and "usb-phy" nodes in the kernel. This change doesn't look backwards-compatible, since e.g. the vbus-supply node moved from the "usb" node (which U-Boot currently processes) to the "usb-phy" node (which U-Boot does not know about). There are probably other more minor examples of similar issues. 3) Having all HW represented in the DTs in U-Boot is certainly a change in policy at least for Tegra. I hope it won't give the impression incorrect that U-Boot actually processes all those DT nodes and uses them as an information source. This is mainly just a mind-set change though, so shouldn't be too much of an issue. To address your last question above: pinctrl is one obvious example where this wouldn't be true. Regulators are another. Neither of those currently have any DT integration in U-Boot, for Tegra at least. Clocks and resets are only partially integrated with DT; the clock/reset IDs are parsed from properties in client nodes, but the provider side nodes are entirely ignored. Due to all that, I'd still strongly prefer this patch only sync the display-related nodes in order to limit and possible fall-out to display functionality; the topic of the series. I'm fine with syncing the other nodes too, where possible. However, I'd like to see the sync split up into a variety of separate patches, likely based on node/HW type, to make "git bisect" easier in the face of any problems that crop up. Nothing would be more annoying than trying to debug an issue with display not working but being unable to do so because a new I2C controller's driver was causing the system to hard-hang by touching an unclocked register. Equally, just blindly syncing the entire DT content isn't going to work e.g. due to the USB binding differences I mentioned. In summary, perhaps we can have a patch series like: * Add/update all I2C nodes * Add/update all MMC nodes * Add/update all USB nodes * Add/update all PCIe nodes * Add/update all host1x/display/LCD/... nodes * Add/update any misc nodes * Add all nodes for which we know there's no kernel driver That will make it much easier to debug any problems that do arise. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux 2016-05-10 17:45 ` Stephen Warren @ 2016-05-13 3:11 ` Simon Glass 0 siblings, 0 replies; 12+ messages in thread From: Simon Glass @ 2016-05-13 3:11 UTC (permalink / raw) To: u-boot Hi Stephen, On 10 May 2016 at 11:45, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 05/09/2016 01:26 PM, Simon Glass wrote: >> >> Hi Stephen, >> >> On 9 May 2016 at 11:09, Stephen Warren <swarren@wwwdotorg.org> wrote: >>> >>> On 05/08/2016 04:55 PM, Simon Glass wrote: >>>> >>>> >>>> Sync everything except the display panel, which will come in a future >>>> patch. >>>> One USB port is left disabled since we don't want to support it in >>>> U-Boot. >>> >>> >>> >>> I'd rather be a bit more careful here, and only import the DT nodes >>> directly >>> related to display output. >>> >>> This change brings in a slew of other nodes that aren't used by U-Boot >>> (something we've historically explicitly avoided) such as pinctrl, audio, >>> Tegra KBC, I2C mux, & regulators. >> >> >> I believe that audio, KBC and regulators are used. > > > Audio and regulators certainly aren't used by mainline U-Boot; we don't have > any audio drivers and IIRC we don't have any regulators instantiated in the > DTs currently in U-Boot for Tegra devices. Regulators are used by the new LCD support. Yes you are right about audio. > >>> It also doesn't sync the /aliases node with the kernel (e.g. Seaboard >>> I2C, >>> and I think USB for all boards), and at least Harmony's USB nodes don't >>> seem >>> to match what's in the kernel so I'm not sure where the DT content came >>> from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer >>> rather than GPIO_ACTIVE_LOW, which is present in at least the most recent >>> kernel release (v4.5). >> >> >> This was against v4.4, but I may have messed up the merge in some >> cases. since I had to change the addresses from 64 bit. > > > It looks like that particular change was made in v3.11 in the kernel. > >>> Splitting this up a bit or limiting it to just display-related nodes >>> would >>> make it easier to debug any issues that crop up with the sync. Also, have >>> we >>> made an explicit decision to change the policy of only including DT nodes >>> that U-Boot actually uses, rather than simply copying the entire kernel >>> DT >>> into U-Boot? I'm pretty sure that some board(s) have deliberate >>> differences >>> in areas other than display, e.g. since U-Boot doesn't (or at least >>> didn't) >>> support pinctrl-based I2C muxed which are used on some Tegra20 boards in >>> the >>> kernel at least, and hence U-Boot likely either disabled those I2C ports >>> or >>> picked an explicit pinmux configuration to hard-code to. >> >> >> I think I know what you mean, and I don't believe that actually >> affects any I2C ports that are used in U-Boot. Do you have any >> example? > > > In tegra20-seaboard.dts, the kernel DT has a pinctrl-based I2C mux on > controller /i2c at 7000c400, whereas U-Boot has that I2C controller routed to > some fixed pinctrl setting, and is currently enabled. Thinking more about > this, since the i2c-mux-pinctrl node won't currently be processed by U-Boot > in any way, since there is no driver for it, that mux node shouldn't affect > the I2C controller's operation any way in U-Boot, so everything should work > out fine. > > tegra20-ventana.dts has an i2c-mux-pinctrl node in the kernel DT, but the > I2C controller isn't enabled in U-Boot, so there should be no possibility of > regression. > > tegra20-tamonten.dtsi already has the i2c-mux-pinctrl node in the U-Boot DT > without issue. > >> I'd rather have the DT completely in sync, so far as can be done. We >> have this merge window to find problems. I don't see a big benefit to >> leaving stuff out...at least with other boards we've defaulted to just >> bringing everything in. >> >> Are we mostly talking about the pinmux stuff? > > > I guess keeping the DT completely in sync, or as close as possible, will > simply future comparisons. However, I have the following concerns, > especially just doing it all at once: > > 1) This likely enables a lot more devices. In particular, there are > certainly I2C controllers enabled in some kernel DTs that aren't enabled in > U-Boot DTs yet, since we simply haven't needed them. Likewise, we don't > instantiate complete regulator drivers (at least for Tegra) in (m)any cases > in U-Boot. In theory, this will not cause any issue. However, there might be > bugs such as: > > * The clock driver doesn't correctly support/implement certain clocks/resets > we haven't yet happened to use. This is quite likely. > > * I2C controller driver is broken and doesn't call the clock driver with the > correct parameters to enable clock and release reset for some controllers we > haven't used yet. This is less likely. > > * pinmux may not be set up correctly for controllers we haven't used yet. > This is especially likely on older boards where U-Boot only partially > programs the pinmux for controllers known to be used, rather than > programming the entire thing at once to the final configuration. Hopefully > this won't cause any issues, but in the worst case it could cause some > individual controller to malfunction, which just perhaps could impact some > other part of the system. > > * Hopefully any regulator driver doesn't touch the HW unless explicitly > requested to by some client, so hopefully we don't end up with rails being > explicitly disabled at boot, this preventing HW from operating when it > worked fine without the driver. The regulators are not used unless enabled, but they will be enabled if a display is used. I worry that what you are saying above is that we *need* a different device tree from Linux. Would it not be better to make it the same and then fix any problems we discover? > > 2) There are some bindings that are different between U-Boot and the kernel. > One obvious example is the Tegra USB controller, which has a single "usb" > node in U-Boot but separate "usb" and "usb-phy" nodes in the kernel. This > change doesn't look backwards-compatible, since e.g. the vbus-supply node > moved from the "usb" node (which U-Boot currently processes) to the > "usb-phy" node (which U-Boot does not know about). > > There are probably other more minor examples of similar issues. Hmm well that's the sort of thing I'd like to tidy up. > > 3) Having all HW represented in the DTs in U-Boot is certainly a change in > policy at least for Tegra. I hope it won't give the impression incorrect > that U-Boot actually processes all those DT nodes and uses them as an > information source. This is mainly just a mind-set change though, so > shouldn't be too much of an issue. > > To address your last question above: pinctrl is one obvious example where > this wouldn't be true. Regulators are another. Neither of those currently > have any DT integration in U-Boot, for Tegra at least. Clocks and resets are > only partially integrated with DT; the clock/reset IDs are parsed from > properties in client nodes, but the provider side nodes are entirely > ignored. I'm hoping that you will create a pinctrl driver. Regulators are well supported in U-Boot now - please see drivers/power/regulator. > > > Due to all that, I'd still strongly prefer this patch only sync the > display-related nodes in order to limit and possible fall-out to display > functionality; the topic of the series. > > I'm fine with syncing the other nodes too, where possible. However, I'd like > to see the sync split up into a variety of separate patches, likely based on > node/HW type, to make "git bisect" easier in the face of any problems that > crop up. Nothing would be more annoying than trying to debug an issue with > display not working but being unable to do so because a new I2C controller's > driver was causing the system to hard-hang by touching an unclocked > register. Equally, just blindly syncing the entire DT content isn't going to > work e.g. due to the USB binding differences I mentioned. > > In summary, perhaps we can have a patch series like: > > * Add/update all I2C nodes > * Add/update all MMC nodes > * Add/update all USB nodes > * Add/update all PCIe nodes > * Add/update all host1x/display/LCD/... nodes > * Add/update any misc nodes > * Add all nodes for which we know there's no kernel driver > > That will make it much easier to debug any problems that do arise. OK I'll take a look at this. Really I wish the Tegra maintainer would do this :-) Regards, Simon ^ permalink raw reply [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 4/6] video: tegra: Move to using simple-panel and pwm-backlight 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass ` (2 preceding siblings ...) 2016-05-08 22:55 ` [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux Simon Glass @ 2016-05-08 22:55 ` Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 5/6] tegra: video: Always use write-through cache on LCD Simon Glass ` (2 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw) To: u-boot We have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code. This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings: - colibri - medcom-wide - paz00 - tec Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: - Don't enable CONFIG_ERRNO_STR for each board arch/arm/dts/tegra20-harmony.dts | 48 +++--- arch/arm/dts/tegra20-seaboard.dts | 45 +++--- arch/arm/dts/tegra20-ventana.dts | 54 +++---- configs/colibri_t20_defconfig | 3 + configs/harmony_defconfig | 3 + configs/medcom-wide_defconfig | 3 + configs/paz00_defconfig | 3 + configs/seaboard_defconfig | 3 + configs/tec_defconfig | 3 + configs/ventana_defconfig | 3 + drivers/video/tegra.c | 312 ++++++-------------------------------- 11 files changed, 145 insertions(+), 335 deletions(-) diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index a8540d4..8e9fe5a 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -31,7 +31,23 @@ status = "okay"; rgb { status = "okay"; - nvidia,panel = <&lcd_panel>; + + nvidia,panel = <&panel>; + + display-timings { + timing at 0 { + /* Seaboard has 1366x768 */ + clock-frequency = <42430000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <138>; + hfront-porch = <34>; + hsync-len = <136>; + vback-porch = <21>; + vfront-porch = <4>; + vsync-len = <4>; + }; + }; }; }; @@ -678,29 +694,13 @@ }; }; - lcd_panel: panel { - clock = <42430000>; - xres = <1024>; - yres = <600>; - left-margin = <138>; - right-margin = <34>; - hsync-len = <136>; - lower-margin = <4>; - upper-margin = <21>; - vsync-len = <4>; - hsync-active-high; - vsyncx-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 0 0>; - nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5) - GPIO_ACTIVE_HIGH>; - nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) - GPIO_ACTIVE_HIGH>; - nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) - GPIO_ACTIVE_HIGH>; - nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) - GPIO_ACTIVE_HIGH>; - nvidia,panel-timings = <0 0 200 0 0>; + panel: panel { + compatible = "auo,b101aw03", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; }; regulators { diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index 6169094..0a454f9 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -42,6 +42,22 @@ status = "okay"; nvidia,panel = <&panel>; + + display-timings { + timing at 0 { + /* Seaboard has 1366x768 */ + clock-frequency = <70600000>; + hactive = <1366>; + vactive = <768>; + hback-porch = <58>; + hfront-porch = <58>; + hsync-len = <58>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <4>; + hsync-active = <1>; + }; + }; }; }; @@ -852,28 +868,13 @@ }; panel: panel { - /* Seaboard has 1366x768 */ - clock = <70600000>; - xres = <1366>; - yres = <768>; - left-margin = <58>; - right-margin = <58>; - hsync-len = <58>; - lower-margin = <4>; - upper-margin = <4>; - vsync-len = <4>; - hsync-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 2 0>; - nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4) - GPIO_ACTIVE_HIGH>; - nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) - GPIO_ACTIVE_HIGH>; - nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) - GPIO_ACTIVE_HIGH>; - nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) - GPIO_ACTIVE_HIGH>; - nvidia,panel-timings = <400 4 203 17 15>; + compatible = "chunghwa,claa101wa01a", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; }; regulators { diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 0ce46ae..143e964 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -30,7 +30,24 @@ status = "okay"; rgb { status = "okay"; - nvidia,panel = <&lcd_panel>; + + nvidia,panel = <&panel>; + + display-timings { + timing at 0 { + /* Seaboard has 1366x768 */ + clock-frequency = <70600000>; + hactive = <1366>; + vactive = <768>; + hback-porch = <58>; + hfront-porch = <58>; + hsync-len = <58>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <4>; + hsync-active = <1>; + }; + }; }; }; @@ -613,6 +630,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wa01a", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -667,31 +694,6 @@ }; }; - lcd_panel: panel { - clock = <72072000>; - xres = <1366>; - yres = <768>; - left-margin = <58>; - right-margin = <58>; - hsync-len = <58>; - lower-margin = <4>; - upper-margin = <4>; - vsync-len = <4>; - hsync-active-high; - vsync-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 2 0>; - nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(D, 4) - GPIO_ACTIVE_HIGH>; - nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) - GPIO_ACTIVE_HIGH>; - nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) - GPIO_ACTIVE_HIGH>; - nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) - GPIO_ACTIVE_HIGH>; - nvidia,panel-timings = <0 0 200 0 0>; - }; - sound { compatible = "nvidia,tegra-audio-wm8903-ventana", "nvidia,tegra-audio-wm8903"; diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index a3b2a3c..5907a33 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -23,6 +23,8 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -30,6 +32,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 129a72b..e0b9559 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 02eb704..14cb53a 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 0fe43b1..000bbfb 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 3f8648d..3c5c413 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 2055101..dc7169b 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 97b13a1..07a4afe 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index c01809e..5c48c3b 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> #include <fdtdec.h> +#include <panel.h> #include <pwm.h> #include <video.h> #include <asm/system.h> @@ -21,28 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* These are the stages we go throuh in enabling the LCD */ -enum stage_t { - STAGE_START, - STAGE_PANEL_VDD, - STAGE_LVDS, - STAGE_BACKLIGHT_VDD, - STAGE_PWM, - STAGE_BACKLIGHT_EN, - STAGE_DONE, -}; - -#define FDT_LCD_TIMINGS 4 - -enum { - FDT_LCD_TIMING_REF_TO_SYNC, - FDT_LCD_TIMING_SYNC_WIDTH, - FDT_LCD_TIMING_BACK_PORCH, - FDT_LCD_TIMING_FRONT_PORCH, - - FDT_LCD_TIMING_COUNT, -}; - enum lcd_cache_t { FDT_LCD_CACHE_OFF = 0, FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, @@ -54,37 +33,15 @@ enum lcd_cache_t { /* Information about the display controller */ struct tegra_lcd_priv { - enum stage_t stage; /* Current stage we are@*/ - unsigned long timer_next; /* Time we can move onto next stage */ int width; /* width in pixels */ int height; /* height in pixels */ - - /* - * log2 of number of bpp, in general, unless it bpp is 24 in which - * case this field holds 24 also! This is a U-Boot thing. - */ - int log2_bpp; + enum video_log2_bpp log2_bpp; /* colour depth */ + struct display_timing timing; + struct udevice *panel; struct disp_ctlr *disp; /* Display controller to use */ fdt_addr_t frame_buffer; /* Address of frame buffer */ unsigned pixel_clock; /* Pixel clock in Hz */ - uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ - uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ - struct udevice *pwm; - int pwm_channel; /* PWM channel to use for backlight */ enum lcd_cache_t cache_type; - - struct gpio_desc backlight_en; /* GPIO for backlight enable */ - struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */ - struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */ - struct gpio_desc panel_vdd; /* GPIO for panel vdd */ - /* - * Panel required timings - * Timing 1: delay between panel_vdd-rise and data-rise - * Timing 2: delay between data-rise and backlight_vdd-rise - * Timing 3: delay between backlight_vdd and pwm-rise - * Timing 4: delay between pwm-rise and backlight_en-rise - */ - uint panel_timings[FDT_LCD_TIMINGS]; }; enum { @@ -150,26 +107,23 @@ static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) writel(val, &dc->cmd.state_ctrl); } -static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg) -{ - writel(priv->horiz_timing[item] | - (priv->vert_timing[item] << 16), reg); -} - static int update_display_mode(struct dc_disp_reg *disp, struct tegra_lcd_priv *priv) { + struct display_timing *dt = &priv->timing; unsigned long val; unsigned long rate; unsigned long div; writel(0x0, &disp->disp_timing_opt); - write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync); - write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width); - write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch); - write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch); - writel(priv->width | (priv->height << 16), &disp->disp_active); + writel(1 | 1 << 16, &disp->ref_to_sync); + writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width); + writel(dt->hback_porch.typ | dt->vback_porch.typ << 16, + &disp->back_porch); + writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16, + &disp->front_porch); + writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active); val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; @@ -287,12 +241,11 @@ static int setup_window(struct disp_ctl_win *win, win->stride = priv->width * (1 << priv->log2_bpp) / 8; debug("%s: depth = %d\n", __func__, priv->log2_bpp); switch (priv->log2_bpp) { - case 5: - case 24: + case VIDEO_BPP32: win->fmt = COLOR_DEPTH_R8G8B8A8; win->bpp = 32; break; - case 4: + case VIDEO_BPP16: win->fmt = COLOR_DEPTH_B5G6R5; win->bpp = 16; break; @@ -305,18 +258,6 @@ static int setup_window(struct disp_ctl_win *win, return 0; } -static void debug_timing(const char *name, unsigned int timing[]) -{ -#ifdef DEBUG - int i; - - debug("%s timing: ", name); - for (i = 0; i < FDT_LCD_TIMING_COUNT; i++) - debug("%d ", timing[i]); - debug("\n"); -#endif -} - /** * Register a new display based on device tree configuration. * @@ -363,112 +304,6 @@ static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv, return 0; } -/** - * Handle the next stage of device init - */ -static int handle_stage(const void *blob, struct tegra_lcd_priv *priv) -{ - debug("%s: stage %d\n", __func__, priv->stage); - - /* do the things for this stage */ - switch (priv->stage) { - case STAGE_START: - /* - * It is possible that the FDT has requested that the LCD be - * disabled. We currently don't support this. It would require - * changes to U-Boot LCD subsystem to have LCD support - * compiled in but not used. An easier option might be to - * still have a frame buffer, but leave the backlight off and - * remove all mention of lcd in the stdout environment - * variable. - */ - - funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); - break; - case STAGE_PANEL_VDD: - if (dm_gpio_is_valid(&priv->panel_vdd)) - dm_gpio_set_value(&priv->panel_vdd, 1); - break; - case STAGE_LVDS: - if (dm_gpio_is_valid(&priv->lvds_shutdown)) - dm_gpio_set_value(&priv->lvds_shutdown, 1); - break; - case STAGE_BACKLIGHT_VDD: - if (dm_gpio_is_valid(&priv->backlight_vdd)) - dm_gpio_set_value(&priv->backlight_vdd, 1); - break; - case STAGE_PWM: - /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ - pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); - pinmux_tristate_disable(PMUX_PINGRP_GPU); - - pwm_set_config(priv->pwm, priv->pwm_channel, 0xdf, 0xff); - pwm_set_enable(priv->pwm, priv->pwm_channel, true); - break; - case STAGE_BACKLIGHT_EN: - if (dm_gpio_is_valid(&priv->backlight_en)) - dm_gpio_set_value(&priv->backlight_en, 1); - break; - case STAGE_DONE: - break; - } - - /* set up timer for next stage */ - priv->timer_next = timer_get_us(); - if (priv->stage < FDT_LCD_TIMINGS) - priv->timer_next += priv->panel_timings[priv->stage] * 1000; - - /* move to next stage */ - priv->stage++; - return 0; -} - -/** - * Perform the next stage of the LCD init if it is time to do so. - * - * LCD init can be time-consuming because of the number of delays we need - * while waiting for the backlight power supply, etc. This function can - * be called at various times during U-Boot operation to advance the - * initialization of the LCD to the next stage if sufficient time has - * passed since the last stage. It keeps track of what stage it is up to - * and the time that it is permitted to move to the next stage. - * - * The final call should have wait=1 to complete the init. - * - * @param blob fdt blob containing LCD information - * @param wait 1 to wait until all init is complete, and then return - * 0 to return immediately, potentially doing nothing if it is - * not yet time for the next init. - */ -static int tegra_lcd_check_next_stage(const void *blob, - struct tegra_lcd_priv *priv, int wait) -{ - if (priv->stage == STAGE_DONE) - return 0; - - do { - /* wait if we need to */ - debug("%s: stage %d\n", __func__, priv->stage); - if (priv->stage != STAGE_START) { - int delay = priv->timer_next - timer_get_us(); - - if (delay > 0) { - if (wait) - udelay(delay); - else - return 0; - } - } - - if (handle_stage(blob, priv)) - return -1; - } while (wait && priv->stage != STAGE_DONE); - if (priv->stage == STAGE_DONE) - debug("%s: LCD init complete\n", __func__); - - return 0; -} - static int tegra_lcd_probe(struct udevice *dev) { struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); @@ -476,14 +311,23 @@ static int tegra_lcd_probe(struct udevice *dev) struct tegra_lcd_priv *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; int type = DCACHE_OFF; + int ret; /* Initialize the Tegra display controller */ + funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); if (tegra_display_probe(blob, priv, (void *)plat->base)) { printf("%s: Failed to probe display driver\n", __func__); return -1; } - tegra_lcd_check_next_stage(blob, priv, 1); + pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); + pinmux_tristate_disable(PMUX_PINGRP_GPU); + + ret = panel_enable_backlight(priv->panel); + if (ret) { + debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret); + return ret; + } /* Set up the LCD caching as requested */ if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH) @@ -507,13 +351,11 @@ static int tegra_lcd_probe(struct udevice *dev) static int tegra_lcd_ofdata_to_platdata(struct udevice *dev) { struct tegra_lcd_priv *priv = dev_get_priv(dev); - struct fdtdec_phandle_args args; const void *blob = gd->fdt_blob; + struct display_timing *timing; int node = dev->of_offset; - int front, back, ref; int panel_node; int rgb; - int bpp, bit; int ret; priv->disp = (struct disp_ctlr *)dev_get_addr(dev); @@ -523,96 +365,40 @@ static int tegra_lcd_ofdata_to_platdata(struct udevice *dev) } rgb = fdt_subnode_offset(blob, node, "rgb"); - - panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); - if (panel_node < 0) { - debug("%s: Cannot find panel information\n", __func__); + if (rgb < 0) { + debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n", + __func__, dev->name, rgb); return -EINVAL; } - priv->width = fdtdec_get_int(blob, panel_node, "xres", -1); - priv->height = fdtdec_get_int(blob, panel_node, "yres", -1); - priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0); - if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) { - debug("%s: Pixel parameters missing\n", __func__); - return -EINVAL; - } - - back = fdtdec_get_int(blob, panel_node, "left-margin", -1); - front = fdtdec_get_int(blob, panel_node, "right-margin", -1); - ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1); - if ((back | front | ref) == -1) { - debug("%s: Horizontal parameters missing\n", __func__); - return -EINVAL; - } - - /* Use a ref-to-sync of 1 always, and take this from the front porch */ - priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; - priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; - priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back; - priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - - priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC]; - debug_timing("horiz", priv->horiz_timing); - - back = fdtdec_get_int(blob, panel_node, "upper-margin", -1); - front = fdtdec_get_int(blob, panel_node, "lower-margin", -1); - ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1); - if ((back | front | ref) == -1) { - debug("%s: Vertical parameters missing\n", __func__); - return -EINVAL; - } - - priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; - priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; - priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back; - priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - - priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC]; - debug_timing("vert", priv->vert_timing); - - bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1); - bit = ffs(bpp) - 1; - if (bpp == (1 << bit)) - priv->log2_bpp = bit; - else - priv->log2_bpp = bpp; - if (bpp == -1) { - debug("%s: Pixel bpp parameters missing\n", __func__); + ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); + if (ret) { + debug("%s: Cannot read display timing for '%s' (ret=%d)\n", + __func__, dev->name, ret); return -EINVAL; } + timing = &priv->timing; + priv->width = timing->hactive.typ; + priv->height = timing->vactive.typ; + priv->pixel_clock = timing->pixelclock.typ; + priv->log2_bpp = VIDEO_BPP16; - if (fdtdec_parse_phandle_with_args(blob, panel_node, "nvidia,pwm", - "#pwm-cells", 0, 0, &args)) { - debug("%s: Unable to decode PWM\n", __func__); + /* + * Sadly the panel phandle is in an rgb subnode so we cannot use + * uclass_get_device_by_phandle(). + */ + panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); + if (panel_node < 0) { + debug("%s: Cannot find panel information\n", __func__); return -EINVAL; } - - ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm); + ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node, + &priv->panel); if (ret) { - debug("%s: Unable to find PWM\n", __func__); - return -EINVAL; + debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__, + dev->name, ret); + return ret; } - priv->pwm_channel = args.args[0]; - - priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type", - FDT_LCD_CACHE_WRITE_BACK_FLUSH); - - /* These GPIOs are all optional */ - gpio_request_by_name_nodev(blob, panel_node, - "nvidia,backlight-enable-gpios", 0, - &priv->backlight_en, GPIOD_IS_OUT); - gpio_request_by_name_nodev(blob, panel_node, - "nvidia,lvds-shutdown-gpios", 0, - &priv->lvds_shutdown, GPIOD_IS_OUT); - gpio_request_by_name_nodev(blob, panel_node, - "nvidia,backlight-vdd-gpios", 0, - &priv->backlight_vdd, GPIOD_IS_OUT); - gpio_request_by_name_nodev(blob, panel_node, - "nvidia,panel-vdd-gpios", 0, - &priv->panel_vdd, GPIOD_IS_OUT); - - if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings", - priv->panel_timings, FDT_LCD_TIMINGS)) - return -EINVAL; return 0; } -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 5/6] tegra: video: Always use write-through cache on LCD 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass ` (3 preceding siblings ...) 2016-05-08 22:55 ` [U-Boot] [PATCH v2 4/6] video: tegra: Move to using simple-panel and pwm-backlight Simon Glass @ 2016-05-08 22:55 ` Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 6/6] fdt: Drop some unused compatible strings Simon Glass 2016-05-09 16:53 ` [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Stephen Warren 6 siblings, 0 replies; 12+ messages in thread From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw) To: u-boot This seems to give the best performance, so let's use it always. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> --- Changes in v2: None drivers/video/tegra.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 5c48c3b..217f05f 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -22,15 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -enum lcd_cache_t { - FDT_LCD_CACHE_OFF = 0, - FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, - FDT_LCD_CACHE_WRITE_BACK = 1 << 1, - FDT_LCD_CACHE_FLUSH = 1 << 2, - FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | - FDT_LCD_CACHE_FLUSH, -}; - /* Information about the display controller */ struct tegra_lcd_priv { int width; /* width in pixels */ @@ -41,7 +32,6 @@ struct tegra_lcd_priv { struct disp_ctlr *disp; /* Display controller to use */ fdt_addr_t frame_buffer; /* Address of frame buffer */ unsigned pixel_clock; /* Pixel clock in Hz */ - enum lcd_cache_t cache_type; }; enum { @@ -310,7 +300,6 @@ static int tegra_lcd_probe(struct udevice *dev) struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct tegra_lcd_priv *priv = dev_get_priv(dev); const void *blob = gd->fdt_blob; - int type = DCACHE_OFF; int ret; /* Initialize the Tegra display controller */ @@ -329,15 +318,11 @@ static int tegra_lcd_probe(struct udevice *dev) return ret; } - /* Set up the LCD caching as requested */ - if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH) - type = DCACHE_WRITETHROUGH; - else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK) - type = DCACHE_WRITEBACK; - mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type); + mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, + DCACHE_WRITETHROUGH); /* Enable flushing after LCD writes if requested */ - video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH); + video_set_flush_dcache(dev, true); uc_priv->xsize = priv->width; uc_priv->ysize = priv->height; -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 6/6] fdt: Drop some unused compatible strings 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass ` (4 preceding siblings ...) 2016-05-08 22:55 ` [U-Boot] [PATCH v2 5/6] tegra: video: Always use write-through cache on LCD Simon Glass @ 2016-05-08 22:55 ` Simon Glass 2016-05-09 16:53 ` [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Stephen Warren 6 siblings, 0 replies; 12+ messages in thread From: Simon Glass @ 2016-05-08 22:55 UTC (permalink / raw) To: u-boot We have driver-model drivers for some of these now, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: None include/fdtdec.h | 4 ---- lib/fdtdec.c | 4 ---- 2 files changed, 8 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index fb88273..1c0b52a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -119,10 +119,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ - COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ - COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ - COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ @@ -145,7 +142,6 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS_DWMMC, /* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC, /* Exynos MMC controller */ - COMPAT_SAMSUNG_EXYNOS_SERIAL, /* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 70acc29..93be86c 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -26,10 +26,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"), COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"), COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), - COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), - COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"), COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"), - COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"), COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), @@ -50,7 +47,6 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"), COMPAT(SAMSUNG_EXYNOS_DWMMC, "samsung,exynos-dwmmc"), COMPAT(SAMSUNG_EXYNOS_MMC, "samsung,exynos-mmc"), - COMPAT(SAMSUNG_EXYNOS_SERIAL, "samsung,exynos4210-uart"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686"), COMPAT(GENERIC_SPI_FLASH, "spi-flash"), COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"), -- 2.8.0.rc3.226.g39d4020 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass ` (5 preceding siblings ...) 2016-05-08 22:55 ` [U-Boot] [PATCH v2 6/6] fdt: Drop some unused compatible strings Simon Glass @ 2016-05-09 16:53 ` Stephen Warren 6 siblings, 0 replies; 12+ messages in thread From: Stephen Warren @ 2016-05-09 16:53 UTC (permalink / raw) To: u-boot On 05/08/2016 04:55 PM, Simon Glass wrote: > The original tegra20 display driver was written before Linux had device tree > bindings for display. Since then Linux has developed a robust set of bindings > covering various aspects of enabling a display. > > This series moves closer to those bindings by using the panel and backlight > as separate drivers. The device tree files for seaboard, ventana and harmony > thereby become almost the same as Linux. Thierry, since you're most familiar with display support and IIRC have worked on this in U-Boot too, perhaps you could review this series? Let me know if you need me to forward the emails to you. > Unfortunately this breaks the other boards, which will need a similar sync. > So I'm not sure how easy it will be to accept this series. Still, it seems > worth sending it out in the hope that board maintainers can help. I have > kept this series separate so that it can progress separately. Which boards in particular? If this is just other Tegra20 boards and simply because you haven't copied the relevant DTs from the kernel and/or made updates to any U-Boot defconfigs and/or config headers, can't you do that mechanically too? Sure you'll need other people to test boards you don't have, but IIUC the source changes are mechanical. If it's non-Tegra20 boards, can you expand on the cause of the breakage? ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-05-13 3:11 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-05-08 22:55 [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 1/6] errno: Add copyright header and header guard Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 2/6] errno: Allow errno_str() to be used without CONFIG_ERRNO_STR Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 3/6] tegra: dts: Sync tegra20 device tree files with Linux Simon Glass 2016-05-09 17:09 ` Stephen Warren 2016-05-09 19:26 ` Simon Glass 2016-05-10 17:45 ` Stephen Warren 2016-05-13 3:11 ` Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 4/6] video: tegra: Move to using simple-panel and pwm-backlight Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 5/6] tegra: video: Always use write-through cache on LCD Simon Glass 2016-05-08 22:55 ` [U-Boot] [PATCH v2 6/6] fdt: Drop some unused compatible strings Simon Glass 2016-05-09 16:53 ` [U-Boot] [PATCH v2 0/6] tegra: Move tegra20 towards the 'new' display bindings Stephen Warren
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