[PATCH RESEND v4 0/9] MIPS: Loongson: Add the Loongson-1A processor support

[PATCH RESEND v4 0/9] MIPS: Loongson: Add the Loongson-1A processor support

[Binbin Zhou]

The Loongson 1A is similar with Loongson 1B, which is a 32-bit SoC.
It implements the MIPS32 release 2 instruction set.

They share the same PRID, so we rewrite the PRID_REV_LOONGSON1B to
PRID_REV_LOONGSON1A_1B, and use their CPU macros to distinguish.

However, the pll register of Loongson-1A is write-only, so the cpu clk 
should be set manually with the command line.

The format of command is cpu_clk=osc_clk,cpu_mul
the osc_clk standby cpu clock and the cpu_mul repect the clock multiplier.

For example, we use the command cpu_clk=33333333,8

Changes since v1:

- According commit c908656a7531771ae7642990a7c5f3c7307bd612
  (MIPS: Loongson: Naming style cleanup and rework) to fix the naming style.

Changes since v2:

- Remove__irq_set_handler_locked()
- Rebases on top of v4.5-rc5.

Changes since v3:
- Move ls1x CPU irq setting to driver/irqchip
- Rebases on top of v4.6-rc7.

Binbin Zhou(9):
 MIPS: Loongson: Add basic Loongson-1A CPU support
 MIPS: Loongson: Add Loongson-1A Kconfig options
 MIPS: Loongson: Add platform devices for Loongson-1A/1B
 MIPS: Loongson: Add loongson-1A board support
 MIPS: Loongson-1A: workaround of pll register's write-only property
 MIPS: irqchip/ls1x-cpu: Move the CPU IRQ driver from arch/mips/loongson32/common/
 MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM
 MIPS: Loongson-1B: Update config file
 MIPS: Loongson: Add a Loongson-1A default config file

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
-- 
 arch/mips/Kconfig                                 |  11 ++++++
 arch/mips/configs/loongson1a_defconfig            | 131 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/configs/loongson1b_defconfig            |   1 +
 arch/mips/include/asm/cpu-type.h                  |   3 +-
 arch/mips/include/asm/cpu.h                       |   2 +-
 arch/mips/include/asm/irq_cpu.h                   |   1 +
 arch/mips/include/asm/mach-loongson32/dma.h       |   1 +
 arch/mips/include/asm/mach-loongson32/irq.h       |   1 +
 arch/mips/include/asm/mach-loongson32/loongson1.h | 183 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------
 arch/mips/include/asm/mach-loongson32/nand.h      |   1 +
 arch/mips/include/asm/mach-loongson32/platform.h  |  14 ++++++++
 arch/mips/include/asm/mach-loongson32/regs-mux.h  |   2 +-
 arch/mips/include/asm/sparsemem.h                 |   6 +++-
 arch/mips/kernel/cpu-probe.c                      |   6 +++-
 arch/mips/loongson32/Kconfig                      |  17 +++++++++
 arch/mips/loongson32/Makefile                     |   6 ++++
 arch/mips/loongson32/Platform                     |   1 +
 arch/mips/loongson32/common/irq.c                 | 128 +------------------------------------------------------------------
 arch/mips/loongson32/common/platform.c            | 256 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
 arch/mips/loongson32/common/prom.c                |   6 ++++
 arch/mips/loongson32/common/reset.c               |   6 ++++
 arch/mips/loongson32/common/setup.c               |  49 +++++++++++++++++++++++++-
 arch/mips/loongson32/ls1a/Makefile                |   5 +++
 arch/mips/loongson32/ls1a/board.c                 | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/mm/c-r4k.c                              |   9 +++++
 drivers/clk/clk-ls1x.c                            |  22 +++++++++---
 drivers/irqchip/Makefile                          |   1 +
 drivers/irqchip/irq-ls1x-cpu.c                    | 242 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 28 files changed, 1054 insertions(+), 179 deletions(-)
 create mode 100644 arch/mips/configs/loongson1a_defconfig
 create mode 100644 arch/mips/loongson32/ls1a/Makefile
 create mode 100644 arch/mips/loongson32/ls1a/board.c
 create mode 100644 drivers/irqchip/irq-ls1x-cpu.c
--
1.9.0

[PATCH RESEND v4 1/9] MIPS: Loongson: Add basic Loongson-1A CPU support

[Binbin Zhou]

The Loongson 1A is similar with Loongson 1B, which is a 32-bit SoC.
It implements the MIPS32 release 2 instruction set.

They share the same PRID, so we rewrite the PRID_REV_LOONGSON1B to
PRID_REV_LOONGSON1A_1B, and use their CPU macros to distinguish.

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/cpu-type.h    | 3 ++-
 arch/mips/include/asm/cpu.h         | 2 +-
 arch/mips/kernel/cpu-probe.c        | 6 +++++-
 arch/mips/loongson32/Platform       | 1 +
 arch/mips/loongson32/common/setup.c | 6 +++++-
 arch/mips/mm/c-r4k.c                | 9 +++++++++
 6 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index fbe1881..ab69178 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -24,7 +24,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 	case CPU_LOONGSON3:
 #endif
 
-#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1A) || \
+    defined(CONFIG_SYS_HAS_CPU_LOONGSON1B)
 	case CPU_LOONGSON1:
 #endif
 
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f672df8..43812ba 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -239,7 +239,7 @@
 #define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
 #define PRID_REV_VR4130		0x0080
 #define PRID_REV_34K_V1_0_2	0x0022
-#define PRID_REV_LOONGSON1B	0x0020
+#define PRID_REV_LOONGSON1A_1B	0x0020
 #define PRID_REV_LOONGSON2E	0x0002
 #define PRID_REV_LOONGSON2F	0x0003
 #define PRID_REV_LOONGSON3A_R1	0x0005
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5ac5c3e..efa8c33 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1497,8 +1497,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 		c->cputype = CPU_LOONGSON1;
 
 		switch (c->processor_id & PRID_REV_MASK) {
-		case PRID_REV_LOONGSON1B:
+		case PRID_REV_LOONGSON1A_1B:
+#ifdef CONFIG_CPU_LOONGSON1A
+			__cpu_name[cpu] = "Loongson 1A";
+#else
 			__cpu_name[cpu] = "Loongson 1B";
+#endif
 			break;
 		}
 
diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
index ebb6dc2..e114c85 100644
--- a/arch/mips/loongson32/Platform
+++ b/arch/mips/loongson32/Platform
@@ -4,4 +4,5 @@ cflags-$(CONFIG_CPU_LOONGSON1)	+= \
 
 platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/
 cflags-$(CONFIG_MACH_LOONGSON32)	+= -I$(srctree)/arch/mips/include/asm/mach-loongson32
+load-$(CONFIG_LOONGSON1_LS1A)		+= 0xffffffff80200000
 load-$(CONFIG_LOONGSON1_LS1B)		+= 0xffffffff80100000
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 62f41af..c3d2036 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -21,8 +21,12 @@ const char *get_system_type(void)
 	unsigned int processor_id = (&current_cpu_data)->processor_id;
 
 	switch (processor_id & PRID_REV_MASK) {
-	case PRID_REV_LOONGSON1B:
+	case PRID_REV_LOONGSON1A_1B:
+#ifdef CONFIG_CPU_LOONGSON1A
+		return "LOONGSON LS1A";
+#else
 		return "LOONGSON LS1B";
+#endif
 	default:
 		return "LOONGSON (unknown)";
 	}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ef7f925..8c9eabc 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1306,6 +1306,15 @@ static void probe_pcache(void)
 			c->dcache.flags |= MIPS_CACHE_PINDEX;
 			break;
 		}
+	case CPU_LOONGSON1:
+		if ((read_c0_config7() & (1 << 16))) {
+			/*
+			 * effectively physically indexed dcache,
+			 * thus no virtual aliases.
+			 */
+			c->dcache.flags |= MIPS_CACHE_PINDEX;
+			break;
+		}
 	default:
 		if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
 			c->dcache.flags |= MIPS_CACHE_ALIASES;
-- 
1.9.1

Re: [PATCH RESEND v4 1/9] MIPS: Loongson: Add basic Loongson-1A CPU support

[Ralf Baechle]

On Thu, May 19, 2016 at 09:38:26AM +0800, Binbin Zhou wrote:

> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1497,8 +1497,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
>  		c->cputype = CPU_LOONGSON1;
>  
>  		switch (c->processor_id & PRID_REV_MASK) {
> -		case PRID_REV_LOONGSON1B:
> +		case PRID_REV_LOONGSON1A_1B:
> +#ifdef CONFIG_CPU_LOONGSON1A
> +			__cpu_name[cpu] = "Loongson 1A";
> +#else
>  			__cpu_name[cpu] = "Loongson 1B";
> +#endif

Is there no way to distinguish between Loongson 1A and 1B at runtime for
example by looking at the version number or similar?

> --- a/arch/mips/loongson32/common/setup.c
> +++ b/arch/mips/loongson32/common/setup.c
> @@ -21,8 +21,12 @@ const char *get_system_type(void)
>  	unsigned int processor_id = (&current_cpu_data)->processor_id;
>  
>  	switch (processor_id & PRID_REV_MASK) {
> -	case PRID_REV_LOONGSON1B:
> +	case PRID_REV_LOONGSON1A_1B:
> +#ifdef CONFIG_CPU_LOONGSON1A
> +		return "LOONGSON LS1A";
> +#else
>  		return "LOONGSON LS1B";
> +#endif
>  	default:
>  		return "LOONGSON (unknown)";
>  	}

Ditto.

  Ralf

[PATCH RESEND v4 2/9] MIPS: Loongson: Add Loongson-1A Kconfig options

[Binbin Zhou]

Added Kconfig options include: Loongson-1A CPU and machine definition,
CPU cache features, 32-bit kernel and early printk support.

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/Kconfig            | 11 +++++++++++
 arch/mips/loongson32/Kconfig | 16 ++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ac9bfad..dffa359 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1402,6 +1402,14 @@ config CPU_LOONGSON2F
 	  have a similar programming interface with FPGA northbridge used in
 	  Loongson2E.
 
+config CPU_LOONGSON1A
+	bool "Loongson 1A"
+	depends on SYS_HAS_CPU_LOONGSON1A
+	select CPU_LOONGSON1
+	help
+	  The Loongson 1A is a 32-bit SoC, which implements the MIPS32
+	  release 2 instruction set.
+
 config CPU_LOONGSON1B
 	bool "Loongson 1B"
 	depends on SYS_HAS_CPU_LOONGSON1B
@@ -1856,6 +1864,9 @@ config SYS_HAS_CPU_LOONGSON2F
 	select CPU_SUPPORTS_ADDRWINCFG if 64BIT
 	select CPU_SUPPORTS_UNCACHED_ACCELERATED
 
+config SYS_HAS_CPU_LOONGSON1A
+	bool
+
 config SYS_HAS_CPU_LOONGSON1B
 	bool
 
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 7704f20..35effa8 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -3,6 +3,22 @@ if MACH_LOONGSON32
 choice
 	prompt "Machine Type"
 
+config LOONGSON1_LS1A
+	bool "Loongson LS1A board"
+	select CEVT_R4K
+	select CSRC_R4K
+	select SYS_HAS_CPU_LOONGSON1A
+	select DMA_NONCOHERENT
+	select BOOT_ELF32
+	select IRQ_MIPS_CPU
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_SUPPORTS_MIPS16
+	select SYS_HAS_EARLY_PRINTK
+	select USE_GENERIC_EARLY_PRINTK_8250
+	select COMMON_CLK
+
 config LOONGSON1_LS1B
 	bool "Loongson LS1B board"
 	select CEVT_R4K if !MIPS_EXTERNAL_TIMER
-- 
1.9.1

[PATCH RESEND v4 3/9] MIPS: Loongson: Add platform devices for Loongson-1A/1B

[Binbin Zhou]

Added basic platform devices for Loongson 1A, including serial port,
ethernet, AHCI, USB, RTC, SPI and so on.

Most of the devices are shared with Loongson 1B, like serial port,
ethernet, USB and so on.
Specially, something like AHCI is only used in Loonson 1A.

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/mach-loongson32/dma.h       |   1 +
 arch/mips/include/asm/mach-loongson32/irq.h       |   1 +
 arch/mips/include/asm/mach-loongson32/loongson1.h | 172 ++++++++++++---
 arch/mips/include/asm/mach-loongson32/nand.h      |   1 +
 arch/mips/include/asm/mach-loongson32/platform.h  |  10 +
 arch/mips/include/asm/mach-loongson32/regs-mux.h  |   2 +-
 arch/mips/loongson32/common/irq.c                 |   2 +-
 arch/mips/loongson32/common/platform.c            | 243 +++++++++++++++++++++-
 8 files changed, 390 insertions(+), 42 deletions(-)

diff --git a/arch/mips/include/asm/mach-loongson32/dma.h b/arch/mips/include/asm/mach-loongson32/dma.h
index ad1dec7..170c16a 100644
--- a/arch/mips/include/asm/mach-loongson32/dma.h
+++ b/arch/mips/include/asm/mach-loongson32/dma.h
@@ -20,6 +20,7 @@ struct plat_ls1x_dma {
 	int nr_channels;
 };
 
+extern struct plat_ls1x_dma ls1a_dma_pdata;
 extern struct plat_ls1x_dma ls1b_dma_pdata;
 
 #endif /* __ASM_MACH_LOONGSON32_DMA_H */
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index c1c7441..e17232c 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -64,6 +64,7 @@
 #define LS1X_OHCI_IRQ			LS1X_IRQ(1, 1)
 #define LS1X_GMAC0_IRQ			LS1X_IRQ(1, 2)
 #define LS1X_GMAC1_IRQ			LS1X_IRQ(1, 3)
+#define LS1X_AHCI_IRQ			LS1X_IRQ(1, 4)
 
 #define LS1X_IRQS		(LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
 
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 978f6df..8ba34f9 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -14,35 +14,149 @@
 
 #define DEFAULT_MEMSIZE			256	/* If no memsize provided */
 
-/* Loongson 1 Register Bases */
-#define LS1X_MUX_BASE			0x1fd00420
-#define LS1X_INTC_BASE			0x1fd01040
-#define LS1X_GPIO0_BASE			0x1fd010c0
-#define LS1X_GPIO1_BASE			0x1fd010c4
-#define LS1X_DMAC_BASE			0x1fd01160
-#define LS1X_EHCI_BASE			0x1fe00000
-#define LS1X_OHCI_BASE			0x1fe08000
-#define LS1X_GMAC0_BASE			0x1fe10000
-#define LS1X_GMAC1_BASE			0x1fe20000
-
-#define LS1X_UART0_BASE			0x1fe40000
-#define LS1X_UART1_BASE			0x1fe44000
-#define LS1X_UART2_BASE			0x1fe48000
-#define LS1X_UART3_BASE			0x1fe4c000
-#define LS1X_CAN0_BASE			0x1fe50000
-#define LS1X_CAN1_BASE			0x1fe54000
-#define LS1X_I2C0_BASE			0x1fe58000
-#define LS1X_I2C1_BASE			0x1fe68000
-#define LS1X_I2C2_BASE			0x1fe70000
-#define LS1X_PWM0_BASE			0x1fe5c000
-#define LS1X_PWM1_BASE			0x1fe5c010
-#define LS1X_PWM2_BASE			0x1fe5c020
-#define LS1X_PWM3_BASE			0x1fe5c030
-#define LS1X_WDT_BASE			0x1fe5c060
-#define LS1X_RTC_BASE			0x1fe64000
-#define LS1X_AC97_BASE			0x1fe74000
-#define LS1X_NAND_BASE			0x1fe78000
-#define LS1X_CLK_BASE			0x1fe78030
+#define LS1X_DC_REG_BASE		0x1c200000
+#define LS1X_MUX_REG_BASE		0x1f000000
+
+#define LS1X_CFG_REG_BASE		(LS1X_MUX_REG_BASE + 0x00d00000)
+
+#define LS1X_GPIO_MUX_BASE		(LS1X_CFG_REG_BASE + 0x0420)
+
+/*INT regs */
+#define LS1X_INT_REG_BASE		(LS1X_CFG_REG_BASE + 0x1040)
+
+/* GPIO regs */
+#define LS1X_GPIO_REG_BASE		(LS1X_CFG_REG_BASE + 0x10c0)
+#define LS1X_GPIO_CFG0_REG		(LS1X_CFG_REG_BASE + 0x10c0)
+#define LS1X_GPIO_CFG1_REG		(LS1X_CFG_REG_BASE + 0x10c4)
+#define LS1X_GPIO_CFG2_REG		(LS1X_CFG_REG_BASE + 0x10c8)
+#define LS1X_GPIO_OE0_REG		(LS1X_CFG_REG_BASE + 0x10d0)
+#define LS1X_GPIO_OE1_REG		(LS1X_CFG_REG_BASE + 0x10d4)
+#define LS1X_GPIO_OE2_REG		(LS1X_CFG_REG_BASE + 0x10d8)
+#define LS1X_GPIO_IN0_REG		(LS1X_CFG_REG_BASE + 0x10e0)
+#define LS1X_GPIO_IN1_REG		(LS1X_CFG_REG_BASE + 0x10e4)
+#define LS1X_GPIO_IN2_REG		(LS1X_CFG_REG_BASE + 0x10e8)
+#define LS1X_GPIO_OUT0_REG		(LS1X_CFG_REG_BASE + 0x10f0)
+#define LS1X_GPIO_OUT1_REG		(LS1X_CFG_REG_BASE + 0x10f4)
+#define LS1X_GPIO_OUT2_REG		(LS1X_CFG_REG_BASE + 0x10f8)
+
+#define LS1X_DMA_ORDER_REG		(LS1X_CFG_REG_BASE + 0x1160)
+
+/* USB regs */
+#define LS1X_EHCI_BASE			(LS1X_MUX_REG_BASE + 0x00e00000)
+#define LS1X_OHCI_BASE			(LS1X_MUX_REG_BASE + 0x00e08000)
+
+/* GMAC regs */
+#define LS1X_GMAC0_BASE			(LS1X_MUX_REG_BASE + 0x00e10000)
+#define LS1X_GMAC0_DMA_REG		(LS1X_GMAC0_BASE + 0x1000)
+#define LS1X_GMAC1_BASE			(LS1X_MUX_REG_BASE + 0x00e20000)
+#define LS1X_GMAC1_DMA_REG		(LS1X_GMAC1_BASE + 0x1000)
+
+/* SATA regs */
+#define LS1X_AHCI_BASE			(LS1X_MUX_REG_BASE + 0x00e30000)
+
+/* APB regs */
+#define LS1X_APB_REG_BASE		(LS1X_MUX_REG_BASE + 0x00e40000)
+
+/* UART regs */
+#define LS1X_UART0_BASE			(LS1X_APB_REG_BASE + 0x0000)
+#define LS1X_UART1_BASE			(LS1X_APB_REG_BASE + 0x4000)
+#define LS1X_UART2_BASE			(LS1X_APB_REG_BASE + 0x8000)
+#define LS1X_UART3_BASE			(LS1X_APB_REG_BASE + 0xc000)
+
+/* CAN regs */
+#define LS1X_CAN0_BASE			(LS1X_APB_REG_BASE + 0x10000)
+#define LS1X_CAN1_BASE			(LS1X_APB_REG_BASE + 0x14000)
+
+/* I2C regs */
+#define LS1X_I2C0_BASE			(LS1X_APB_REG_BASE + 0x18000)
+#define LS1X_I2C0_PRER_LO_REG		(LS1X_I2C0_BASE + 0x0)
+#define LS1X_I2C0_PRER_HI_REG		(LS1X_I2C0_BASE + 0x1)
+#define LS1X_I2C0_CTR_REG		(LS1X_I2C0_BASE + 0x2)
+#define LS1X_I2C0_TXR_REG		(LS1X_I2C0_BASE + 0x3)
+#define LS1X_I2C0_RXR_REG		(LS1X_I2C0_BASE + 0x3)
+#define LS1X_I2C0_CR_REG		(LS1X_I2C0_BASE + 0x4)
+#define LS1X_I2C0_SR_REG		(LS1X_I2C0_BASE + 0x4)
+
+#define LS1X_I2C1_BASE			(LS1X_APB_REG_BASE + 0x28000)
+#define LS1X_I2C1_PRER_LO_REG		(LS1X_I2C1_BASE + 0x0)
+#define LS1X_I2C1_PRER_HI_REG		(LS1X_I2C1_BASE + 0x1)
+#define LS1X_I2C1_CTR_REG		(LS1X_I2C1_BASE + 0x2)
+#define LS1X_I2C1_TXR_REG		(LS1X_I2C1_BASE + 0x3)
+#define LS1X_I2C1_RXR_REG		(LS1X_I2C1_BASE + 0x3)
+#define LS1X_I2C1_CR_REG		(LS1X_I2C1_BASE + 0x4)
+#define LS1X_I2C1_SR_REG		(LS1X_I2C1_BASE + 0x4)
+
+#define LS1X_I2C2_BASE			(LS1X_APB_REG_BASE + 0x30000)
+#define LS1X_I2C2_PRER_LO_REG		(LS1X_I2C2_BASE + 0x0)
+#define LS1X_I2C2_PRER_HI_REG		(LS1X_I2C2_BASE + 0x1)
+#define LS1X_I2C2_CTR_REG		(LS1X_I2C2_BASE + 0x2)
+#define LS1X_I2C2_TXR_REG		(LS1X_I2C2_BASE + 0x3)
+#define LS1X_I2C2_RXR_REG		(LS1X_I2C2_BASE + 0x3)
+#define LS1X_I2C2_CR_REG		(LS1X_I2C2_BASE + 0x4)
+#define LS1X_I2C2_SR_REG		(LS1X_I2C2_BASE + 0x4)
+
+#define LS1X_PWM_REG_BASE		(LS1X_APB_REG_BASE + 0x1c000)
+#define LS1X_PWM0_BASE			(LS1X_PWM_REG_BASE + 0x00)
+#define LS1X_PWM1_BASE			(LS1X_PWM_REG_BASE + 0x10)
+#define LS1X_PWM2_BASE			(LS1X_PWM_REG_BASE + 0x20)
+#define LS1X_PWM3_BASE			(LS1X_PWM_REG_BASE + 0x30)
+
+/* RTC regs */
+#define LS1X_RTC_BASE			(LS1X_APB_REG_BASE + 0x24000)
+
+/* AC97 regs */
+#define LS1X_AC97_BASE			(LS1X_APB_REG_BASE + 0x34000)
+
+/* Watchdog regs */
+#ifdef CONFIG_CPU_LOONGSON1A
+#define LS1X_WDT_BASE			(LS1X_MUX_REG_BASE + 0x00e7c060)
+#else
+#define LS1X_WDT_BASE			(LS1X_MUX_REG_BASE + 0x00e5c060)
+#endif
+
+/* CLK regs */
+#define LS1X_CLK_BASE			(LS1X_MUX_REG_BASE + 0x00e78030)
+
+/* NAND regs */
+#define LS1X_NAND_REG_BASE		(LS1X_APB_REG_BASE + 0x38000)
+#define LS1X_NAND_CMD_REG		(LS1X_NAND_REG_BASE + 0x0000)
+#define LS1X_NAND_ADDR_C_REG		(LS1X_NAND_REG_BASE + 0x0004)
+#define LS1X_NAND_ADDR_R_REG		(LS1X_NAND_REG_BASE + 0x0008)
+#define LS1X_NAND_TIMING_REG		(LS1X_NAND_REG_BASE + 0x000c)
+#define LS1X_NAND_IDL_REG		(LS1X_NAND_REG_BASE + 0x0010)
+#define LS1X_NAND_STA_IDH_REG		(LS1X_NAND_REG_BASE + 0x0014)
+#define LS1X_NAND_PARAM_REG		(LS1X_NAND_REG_BASE + 0x0018)
+#define LS1X_NAND_OP_NUM_REG		(LS1X_NAND_REG_BASE + 0x001c)
+#define LS1X_NAND_CSRDY_MAP_REG		(LS1X_NAND_REG_BASE + 0x0020)
+#define LS1X_NAND_DMA_ACC_REG		(LS1X_NAND_REG_BASE + 0x0040)
+
+/* ACPI regs for ls1a */
+#define LS1X_ACPI_REG_BASE		(LS1X_APB_REG_BASE + 0x3c000)
+#define LS1X_PM1_STS_REG		(LS1X_ACPI_REG_BASE + 0x0000)
+#define LS1X_PM1_EN_REG			(LS1X_ACPI_REG_BASE + 0x0004)
+#define LS1X_PM1_CNT_REG		(LS1X_ACPI_REG_BASE + 0x0008)
+#define LS1X_PM1_TMR_REG		(LS1X_ACPI_REG_BASE + 0x000c)
+#define LS1X_P_CNT_REG			(LS1X_ACPI_REG_BASE + 0x0010)
+#define LS1X_P_LVL2_REG			(LS1X_ACPI_REG_BASE + 0x0014)
+#define LS1X_P_LVL3_REG			(LS1X_ACPI_REG_BASE + 0x0018)
+#define LS1X_GPE0_STS_REG		(LS1X_ACPI_REG_BASE + 0x0020)
+#define LS1X_GPE0_EN_REG		(LS1X_ACPI_REG_BASE + 0x0024)
+#define LS1X_PM_CONF1_REG		(LS1X_ACPI_REG_BASE + 0x0030)
+#define LS1X_PM_CONF2_REG		(LS1X_ACPI_REG_BASE + 0x0034)
+#define LS1X_PM_CONF3_REG		(LS1X_ACPI_REG_BASE + 0x0038)
+#define LS1X_RST_CNT_REG		(LS1X_ACPI_REG_BASE + 0x0044)
+#define LS1X_CPU_INIT_REG		(LS1X_ACPI_REG_BASE + 0x0050)
+
+#define LS1X_SPI0_REG_BASE		(LS1X_MUX_REG_BASE + 0x00e80000)
+#define LS1X_SPI1_REG_BASE		(LS1X_MUX_REG_BASE + 0x00ec0000)
+
+/* LPC regs */
+#define LS1X_LPC_IO_BASE		(LS1X_MUX_REG_BASE + 0x00f00000)
+#define LS1X_LPC_REG_BASE		(LS1X_MUX_REG_BASE + 0x00f10200)
+#define LS1X_LPC_CFG0_REG		(LS1X_LPC_REG_BASE + 0x0)
+#define LS1X_LPC_CFG1_REG		(LS1X_LPC_REG_BASE + 0x4)
+#define LS1X_LPC_CFG2_REG		(LS1X_LPC_REG_BASE + 0x8)
+#define LS1X_LPC_CFG3_REG		(LS1X_LPC_REG_BASE + 0xc)
 
 #include <regs-clk.h>
 #include <regs-mux.h>
diff --git a/arch/mips/include/asm/mach-loongson32/nand.h b/arch/mips/include/asm/mach-loongson32/nand.h
index e274912..d141e0a 100644
--- a/arch/mips/include/asm/mach-loongson32/nand.h
+++ b/arch/mips/include/asm/mach-loongson32/nand.h
@@ -23,6 +23,7 @@ struct plat_ls1x_nand {
 	int wait_cycle;
 };
 
+extern struct plat_ls1x_nand ls1a_nand_pdata;
 extern struct plat_ls1x_nand ls1b_nand_pdata;
 
 bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param);
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index 672531a..c48f17b 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -25,6 +25,16 @@ extern struct platform_device ls1x_gpio0_pdev;
 extern struct platform_device ls1x_gpio1_pdev;
 extern struct platform_device ls1x_nand_pdev;
 extern struct platform_device ls1x_rtc_pdev;
+extern struct platform_device ls1x_fb_pdev;
+extern struct platform_device ls1x_i2c0_pdev;
+extern struct platform_device ls1x_i2c1_pdev;
+extern struct platform_device ls1x_i2c2_pdev;
+extern struct platform_device ls1x_ahci_pdev;
+extern struct platform_device ls1x_ohci_pdev;
+extern struct platform_device ls1x_wat_pdev;
+extern struct platform_device ls1x_audio_pdev;
+extern struct platform_device ls1x_spi0_pdev;
+extern struct platform_device ls1x_spi1_pdev;
 
 void __init ls1x_clk_init(void);
 void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
index 7c394f9..d52ea03 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-mux.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -13,7 +13,7 @@
 #define __ASM_MACH_LOONGSON32_REGS_MUX_H
 
 #define LS1X_MUX_REG(x) \
-		((void __iomem *)KSEG1ADDR(LS1X_MUX_BASE + (x)))
+		((void __iomem *)KSEG1ADDR(LS1X_GPIO_MUX_BASE + (x)))
 
 #define LS1X_MUX_CTRL0			LS1X_MUX_REG(0x0)
 #define LS1X_MUX_CTRL1			LS1X_MUX_REG(0x4)
diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/common/irq.c
index 455a770..f2520f2 100644
--- a/arch/mips/loongson32/common/irq.c
+++ b/arch/mips/loongson32/common/irq.c
@@ -15,7 +15,7 @@
 #include <irq.h>
 
 #define LS1X_INTC_REG(n, x) \
-		((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
+		((void __iomem *)KSEG1ADDR(LS1X_INT_REG_BASE + (n * 0x18) + (x)))
 
 #define LS1X_INTC_INTISR(n)		LS1X_INTC_REG(n, 0x0)
 #define LS1X_INTC_INTIEN(n)		LS1X_INTC_REG(n, 0x4)
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index f2c714d..24f35b6 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -7,7 +7,10 @@
  * option) any later version.
  */
 
+#include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/err.h>
 #include <linux/mtd/partitions.h>
@@ -15,7 +18,15 @@
 #include <linux/phy.h>
 #include <linux/serial_8250.h>
 #include <linux/stmmac.h>
+#include <linux/resource.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/platform_device.h>
 
 #include <loongson1.h>
 #include <cpufreq.h>
@@ -26,6 +37,7 @@
 #define LS1X_UART(_id)						\
 	{							\
 		.mapbase	= LS1X_UART ## _id ## _BASE,	\
+		.membase	= (u8 *)KSEG1ADDR(LS1X_UART ## _id ## _BASE), \
 		.irq		= LS1X_UART ## _id ## _IRQ,	\
 		.iotype		= UPIO_MEM,			\
 		.flags		= UPF_IOREMAP | UPF_FIXED_TYPE, \
@@ -83,8 +95,8 @@ struct platform_device ls1x_cpufreq_pdev = {
 /* DMA */
 static struct resource ls1x_dma_resources[] = {
 	[0] = {
-		.start = LS1X_DMAC_BASE,
-		.end = LS1X_DMAC_BASE + SZ_4 - 1,
+		.start = LS1X_DMA_ORDER_REG,
+		.end = LS1X_DMA_ORDER_REG + SZ_4 - 1,
 		.flags = IORESOURCE_MEM,
 	},
 	[1] = {
@@ -240,8 +252,8 @@ struct platform_device ls1x_eth1_pdev = {
 /* GPIO */
 static struct resource ls1x_gpio0_resources[] = {
 	[0] = {
-		.start	= LS1X_GPIO0_BASE,
-		.end	= LS1X_GPIO0_BASE + SZ_4 - 1,
+		.start	= LS1X_GPIO_CFG0_REG,
+		.end	= LS1X_GPIO_CFG0_REG + SZ_4 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
@@ -255,8 +267,8 @@ struct platform_device ls1x_gpio0_pdev = {
 
 static struct resource ls1x_gpio1_resources[] = {
 	[0] = {
-		.start	= LS1X_GPIO1_BASE,
-		.end	= LS1X_GPIO1_BASE + SZ_4 - 1,
+		.start	= LS1X_GPIO_CFG1_REG,
+		.end	= LS1X_GPIO_CFG1_REG + SZ_4 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
@@ -268,11 +280,12 @@ struct platform_device ls1x_gpio1_pdev = {
 	.resource	= ls1x_gpio1_resources,
 };
 
+
 /* NAND Flash */
 static struct resource ls1x_nand_resources[] = {
 	[0] = {
-		.start	= LS1X_NAND_BASE,
-		.end	= LS1X_NAND_BASE + SZ_32 - 1,
+		.start	= LS1X_NAND_REG_BASE,
+		.end	= LS1X_NAND_REG_BASE + SZ_32 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
@@ -295,9 +308,9 @@ void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata)
 	ls1x_nand_pdev.dev.platform_data = pdata;
 }
 
-/* USB EHCI */
-static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
+static u64 platform_dma_mask = DMA_BIT_MASK(32);
 
+/* USB EHCI */
 static struct resource ls1x_ehci_resources[] = {
 	[0] = {
 		.start	= LS1X_EHCI_BASE,
@@ -319,13 +332,221 @@ struct platform_device ls1x_ehci_pdev = {
 	.num_resources	= ARRAY_SIZE(ls1x_ehci_resources),
 	.resource	= ls1x_ehci_resources,
 	.dev		= {
-		.dma_mask = &ls1x_ehci_dmamask,
+		.dma_mask = &platform_dma_mask,
 		.platform_data = &ls1x_ehci_pdata,
 	},
 };
 
+/* USB OHCI */
+static struct resource ls1x_ohci_resources[] = {
+	[0] = {
+		.start	= LS1X_OHCI_BASE,
+		.end	= LS1X_OHCI_BASE + SZ_32K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= LS1X_OHCI_IRQ,
+		.end	= LS1X_OHCI_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct usb_ohci_pdata ls1x_ohci_data = {
+};
+
+struct platform_device ls1x_ohci_pdev = {
+	.name		= "ohci-platform",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ls1x_ohci_resources),
+	.resource	= ls1x_ohci_resources,
+	.dev = {
+		.dma_mask	= &platform_dma_mask,
+		.platform_data	= &ls1x_ohci_data,
+	},
+};
+
+/* AHCI */
+static struct resource ls1x_ahci_resources[] = {
+	[0] = {
+		.start	= LS1X_AHCI_BASE,
+		.end	= LS1X_AHCI_BASE + SZ_64K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= LS1X_AHCI_IRQ,
+		.end	= LS1X_AHCI_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ls1x_ahci_pdev = {
+	.name		= "ahci",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ls1x_ahci_resources),
+	.resource	= ls1x_ahci_resources,
+	.dev		= {
+		.dma_mask = &platform_dma_mask,
+	},
+};
+
+/* Real Time Clock */
+static struct resource ls1x_rtc_resource[] = {
+	[0] = {
+		.start	= LS1X_RTC_BASE,
+		.end	= LS1X_RTC_BASE + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= LS1X_TOY_INT2_IRQ,
+		.end	= LS1X_TOY_INT2_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
 /* Real Time Clock */
 struct platform_device ls1x_rtc_pdev = {
 	.name		= "ls1x-rtc",
 	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ls1x_rtc_resource),
+	.resource	= ls1x_rtc_resource,
+};
+
+/* FrameBuffer */
+static struct resource ls1x_fb_resources[] = {
+	[0] = {
+		.start	= LS1X_DC_REG_BASE,
+		.end	= LS1X_DC_REG_BASE + SZ_1M - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device ls1x_fb_pdev = {
+	.name           = "ls1x-fb",
+	.id             = -1,
+	.num_resources	= ARRAY_SIZE(ls1x_fb_resources),
+	.resource	= ls1x_fb_resources,
+};
+
+/* I2C */
+static struct resource ls1x_i2c0_resource[] = {
+	[0] = {
+		.start	= LS1X_I2C0_BASE,
+		.end	= LS1X_I2C0_BASE + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device ls1x_i2c0_pdev = {
+	.name		= "ls1x-i2c",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(ls1x_i2c0_resource),
+	.resource	= ls1x_i2c0_resource,
+};
+
+static struct resource ls1x_i2c1_resource[] = {
+	[0] = {
+		.start	= LS1X_I2C1_BASE,
+		.end	= LS1X_I2C1_BASE + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device ls1x_i2c1_pdev = {
+	.name		= "ls1x-i2c",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(ls1x_i2c1_resource),
+	.resource	= ls1x_i2c1_resource,
+};
+
+static struct resource ls1x_i2c2_resource[] = {
+	[0] = {
+		.start	= LS1X_I2C2_BASE,
+		.end	= LS1X_I2C2_BASE + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device ls1x_i2c2_pdev = {
+	.name		= "ls1x-i2c",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(ls1x_i2c2_resource),
+	.resource	= ls1x_i2c2_resource,
+};
+
+/* Watchdog */
+static struct resource ls1x_wat_resource[] = {
+	[0] = {
+		.start	= LS1X_WDT_BASE,
+		.end	= LS1X_WDT_BASE + SZ_8,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device ls1x_wat_pdev = {
+	.name		= "ls1x-wdt",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ls1x_wat_resource),
+	.resource	= ls1x_wat_resource,
+};
+
+/* AC97 Audio */
+static struct resource ls1x_audio_resources[] = {
+	[0] = {
+		.start = LS1X_AC97_BASE,
+		.end   = LS1X_AC97_BASE + SZ_16K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = LS1X_AC97_IRQ,
+		.end   = LS1X_AC97_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ls1x_audio_pdev = {
+	.name		= "ls1x-audio",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ls1x_audio_resources),
+	.resource	= ls1x_audio_resources,
+};
+
+/* SPI */
+static struct resource ls1x_spi0_resources[] = {
+	[1] = {
+		.start	= LS1X_SPI0_REG_BASE,
+		.end	= LS1X_SPI0_REG_BASE,
+		.flags	= IORESOURCE_MEM,
+	},
+	[2] = {
+		.start	= LS1X_SPI0_IRQ,
+		.end	= LS1X_SPI0_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ls1x_spi0_pdev = {
+	.name		= "ls1x-spi",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(ls1x_spi0_resources),
+	.resource	= ls1x_spi0_resources,
+};
+
+static struct resource ls1x_spi1_resources[] = {
+	[1] = {
+		.start	= LS1X_SPI1_REG_BASE,
+		.end	= LS1X_SPI1_REG_BASE,
+		.flags	= IORESOURCE_MEM,
+	},
+	[2] = {
+		.start	= LS1X_SPI1_IRQ,
+		.end	= LS1X_SPI1_IRQ,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ls1x_spi1_pdev = {
+	.name		= "ls1x-spi",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(ls1x_spi1_resources),
+	.resource	= ls1x_spi1_resources,
 };
-- 
1.9.1

[PATCH RESEND v4 4/9] MIPS: Loongson: Add loongson-1A board support

[Binbin Zhou]

Loongson 1A's platform devices register.

Specially, Loongson 1A use ACPI to control restart/poweroff/halt.

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/mach-loongson32/loongson1.h |  11 +++
 arch/mips/loongson32/Makefile                     |   6 ++
 arch/mips/loongson32/common/prom.c                |   6 ++
 arch/mips/loongson32/common/reset.c               |   6 ++
 arch/mips/loongson32/common/setup.c               |  42 +++++++++
 arch/mips/loongson32/ls1a/Makefile                |   5 ++
 arch/mips/loongson32/ls1a/board.c                 | 105 ++++++++++++++++++++++
 7 files changed, 181 insertions(+)
 create mode 100644 arch/mips/loongson32/ls1a/Makefile
 create mode 100644 arch/mips/loongson32/ls1a/board.c

diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 8ba34f9..67ca11c 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -158,6 +158,17 @@
 #define LS1X_LPC_CFG2_REG		(LS1X_LPC_REG_BASE + 0x8)
 #define LS1X_LPC_CFG3_REG		(LS1X_LPC_REG_BASE + 0xc)
 
+#define LS1X_PCIIO_BASE			0x1c000000
+#define LS1X_PCIIO_SIZE			0x00100000	/* 1M */
+
+/* reg access */
+#define ls1x_readb(addr)		(*(volatile u8 *)CKSEG1ADDR(addr))
+#define ls1x_readw(addr)		(*(volatile u16 *)CKSEG1ADDR(addr))
+#define ls1x_readl(addr)		(*(volatile u32 *)CKSEG1ADDR(addr))
+#define ls1x_writeb(val, addr)		(*(volatile u8 *)CKSEG1ADDR(addr) = (val))
+#define ls1x_writew(val, addr)		(*(volatile u16 *)CKSEG1ADDR(addr) = (val))
+#define ls1x_writel(val, addr)		(*(volatile u32 *)CKSEG1ADDR(addr) = (val))
+
 #include <regs-clk.h>
 #include <regs-mux.h>
 #include <regs-pwm.h>
diff --git a/arch/mips/loongson32/Makefile b/arch/mips/loongson32/Makefile
index 5f4bd6e..c2a6559 100644
--- a/arch/mips/loongson32/Makefile
+++ b/arch/mips/loongson32/Makefile
@@ -5,6 +5,12 @@
 obj-$(CONFIG_MACH_LOONGSON32) += common/
 
 #
+# Loongson LS1A board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1A)  += ls1a/
+
+#
 # Loongson LS1B board
 #
 
diff --git a/arch/mips/loongson32/common/prom.c b/arch/mips/loongson32/common/prom.c
index 6860098..e07e473 100644
--- a/arch/mips/loongson32/common/prom.c
+++ b/arch/mips/loongson32/common/prom.c
@@ -64,6 +64,12 @@ void __init prom_init(void)
 
 	prom_init_cmdline();
 
+#ifdef CONFIG_CPU_LOONGSON1A
+	/* init base address of io space */
+	set_io_port_base((unsigned long)
+		ioremap(LS1X_PCIIO_BASE, LS1X_PCIIO_SIZE));
+#endif
+
 	memsize = env_or_default("memsize", DEFAULT_MEMSIZE);
 	highmemsize = env_or_default("highmemsize", 0x0);
 
diff --git a/arch/mips/loongson32/common/reset.c b/arch/mips/loongson32/common/reset.c
index 8a1d9cc..0b653eb 100644
--- a/arch/mips/loongson32/common/reset.c
+++ b/arch/mips/loongson32/common/reset.c
@@ -19,10 +19,16 @@ static void __iomem *wdt_reg_base;
 
 static void ls1x_halt(void)
 {
+#ifdef CONFIG_CPU_LOONGSON1A
+	u32 tmp;
+	tmp = ls1x_readl(LS1X_PM1_CNT_REG);
+	ls1x_writel(tmp | 0x3d00, LS1X_PM1_CNT_REG);
+#else
 	while (1) {
 		if (cpu_wait)
 			cpu_wait();
 	}
+#endif
 }
 
 static void ls1x_restart(char *command)
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index c3d2036..95b0155 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -7,13 +7,55 @@
  * option) any later version.
  */
 
+#include <linux/ioport.h>
+#include <linux/screen_info.h>
 #include <asm/bootinfo.h>
 
 #include <prom.h>
 
+#define IO_MEM_RESOURCE_START   0UL
+#define IO_MEM_RESOURCE_END     0xffffffffUL
+
+#ifdef CONFIG_CPU_LOONGSON1A
+void (*__wbflush)(void);
+static void wbflush_ls1x(void)
+{
+	asm(".set\tpush\n\t"
+	    ".set\tnoreorder\n\t"
+	    ".set mips3\n\t"
+	    "sync\n\t"
+	    "nop\n\t"
+	    ".set\tpop\n\t"
+	    ".set mips0\n\t");
+}
+
+static void __init iomem_resource_init(void)
+{
+	iomem_resource.start	= IO_MEM_RESOURCE_START;
+	iomem_resource.end	= IO_MEM_RESOURCE_END;
+}
+#endif
+
 void __init plat_mem_setup(void)
 {
 	add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+
+#ifdef CONFIG_CPU_LOONGSON1A
+	iomem_resource_init();
+	__wbflush = wbflush_ls1x;
+
+#if defined(CONFIG_VGA_CONSOLE)
+	screen_info = (struct screen_info) {
+		.orig_x			= 0,
+		.orig_y			= 25,
+		.orig_video_cols	= 80,
+		.orig_video_lines	= 25,
+		.orig_video_isVGA	= VIDEO_TYPE_VGAC,
+		.orig_video_points	= 16,
+	};
+#endif
+	add_memory_region(0x20000000, 0x30000000, BOOT_MEM_RESERVED);
+#endif
 }
 
 const char *get_system_type(void)
diff --git a/arch/mips/loongson32/ls1a/Makefile b/arch/mips/loongson32/ls1a/Makefile
new file mode 100644
index 0000000..7f2baf3
--- /dev/null
+++ b/arch/mips/loongson32/ls1a/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for Loongson 1A based machines.
+#
+
+obj-y += board.o
diff --git a/arch/mips/loongson32/ls1a/board.c b/arch/mips/loongson32/ls1a/board.c
new file mode 100644
index 0000000..56c0dbb
--- /dev/null
+++ b/arch/mips/loongson32/ls1a/board.c
@@ -0,0 +1,105 @@
+/*
+ * Platform device support for GS232 SoCs.
+ *
+ * Copyright 2009, Su Wen <suwen@ict.ac.cn>
+ *
+ * base on Au1xxx Socs drivers by Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <irq.h>
+#include <platform.h>
+#include <loongson1.h>
+
+static struct platform_device *ls1a_platform_devices[] __initdata = {
+	&ls1x_nand_pdev,
+	&ls1x_uart_pdev,
+	&ls1x_ahci_pdev,
+	&ls1x_ohci_pdev,
+	&ls1x_ehci_pdev,
+	&ls1x_eth0_pdev,
+	&ls1x_eth1_pdev,
+	&ls1x_wat_pdev,
+	&ls1x_rtc_pdev,
+	&ls1x_audio_pdev,
+	&ls1x_fb_pdev,
+	&ls1x_i2c0_pdev,
+	&ls1x_i2c1_pdev,
+	&ls1x_i2c2_pdev,
+	&ls1x_spi0_pdev,
+	&ls1x_spi1_pdev,
+};
+
+struct i2c_board_info ls1a_pcf8563 __initdata = {
+	I2C_BOARD_INFO("pcf8563", 0x51),
+};
+
+struct flash_platform_data ls1a_spiflash_data = {
+	.name		= "m25p80",
+	.parts		= NULL,
+	.nr_parts	= 0,
+	.type		= "m25p80",
+};
+
+struct spi_board_info ls1a_spi_info[] __initdata = {
+	{
+		.modalias	= "m25p80",
+		.max_speed_hz	= 1000000,
+		.bus_num	= 0,
+		.chip_select	= 1,
+		.platform_data	= &ls1a_spiflash_data,
+	},
+};
+
+void ls1a_route_setting(void)
+{
+	/*set gpio 48-61 as normal pin*/
+	ls1x_writel(ls1x_readl(LS1X_GPIO_CFG1_REG) & 0xc000ffff,
+					LS1X_GPIO_CFG1_REG);
+
+	/*set gpio mux : gmac1 to use uart0, uart1 pins*/
+	ls1x_writel((ls1x_readl(LS1X_MUX_REG_BASE) & 0x00fff5ff) | 0x0a0000c0,
+					LS1X_GPIO_CFG1_REG);
+
+	/*multiplex int0 as gpio0 */
+	ls1x_writel(ls1x_readl(LS1X_GPIO_CFG0_REG) | 0x00000001,
+					LS1X_GPIO_CFG0_REG);
+	ls1x_writel(ls1x_readl(LS1X_GPIO_OE0_REG) | 0x00000001,
+					LS1X_GPIO_OE0_REG);
+	ls1x_writel(ls1x_readl(LS1X_GPIO_IN0_REG) & 0xfffffffe,
+					LS1X_GPIO_IN0_REG);
+
+	/*i2c gpio configuartion gpio64 scl and gpio65 sda*/
+	ls1x_writel(ls1x_readl(LS1X_GPIO_CFG2_REG) & 0xfffffffd,
+					LS1X_GPIO_CFG2_REG);
+
+	mdelay(1);
+
+	/*ls1a usb reset stop*/
+	ls1x_writel(0x40000000, LS1X_LPC_CFG1_REG);
+
+	/* Reset GMAC0/1 to avoid DMA error */
+	ls1x_writel(ls1x_readl(LS1X_GMAC0_DMA_REG) | 1, LS1X_GMAC0_DMA_REG);
+	ls1x_writel(ls1x_readl(LS1X_GMAC1_DMA_REG) | 1, LS1X_GMAC1_DMA_REG);
+}
+
+int __init ls1a_platform_init(void)
+{
+	ls1a_route_setting();
+
+	i2c_register_board_info(1, &ls1a_pcf8563, 1);
+	spi_register_board_info(ls1a_spi_info, ARRAY_SIZE(ls1a_spi_info));
+
+	return platform_add_devices(ls1a_platform_devices,
+					ARRAY_SIZE(ls1a_platform_devices));
+}
+
+arch_initcall(ls1a_platform_init);
-- 
1.9.1

[PATCH RESEND v4 7/9] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM

[Binbin Zhou]

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/include/asm/sparsemem.h   | 6 +++++-
 arch/mips/loongson32/Kconfig        | 1 +
 arch/mips/loongson32/common/setup.c | 3 ++-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index b1071c1..f73e671 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,11 @@
 #else
 # define SECTION_SIZE_BITS	28
 #endif
-#define MAX_PHYSMEM_BITS	48
+#ifdef CONFIG_64BIT
+# define MAX_PHYSMEM_BITS	48
+#else
+# define MAX_PHYSMEM_BITS	36
+#endif
 
 #endif /* CONFIG_SPARSEMEM */
 #endif /* _MIPS_SPARSEMEM_H */
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 35effa8..0b5a125 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -7,6 +7,7 @@ config LOONGSON1_LS1A
 	bool "Loongson LS1A board"
 	select CEVT_R4K
 	select CSRC_R4K
+	select ARCH_SPARSEMEM_ENABLE
 	select SYS_HAS_CPU_LOONGSON1A
 	select DMA_NONCOHERENT
 	select BOOT_ELF32
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 95b0155..af9ccee 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -54,7 +54,8 @@ void __init plat_mem_setup(void)
 		.orig_video_points	= 16,
 	};
 #endif
-	add_memory_region(0x20000000, 0x30000000, BOOT_MEM_RESERVED);
+	if (highmemsize > 0)
+		add_memory_region(0x50000000, highmemsize << 20, BOOT_MEM_RAM);
 #endif
 }
 
-- 
1.9.1

Re: [PATCH RESEND v4 7/9] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM

[Ralf Baechle]

On Thu, May 19, 2016 at 09:38:30AM +0800, Binbin Zhou wrote:

> diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
> index b1071c1..f73e671 100644
> --- a/arch/mips/include/asm/sparsemem.h
> +++ b/arch/mips/include/asm/sparsemem.h
> @@ -11,7 +11,11 @@
>  #else
>  # define SECTION_SIZE_BITS	28
>  #endif
> -#define MAX_PHYSMEM_BITS	48
> +#ifdef CONFIG_64BIT
> +# define MAX_PHYSMEM_BITS	48
> +#else
> +# define MAX_PHYSMEM_BITS	36
> +#endif

This doesn't look right for XPA.  What do you think, James?

I think we don't use sparsemem on XPA atm so I can apply this safely -
but it should be fixed properly.

  Ralf

Re: [PATCH RESEND v4 7/9] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 1394 bytes --]

On Tue, Aug 02, 2016 at 10:29:23AM +0200, Ralf Baechle wrote:
> On Thu, May 19, 2016 at 09:38:30AM +0800, Binbin Zhou wrote:
> 
> > diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
> > index b1071c1..f73e671 100644
> > --- a/arch/mips/include/asm/sparsemem.h
> > +++ b/arch/mips/include/asm/sparsemem.h
> > @@ -11,7 +11,11 @@
> >  #else
> >  # define SECTION_SIZE_BITS	28
> >  #endif
> > -#define MAX_PHYSMEM_BITS	48
> > +#ifdef CONFIG_64BIT
> > +# define MAX_PHYSMEM_BITS	48
> > +#else
> > +# define MAX_PHYSMEM_BITS	36
> > +#endif
> 
> This doesn't look right for XPA.  What do you think, James?

XPA appears to naturally support up to 59 physical address bits, but
with a "practical limit" of 40 bits. I haven't quite figured out what
the practical limit means to be honest (maybe MIPS32 XPA implementations
are simply expected not to exceed 40 bits in practice).

So yeh, it should probably be at least 40 when CONFIG_XPA is enabled,
although I'm unclear about the consequences. E.g. a bigger
MAX_PHYSMEM_BITS increases the number of segment id bits
(MAX_PHYSMEM_BITS - SECTION_SIZE_BITS).

> 
> I think we don't use sparsemem on XPA atm so I can apply this safely -
> but it should be fixed properly.

Right, sparsemem seems to be enabled depending on the platform, so it
may only be a matter of time.

Cheers
James

[-- Attachment #2: Digital signature --]
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Re: [PATCH RESEND v4 7/9] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 1394 bytes --]

On Tue, Aug 02, 2016 at 10:29:23AM +0200, Ralf Baechle wrote:
> On Thu, May 19, 2016 at 09:38:30AM +0800, Binbin Zhou wrote:
> 
> > diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
> > index b1071c1..f73e671 100644
> > --- a/arch/mips/include/asm/sparsemem.h
> > +++ b/arch/mips/include/asm/sparsemem.h
> > @@ -11,7 +11,11 @@
> >  #else
> >  # define SECTION_SIZE_BITS	28
> >  #endif
> > -#define MAX_PHYSMEM_BITS	48
> > +#ifdef CONFIG_64BIT
> > +# define MAX_PHYSMEM_BITS	48
> > +#else
> > +# define MAX_PHYSMEM_BITS	36
> > +#endif
> 
> This doesn't look right for XPA.  What do you think, James?

XPA appears to naturally support up to 59 physical address bits, but
with a "practical limit" of 40 bits. I haven't quite figured out what
the practical limit means to be honest (maybe MIPS32 XPA implementations
are simply expected not to exceed 40 bits in practice).

So yeh, it should probably be at least 40 when CONFIG_XPA is enabled,
although I'm unclear about the consequences. E.g. a bigger
MAX_PHYSMEM_BITS increases the number of segment id bits
(MAX_PHYSMEM_BITS - SECTION_SIZE_BITS).

> 
> I think we don't use sparsemem on XPA atm so I can apply this safely -
> but it should be fixed properly.

Right, sparsemem seems to be enabled depending on the platform, so it
may only be a matter of time.

Cheers
James

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[PATCH RESEND v4 8/9] MIPS: Loongson-1B: Update config file

[Binbin Zhou]

CONFIG_LOONGSON1_LS1B=y is needed to be set, while Loongson-1A is added.

Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/configs/loongson1b_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/configs/loongson1b_defconfig b/arch/mips/configs/loongson1b_defconfig
index c442f27..7b8ac02 100644
--- a/arch/mips/configs/loongson1b_defconfig
+++ b/arch/mips/configs/loongson1b_defconfig
@@ -1,4 +1,5 @@
 CONFIG_MACH_LOONGSON32=y
+CONFIG_LOONGSON1_LS1B=y
 CONFIG_PREEMPT=y
 # CONFIG_SECCOMP is not set
 # CONFIG_LOCALVERSION_AUTO is not set
-- 
1.9.1




[i

[PATCH RESEND v4 9/9] MIPS: Loongson: Add a Loongson-1A default config file

[Binbin Zhou]

Signed-off-by: Chunbo Cui <cuichboo@163.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/configs/loongson1a_defconfig | 131 +++++++++++++++++++++++++++++++++
 1 file changed, 131 insertions(+)
 create mode 100644 arch/mips/configs/loongson1a_defconfig

diff --git a/arch/mips/configs/loongson1a_defconfig b/arch/mips/configs/loongson1a_defconfig
new file mode 100644
index 0000000..6a0450e
--- /dev/null
+++ b/arch/mips/configs/loongson1a_defconfig
@@ -0,0 +1,131 @@
+CONFIG_MACH_LOONGSON32=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_HIGHMEM=y
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_SECCOMP is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_EXPERT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=m
+CONFIG_USB_GADGET=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_XZ_DEC=y
-- 
1.9.1