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From: Yakir Yang <ykk@rock-chips.com>
To: Mark Yao <yzq@rock-chips.com>, Inki Dae <inki.dae@samsung.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Heiko Stuebner <heiko@sntech.de>
Cc: "Javier Martinez Canillas" <javier@osg.samsung.com>,
	"Stéphane Marchesin" <marcheu@chromium.org>,
	"Sean Paul" <seanpaul@chromium.org>,
	"Tomasz Figa" <tfiga@chromium.org>,
	"David Airlie" <airlied@linux.ie>,
	daniel.vetter@ffwll.ch, "Thierry Reding" <treding@nvidia.com>,
	dianders@chromium.org,
	"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
	emil.l.velikov@gmail.com,
	"Dan Carpenter" <dan.carpenter@oracle.com>,
	"Yakir Yang" <ykk@rock-chips.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-samsung-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org
Subject: [PATCH v4 02/11] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
Date: Wed, 29 Jun 2016 17:15:05 +0800	[thread overview]
Message-ID: <1467191705-17177-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1467191657-16941-1-git-send-email-ykk@rock-chips.com>

There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v4:
- Add reviewed flag from Sean

Changes in v3:
- Add reviewed flag from Tomasz.
    [https://chromium-review.googlesource.com/#/c/346315/15]
- Add tested flag from Javier

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 337912b..88d56ad 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -163,8 +163,8 @@
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
 /* ANALOGIX_DP_PLL_REG_1 */
-#define REF_CLK_24M				(0x1 << 1)
-#define REF_CLK_27M				(0x0 << 1)
+#define REF_CLK_24M				(0x1 << 0)
+#define REF_CLK_27M				(0x0 << 0)
 
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
-- 
1.9.1

WARNING: multiple messages have this Message-ID (diff)
From: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
To: Mark Yao <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
	Jingoo Han <jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: "Krzysztof Kozlowski"
	<k.kozlowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>,
	linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	"David Airlie" <airlied-cv59FeDIM0c@public.gmane.org>,
	daniel.vetter-/w4YWyX8dFk@public.gmane.org,
	emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
	dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	"Tomasz Figa" <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	"Javier Martinez Canillas"
	<javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>,
	"Sean Paul" <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	"Yakir Yang" <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>,
	"Stéphane Marchesin"
	<marcheu-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	"Thierry Reding"
	<treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
	"Dan Carpenter"
	<dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
Subject: [PATCH v4 02/11] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1
Date: Wed, 29 Jun 2016 17:15:05 +0800	[thread overview]
Message-ID: <1467191705-17177-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1467191657-16941-1-git-send-email-ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special
registers setting").

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Signed-off-by: Yakir Yang <ykk-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Reviewed-by: Tomasz Figa <tomasz.figa-F7+t8E8rja9Wk0Htik3J/w@public.gmane.org>
Tested-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
---
Changes in v4:
- Add reviewed flag from Sean

Changes in v3:
- Add reviewed flag from Tomasz.
    [https://chromium-review.googlesource.com/#/c/346315/15]
- Add tested flag from Javier

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 337912b..88d56ad 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -163,8 +163,8 @@
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
 /* ANALOGIX_DP_PLL_REG_1 */
-#define REF_CLK_24M				(0x1 << 1)
-#define REF_CLK_27M				(0x0 << 1)
+#define REF_CLK_24M				(0x1 << 0)
+#define REF_CLK_27M				(0x0 << 0)
 
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
-- 
1.9.1

  parent reply	other threads:[~2016-06-29  9:15 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-29  9:14 [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver Yakir Yang
2016-06-29  9:14 ` Yakir Yang
2016-06-29  9:15 ` [PATCH v4 01/11] drm/rockchip: analogix_dp: split the lcdc select setting into device data Yakir Yang
2016-06-29  9:15   ` Yakir Yang
2016-06-29 13:44   ` Sean Paul
2016-06-29  9:15 ` Yakir Yang [this message]
2016-06-29  9:15   ` [PATCH v4 02/11] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 Yakir Yang
2016-06-29  9:15 ` [PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Yakir Yang
2016-06-29  9:15   ` Yakir Yang
2016-06-29 13:46   ` Sean Paul
2016-06-29 13:46     ` Sean Paul
2016-06-29  9:15 ` [PATCH v4 04/11] drm/rockchip: analogix_dp: add rk3399 eDP support Yakir Yang
2016-06-29  9:15   ` Yakir Yang
2016-06-29 13:52   ` Sean Paul
2016-06-29 13:52     ` Sean Paul
2016-06-29  9:15 ` [PATCH v4 05/11] drm/rockchip: analogix_dp: make panel detect to an optional action Yakir Yang
2016-06-29 13:55   ` Sean Paul
2016-06-29 13:55     ` Sean Paul
2016-06-29  9:15 ` [PATCH v4 06/11] drm/bridge: analogix_dp: passing the connector as an argument in .get_modes() Yakir Yang
2016-06-29  9:15   ` Yakir Yang
2016-06-29  9:15 ` [PATCH v4 07/11] drm/rockchip: analogix_dp: correct the connector display color format and bpc Yakir Yang
2016-06-29  9:15   ` Yakir Yang
2016-06-29 13:57   ` Sean Paul
2016-06-29 13:57     ` Sean Paul
2016-06-29  9:15 ` [PATCH v4 08/11] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode Yakir Yang
2016-06-29  9:15   ` Yakir Yang
2016-06-29 13:58   ` Sean Paul
2016-06-29  9:15 ` [PATCH v4 09/11] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in Yakir Yang
2016-06-29  9:16 ` [PATCH v4 10/11] drm/rockchip: analogix_dp: introduce the pclk for grf Yakir Yang
2016-06-29  9:16   ` Yakir Yang
2016-06-29  9:16 ` [PATCH v4 11/11] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name Yakir Yang
2016-06-29  9:16   ` Yakir Yang
2016-06-29 14:01 ` [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver Sean Paul
2016-06-29 14:01   ` Sean Paul
2016-06-30  6:31   ` [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver[Involving remittance information, please pay attention to the safety of property] Yakir Yang

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