From: Sean Paul <seanpaul@chromium.org> To: Yakir Yang <ykk@rock-chips.com> Cc: "Mark Yao" <yzq@rock-chips.com>, "Inki Dae" <inki.dae@samsung.com>, "Jingoo Han" <jingoohan1@gmail.com>, "Heiko Stuebner" <heiko@sntech.de>, "Javier Martinez Canillas" <javier@osg.samsung.com>, "Stéphane Marchesin" <marcheu@chromium.org>, "Tomasz Figa" <tfiga@chromium.org>, "David Airlie" <airlied@linux.ie>, "Daniel Vetter" <daniel.vetter@ffwll.ch>, "Thierry Reding" <treding@nvidia.com>, "Douglas Anderson" <dianders@chromium.org>, "Krzysztof Kozlowski" <k.kozlowski@samsung.com>, "Emil Velikov" <emil.l.velikov@gmail.com>, "Dan Carpenter" <dan.carpenter@oracle.com>, "Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>, dri-devel <dri-devel@lists.freedesktop.org>, linux-samsung-soc <linux-samsung-soc@vger.kernel.org>, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Date: Wed, 29 Jun 2016 09:46:52 -0400 [thread overview] Message-ID: <CAOw6vb++FWiy=27o10o914uR9Grh87Sc1VKar3f5LiZrB-qe9Q@mail.gmail.com> (raw) In-Reply-To: <1467191718-17221-1-git-send-email-ykk@rock-chips.com> On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang <ykk@rock-chips.com> wrote: > As vendor document indicate, when REF_CLK bit set 0, then DP > phy's REF_CLK should switch to 24M source clock. > > But due to IC PHY layout mistaken, some chips need to flip this > bit(like RK3288), and unfortunately they didn't indicate in the > DP version register. That's why we have to make this little hack. > > Signed-off-by: Yakir Yang <ykk@rock-chips.com> > Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> > Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> > --- > Changes in v4: > - Remove subdev_type number, and add 'is_rockchip(type)' helper function (Sean) > - Add reviewed flag from Tomasz. > > Changes in v3: > - Make this hack code more clear (Tomasz, reviewed at Google Gerrit) > reg = ~reg & REF_CLK_MASK; ---> reg ^= REF_CLK_MASK; > [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c@80] > - Add tested flag from Javier > > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 12 ++++++++---- > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 + > include/drm/bridge/analogix_dp.h | 5 +++++ > 3 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index 49205ef..48030f0 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) > reg = SEL_24M | TX_DVDD_BIT_1_0625V; > writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); > > - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) { > - writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { > + reg = REF_CLK_24M; > + if (dp->plat_data->dev_type == RK3288_DP) > + reg ^= REF_CLK_MASK; > + > + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); > writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); > writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); > writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); > @@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, > u32 reg; > u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; > > - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > phy_pd_addr = ANALOGIX_DP_PD; > > switch (block) { > @@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) > analogix_dp_reset_aux(dp); > > /* Disable AUX transaction H/W retry */ > - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | > AUX_HW_RETRY_COUNT_SEL(3) | > AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index 88d56ad..cdcc6c5 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -165,6 +165,7 @@ > /* ANALOGIX_DP_PLL_REG_1 */ > #define REF_CLK_24M (0x1 << 0) > #define REF_CLK_27M (0x0 << 0) > +#define REF_CLK_MASK (0x1 << 0) > > /* ANALOGIX_DP_LANE_MAP */ > #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) > diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h > index 25afb31..790ab5d 100644 > --- a/include/drm/bridge/analogix_dp.h > +++ b/include/drm/bridge/analogix_dp.h > @@ -18,6 +18,11 @@ enum analogix_dp_devtype { > RK3288_DP, > }; > > +static inline bool is_rockchip(enum analogix_dp_devtype type) > +{ > + return type == RK3288_DP; > +} > + > struct analogix_dp_plat_data { > enum analogix_dp_devtype dev_type; > struct drm_panel *panel; > -- > 1.9.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Sean Paul <seanpaul@chromium.org> To: Yakir Yang <ykk@rock-chips.com> Cc: "Krzysztof Kozlowski" <k.kozlowski@samsung.com>, linux-samsung-soc <linux-samsung-soc@vger.kernel.org>, "Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>, linux-rockchip@lists.infradead.org, "Mark Yao" <yzq@rock-chips.com>, "Jingoo Han" <jingoohan1@gmail.com>, "Emil Velikov" <emil.l.velikov@gmail.com>, "Douglas Anderson" <dianders@chromium.org>, dri-devel <dri-devel@lists.freedesktop.org>, "Tomasz Figa" <tfiga@chromium.org>, "Javier Martinez Canillas" <javier@osg.samsung.com>, "Daniel Vetter" <daniel.vetter@ffwll.ch>, "Stéphane Marchesin" <marcheu@chromium.org>, "Thierry Reding" <treding@nvidia.com>, "Dan Carpenter" <dan.carpenter@oracle.com> Subject: Re: [PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Date: Wed, 29 Jun 2016 09:46:52 -0400 [thread overview] Message-ID: <CAOw6vb++FWiy=27o10o914uR9Grh87Sc1VKar3f5LiZrB-qe9Q@mail.gmail.com> (raw) In-Reply-To: <1467191718-17221-1-git-send-email-ykk@rock-chips.com> On Wed, Jun 29, 2016 at 5:15 AM, Yakir Yang <ykk@rock-chips.com> wrote: > As vendor document indicate, when REF_CLK bit set 0, then DP > phy's REF_CLK should switch to 24M source clock. > > But due to IC PHY layout mistaken, some chips need to flip this > bit(like RK3288), and unfortunately they didn't indicate in the > DP version register. That's why we have to make this little hack. > > Signed-off-by: Yakir Yang <ykk@rock-chips.com> > Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> > Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> > --- > Changes in v4: > - Remove subdev_type number, and add 'is_rockchip(type)' helper function (Sean) > - Add reviewed flag from Tomasz. > > Changes in v3: > - Make this hack code more clear (Tomasz, reviewed at Google Gerrit) > reg = ~reg & REF_CLK_MASK; ---> reg ^= REF_CLK_MASK; > [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c@80] > - Add tested flag from Javier > > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 12 ++++++++---- > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 + > include/drm/bridge/analogix_dp.h | 5 +++++ > 3 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index 49205ef..48030f0 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) > reg = SEL_24M | TX_DVDD_BIT_1_0625V; > writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); > > - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) { > - writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { > + reg = REF_CLK_24M; > + if (dp->plat_data->dev_type == RK3288_DP) > + reg ^= REF_CLK_MASK; > + > + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); > writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); > writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); > writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); > @@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, > u32 reg; > u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; > > - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > phy_pd_addr = ANALOGIX_DP_PD; > > switch (block) { > @@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) > analogix_dp_reset_aux(dp); > > /* Disable AUX transaction H/W retry */ > - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | > AUX_HW_RETRY_COUNT_SEL(3) | > AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index 88d56ad..cdcc6c5 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -165,6 +165,7 @@ > /* ANALOGIX_DP_PLL_REG_1 */ > #define REF_CLK_24M (0x1 << 0) > #define REF_CLK_27M (0x0 << 0) > +#define REF_CLK_MASK (0x1 << 0) > > /* ANALOGIX_DP_LANE_MAP */ > #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) > diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h > index 25afb31..790ab5d 100644 > --- a/include/drm/bridge/analogix_dp.h > +++ b/include/drm/bridge/analogix_dp.h > @@ -18,6 +18,11 @@ enum analogix_dp_devtype { > RK3288_DP, > }; > > +static inline bool is_rockchip(enum analogix_dp_devtype type) > +{ > + return type == RK3288_DP; > +} > + > struct analogix_dp_plat_data { > enum analogix_dp_devtype dev_type; > struct drm_panel *panel; > -- > 1.9.1 > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2016-06-29 14:13 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-29 9:14 [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver Yakir Yang 2016-06-29 9:14 ` Yakir Yang 2016-06-29 9:15 ` [PATCH v4 01/11] drm/rockchip: analogix_dp: split the lcdc select setting into device data Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:44 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 02/11] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 9:15 ` [PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:46 ` Sean Paul [this message] 2016-06-29 13:46 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 04/11] drm/rockchip: analogix_dp: add rk3399 eDP support Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:52 ` Sean Paul 2016-06-29 13:52 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 05/11] drm/rockchip: analogix_dp: make panel detect to an optional action Yakir Yang 2016-06-29 13:55 ` Sean Paul 2016-06-29 13:55 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 06/11] drm/bridge: analogix_dp: passing the connector as an argument in .get_modes() Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 9:15 ` [PATCH v4 07/11] drm/rockchip: analogix_dp: correct the connector display color format and bpc Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:57 ` Sean Paul 2016-06-29 13:57 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 08/11] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:58 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 09/11] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in Yakir Yang 2016-06-29 9:16 ` [PATCH v4 10/11] drm/rockchip: analogix_dp: introduce the pclk for grf Yakir Yang 2016-06-29 9:16 ` Yakir Yang 2016-06-29 9:16 ` [PATCH v4 11/11] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name Yakir Yang 2016-06-29 9:16 ` Yakir Yang 2016-06-29 14:01 ` [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver Sean Paul 2016-06-29 14:01 ` Sean Paul 2016-06-30 6:31 ` [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver[Involving remittance information, please pay attention to the safety of property] Yakir Yang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to='CAOw6vb++FWiy=27o10o914uR9Grh87Sc1VKar3f5LiZrB-qe9Q@mail.gmail.com' \ --to=seanpaul@chromium.org \ --cc=airlied@linux.ie \ --cc=dan.carpenter@oracle.com \ --cc=daniel.vetter@ffwll.ch \ --cc=dianders@chromium.org \ --cc=dri-devel@lists.freedesktop.org \ --cc=emil.l.velikov@gmail.com \ --cc=heiko@sntech.de \ --cc=inki.dae@samsung.com \ --cc=javier@osg.samsung.com \ --cc=jingoohan1@gmail.com \ --cc=k.kozlowski@samsung.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-rockchip@lists.infradead.org \ --cc=linux-samsung-soc@vger.kernel.org \ --cc=marcheu@chromium.org \ --cc=tfiga@chromium.org \ --cc=treding@nvidia.com \ --cc=ykk@rock-chips.com \ --cc=yzq@rock-chips.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.