From: Yakir Yang <ykk@rock-chips.com> To: Mark Yao <yzq@rock-chips.com>, Inki Dae <inki.dae@samsung.com>, Jingoo Han <jingoohan1@gmail.com>, Heiko Stuebner <heiko@sntech.de> Cc: "Javier Martinez Canillas" <javier@osg.samsung.com>, "Stéphane Marchesin" <marcheu@chromium.org>, "Sean Paul" <seanpaul@chromium.org>, "Tomasz Figa" <tfiga@chromium.org>, "David Airlie" <airlied@linux.ie>, daniel.vetter@ffwll.ch, "Thierry Reding" <treding@nvidia.com>, dianders@chromium.org, "Krzysztof Kozlowski" <k.kozlowski@samsung.com>, emil.l.velikov@gmail.com, "Dan Carpenter" <dan.carpenter@oracle.com>, "Yakir Yang" <ykk@rock-chips.com>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: [PATCH v4 10/11] drm/rockchip: analogix_dp: introduce the pclk for grf Date: Wed, 29 Jun 2016 17:16:05 +0800 [thread overview] Message-ID: <1467191765-17523-1-git-send-email-ykk@rock-chips.com> (raw) In-Reply-To: <1467191657-16941-1-git-send-email-ykk@rock-chips.com> For RK3399's GRF module, if we want to operate the graphic related grf registers, we need to enable the pclk_vio_grf which supply power for VIO GRF IOs, so it's better to introduce an optional grf clock in driver. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> --- Changes in v4: - Add reviewed flag from Doug. - Add reviewed flag from Tomasz. - Fix compiled error, sorry. "dp->cgfclk" --> 'dp->grfclk' - Check the the error code properly, 'EPROBE_DEFER' should be returned, 'ENOENT' should assign a NULL point to grfclk, other errors should be regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c@249] - Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/] Changes in v3: - Add this patch in v3 .../display/rockchip/analogix_dp-rockchip.txt | 6 ++++++ drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 23 +++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt index 726c945..0b39256 100644 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -28,6 +28,12 @@ Required properties: Port 0: contained 2 endpoints, connecting to the output of vop. Port 1: contained 1 endpoint, connecting to the input of panel. +Optional property for different chips: +- clocks: from common clock binding: handle to grf_vio clock. + +- clock-names: from common clock binding: + Required elements: "grf" + For the below properties, please refer to Analogix DP binding document: * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt - phys (required) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 850edc4..e81e19a 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -64,6 +64,7 @@ struct rockchip_dp_device { struct drm_display_mode mode; struct clk *pclk; + struct clk *grfclk; struct regmap *grf; struct reset_control *rst; @@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); - ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); - if (ret != 0) { - dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + ret = clk_prepare_enable(dp->grfclk); + if (ret < 0) { + dev_err(dp->dev, "failed to enable grfclk %d\n", ret); return; } + + ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); + if (ret != 0) + dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + + clk_disable_unprepare(dp->grfclk); } static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) @@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp) return PTR_ERR(dp->grf); } + dp->grfclk = devm_clk_get(dev, "grf"); + if (PTR_ERR(dp->grfclk) == -ENOENT) { + dp->grfclk = NULL; + } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(dp->grfclk)) { + dev_err(dev, "failed to get grf clock\n"); + return PTR_ERR(dp->grfclk); + } + dp->pclk = devm_clk_get(dev, "pclk"); if (IS_ERR(dp->pclk)) { dev_err(dev, "failed to get pclk property\n"); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Yakir Yang <ykk@rock-chips.com> To: Mark Yao <yzq@rock-chips.com>, Inki Dae <inki.dae@samsung.com>, Jingoo Han <jingoohan1@gmail.com>, Heiko Stuebner <heiko@sntech.de> Cc: "Krzysztof Kozlowski" <k.kozlowski@samsung.com>, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, daniel.vetter@ffwll.ch, emil.l.velikov@gmail.com, dianders@chromium.org, dri-devel@lists.freedesktop.org, "Tomasz Figa" <tfiga@chromium.org>, "Javier Martinez Canillas" <javier@osg.samsung.com>, "Stéphane Marchesin" <marcheu@chromium.org>, "Thierry Reding" <treding@nvidia.com>, "Dan Carpenter" <dan.carpenter@oracle.com> Subject: [PATCH v4 10/11] drm/rockchip: analogix_dp: introduce the pclk for grf Date: Wed, 29 Jun 2016 17:16:05 +0800 [thread overview] Message-ID: <1467191765-17523-1-git-send-email-ykk@rock-chips.com> (raw) In-Reply-To: <1467191657-16941-1-git-send-email-ykk@rock-chips.com> For RK3399's GRF module, if we want to operate the graphic related grf registers, we need to enable the pclk_vio_grf which supply power for VIO GRF IOs, so it's better to introduce an optional grf clock in driver. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com> --- Changes in v4: - Add reviewed flag from Doug. - Add reviewed flag from Tomasz. - Fix compiled error, sorry. "dp->cgfclk" --> 'dp->grfclk' - Check the the error code properly, 'EPROBE_DEFER' should be returned, 'ENOENT' should assign a NULL point to grfclk, other errors should be regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c@249] - Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/] Changes in v3: - Add this patch in v3 .../display/rockchip/analogix_dp-rockchip.txt | 6 ++++++ drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 23 +++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt index 726c945..0b39256 100644 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -28,6 +28,12 @@ Required properties: Port 0: contained 2 endpoints, connecting to the output of vop. Port 1: contained 1 endpoint, connecting to the input of panel. +Optional property for different chips: +- clocks: from common clock binding: handle to grf_vio clock. + +- clock-names: from common clock binding: + Required elements: "grf" + For the below properties, please refer to Analogix DP binding document: * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt - phys (required) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 850edc4..e81e19a 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -64,6 +64,7 @@ struct rockchip_dp_device { struct drm_display_mode mode; struct clk *pclk; + struct clk *grfclk; struct regmap *grf; struct reset_control *rst; @@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder) dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG"); - ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); - if (ret != 0) { - dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + ret = clk_prepare_enable(dp->grfclk); + if (ret < 0) { + dev_err(dp->dev, "failed to enable grfclk %d\n", ret); return; } + + ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); + if (ret != 0) + dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + + clk_disable_unprepare(dp->grfclk); } static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) @@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp) return PTR_ERR(dp->grf); } + dp->grfclk = devm_clk_get(dev, "grf"); + if (PTR_ERR(dp->grfclk) == -ENOENT) { + dp->grfclk = NULL; + } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(dp->grfclk)) { + dev_err(dev, "failed to get grf clock\n"); + return PTR_ERR(dp->grfclk); + } + dp->pclk = devm_clk_get(dev, "pclk"); if (IS_ERR(dp->pclk)) { dev_err(dev, "failed to get pclk property\n"); -- 1.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2016-06-29 9:16 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-29 9:14 [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver Yakir Yang 2016-06-29 9:14 ` Yakir Yang 2016-06-29 9:15 ` [PATCH v4 01/11] drm/rockchip: analogix_dp: split the lcdc select setting into device data Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:44 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 02/11] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 9:15 ` [PATCH v4 03/11] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:46 ` Sean Paul 2016-06-29 13:46 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 04/11] drm/rockchip: analogix_dp: add rk3399 eDP support Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:52 ` Sean Paul 2016-06-29 13:52 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 05/11] drm/rockchip: analogix_dp: make panel detect to an optional action Yakir Yang 2016-06-29 13:55 ` Sean Paul 2016-06-29 13:55 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 06/11] drm/bridge: analogix_dp: passing the connector as an argument in .get_modes() Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 9:15 ` [PATCH v4 07/11] drm/rockchip: analogix_dp: correct the connector display color format and bpc Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:57 ` Sean Paul 2016-06-29 13:57 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 08/11] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode Yakir Yang 2016-06-29 9:15 ` Yakir Yang 2016-06-29 13:58 ` Sean Paul 2016-06-29 9:15 ` [PATCH v4 09/11] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in Yakir Yang 2016-06-29 9:16 ` Yakir Yang [this message] 2016-06-29 9:16 ` [PATCH v4 10/11] drm/rockchip: analogix_dp: introduce the pclk for grf Yakir Yang 2016-06-29 9:16 ` [PATCH v4 11/11] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name Yakir Yang 2016-06-29 9:16 ` Yakir Yang 2016-06-29 14:01 ` [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver Sean Paul 2016-06-29 14:01 ` Sean Paul 2016-06-30 6:31 ` [PATCH v4 0/11] Misc fixup and add RK3399 eDP support to Analogix DP driver[Involving remittance information, please pay attention to the safety of property] Yakir Yang
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