* [U-Boot] [PATCH 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 15:55 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 02/11] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10 Chin Liang See
` (9 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Add base address header file for Stratix10 SoC
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
new file mode 100755
index 0000000..cd29a59
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SMMU_ADDRESS 0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS 0xff800000
+#define SOCFPGA_EMAC1_ADDRESS 0xff802000
+#define SOCFPGA_EMAC2_ADDRESS 0xff804000
+#define SOCFPGA_SDMMC_ADDRESS 0xff808000
+#define SOCFPGA_USB0_ADDRESS 0xffb00000
+#define SOCFPGA_USB1_ADDRESS 0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS 0xffb90000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc02100
+#define SOCFPGA_I2C0_ADDRESS 0xffc02800
+#define SOCFPGA_I2C1_ADDRESS 0xffc02900
+#define SOCFPGA_I2C2_ADDRESS 0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS 0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS 0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS 0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS 0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS 0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS 0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS 0xffd00500
+#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS 0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS 0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS 0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS 0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address
2016-08-22 15:02 ` [U-Boot] [PATCH 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chin Liang See
@ 2016-09-05 15:55 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 15:55 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Add base address header file for Stratix10 SoC
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
Acked-by: Marek Vasut <marex@denx.de>
> ---
> arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48 ++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100755 arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> new file mode 100755
> index 0000000..cd29a59
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (C) 2016, Intel Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> +
> +#define SOCFPGA_SMMU_ADDRESS 0xfa000000
> +#define SOCFPGA_EMAC0_ADDRESS 0xff800000
> +#define SOCFPGA_EMAC1_ADDRESS 0xff802000
> +#define SOCFPGA_EMAC2_ADDRESS 0xff804000
> +#define SOCFPGA_SDMMC_ADDRESS 0xff808000
> +#define SOCFPGA_USB0_ADDRESS 0xffb00000
> +#define SOCFPGA_USB1_ADDRESS 0xffb40000
> +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000
> +#define SOCFPGA_NANDDATA_ADDRESS 0xffb90000
> +#define SOCFPGA_UART0_ADDRESS 0xffc02000
> +#define SOCFPGA_UART1_ADDRESS 0xffc02100
> +#define SOCFPGA_I2C0_ADDRESS 0xffc02800
> +#define SOCFPGA_I2C1_ADDRESS 0xffc02900
> +#define SOCFPGA_I2C2_ADDRESS 0xffc02a00
> +#define SOCFPGA_I2C3_ADDRESS 0xffc02b00
> +#define SOCFPGA_I2C4_ADDRESS 0xffc02c00
> +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
> +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
> +#define SOCFPGA_GPIO0_ADDRESS 0xffc03200
> +#define SOCFPGA_GPIO1_ADDRESS 0xffc03300
> +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
> +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
> +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
> +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300
> +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400
> +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500
> +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
> +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
> +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
> +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
> +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
> +#define SOCFPGA_SPIS0_ADDRESS 0xffda2000
> +#define SOCFPGA_SPIS1_ADDRESS 0xffda3000
> +#define SOCFPGA_SPIM0_ADDRESS 0xffda4000
> +#define SOCFPGA_SPIM1_ADDRESS 0xffda5000
> +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
> +
> +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 02/11] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
2016-08-22 15:02 ` [U-Boot] [PATCH 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 15:56 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 03/11] arm: socfpga: rstmgr: Segregate the " Chin Liang See
` (8 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Add Reset Manager registers structure for Stratix 10 SoC
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..1f868da 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,11 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
};
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+struct socfpga_reset_manager {
+ u32 status;
+ u32 mpu_rst_stat;
+ u32 misc_stat;
+ u32 padding1;
+ u32 hdsk_en;
+ u32 hdsk_req;
+ u32 hdsk_ack;
+ u32 hdsk_stall;
+ u32 mpu_mod_reset;
+ u32 per_mod_reset; /* stated as per0_mod_reset in S10 datasheet */
+ u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
+ u32 brg_mod_reset;
+ u32 padding2;
+ u32 cold_mod_reset;
+ u32 padding3;
+ u32 dbg_mod_reset;
+ u32 tap_mod_reset;
+ u32 padding4;
+ u32 padding5;
+ u32 brg_warm_mask;
+ u32 padding6[3];
+ u32 tst_stat;
+ u32 padding7;
+ u32 hdsk_timeout;
+ u32 mpul2flushtimeout;
+ u32 dbghdsktimeout;
+};
+#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
#else
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+#define RSTMGR_MPUMODRST_CORE0 1
#endif
/*
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 02/11] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10
2016-08-22 15:02 ` [U-Boot] [PATCH 02/11] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10 Chin Liang See
@ 2016-09-05 15:56 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 15:56 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Add Reset Manager registers structure for Stratix 10 SoC
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
Acked-by: Marek Vasut <marex@denx.de>
> ---
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 2f070f2..1f868da 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
> void socfpga_per_reset(u32 reset, int set);
> void socfpga_per_reset_all(void);
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> struct socfpga_reset_manager {
> u32 status;
> u32 ctrl;
> @@ -28,11 +29,42 @@ struct socfpga_reset_manager {
> u32 padding2[12];
> u32 tstscratch;
> };
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> +struct socfpga_reset_manager {
> + u32 status;
> + u32 mpu_rst_stat;
> + u32 misc_stat;
> + u32 padding1;
> + u32 hdsk_en;
> + u32 hdsk_req;
> + u32 hdsk_ack;
> + u32 hdsk_stall;
> + u32 mpu_mod_reset;
> + u32 per_mod_reset; /* stated as per0_mod_reset in S10 datasheet */
> + u32 per2_mod_reset; /* stated as per1_mod_reset in S10 datasheet */
> + u32 brg_mod_reset;
> + u32 padding2;
> + u32 cold_mod_reset;
> + u32 padding3;
> + u32 dbg_mod_reset;
> + u32 tap_mod_reset;
> + u32 padding4;
> + u32 padding5;
> + u32 brg_warm_mask;
> + u32 padding6[3];
> + u32 tst_stat;
> + u32 padding7;
> + u32 hdsk_timeout;
> + u32 mpul2flushtimeout;
> + u32 dbghdsktimeout;
> +};
> +#endif
>
> #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
> #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
> #else
> #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
> +#define RSTMGR_MPUMODRST_CORE0 1
> #endif
>
> /*
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 03/11] arm: socfpga: rstmgr: Segregate the Reset Manager for Stratix 10
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
2016-08-22 15:02 ` [U-Boot] [PATCH 01/11] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chin Liang See
2016-08-22 15:02 ` [U-Boot] [PATCH 02/11] arm: socfpga: rstmgr: Add Reset Manager for Stratix 10 Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 15:57 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock " Chin Liang See
` (7 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Segregate the Reset Manager to support both GEN5 SoC and
Stratix 10 SoC.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/reset_manager.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..0fa5f1a 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -15,8 +15,10 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
@@ -31,8 +33,10 @@ void socfpga_per_reset(u32 reset, int set)
reg = &reset_manager_base->per2_mod_reset;
else if (RSTMGR_BANK(reset) == 3)
reg = &reset_manager_base->brg_mod_reset;
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
else if (RSTMGR_BANK(reset) == 4)
reg = &reset_manager_base->misc_mod_reset;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
else /* Invalid reset register, do nothing */
return;
@@ -60,9 +64,15 @@ void socfpga_per_reset_all(void)
*/
void reset_cpu(ulong addr)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* request a warm reset */
writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
&reset_manager_base->ctrl);
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+ writel((1 << RSTMGR_MPUMODRST_CORE0),
+ &reset_manager_base->mpu_mod_reset);
+#endif
+
/*
* infinite loop here as watchdog will trigger and reset
* the processor
@@ -92,6 +102,7 @@ void socfpga_bridges_reset(int enable)
void socfpga_bridges_reset(int enable)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
L3REGS_REMAP_HPS2FPGA_MASK |
L3REGS_REMAP_OCRAM_MASK;
@@ -116,5 +127,6 @@ void socfpga_bridges_reset(int enable)
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
}
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
}
#endif
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 03/11] arm: socfpga: rstmgr: Segregate the Reset Manager for Stratix 10
2016-08-22 15:02 ` [U-Boot] [PATCH 03/11] arm: socfpga: rstmgr: Segregate the " Chin Liang See
@ 2016-09-05 15:57 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 15:57 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Segregate the Reset Manager to support both GEN5 SoC and
> Stratix 10 SoC.
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
Acked-by: Marek Vasut <marex@denx.de>
> ---
> arch/arm/mach-socfpga/reset_manager.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
> index b6beaa2..0fa5f1a 100644
> --- a/arch/arm/mach-socfpga/reset_manager.c
> +++ b/arch/arm/mach-socfpga/reset_manager.c
> @@ -15,8 +15,10 @@ DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_reset_manager *reset_manager_base =
> (void *)SOCFPGA_RSTMGR_ADDRESS;
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
>
> /* Assert or de-assert SoCFPGA reset manager reset. */
> void socfpga_per_reset(u32 reset, int set)
> @@ -31,8 +33,10 @@ void socfpga_per_reset(u32 reset, int set)
> reg = &reset_manager_base->per2_mod_reset;
> else if (RSTMGR_BANK(reset) == 3)
> reg = &reset_manager_base->brg_mod_reset;
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> else if (RSTMGR_BANK(reset) == 4)
> reg = &reset_manager_base->misc_mod_reset;
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
> else /* Invalid reset register, do nothing */
> return;
>
> @@ -60,9 +64,15 @@ void socfpga_per_reset_all(void)
> */
> void reset_cpu(ulong addr)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> /* request a warm reset */
> writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
> &reset_manager_base->ctrl);
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> + writel((1 << RSTMGR_MPUMODRST_CORE0),
> + &reset_manager_base->mpu_mod_reset);
> +#endif
> +
> /*
> * infinite loop here as watchdog will trigger and reset
> * the processor
> @@ -92,6 +102,7 @@ void socfpga_bridges_reset(int enable)
>
> void socfpga_bridges_reset(int enable)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
> L3REGS_REMAP_HPS2FPGA_MASK |
> L3REGS_REMAP_OCRAM_MASK;
> @@ -116,5 +127,6 @@ void socfpga_bridges_reset(int enable)
> /* Remap the bridges into memory map */
> writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
> }
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5) */
> }
> #endif
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (2 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 03/11] arm: socfpga: rstmgr: Segregate the " Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 15:58 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the FPGA " Chin Liang See
` (6 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Segregate the Clock Manager to support both GEN5 SoC and
Stratix 10 SoC.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..0d67b3c 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,6 +10,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
@@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
return clock;
}
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
unsigned int cm_get_mmc_controller_clk_hz(void)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
uint32_t reg, clock = 0;
/* identify the source of MMC clock */
@@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
/* further divide by 4 as we have fixed divider at wrapper */
clock /= 4;
return clock;
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+ return 25000000;
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
unsigned int cm_get_qspi_controller_clk_hz(void)
{
uint32_t reg, clock = 0;
@@ -556,3 +563,4 @@ U_BOOT_CMD(
"display clocks",
""
);
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10
2016-08-22 15:02 ` [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock " Chin Liang See
@ 2016-09-05 15:58 ` Marek Vasut
2016-09-06 5:14 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 15:58 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Segregate the Clock Manager to support both GEN5 SoC and
> Stratix 10 SoC.
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
> index aa71636..0d67b3c 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -10,6 +10,7 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> static const struct socfpga_clock_manager *clock_manager_base =
> (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>
> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>
> return clock;
> }
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
> unsigned int cm_get_mmc_controller_clk_hz(void)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> uint32_t reg, clock = 0;
>
> /* identify the source of MMC clock */
> @@ -475,8 +478,12 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
> /* further divide by 4 as we have fixed divider at wrapper */
> clock /= 4;
> return clock;
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> + return 25000000;
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> }
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> unsigned int cm_get_qspi_controller_clk_hz(void)
Are you sure this won't cause build breakage ? I believe this is still
used by the cadence qspi driver.
> {
> uint32_t reg, clock = 0;
> @@ -556,3 +563,4 @@ U_BOOT_CMD(
> "display clocks",
> ""
> );
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10
2016-09-05 15:58 ` Marek Vasut
@ 2016-09-06 5:14 ` Chin Liang See
2016-09-06 12:08 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-06 5:14 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the Clock Manager to support both GEN5 SoC and
> > Stratix 10 SoC.
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> > arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach
> > -socfpga/clock_manager.c
> > index aa71636..0d67b3c 100644
> > --- a/arch/arm/mach-socfpga/clock_manager.c
> > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > @@ -10,6 +10,7 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > static const struct socfpga_clock_manager *clock_manager_base =
> > (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> >
> > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >
> > return clock;
> > }
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >
> > unsigned int cm_get_mmc_controller_clk_hz(void)
> > {
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > uint32_t reg, clock = 0;
> >
> > /* identify the source of MMC clock */
> > @@ -475,8 +478,12 @@ unsigned int
> > cm_get_mmc_controller_clk_hz(void)
> > /* further divide by 4 as we have fixed divider at wrapper
> > */
> > clock /= 4;
> > return clock;
> > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > + return 25000000;
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > }
> >
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > unsigned int cm_get_qspi_controller_clk_hz(void)
>
> Are you sure this won't cause build breakage ? I believe this is
> still
> used by the cadence qspi driver.
That is a good question. As for SOC Virtual Platform, we are not
enabling the QSPI controller.
Thanks
Chin Liang
>
> > {
> > uint32_t reg, clock = 0;
> > @@ -556,3 +563,4 @@ U_BOOT_CMD(
> > "display clocks",
> > ""
> > );
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10
2016-09-06 5:14 ` Chin Liang See
@ 2016-09-06 12:08 ` Marek Vasut
2016-09-07 13:26 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-06 12:08 UTC (permalink / raw)
To: u-boot
On 09/06/2016 07:14 AM, Chin Liang See wrote:
> On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>> Segregate the Clock Manager to support both GEN5 SoC and
>>> Stratix 10 SoC.
>>>
>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>> Cc: Ley Foon Tan <lftan@altera.com>
>>> ---
>>> arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
>>> 1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach
>>> -socfpga/clock_manager.c
>>> index aa71636..0d67b3c 100644
>>> --- a/arch/arm/mach-socfpga/clock_manager.c
>>> +++ b/arch/arm/mach-socfpga/clock_manager.c
>>> @@ -10,6 +10,7 @@
>>>
>>> DECLARE_GLOBAL_DATA_PTR;
>>>
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>> static const struct socfpga_clock_manager *clock_manager_base =
>>> (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>>>
>>> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>>>
>>> return clock;
>>> }
>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>
>>> unsigned int cm_get_mmc_controller_clk_hz(void)
>>> {
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>> uint32_t reg, clock = 0;
>>>
>>> /* identify the source of MMC clock */
>>> @@ -475,8 +478,12 @@ unsigned int
>>> cm_get_mmc_controller_clk_hz(void)
>>> /* further divide by 4 as we have fixed divider at wrapper
>>> */
>>> clock /= 4;
>>> return clock;
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>> + return 25000000;
>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>> }
>>>
>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>> unsigned int cm_get_qspi_controller_clk_hz(void)
>>
>> Are you sure this won't cause build breakage ? I believe this is
>> still
>> used by the cadence qspi driver.
>
> That is a good question. As for SOC Virtual Platform, we are not
> enabling the QSPI controller.
When stratix 10 ships, this will be left broken then ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10
2016-09-06 12:08 ` Marek Vasut
@ 2016-09-07 13:26 ` Chin Liang See
2016-09-07 14:57 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-07 13:26 UTC (permalink / raw)
To: u-boot
On Tue, 2016-09-06 at 14:08 +0200, Marek Vasut wrote:
> On 09/06/2016 07:14 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Segregate the Clock Manager to support both GEN5 SoC and
> > > > Stratix 10 SoC.
> > > >
> > > > Signed-off-by: Chin Liang See <clsee@altera.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lftan@altera.com>
> > > > ---
> > > > arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
> > > > 1 file changed, 8 insertions(+)
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c
> > > > b/arch/arm/mach
> > > > -socfpga/clock_manager.c
> > > > index aa71636..0d67b3c 100644
> > > > --- a/arch/arm/mach-socfpga/clock_manager.c
> > > > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > > > @@ -10,6 +10,7 @@
> > > >
> > > > DECLARE_GLOBAL_DATA_PTR;
> > > >
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > static const struct socfpga_clock_manager *clock_manager_base
> > > > =
> > > > (struct socfpga_clock_manager
> > > > *)SOCFPGA_CLKMGR_ADDRESS;
> > > >
> > > > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > > >
> > > > return clock;
> > > > }
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > >
> > > > unsigned int cm_get_mmc_controller_clk_hz(void)
> > > > {
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > uint32_t reg, clock = 0;
> > > >
> > > > /* identify the source of MMC clock */
> > > > @@ -475,8 +478,12 @@ unsigned int
> > > > cm_get_mmc_controller_clk_hz(void)
> > > > /* further divide by 4 as we have fixed divider at
> > > > wrapper
> > > > */
> > > > clock /= 4;
> > > > return clock;
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > > + return 25000000;
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > > }
> > > >
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > unsigned int cm_get_qspi_controller_clk_hz(void)
> > >
> > > Are you sure this won't cause build breakage ? I believe this is
> > > still
> > > used by the cadence qspi driver.
> >
> > That is a good question. As for SOC Virtual Platform, we are not
> > enabling the QSPI controller.
>
> When stratix 10 ships, this will be left broken then ?
>
Definitely not as we will enable and validate this against emulation in
coming weeks.
Thanks
Chin Liang
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock Manager for Stratix 10
2016-09-07 13:26 ` Chin Liang See
@ 2016-09-07 14:57 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-07 14:57 UTC (permalink / raw)
To: u-boot
On 09/07/2016 03:26 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:08 +0200, Marek Vasut wrote:
>> On 09/06/2016 07:14 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Segregate the Clock Manager to support both GEN5 SoC and
>>>>> Stratix 10 SoC.
>>>>>
>>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>>>> Cc: Ley Foon Tan <lftan@altera.com>
>>>>> ---
>>>>> arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
>>>>> 1 file changed, 8 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/clock_manager.c
>>>>> b/arch/arm/mach
>>>>> -socfpga/clock_manager.c
>>>>> index aa71636..0d67b3c 100644
>>>>> --- a/arch/arm/mach-socfpga/clock_manager.c
>>>>> +++ b/arch/arm/mach-socfpga/clock_manager.c
>>>>> @@ -10,6 +10,7 @@
>>>>>
>>>>> DECLARE_GLOBAL_DATA_PTR;
>>>>>
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>> static const struct socfpga_clock_manager *clock_manager_base
>>>>> =
>>>>> (struct socfpga_clock_manager
>>>>> *)SOCFPGA_CLKMGR_ADDRESS;
>>>>>
>>>>> @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>>>>>
>>>>> return clock;
>>>>> }
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>
>>>>> unsigned int cm_get_mmc_controller_clk_hz(void)
>>>>> {
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>> uint32_t reg, clock = 0;
>>>>>
>>>>> /* identify the source of MMC clock */
>>>>> @@ -475,8 +478,12 @@ unsigned int
>>>>> cm_get_mmc_controller_clk_hz(void)
>>>>> /* further divide by 4 as we have fixed divider at
>>>>> wrapper
>>>>> */
>>>>> clock /= 4;
>>>>> return clock;
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>>>> + return 25000000;
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>> }
>>>>>
>>>>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>>>> unsigned int cm_get_qspi_controller_clk_hz(void)
>>>>
>>>> Are you sure this won't cause build breakage ? I believe this is
>>>> still
>>>> used by the cadence qspi driver.
>>>
>>> That is a good question. As for SOC Virtual Platform, we are not
>>> enabling the QSPI controller.
>>
>> When stratix 10 ships, this will be left broken then ?
>>
>
> Definitely not as we will enable and validate this against emulation in
> coming weeks.
Great, thanks. U-Boot 2016.09 is out on sept. 12 , so that should give
you some space to clean this up.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the FPGA Manager for Stratix 10
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (3 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the Clock " Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 16:00 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c " Chin Liang See
` (5 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Segregate the FPGA Manager to support both GEN5 SoC and
Stratix 10 SoC.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/fpga_manager.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c
index 43fd2fe..a01e062 100644
--- a/arch/arm/mach-socfpga/fpga_manager.c
+++ b/arch/arm/mach-socfpga/fpga_manager.c
@@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* Timeout count */
#define FPGA_TIMEOUT_CNT 0x1000000
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
@@ -76,3 +78,5 @@ int fpgamgr_poll_fpga_ready(void)
return 0;
}
+
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the FPGA Manager for Stratix 10
2016-08-22 15:02 ` [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the FPGA " Chin Liang See
@ 2016-09-05 16:00 ` Marek Vasut
2016-09-06 5:44 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 16:00 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Segregate the FPGA Manager to support both GEN5 SoC and
> Stratix 10 SoC.
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> arch/arm/mach-socfpga/fpga_manager.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach-socfpga/fpga_manager.c
> index 43fd2fe..a01e062 100644
> --- a/arch/arm/mach-socfpga/fpga_manager.c
> +++ b/arch/arm/mach-socfpga/fpga_manager.c
> @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
> /* Timeout count */
> #define FPGA_TIMEOUT_CNT 0x1000000
>
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +
> static struct socfpga_fpga_manager *fpgamgr_regs =
> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
>
> @@ -76,3 +78,5 @@ int fpgamgr_poll_fpga_ready(void)
>
> return 0;
> }
> +
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
Did you just disable the whole file ? If so, then just don't compile it
at all, just add conditional into the Makefile.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the FPGA Manager for Stratix 10
2016-09-05 16:00 ` Marek Vasut
@ 2016-09-06 5:44 ` Chin Liang See
0 siblings, 0 replies; 40+ messages in thread
From: Chin Liang See @ 2016-09-06 5:44 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-05 at 18:00 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the FPGA Manager to support both GEN5 SoC and
> > Stratix 10 SoC.
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> > arch/arm/mach-socfpga/fpga_manager.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach
> > -socfpga/fpga_manager.c
> > index 43fd2fe..a01e062 100644
> > --- a/arch/arm/mach-socfpga/fpga_manager.c
> > +++ b/arch/arm/mach-socfpga/fpga_manager.c
> > @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
> > /* Timeout count */
> > #define FPGA_TIMEOUT_CNT 0x1000000
> >
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +
> > static struct socfpga_fpga_manager *fpgamgr_regs =
> > (struct socfpga_fpga_manager
> > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> >
> > @@ -76,3 +78,5 @@ int fpgamgr_poll_fpga_ready(void)
> >
> > return 0;
> > }
> > +
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >
> Did you just disable the whole file ? If so, then just don't compile
> it
> at all, just add conditional into the Makefile.
>
Yes, I just realize that :) I shall fix the Makefile instead of this
patch.
Thanks
Chin Liang
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c for Stratix 10
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (4 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the FPGA " Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 16:01 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64 Chin Liang See
` (4 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5cbd8a4..295121f 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -24,6 +24,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
+
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
static struct socfpga_system_manager *sysmgr_regs =
@@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+#endif
int dram_init(void)
{
@@ -41,6 +44,7 @@ int dram_init(void)
return 0;
}
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
void enable_caches(void)
{
#ifndef CONFIG_SYS_ICACHE_OFF
@@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id)
socfpga_fpga_model[i].name, version);
return i;
}
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
/*
* Print CPU information
@@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool print_id)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
puts("CPU: Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
printf("BOOT: %s\n", bsel_str[bsel].name);
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+ puts("CPU: Altera SoCFPGA Platform\n");
+ puts("FPGA: Altera Stratix 10\n");
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
return 0;
}
#endif
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
@@ -469,3 +480,4 @@ U_BOOT_CMD(
"bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
""
);
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c for Stratix 10
2016-08-22 15:02 ` [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c " Chin Liang See
@ 2016-09-05 16:01 ` Marek Vasut
2016-09-06 6:19 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 16:01 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 5cbd8a4..295121f 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -24,6 +24,8 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> +
> static struct pl310_regs *const pl310 =
> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> static struct socfpga_system_manager *sysmgr_regs =
> @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> static struct scu_registers *scu_regs =
> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> +#endif
>
> int dram_init(void)
> {
> @@ -41,6 +44,7 @@ int dram_init(void)
> return 0;
> }
>
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> void enable_caches(void)
> {
> #ifndef CONFIG_SYS_ICACHE_OFF
> @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id)
> socfpga_fpga_model[i].name, version);
> return i;
> }
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
> /*
> * Print CPU information
> @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool print_id)
> #if defined(CONFIG_DISPLAY_CPUINFO)
> int print_cpuinfo(void)
> {
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> puts("CPU: Altera SoCFPGA Platform\n");
> socfpga_fpga_id(1);
> printf("BOOT: %s\n", bsel_str[bsel].name);
> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> + puts("CPU: Altera SoCFPGA Platform\n");
> + puts("FPGA: Altera Stratix 10\n");
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
Can't you decode the boot mode and FPGA type instead ?
> return 0;
> }
> #endif
>
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> #ifdef CONFIG_ARCH_MISC_INIT
> int arch_misc_init(void)
> {
> @@ -469,3 +480,4 @@ U_BOOT_CMD(
> "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
> ""
> );
> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c for Stratix 10
2016-09-05 16:01 ` Marek Vasut
@ 2016-09-06 6:19 ` Chin Liang See
2016-09-06 12:09 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-06 6:19 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> > arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
> > -socfpga/misc.c
> > index 5cbd8a4..295121f 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -24,6 +24,8 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > +
> > static struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > static struct socfpga_system_manager *sysmgr_regs =
> > @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
> > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > static struct scu_registers *scu_regs =
> > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > +#endif
> >
> > int dram_init(void)
> > {
> > @@ -41,6 +44,7 @@ int dram_init(void)
> > return 0;
> > }
> >
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > void enable_caches(void)
> > {
> > #ifndef CONFIG_SYS_ICACHE_OFF
> > @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id)
> > socfpga_fpga_model[i].name, version);
> > return i;
> > }
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >
> > /*
> > * Print CPU information
> > @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool
> > print_id)
> > #if defined(CONFIG_DISPLAY_CPUINFO)
> > int print_cpuinfo(void)
> > {
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> > puts("CPU: Altera SoCFPGA Platform\n");
> > socfpga_fpga_id(1);
> > printf("BOOT: %s\n", bsel_str[bsel].name);
> > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > + puts("CPU: Altera SoCFPGA Platform\n");
> > + puts("FPGA: Altera Stratix 10\n");
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>
> Can't you decode the boot mode and FPGA type instead ?
That is a good question. This is now not available in SOC Virtual
Platform. But will definitely enhance this in later stage with hardware
available.
Thanks
Chin Liang
>
> > return 0;
> > }
> > #endif
> >
> > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > #ifdef CONFIG_ARCH_MISC_INIT
> > int arch_misc_init(void)
> > {
> > @@ -469,3 +480,4 @@ U_BOOT_CMD(
> > "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS
> > -to-FPGA bridges\n"
> > ""
> > );
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c for Stratix 10
2016-09-06 6:19 ` Chin Liang See
@ 2016-09-06 12:09 ` Marek Vasut
2016-09-07 13:28 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-06 12:09 UTC (permalink / raw)
To: u-boot
On 09/06/2016 08:19 AM, Chin Liang See wrote:
> On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:
>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>> Segregate the misc.c to support both GEN5 SoC and Stratix 10 SoC.
>>>
>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>> Cc: Ley Foon Tan <lftan@altera.com>
>>> ---
>>> arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
>>> 1 file changed, 12 insertions(+)
>>>
>>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
>>> -socfpga/misc.c
>>> index 5cbd8a4..295121f 100644
>>> --- a/arch/arm/mach-socfpga/misc.c
>>> +++ b/arch/arm/mach-socfpga/misc.c
>>> @@ -24,6 +24,8 @@
>>>
>>> DECLARE_GLOBAL_DATA_PTR;
>>>
>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>> +
>>> static struct pl310_regs *const pl310 =
>>> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>>> static struct socfpga_system_manager *sysmgr_regs =
>>> @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
>>> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>>> static struct scu_registers *scu_regs =
>>> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>>> +#endif
>>>
>>> int dram_init(void)
>>> {
>>> @@ -41,6 +44,7 @@ int dram_init(void)
>>> return 0;
>>> }
>>>
>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>> void enable_caches(void)
>>> {
>>> #ifndef CONFIG_SYS_ICACHE_OFF
>>> @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool print_id)
>>> socfpga_fpga_model[i].name, version);
>>> return i;
>>> }
>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>
>>> /*
>>> * Print CPU information
>>> @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool
>>> print_id)
>>> #if defined(CONFIG_DISPLAY_CPUINFO)
>>> int print_cpuinfo(void)
>>> {
>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>> const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
>>> puts("CPU: Altera SoCFPGA Platform\n");
>>> socfpga_fpga_id(1);
>>> printf("BOOT: %s\n", bsel_str[bsel].name);
>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>> + puts("CPU: Altera SoCFPGA Platform\n");
>>> + puts("FPGA: Altera Stratix 10\n");
>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>
>> Can't you decode the boot mode and FPGA type instead ?
>
> That is a good question. This is now not available in SOC Virtual
> Platform. But will definitely enhance this in later stage with hardware
> available.
What do you mean not available ? Does the VT not emulate the SoC precisely ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c for Stratix 10
2016-09-06 12:09 ` Marek Vasut
@ 2016-09-07 13:28 ` Chin Liang See
2016-09-07 14:57 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-07 13:28 UTC (permalink / raw)
To: u-boot
On Tue, 2016-09-06 at 14:09 +0200, Marek Vasut wrote:
> On 09/06/2016 08:19 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Segregate the misc.c to support both GEN5 SoC and Stratix 10
> > > > SoC.
> > > >
> > > > Signed-off-by: Chin Liang See <clsee@altera.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lftan@altera.com>
> > > > ---
> > > > arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
> > > > 1 file changed, 12 insertions(+)
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
> > > > -socfpga/misc.c
> > > > index 5cbd8a4..295121f 100644
> > > > --- a/arch/arm/mach-socfpga/misc.c
> > > > +++ b/arch/arm/mach-socfpga/misc.c
> > > > @@ -24,6 +24,8 @@
> > > >
> > > > DECLARE_GLOBAL_DATA_PTR;
> > > >
> > > > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > > > +
> > > > static struct pl310_regs *const pl310 =
> > > > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > static struct socfpga_system_manager *sysmgr_regs =
> > > > @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
> > > > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > > > static struct scu_registers *scu_regs =
> > > > (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > > > +#endif
> > > >
> > > > int dram_init(void)
> > > > {
> > > > @@ -41,6 +44,7 @@ int dram_init(void)
> > > > return 0;
> > > > }
> > > >
> > > > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > > > void enable_caches(void)
> > > > {
> > > > #ifndef CONFIG_SYS_ICACHE_OFF
> > > > @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool
> > > > print_id)
> > > > socfpga_fpga_model[i].name, version);
> > > > return i;
> > > > }
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > > >
> > > > /*
> > > > * Print CPU information
> > > > @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool
> > > > print_id)
> > > > #if defined(CONFIG_DISPLAY_CPUINFO)
> > > > int print_cpuinfo(void)
> > > > {
> > > > +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > > > const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> > > > puts("CPU: Altera SoCFPGA Platform\n");
> > > > socfpga_fpga_id(1);
> > > > printf("BOOT: %s\n", bsel_str[bsel].name);
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > > > + puts("CPU: Altera SoCFPGA Platform\n");
> > > > + puts("FPGA: Altera Stratix 10\n");
> > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > >
> > > Can't you decode the boot mode and FPGA type instead ?
> >
> > That is a good question. This is now not available in SOC Virtual
> > Platform. But will definitely enhance this in later stage with
> > hardware
> > available.
>
> What do you mean not available ? Does the VT not emulate the SoC
> precisely ?
>
The VT doesn't emulate the Secure Device Manager (SDM) part as its
focusing on ARM64 for this phase.
Thanks
Chin Liang
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c for Stratix 10
2016-09-07 13:28 ` Chin Liang See
@ 2016-09-07 14:57 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-07 14:57 UTC (permalink / raw)
To: u-boot
On 09/07/2016 03:28 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:09 +0200, Marek Vasut wrote:
>> On 09/06/2016 08:19 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 18:01 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Segregate the misc.c to support both GEN5 SoC and Stratix 10
>>>>> SoC.
>>>>>
>>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>>>> Cc: Ley Foon Tan <lftan@altera.com>
>>>>> ---
>>>>> arch/arm/mach-socfpga/misc.c | 12 ++++++++++++
>>>>> 1 file changed, 12 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
>>>>> -socfpga/misc.c
>>>>> index 5cbd8a4..295121f 100644
>>>>> --- a/arch/arm/mach-socfpga/misc.c
>>>>> +++ b/arch/arm/mach-socfpga/misc.c
>>>>> @@ -24,6 +24,8 @@
>>>>>
>>>>> DECLARE_GLOBAL_DATA_PTR;
>>>>>
>>>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> +
>>>>> static struct pl310_regs *const pl310 =
>>>>> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
>>>>> static struct socfpga_system_manager *sysmgr_regs =
>>>>> @@ -34,6 +36,7 @@ static struct nic301_registers *nic301_regs =
>>>>> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
>>>>> static struct scu_registers *scu_regs =
>>>>> (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
>>>>> +#endif
>>>>>
>>>>> int dram_init(void)
>>>>> {
>>>>> @@ -41,6 +44,7 @@ int dram_init(void)
>>>>> return 0;
>>>>> }
>>>>>
>>>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> void enable_caches(void)
>>>>> {
>>>>> #ifndef CONFIG_SYS_ICACHE_OFF
>>>>> @@ -246,6 +250,7 @@ static int socfpga_fpga_id(const bool
>>>>> print_id)
>>>>> socfpga_fpga_model[i].name, version);
>>>>> return i;
>>>>> }
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>>
>>>>> /*
>>>>> * Print CPU information
>>>>> @@ -253,14 +258,20 @@ static int socfpga_fpga_id(const bool
>>>>> print_id)
>>>>> #if defined(CONFIG_DISPLAY_CPUINFO)
>>>>> int print_cpuinfo(void)
>>>>> {
>>>>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>>>> const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
>>>>> puts("CPU: Altera SoCFPGA Platform\n");
>>>>> socfpga_fpga_id(1);
>>>>> printf("BOOT: %s\n", bsel_str[bsel].name);
>>>>> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
>>>>> + puts("CPU: Altera SoCFPGA Platform\n");
>>>>> + puts("FPGA: Altera Stratix 10\n");
>>>>> +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
>>>>
>>>> Can't you decode the boot mode and FPGA type instead ?
>>>
>>> That is a good question. This is now not available in SOC Virtual
>>> Platform. But will definitely enhance this in later stage with
>>> hardware
>>> available.
>>
>> What do you mean not available ? Does the VT not emulate the SoC
>> precisely ?
>>
>
> The VT doesn't emulate the Secure Device Manager (SDM) part as its
> focusing on ARM64 for this phase.
And the SDM is now the place from which you fish out the information
about the FPGA and bootmode ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (5 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 06/11] arm: socfpga: misc: Segregate the misc.c " Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 16:02 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 08/11] arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC Chin Liang See
` (3 subsequent siblings)
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Fix casting warning to pointer from integer of different size
when enabling ARM64 support
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/system_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..89161bd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -56,7 +56,7 @@ static void populate_sysmgr_fpgaintf_module(void)
*/
void sysmgr_pinmux_init(void)
{
- uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
+ uint32_t *regs = (uint32_t *)&sysmgr_regs->emacio[0];
const u8 *sys_mgr_init_table;
unsigned int len;
int i;
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64
2016-08-22 15:02 ` [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64 Chin Liang See
@ 2016-09-05 16:02 ` Marek Vasut
2016-09-06 9:41 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 16:02 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Fix casting warning to pointer from integer of different size
> when enabling ARM64 support
What sort of error did you observe ?
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> arch/arm/mach-socfpga/system_manager.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c
> index 75a65f3..89161bd 100644
> --- a/arch/arm/mach-socfpga/system_manager.c
> +++ b/arch/arm/mach-socfpga/system_manager.c
> @@ -56,7 +56,7 @@ static void populate_sysmgr_fpgaintf_module(void)
> */
> void sysmgr_pinmux_init(void)
> {
> - uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
> + uint32_t *regs = (uint32_t *)&sysmgr_regs->emacio[0];
> const u8 *sys_mgr_init_table;
> unsigned int len;
> int i;
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64
2016-09-05 16:02 ` Marek Vasut
@ 2016-09-06 9:41 ` Chin Liang See
2016-09-06 12:12 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-06 9:41 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-05 at 18:02 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Fix casting warning to pointer from integer of different size
> > when enabling ARM64 support
>
> What sort of error did you observe ?
The warning is triggered as ARM64 has build flag -Wpointer-to-int-cast
and similar. Here is the build error log
arch/arm/mach-socfpga/system_manager.c: In function sysmgr_pinmux_init:
arch/arm/mach-socfpga/system_manager.c:59:18: warning: cast
from pointer to integer of different size [-Wpointer-to-int-cast]
uint32_t regs = (uint32_t)&sysmgr_regs
->emacio[0];
^
In file
included from arch/arm/mach-socfpga/system_manager.c:8:0:
./arch/arm/include/asm/io.h:78:29: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
#define __arch_putl(v,a) (*(volatile unsigned int
*)(a) = (v))
^
Thanks
Chin Liang
>
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> > arch/arm/mach-socfpga/system_manager.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach
> > -socfpga/system_manager.c
> > index 75a65f3..89161bd 100644
> > --- a/arch/arm/mach-socfpga/system_manager.c
> > +++ b/arch/arm/mach-socfpga/system_manager.c
> > @@ -56,7 +56,7 @@ static void populate_sysmgr_fpgaintf_module(void)
> > */
> > void sysmgr_pinmux_init(void)
> > {
> > - uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
> > + uint32_t *regs = (uint32_t *)&sysmgr_regs->emacio[0];
> > const u8 *sys_mgr_init_table;
> > unsigned int len;
> > int i;
> >
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64
2016-09-06 9:41 ` Chin Liang See
@ 2016-09-06 12:12 ` Marek Vasut
2016-09-07 13:31 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-06 12:12 UTC (permalink / raw)
To: u-boot
On 09/06/2016 11:41 AM, Chin Liang See wrote:
> On Mon, 2016-09-05 at 18:02 +0200, Marek Vasut wrote:
>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>> Fix casting warning to pointer from integer of different size
>>> when enabling ARM64 support
>>
>> What sort of error did you observe ?
>
> The warning is triggered as ARM64 has build flag -Wpointer-to-int-cast
> and similar. Here is the build error log
>
> arch/arm/mach-socfpga/system_manager.c: In function sysmgr_pinmux_init:
>
> arch/arm/mach-socfpga/system_manager.c:59:18: warning: cast
> from pointer to integer of different size [-Wpointer-to-int-cast]
> uint32_t regs = (uint32_t)&sysmgr_regs
> ->emacio[0];
> ^
>
> In file
> included from arch/arm/mach-socfpga/system_manager.c:8:0:
>
> ./arch/arm/include/asm/io.h:78:29: warning: cast to pointer from
> integer of different size [-Wint-to-pointer-cast]
> #define __arch_putl(v,a) (*(volatile unsigned int
> *)(a) = (v))
I see ... Except the code below does regs += sizeof(regs); , which in
the original case increments the address by 4 , but with your change,
the increment would be 16 . So this patch breaks things.
btw it's not worth reposting patches while there is still ongoing
discussion.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64
2016-09-06 12:12 ` Marek Vasut
@ 2016-09-07 13:31 ` Chin Liang See
2016-09-07 14:54 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-07 13:31 UTC (permalink / raw)
To: u-boot
On Tue, 2016-09-06 at 14:12 +0200, Marek Vasut wrote:
> On 09/06/2016 11:41 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 18:02 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Fix casting warning to pointer from integer of different size
> > > > when enabling ARM64 support
> > >
> > > What sort of error did you observe ?
> >
> > The warning is triggered as ARM64 has build flag -Wpointer-to-int
> > -cast
> > and similar. Here is the build error log
> >
> > arch/arm/mach-socfpga/system_manager.c: In function
> > sysmgr_pinmux_init:
> >
> >
> > arch/arm/mach-socfpga/system_manager.c:59:18: warning:
> > cast
> > from pointer to integer of different size [-Wpointer-to-int-cast]
> >
> > uint32_t regs = (uint32_t)&sysmgr_regs
> > ->emacio[0];
> >
> > ^
> >
> >
> >
> > In file
> > included from arch/arm/mach-socfpga/system_manager.c:8:0:
> >
> >
> >
> > ./arch/arm/include/asm/io.h:78:29: warning: cast to pointer
> > from
> > integer of different size [-Wint-to-pointer-cast]
> >
> > #define __arch_putl(v,a) (*(volatile unsigned
> > int
> > *)(a) = (v))
> >
>
> I see ... Except the code below does regs += sizeof(regs); , which in
> the original case increments the address by 4 , but with your change,
> the increment would be 16 . So this patch breaks things.
>
Relook back, this portion is not being used and hence not being
validated. Will put #ifdef in place to skip out these code.
Thanks
Chin Liang
> btw it's not worth reposting patches while there is still ongoing
> discussion.
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64
2016-09-07 13:31 ` Chin Liang See
@ 2016-09-07 14:54 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-07 14:54 UTC (permalink / raw)
To: u-boot
On 09/07/2016 03:31 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:12 +0200, Marek Vasut wrote:
>> On 09/06/2016 11:41 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 18:02 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Fix casting warning to pointer from integer of different size
>>>>> when enabling ARM64 support
>>>>
>>>> What sort of error did you observe ?
>>>
>>> The warning is triggered as ARM64 has build flag -Wpointer-to-int
>>> -cast
>>> and similar. Here is the build error log
>>>
>>> arch/arm/mach-socfpga/system_manager.c: In function
>>> sysmgr_pinmux_init:
>>>
>>>
>>> arch/arm/mach-socfpga/system_manager.c:59:18: warning:
>>> cast
>>> from pointer to integer of different size [-Wpointer-to-int-cast]
>>>
>>> uint32_t regs = (uint32_t)&sysmgr_regs
>>> ->emacio[0];
>>>
>>> ^
>>>
>>>
>>>
>>> In file
>>> included from arch/arm/mach-socfpga/system_manager.c:8:0:
>>>
>>>
>>>
>>> ./arch/arm/include/asm/io.h:78:29: warning: cast to pointer
>>> from
>>> integer of different size [-Wint-to-pointer-cast]
>>>
>>> #define __arch_putl(v,a) (*(volatile unsigned
>>> int
>>> *)(a) = (v))
>>>
>>
>> I see ... Except the code below does regs += sizeof(regs); , which in
>> the original case increments the address by 4 , but with your change,
>> the increment would be 16 . So this patch breaks things.
>>
>
> Relook back, this portion is not being used and hence not being
> validated. Will put #ifdef in place to skip out these code.
Which portion is not used ? I don't understand why this patch is valid,
in fact I think it is wrong.
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 08/11] arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (6 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 07/11] arm: socfpga: sysmgr: Fix casting warning when enabling ARM64 Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-08-22 15:02 ` [U-Boot] [PATCH 09/11] arm: socfpga: stratix10: Add board folder for Stratix 10 socdk Chin Liang See
` (2 subsequent siblings)
10 siblings, 0 replies; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Add memory map layout for Stratix 10 SoC
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/mmu-arm64.c | 71 +++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
create mode 100755 arch/arm/mach-socfpga/mmu-arm64.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 809cd47..af1cc01 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -12,6 +12,8 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += mmu-arm64.o
+
# QTS-generated config file wrappers
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o
obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
diff --git a/arch/arm/mach-socfpga/mmu-arm64.c b/arch/arm/mach-socfpga/mmu-arm64.c
new file mode 100755
index 0000000..3b73143
--- /dev/null
+++ b/arch/arm/mach-socfpga/mmu-arm64.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region socfpga_stratix10_mem_map[] = {
+ {
+ /* MEM 2GB*/
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* FPGA 1.5GB */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x60000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* DEVICE 142MB */
+ .virt = 0xF7000000UL,
+ .phys = 0xF7000000UL,
+ .size = 0x08E00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* OCRAM 1MB but available 256KB */
+ .virt = 0xFFE00000UL,
+ .phys = 0xFFE00000UL,
+ .size = 0x00100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* DEVICE 32KB */
+ .virt = 0xFFFC0000UL,
+ .phys = 0xFFFC0000UL,
+ .size = 0x00008000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* MEM 124GB */
+ .virt = 0x0100000000UL,
+ .phys = 0x0100000000UL,
+ .size = 0x1F00000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* DEVICE 4GB */
+ .virt = 0x2000000000UL,
+ .phys = 0x2000000000UL,
+ .size = 0x0100000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* List terminator */
+ },
+};
+
+struct mm_region *mem_map = socfpga_stratix10_mem_map;
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 09/11] arm: socfpga: stratix10: Add board folder for Stratix 10 socdk
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (7 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 08/11] arm: socfpga: mmu: Add memory map layout for Stratix 10 SoC Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 16:03 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 10/11] arm: dts: socfpga: Add dts " Chin Liang See
2016-08-22 15:02 ` [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit Chin Liang See
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Add board folder for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
board/altera/stratix10-socdk/MAINTAINERS | 8 ++++++++
board/altera/stratix10-socdk/Makefile | 7 +++++++
board/altera/stratix10-socdk/socfpga.c | 7 +++++++
3 files changed, 22 insertions(+)
create mode 100755 board/altera/stratix10-socdk/MAINTAINERS
create mode 100755 board/altera/stratix10-socdk/Makefile
create mode 100755 board/altera/stratix10-socdk/socfpga.c
diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS
new file mode 100755
index 0000000..06f8989
--- /dev/null
+++ b/board/altera/stratix10-socdk/MAINTAINERS
@@ -0,0 +1,8 @@
+SOCFPGA BOARD
+M: Chin-Liang See <clsee@altera.com>
+M: Dinh Nguyen <dinguyen@opensource.altera.com>
+S: Maintained
+F: board/altera/stratix10-socdk/
+F: include/configs/socfpga_stratix10_socdk.h
+F: configs/socfpga_stratix10_defconfig
+
diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
new file mode 100755
index 0000000..a0c8024
--- /dev/null
+++ b/board/altera/stratix10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016, Intel Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := socfpga.o
diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
new file mode 100755
index 0000000..6778c04
--- /dev/null
+++ b/board/altera/stratix10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 09/11] arm: socfpga: stratix10: Add board folder for Stratix 10 socdk
2016-08-22 15:02 ` [U-Boot] [PATCH 09/11] arm: socfpga: stratix10: Add board folder for Stratix 10 socdk Chin Liang See
@ 2016-09-05 16:03 ` Marek Vasut
2016-09-06 6:29 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 16:03 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Add board folder for Stratix 10 SoC development kit
Directory, this is not Windows :-(
Oh, btw also use "separate", not "segregate", in the previous patches.
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> board/altera/stratix10-socdk/MAINTAINERS | 8 ++++++++
> board/altera/stratix10-socdk/Makefile | 7 +++++++
> board/altera/stratix10-socdk/socfpga.c | 7 +++++++
> 3 files changed, 22 insertions(+)
> create mode 100755 board/altera/stratix10-socdk/MAINTAINERS
> create mode 100755 board/altera/stratix10-socdk/Makefile
> create mode 100755 board/altera/stratix10-socdk/socfpga.c
>
> diff --git a/board/altera/stratix10-socdk/MAINTAINERS b/board/altera/stratix10-socdk/MAINTAINERS
> new file mode 100755
> index 0000000..06f8989
> --- /dev/null
> +++ b/board/altera/stratix10-socdk/MAINTAINERS
> @@ -0,0 +1,8 @@
> +SOCFPGA BOARD
> +M: Chin-Liang See <clsee@altera.com>
> +M: Dinh Nguyen <dinguyen@opensource.altera.com>
> +S: Maintained
> +F: board/altera/stratix10-socdk/
> +F: include/configs/socfpga_stratix10_socdk.h
> +F: configs/socfpga_stratix10_defconfig
> +
> diff --git a/board/altera/stratix10-socdk/Makefile b/board/altera/stratix10-socdk/Makefile
> new file mode 100755
> index 0000000..a0c8024
> --- /dev/null
> +++ b/board/altera/stratix10-socdk/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (C) 2016, Intel Corporation
> +#
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +
> +obj-y := socfpga.o
> diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c
> new file mode 100755
> index 0000000..6778c04
> --- /dev/null
> +++ b/board/altera/stratix10-socdk/socfpga.c
> @@ -0,0 +1,7 @@
> +/*
> + * Copyright (C) 2016, Intel Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 09/11] arm: socfpga: stratix10: Add board folder for Stratix 10 socdk
2016-09-05 16:03 ` Marek Vasut
@ 2016-09-06 6:29 ` Chin Liang See
0 siblings, 0 replies; 40+ messages in thread
From: Chin Liang See @ 2016-09-06 6:29 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-05 at 18:03 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Add board folder for Stratix 10 SoC development kit
>
> Directory, this is not Windows :-(
haha... used to the windows term :) Will change this
>
> Oh, btw also use "separate", not "segregate", in the previous
> patches.
Yup, will fix
Thanks
Chin Liang
>
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> > board/altera/stratix10-socdk/MAINTAINERS | 8 ++++++++
> > board/altera/stratix10-socdk/Makefile | 7 +++++++
> > board/altera/stratix10-socdk/socfpga.c | 7 +++++++
> > 3 files changed, 22 insertions(+)
> > create mode 100755 board/altera/stratix10-socdk/MAINTAINERS
> > create mode 100755 board/altera/stratix10-socdk/Makefile
> > create mode 100755 board/altera/stratix10-socdk/socfpga.c
> >
> > diff --git a/board/altera/stratix10-socdk/MAINTAINERS
> > b/board/altera/stratix10-socdk/MAINTAINERS
> > new file mode 100755
> > index 0000000..06f8989
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/MAINTAINERS
> > @@ -0,0 +1,8 @@
> > +SOCFPGA BOARD
> > +M: Chin-Liang See <clsee@altera.com>
> > +M: Dinh Nguyen <dinguyen@opensource.altera.com>
> > +S: Maintained
> > +F: board/altera/stratix10-socdk/
> > +F: include/configs/socfpga_stratix10_socdk.h
> > +F: configs/socfpga_stratix10_defconfig
> > +
> > diff --git a/board/altera/stratix10-socdk/Makefile
> > b/board/altera/stratix10-socdk/Makefile
> > new file mode 100755
> > index 0000000..a0c8024
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/Makefile
> > @@ -0,0 +1,7 @@
> > +#
> > +# Copyright (C) 2016, Intel Corporation
> > +#
> > +# SPDX-License-Identifier: GPL-2.0
> > +#
> > +
> > +obj-y := socfpga.o
> > diff --git a/board/altera/stratix10-socdk/socfpga.c
> > b/board/altera/stratix10-socdk/socfpga.c
> > new file mode 100755
> > index 0000000..6778c04
> > --- /dev/null
> > +++ b/board/altera/stratix10-socdk/socfpga.c
> > @@ -0,0 +1,7 @@
> > +/*
> > + * Copyright (C) 2016, Intel Corporation
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#include <common.h>
> >
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 10/11] arm: dts: socfpga: Add dts for Stratix 10 socdk
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (8 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 09/11] arm: socfpga: stratix10: Add board folder for Stratix 10 socdk Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 16:04 ` Marek Vasut
2016-08-22 15:02 ` [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit Chin Liang See
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Add device tree for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/socfpga_stratix10_socdk.dts | 64 ++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+), 1 deletion(-)
create mode 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 223124e..c5e2d3c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -127,7 +127,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
- socfpga_cyclone5_vining_fpga.dtb
+ socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
new file mode 100755
index 0000000..7a662ee
--- /dev/null
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "skeleton.dtsi"
+
+/ {
+ model = "Altera SOCFPGA Stratix 10 SoC Development Kit";
+ compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ regulator_3_3v: 3-3-v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ ranges;
+
+ mmc0: dwmmc0 at 0xff808000 {
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xff808000 0x1000>;
+ interrupts = <0 139 4>;
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+ fifo-depth = <0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ drvsel = <3>;
+ smplsel = <0>;
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ vmmc-supply = <®ulator_3_3v>;
+ vqmmc-supply = <®ulator_3_3v>;
+ };
+ };
+};
+
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 10/11] arm: dts: socfpga: Add dts for Stratix 10 socdk
2016-08-22 15:02 ` [U-Boot] [PATCH 10/11] arm: dts: socfpga: Add dts " Chin Liang See
@ 2016-09-05 16:04 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 16:04 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Add device tree for Stratix 10 SoC development kit
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
Acked-by: Marek Vasut <marex@denx.de>
> ---
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/socfpga_stratix10_socdk.dts | 64 ++++++++++++++++++++++++++++++++
> 2 files changed, 66 insertions(+), 1 deletion(-)
> create mode 100755 arch/arm/dts/socfpga_stratix10_socdk.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 223124e..c5e2d3c 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -127,7 +127,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
> socfpga_cyclone5_sockit.dtb \
> socfpga_cyclone5_socrates.dtb \
> socfpga_cyclone5_sr1500.dtb \
> - socfpga_cyclone5_vining_fpga.dtb
> + socfpga_cyclone5_vining_fpga.dtb \
> + socfpga_stratix10_socdk.dtb
>
> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
> dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
> new file mode 100755
> index 0000000..7a662ee
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright (C) 2016 Intel Corporation
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +/dts-v1/;
> +/* First 4KB has trampoline code for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;
> +#include "skeleton.dtsi"
> +
> +/ {
> + model = "Altera SOCFPGA Stratix 10 SoC Development Kit";
> + compatible = "altr,socfpga-stratix10", "altr,socfpga";
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + chosen {
> + bootargs = "console=ttyS0,115200";
> + };
> +
> + memory {
> + name = "memory";
> + device_type = "memory";
> + reg = <0x0 0x40000000>; /* 1GB */
> + };
> +
> + regulator_3_3v: 3-3-v-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + device_type = "soc";
> + ranges;
> +
> + mmc0: dwmmc0 at 0xff808000 {
> + compatible = "altr,socfpga-dw-mshc";
> + reg = <0xff808000 0x1000>;
> + interrupts = <0 139 4>;
> + num-slots = <1>;
> + broken-cd;
> + bus-width = <4>;
> + fifo-depth = <0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + drvsel = <3>;
> + smplsel = <0>;
> + status = "okay";
> + u-boot,dm-pre-reloc;
> + vmmc-supply = <®ulator_3_3v>;
> + vqmmc-supply = <®ulator_3_3v>;
> + };
> + };
> +};
> +
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
2016-08-22 15:02 [U-Boot] [PATCH 00/11] Add support for Stratix 10 SoC Chin Liang See
` (9 preceding siblings ...)
2016-08-22 15:02 ` [U-Boot] [PATCH 10/11] arm: dts: socfpga: Add dts " Chin Liang See
@ 2016-08-22 15:02 ` Chin Liang See
2016-09-05 16:06 ` Marek Vasut
10 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-08-22 15:02 UTC (permalink / raw)
To: u-boot
Add support for Stratix 10 SoC development kit
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
---
arch/arm/Kconfig | 7 +-
arch/arm/mach-socfpga/Kconfig | 10 +++
configs/socfpga_stratix10_defconfig | 14 ++++
include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++
4 files changed, 163 insertions(+), 3 deletions(-)
create mode 100755 configs/socfpga_stratix10_defconfig
create mode 100644 include/configs/socfpga_stratix10_socdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef901c..c8e8767 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
- select CPU_V7
- select SUPPORT_SPL
+ select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
+ select ARM64 if TARGET_SOCFPGA_STRATIX10
+ select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
select OF_CONTROL
- select SPL_OF_CONTROL
+ select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 1a43c7b..4e3b238 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5
bool
+config TARGET_SOCFPGA_STRATIX10
+ bool
+
choice
prompt "Altera SOCFPGA board select"
optional
@@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_STRATIX10_SOCDK
+ bool "Altera SOCFPGA SoCDK (Stratix 10)"
+ select TARGET_SOCFPGA_STRATIX10
+
endchoice
config SYS_BOARD
@@ -63,6 +70,7 @@ config SYS_BOARD
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+ default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -72,6 +80,7 @@ config SYS_VENDOR
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
+ default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
config SYS_SOC
default "socfpga"
@@ -86,5 +95,6 @@ config SYS_CONFIG_NAME
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+ default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
endif
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
new file mode 100755
index 0000000..b17eb92
--- /dev/null
+++ b/configs/socfpga_stratix10_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_STRATIX10=y
+CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
+CONFIG_SYS_NS16550=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 0000000..758c995
--- /dev/null
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
+#define __CONFIG_SOCFGPA_STRATIX10_H__
+
+#include <asm/arch/base_addr_s10.h>
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_TEXT_BASE 0x1000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR 0x80000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+# define COUNTER_FREQUENCY 0x01800000
+
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_IDENT_STRING "socfpga_stratix10"
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * U-Boot run time memory configurations
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x40000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+
+/*
+ * U-Boot display configurations
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE 1
+#define CONFIG_ENV_SIZE 0x1000
+
+/*
+ * Boot arguments passed to the boot command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "rdinit=/sbin/init mem=2048M"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootimage=Image\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga_stratix10_swvp.dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+
+/*
+ * Generic Interrupt Controller Definitions
+ */
+#define CONFIG_GICV2
+#define GICD_BASE 0xFFFC1000
+#define GICC_BASE 0xFFFC2000
+
+/*
+ * External memory configurations
+ */
+#define PHYS_SDRAM_1 0x0
+#define PHYS_SDRAM_1_SIZE 0x40000000
+#define CONFIG_SYS_SDRAM_BASE 0
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_MEMTEST_START 0
+#define CONFIG_SYS_MEMTEST_END 0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550_CLK 1000000
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Timer & watchdog configurations
+ */
+#define CONFIG_SYS_TIMERBASE SOCFPGA_SYSTIMER0_ADDRESS
+#define TIMER_LOAD_VAL 0xFFFFFFFF
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
+#endif
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_NO_FLASH
+
+
+#endif /* __CONFIG_H */
--
2.2.2
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
2016-08-22 15:02 ` [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit Chin Liang See
@ 2016-09-05 16:06 ` Marek Vasut
2016-09-06 9:18 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-05 16:06 UTC (permalink / raw)
To: u-boot
On 08/22/2016 05:02 PM, Chin Liang See wrote:
> Add support for Stratix 10 SoC development kit
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> ---
> arch/arm/Kconfig | 7 +-
> arch/arm/mach-socfpga/Kconfig | 10 +++
> configs/socfpga_stratix10_defconfig | 14 ++++
> include/configs/socfpga_stratix10_socdk.h | 135 ++++++++++++++++++++++++++++++
> 4 files changed, 163 insertions(+), 3 deletions(-)
> create mode 100755 configs/socfpga_stratix10_defconfig
> create mode 100644 include/configs/socfpga_stratix10_socdk.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index aef901c..c8e8767 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
>
> config ARCH_SOCFPGA
> bool "Altera SOCFPGA family"
> - select CPU_V7
> - select SUPPORT_SPL
> + select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
> + select ARM64 if TARGET_SOCFPGA_STRATIX10
> + select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
> select OF_CONTROL
> - select SPL_OF_CONTROL
> + select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
Why is the SPL disabled ?
> select DM
> select DM_SPI_FLASH
> select DM_SPI
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 1a43c7b..4e3b238 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
> config TARGET_SOCFPGA_GEN5
> bool
>
> +config TARGET_SOCFPGA_STRATIX10
> + bool
> +
> choice
> prompt "Altera SOCFPGA board select"
> optional
> @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
> bool "Terasic SoCkit (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> +config TARGET_SOCFPGA_STRATIX10_SOCDK
> + bool "Altera SOCFPGA SoCDK (Stratix 10)"
> + select TARGET_SOCFPGA_STRATIX10
> +
> endchoice
>
> config SYS_BOARD
> @@ -63,6 +70,7 @@ config SYS_BOARD
> default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> default "sr1500" if TARGET_SOCFPGA_SR1500
> default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> + default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Keep all the lists sorted .
> config SYS_VENDOR
> default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> @@ -72,6 +80,7 @@ config SYS_VENDOR
> default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
> default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
> + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
>
> config SYS_SOC
> default "socfpga"
> @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME
> default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
> default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> + default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
>
> endif
[...]
btw. what about Arria 10 ? Will it ever land ?
And will I ever get a kit ? :)
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
2016-09-05 16:06 ` Marek Vasut
@ 2016-09-06 9:18 ` Chin Liang See
2016-09-06 12:15 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-06 9:18 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Add support for Stratix 10 SoC development kit
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> > arch/arm/Kconfig | 7 +-
> > arch/arm/mach-socfpga/Kconfig | 10 +++
> > configs/socfpga_stratix10_defconfig | 14 ++++
> > include/configs/socfpga_stratix10_socdk.h | 135
> > ++++++++++++++++++++++++++++++
> > 4 files changed, 163 insertions(+), 3 deletions(-)
> > create mode 100755 configs/socfpga_stratix10_defconfig
> > create mode 100644 include/configs/socfpga_stratix10_socdk.h
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index aef901c..c8e8767 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
> >
> > config ARCH_SOCFPGA
> > bool "Altera SOCFPGA family"
> > - select CPU_V7
> > - select SUPPORT_SPL
> > + select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
> > + select ARM64 if TARGET_SOCFPGA_STRATIX10
> > + select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
> > select OF_CONTROL
> > - select SPL_OF_CONTROL
> > + select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
>
> Why is the SPL disabled ?
We will be having SPL for Stratix 10. It will added in later days as
SPL main function is for DDR setup. This is not needed for SOC Virtual
Platform now.
>
> > select DM
> > select DM_SPI_FLASH
> > select DM_SPI
> > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach
> > -socfpga/Kconfig
> > index 1a43c7b..4e3b238 100644
> > --- a/arch/arm/mach-socfpga/Kconfig
> > +++ b/arch/arm/mach-socfpga/Kconfig
> > @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
> > config TARGET_SOCFPGA_GEN5
> > bool
> >
> > +config TARGET_SOCFPGA_STRATIX10
> > + bool
> > +
> > choice
> > prompt "Altera SOCFPGA board select"
> > optional
> > @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
> > bool "Terasic SoCkit (Cyclone V)"
> > select TARGET_SOCFPGA_CYCLONE5
> >
> > +config TARGET_SOCFPGA_STRATIX10_SOCDK
> > + bool "Altera SOCFPGA SoCDK (Stratix 10)"
> > + select TARGET_SOCFPGA_STRATIX10
> > +
> > endchoice
> >
> > config SYS_BOARD
> > @@ -63,6 +70,7 @@ config SYS_BOARD
> > default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> > default "sr1500" if TARGET_SOCFPGA_SR1500
> > default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > + default "stratix10-socdk" if
> > TARGET_SOCFPGA_STRATIX10_SOCDK
>
> Keep all the lists sorted .
Noted, will fix this.
>
> > config SYS_VENDOR
> > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> > @@ -72,6 +80,7 @@ config SYS_VENDOR
> > default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
> > default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
> > + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
> >
> > config SYS_SOC
> > default "socfpga"
> > @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME
> > default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> > default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
> > default "socfpga_vining_fpga" if
> > TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > + default "socfpga_stratix10_socdk" if
> > TARGET_SOCFPGA_STRATIX10_SOCDK
> >
> > endif
>
> [...]
>
> btw. what about Arria 10 ? Will it ever land ?
> And will I ever get a kit ? :)
Since S10 is good, I will help out the A10 upstreaming once S10 is
intergrated. While for dev kit, let me work that out as we have A10 dev
kit with production silicon :)
Thanks
Chin Liang
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
2016-09-06 9:18 ` Chin Liang See
@ 2016-09-06 12:15 ` Marek Vasut
2016-09-07 13:33 ` Chin Liang See
0 siblings, 1 reply; 40+ messages in thread
From: Marek Vasut @ 2016-09-06 12:15 UTC (permalink / raw)
To: u-boot
On 09/06/2016 11:18 AM, Chin Liang See wrote:
> On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>> Add support for Stratix 10 SoC development kit
>>>
>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>> Cc: Ley Foon Tan <lftan@altera.com>
>>> ---
>>> arch/arm/Kconfig | 7 +-
>>> arch/arm/mach-socfpga/Kconfig | 10 +++
>>> configs/socfpga_stratix10_defconfig | 14 ++++
>>> include/configs/socfpga_stratix10_socdk.h | 135
>>> ++++++++++++++++++++++++++++++
>>> 4 files changed, 163 insertions(+), 3 deletions(-)
>>> create mode 100755 configs/socfpga_stratix10_defconfig
>>> create mode 100644 include/configs/socfpga_stratix10_socdk.h
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index aef901c..c8e8767 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
>>>
>>> config ARCH_SOCFPGA
>>> bool "Altera SOCFPGA family"
>>> - select CPU_V7
>>> - select SUPPORT_SPL
>>> + select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
>>> + select ARM64 if TARGET_SOCFPGA_STRATIX10
>>> + select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
>>> select OF_CONTROL
>>> - select SPL_OF_CONTROL
>>> + select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
>>
>> Why is the SPL disabled ?
>
> We will be having SPL for Stratix 10. It will added in later days as
> SPL main function is for DDR setup. This is not needed for SOC Virtual
> Platform now.
Please do things right from the start, add the SPL and skip the DRAM
init if it's not needed.
>>> select DM
>>> select DM_SPI_FLASH
>>> select DM_SPI
>>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach
>>> -socfpga/Kconfig
>>> index 1a43c7b..4e3b238 100644
>>> --- a/arch/arm/mach-socfpga/Kconfig
>>> +++ b/arch/arm/mach-socfpga/Kconfig
>>> @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
>>> config TARGET_SOCFPGA_GEN5
>>> bool
>>>
>>> +config TARGET_SOCFPGA_STRATIX10
>>> + bool
>>> +
>>> choice
>>> prompt "Altera SOCFPGA board select"
>>> optional
>>> @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
>>> bool "Terasic SoCkit (Cyclone V)"
>>> select TARGET_SOCFPGA_CYCLONE5
>>>
>>> +config TARGET_SOCFPGA_STRATIX10_SOCDK
>>> + bool "Altera SOCFPGA SoCDK (Stratix 10)"
>>> + select TARGET_SOCFPGA_STRATIX10
>>> +
>>> endchoice
>>>
>>> config SYS_BOARD
>>> @@ -63,6 +70,7 @@ config SYS_BOARD
>>> default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
>>> default "sr1500" if TARGET_SOCFPGA_SR1500
>>> default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>>> + default "stratix10-socdk" if
>>> TARGET_SOCFPGA_STRATIX10_SOCDK
>>
>> Keep all the lists sorted .
>
> Noted, will fix this.
>
>>
>>> config SYS_VENDOR
>>> default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
>>> @@ -72,6 +80,7 @@ config SYS_VENDOR
>>> default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>>> default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>>> default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
>>> + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
>>>
>>> config SYS_SOC
>>> default "socfpga"
>>> @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME
>>> default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
>>> default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
>>> default "socfpga_vining_fpga" if
>>> TARGET_SOCFPGA_SAMTEC_VINING_FPGA
>>> + default "socfpga_stratix10_socdk" if
>>> TARGET_SOCFPGA_STRATIX10_SOCDK
>>>
>>> endif
>>
>> [...]
>>
>> btw. what about Arria 10 ? Will it ever land ?
>> And will I ever get a kit ? :)
>
> Since S10 is good, I will help out the A10 upstreaming once S10 is
> intergrated. While for dev kit, let me work that out as we have A10 dev
> kit with production silicon :)
The production silicon a10 is still not available ?
> Thanks
> Chin Liang
>
>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
2016-09-06 12:15 ` Marek Vasut
@ 2016-09-07 13:33 ` Chin Liang See
2016-09-07 14:54 ` Marek Vasut
0 siblings, 1 reply; 40+ messages in thread
From: Chin Liang See @ 2016-09-07 13:33 UTC (permalink / raw)
To: u-boot
On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote:
> On 09/06/2016 11:18 AM, Chin Liang See wrote:
> > On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
> > > On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > > > Add support for Stratix 10 SoC development kit
> > > >
> > > > Signed-off-by: Chin Liang See <clsee@altera.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > > Cc: Ley Foon Tan <lftan@altera.com>
> > > > ---
> > > > arch/arm/Kconfig | 7 +-
> > > > arch/arm/mach-socfpga/Kconfig | 10 +++
> > > > configs/socfpga_stratix10_defconfig | 14 ++++
> > > > include/configs/socfpga_stratix10_socdk.h | 135
> > > > ++++++++++++++++++++++++++++++
> > > > 4 files changed, 163 insertions(+), 3 deletions(-)
> > > > create mode 100755 configs/socfpga_stratix10_defconfig
> > > > create mode 100644 include/configs/socfpga_stratix10_socdk.h
> > > >
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index aef901c..c8e8767 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
> > > >
> > > > config ARCH_SOCFPGA
> > > > bool "Altera SOCFPGA family"
> > > > - select CPU_V7
> > > > - select SUPPORT_SPL
> > > > + select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
> > > > + select ARM64 if TARGET_SOCFPGA_STRATIX10
> > > > + select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
> > > > select OF_CONTROL
> > > > - select SPL_OF_CONTROL
> > > > + select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
> > >
> > > Why is the SPL disabled ?
> >
> > We will be having SPL for Stratix 10. It will added in later days
> > as
> > SPL main function is for DDR setup. This is not needed for SOC
> > Virtual
> > Platform now.
>
> Please do things right from the start, add the SPL and skip the DRAM
> init if it's not needed.
That is my next to do list as I am enabling the Stratix 10 by phases.
In this case, I shall repost this series once getting SPL available.
Thanks
Chin Liang
>
> > > > select DM
> > > > select DM_SPI_FLASH
> > > > select DM_SPI
> > > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach
> > > > -socfpga/Kconfig
> > > > index 1a43c7b..4e3b238 100644
> > > > --- a/arch/arm/mach-socfpga/Kconfig
> > > > +++ b/arch/arm/mach-socfpga/Kconfig
> > > > @@ -11,6 +11,9 @@ config TARGET_SOCFPGA_CYCLONE5
> > > > config TARGET_SOCFPGA_GEN5
> > > > bool
> > > >
> > > > +config TARGET_SOCFPGA_STRATIX10
> > > > + bool
> > > > +
> > > > choice
> > > > prompt "Altera SOCFPGA board select"
> > > > optional
> > > > @@ -51,6 +54,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
> > > > bool "Terasic SoCkit (Cyclone V)"
> > > > select TARGET_SOCFPGA_CYCLONE5
> > > >
> > > > +config TARGET_SOCFPGA_STRATIX10_SOCDK
> > > > + bool "Altera SOCFPGA SoCDK (Stratix 10)"
> > > > + select TARGET_SOCFPGA_STRATIX10
> > > > +
> > > > endchoice
> > > >
> > > > config SYS_BOARD
> > > > @@ -63,6 +70,7 @@ config SYS_BOARD
> > > > default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> > > > default "sr1500" if TARGET_SOCFPGA_SR1500
> > > > default "vining_fpga" if
> > > > TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > > > + default "stratix10-socdk" if
> > > > TARGET_SOCFPGA_STRATIX10_SOCDK
> > >
> > > Keep all the lists sorted .
> >
> > Noted, will fix this.
> >
> > >
> > > > config SYS_VENDOR
> > > > default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> > > > @@ -72,6 +80,7 @@ config SYS_VENDOR
> > > > default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > > > default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
> > > > default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
> > > > + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
> > > >
> > > > config SYS_SOC
> > > > default "socfpga"
> > > > @@ -86,5 +95,6 @@ config SYS_CONFIG_NAME
> > > > default "socfpga_socrates" if
> > > > TARGET_SOCFPGA_EBV_SOCRATES
> > > > default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
> > > > default "socfpga_vining_fpga" if
> > > > TARGET_SOCFPGA_SAMTEC_VINING_FPGA
> > > > + default "socfpga_stratix10_socdk" if
> > > > TARGET_SOCFPGA_STRATIX10_SOCDK
> > > >
> > > > endif
> > >
> > > [...]
> > >
> > > btw. what about Arria 10 ? Will it ever land ?
> > > And will I ever get a kit ? :)
> >
> > Since S10 is good, I will help out the A10 upstreaming once S10 is
> > intergrated. While for dev kit, let me work that out as we have A10
> > dev
> > kit with production silicon :)
>
> The production silicon a10 is still not available ?
>
> > Thanks
> > Chin Liang
> >
> > >
>
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/11] arm: socfpga: Add support for Stratix 10 SoC dev kit
2016-09-07 13:33 ` Chin Liang See
@ 2016-09-07 14:54 ` Marek Vasut
0 siblings, 0 replies; 40+ messages in thread
From: Marek Vasut @ 2016-09-07 14:54 UTC (permalink / raw)
To: u-boot
On 09/07/2016 03:33 PM, Chin Liang See wrote:
> On Tue, 2016-09-06 at 14:15 +0200, Marek Vasut wrote:
>> On 09/06/2016 11:18 AM, Chin Liang See wrote:
>>> On Mon, 2016-09-05 at 18:06 +0200, Marek Vasut wrote:
>>>> On 08/22/2016 05:02 PM, Chin Liang See wrote:
>>>>> Add support for Stratix 10 SoC development kit
>>>>>
>>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
>>>>> Cc: Ley Foon Tan <lftan@altera.com>
>>>>> ---
>>>>> arch/arm/Kconfig | 7 +-
>>>>> arch/arm/mach-socfpga/Kconfig | 10 +++
>>>>> configs/socfpga_stratix10_defconfig | 14 ++++
>>>>> include/configs/socfpga_stratix10_socdk.h | 135
>>>>> ++++++++++++++++++++++++++++++
>>>>> 4 files changed, 163 insertions(+), 3 deletions(-)
>>>>> create mode 100755 configs/socfpga_stratix10_defconfig
>>>>> create mode 100644 include/configs/socfpga_stratix10_socdk.h
>>>>>
>>>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>>>> index aef901c..c8e8767 100644
>>>>> --- a/arch/arm/Kconfig
>>>>> +++ b/arch/arm/Kconfig
>>>>> @@ -600,10 +600,11 @@ config ARCH_SNAPDRAGON
>>>>>
>>>>> config ARCH_SOCFPGA
>>>>> bool "Altera SOCFPGA family"
>>>>> - select CPU_V7
>>>>> - select SUPPORT_SPL
>>>>> + select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
>>>>> + select ARM64 if TARGET_SOCFPGA_STRATIX10
>>>>> + select SUPPORT_SPL if !TARGET_SOCFPGA_STRATIX10
>>>>> select OF_CONTROL
>>>>> - select SPL_OF_CONTROL
>>>>> + select SPL_OF_CONTROL if !TARGET_SOCFPGA_STRATIX10
>>>>
>>>> Why is the SPL disabled ?
>>>
>>> We will be having SPL for Stratix 10. It will added in later days
>>> as
>>> SPL main function is for DDR setup. This is not needed for SOC
>>> Virtual
>>> Platform now.
>>
>> Please do things right from the start, add the SPL and skip the DRAM
>> init if it's not needed.
>
> That is my next to do list as I am enabling the Stratix 10 by phases.
> In this case, I shall repost this series once getting SPL available.
That's fine. When do you see that happening ?
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 40+ messages in thread