* [PATCH net-next 0/3] add support for RGMII on GMAC0 through TRGMII hardware module @ 2016-09-20 7:59 ` sean.wang 0 siblings, 0 replies; 19+ messages in thread From: sean.wang @ 2016-09-20 7:59 UTC (permalink / raw) To: john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf, Sean Wang From: Sean Wang <sean.wang@mediatek.com> By default, GMAC0 is connected to built-in switch called MT7530 through the proprietary interface called Turbo RGMII (TRGMII). TRGMII also supports well for RGMII as generic external PHY uses but requires some slight changes to the setup of TRGMII and doesn't have well support on current driver. So this patchset 1) provides the slight changes of the setup for RGMII can work through TRGMII 2) adds additional setting "trgmii" about phy-mode on device tree to make GMAC0 distinguish which mode it runs 3) changes dynamically source clock, TX/RX delay and interface mode on TRGMII for adapting various link Sean Wang (3): net: ethernet: mediatek: add extension of phy-mode for TRGMII net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 .../devicetree/bindings/net/mediatek-net.txt | 5 +- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 57 ++++++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 32 ++++++++++++ 3 files changed, 90 insertions(+), 4 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH net-next 0/3] add support for RGMII on GMAC0 through TRGMII hardware module @ 2016-09-20 7:59 ` sean.wang 0 siblings, 0 replies; 19+ messages in thread From: sean.wang @ 2016-09-20 7:59 UTC (permalink / raw) To: john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf, Sean Wang From: Sean Wang <sean.wang@mediatek.com> By default, GMAC0 is connected to built-in switch called MT7530 through the proprietary interface called Turbo RGMII (TRGMII). TRGMII also supports well for RGMII as generic external PHY uses but requires some slight changes to the setup of TRGMII and doesn't have well support on current driver. So this patchset 1) provides the slight changes of the setup for RGMII can work through TRGMII 2) adds additional setting "trgmii" about phy-mode on device tree to make GMAC0 distinguish which mode it runs 3) changes dynamically source clock, TX/RX delay and interface mode on TRGMII for adapting various link Sean Wang (3): net: ethernet: mediatek: add extension of phy-mode for TRGMII net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 .../devicetree/bindings/net/mediatek-net.txt | 5 +- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 57 ++++++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 32 ++++++++++++ 3 files changed, 90 insertions(+), 4 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <1474358360-29901-1-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>]
* [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII [not found] ` <1474358360-29901-1-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> @ 2016-09-20 7:59 ` sean.wang-NuS5LvNUpcJWk0Htik3J/w 0 siblings, 0 replies; 19+ messages in thread From: sean.wang-NuS5LvNUpcJWk0Htik3J/w @ 2016-09-20 7:59 UTC (permalink / raw) To: john-Pj+rj9U5foFAfugRpC6u6w, davem-fT/PcQaiUtIeIZ0/mPfg9Q Cc: nbd-p3rKhJxN3npAfugRpC6u6w, keyhaede-Re5JQEeQqe8AvxtiuMwx3w, netdev-u79uwXL29TY76Z2rM5mHXA, Sean Wang, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, objelf-Re5JQEeQqe8AvxtiuMwx3w From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> adds PHY-mode "trgmii" as an extension for the operation mode of the PHY interface, TRGMII can be compatible with RGMII, so the extended mode doesn't really have effects on the target MAC and PHY, is used as the indication if the current MAC is connected to an internal switch or external PHY respectively by the given configuration on the board and then to perform the corresponding setup on TRGMII hardware module. Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 24 ++++++++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index ca6b501..a0e338b 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -135,6 +135,26 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) return _mtk_mdio_read(eth, phy_addr, phy_reg); } +static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np) +{ + int phy_mode, err; + const char *pm; + + phy_mode = of_get_phy_mode(np); + + if (phy_mode >= 0) + return phy_mode; + err = of_property_read_string(np, "phy-mode", &pm); + if (err < 0) + return err; + if (!strcasecmp(pm, "trgmii")) { + mac->trgmii = true; + /* TRGMII could be compatible with RGMII */ + return PHY_INTERFACE_MODE_RGMII; + } else + return -ENODEV; +} + static void mtk_phy_link_adjust(struct net_device *dev) { struct mtk_mac *mac = netdev_priv(dev); @@ -207,7 +227,7 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, return -EINVAL; } addr = be32_to_cpu(*_addr); - phy_mode = of_get_phy_mode(phy_node); + phy_mode = mtk_of_get_phy_mode(mac, phy_node); if (phy_mode < 0) { dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); return -EINVAL; @@ -243,7 +263,7 @@ static int mtk_phy_connect(struct mtk_mac *mac) if (!np) return -ENODEV; - switch (of_get_phy_mode(np)) { + switch (mtk_of_get_phy_mode(mac, np)) { case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 7c5e534..e3b9525 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -529,6 +529,8 @@ struct mtk_eth { * @hw: Backpointer to our main datastruture * @hw_stats: Packet statistics counter * @phy_dev: The attached PHY if available + * @trgmii Indicate if the MAC uses TRGMII connected to internal + switch */ struct mtk_mac { int id; @@ -539,6 +541,7 @@ struct mtk_mac { struct phy_device *phy_dev; __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; int hwlro_ip_cnt; + bool trgmii; }; /* the struct describing the SoC. these are declared in the soc_xyz.c files */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII @ 2016-09-20 7:59 ` sean.wang-NuS5LvNUpcJWk0Htik3J/w 0 siblings, 0 replies; 19+ messages in thread From: sean.wang-NuS5LvNUpcJWk0Htik3J/w @ 2016-09-20 7:59 UTC (permalink / raw) To: john-Pj+rj9U5foFAfugRpC6u6w, davem-fT/PcQaiUtIeIZ0/mPfg9Q Cc: nbd-p3rKhJxN3npAfugRpC6u6w, keyhaede-Re5JQEeQqe8AvxtiuMwx3w, netdev-u79uwXL29TY76Z2rM5mHXA, Sean Wang, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, objelf-Re5JQEeQqe8AvxtiuMwx3w From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> adds PHY-mode "trgmii" as an extension for the operation mode of the PHY interface, TRGMII can be compatible with RGMII, so the extended mode doesn't really have effects on the target MAC and PHY, is used as the indication if the current MAC is connected to an internal switch or external PHY respectively by the given configuration on the board and then to perform the corresponding setup on TRGMII hardware module. Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 24 ++++++++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++ 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index ca6b501..a0e338b 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -135,6 +135,26 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) return _mtk_mdio_read(eth, phy_addr, phy_reg); } +static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np) +{ + int phy_mode, err; + const char *pm; + + phy_mode = of_get_phy_mode(np); + + if (phy_mode >= 0) + return phy_mode; + err = of_property_read_string(np, "phy-mode", &pm); + if (err < 0) + return err; + if (!strcasecmp(pm, "trgmii")) { + mac->trgmii = true; + /* TRGMII could be compatible with RGMII */ + return PHY_INTERFACE_MODE_RGMII; + } else + return -ENODEV; +} + static void mtk_phy_link_adjust(struct net_device *dev) { struct mtk_mac *mac = netdev_priv(dev); @@ -207,7 +227,7 @@ static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, return -EINVAL; } addr = be32_to_cpu(*_addr); - phy_mode = of_get_phy_mode(phy_node); + phy_mode = mtk_of_get_phy_mode(mac, phy_node); if (phy_mode < 0) { dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); return -EINVAL; @@ -243,7 +263,7 @@ static int mtk_phy_connect(struct mtk_mac *mac) if (!np) return -ENODEV; - switch (of_get_phy_mode(np)) { + switch (mtk_of_get_phy_mode(mac, np)) { case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 7c5e534..e3b9525 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -529,6 +529,8 @@ struct mtk_eth { * @hw: Backpointer to our main datastruture * @hw_stats: Packet statistics counter * @phy_dev: The attached PHY if available + * @trgmii Indicate if the MAC uses TRGMII connected to internal + switch */ struct mtk_mac { int id; @@ -539,6 +541,7 @@ struct mtk_mac { struct phy_device *phy_dev; __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT]; int hwlro_ip_cnt; + bool trgmii; }; /* the struct describing the SoC. these are declared in the soc_xyz.c files */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII 2016-09-20 7:59 ` sean.wang-NuS5LvNUpcJWk0Htik3J/w (?) @ 2016-09-20 21:23 ` Florian Fainelli [not found] ` <064d43fb-2942-efd2-6dc7-09f47a256691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> -1 siblings, 1 reply; 19+ messages in thread From: Florian Fainelli @ 2016-09-20 21:23 UTC (permalink / raw) To: sean.wang, john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf On 09/20/2016 12:59 AM, sean.wang@mediatek.com wrote: > From: Sean Wang <sean.wang@mediatek.com> > > adds PHY-mode "trgmii" as an extension for the operation > mode of the PHY interface, TRGMII can be compatible with > RGMII, so the extended mode doesn't really have effects on > the target MAC and PHY, is used as the indication if the > current MAC is connected to an internal switch or external > PHY respectively by the given configuration on the board and > then to perform the corresponding setup on TRGMII hardware > module. Based on my googling, it seems like Turbo RGMII is a Mediatek-specific thing for now, but this could become standard and used by other vendors at some point, so I would be inclined to just extend the phy-mode property to support trgmii as another interface type. If you do so, do you also mind proposing an update to the Device Tree specification: https://www.devicetree.org/specifications/ Thanks! -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <064d43fb-2942-efd2-6dc7-09f47a256691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII [not found] ` <064d43fb-2942-efd2-6dc7-09f47a256691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2016-09-21 7:33 ` Sean Wang 0 siblings, 0 replies; 19+ messages in thread From: Sean Wang @ 2016-09-21 7:33 UTC (permalink / raw) To: f.fainelli-Re5JQEeQqe8AvxtiuMwx3w Cc: nbd-p3rKhJxN3npAfugRpC6u6w, keyhaede-Re5JQEeQqe8AvxtiuMwx3w, netdev-u79uwXL29TY76Z2rM5mHXA, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, john-Pj+rj9U5foFAfugRpC6u6w, davem-fT/PcQaiUtIeIZ0/mPfg9Q Date: Tue, 20 Sep 2016 14:23:24 -0700, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: >On 09/20/2016 12:59 AM, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote: >> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> >> >> adds PHY-mode "trgmii" as an extension for the operation >> mode of the PHY interface, TRGMII can be compatible with >> RGMII, so the extended mode doesn't really have effects on >> the target MAC and PHY, is used as the indication if the >> current MAC is connected to an internal switch or external >> PHY respectively by the given configuration on the board and >> then to perform the corresponding setup on TRGMII hardware >> module. > >Based on my googling, it seems like Turbo RGMII is a Mediatek-specific >thing for now, but this could become standard and used by other vendors >at some point, so I would be inclined to just extend the phy-mode >property to support trgmii as another interface type. > >If you do so, do you also mind proposing an update to the Device Tree >specification: > >https://www.devicetree.org/specifications/ > >Thanks! I am willing to do the these thing 1) in the next version, I will extend rgmii mode as another interface type as PHY_INTERFACE_MODE_TRGMII defined in linux/phy.h instead of extension only inside the current driver. This change also helps to save some code. 2) I send another separate patch for updating the Device Tree specification about TRGMII adding description are these all okay for you? ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII @ 2016-09-21 7:33 ` Sean Wang 0 siblings, 0 replies; 19+ messages in thread From: Sean Wang @ 2016-09-21 7:33 UTC (permalink / raw) To: f.fainelli-Re5JQEeQqe8AvxtiuMwx3w Cc: nbd-p3rKhJxN3npAfugRpC6u6w, keyhaede-Re5JQEeQqe8AvxtiuMwx3w, netdev-u79uwXL29TY76Z2rM5mHXA, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, john-Pj+rj9U5foFAfugRpC6u6w, davem-fT/PcQaiUtIeIZ0/mPfg9Q Date: Tue, 20 Sep 2016 14:23:24 -0700, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: >On 09/20/2016 12:59 AM, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote: >> From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> >> >> adds PHY-mode "trgmii" as an extension for the operation >> mode of the PHY interface, TRGMII can be compatible with >> RGMII, so the extended mode doesn't really have effects on >> the target MAC and PHY, is used as the indication if the >> current MAC is connected to an internal switch or external >> PHY respectively by the given configuration on the board and >> then to perform the corresponding setup on TRGMII hardware >> module. > >Based on my googling, it seems like Turbo RGMII is a Mediatek-specific >thing for now, but this could become standard and used by other vendors >at some point, so I would be inclined to just extend the phy-mode >property to support trgmii as another interface type. > >If you do so, do you also mind proposing an update to the Device Tree >specification: > >https://www.devicetree.org/specifications/ > >Thanks! I am willing to do the these thing 1) in the next version, I will extend rgmii mode as another interface type as PHY_INTERFACE_MODE_TRGMII defined in linux/phy.h instead of extension only inside the current driver. This change also helps to save some code. 2) I send another separate patch for updating the Device Tree specification about TRGMII adding description are these all okay for you? ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII 2016-09-21 7:33 ` Sean Wang (?) @ 2016-09-21 16:59 ` Florian Fainelli -1 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2016-09-21 16:59 UTC (permalink / raw) To: Sean Wang; +Cc: john, davem, nbd, netdev, linux-mediatek, keyhaede On 09/21/2016 12:33 AM, Sean Wang wrote: > Date: Tue, 20 Sep 2016 14:23:24 -0700, Florian Fainelli <f.fainelli@gmail.com> wrote: >> On 09/20/2016 12:59 AM, sean.wang@mediatek.com wrote: >>> From: Sean Wang <sean.wang@mediatek.com> >>> >>> adds PHY-mode "trgmii" as an extension for the operation >>> mode of the PHY interface, TRGMII can be compatible with >>> RGMII, so the extended mode doesn't really have effects on >>> the target MAC and PHY, is used as the indication if the >>> current MAC is connected to an internal switch or external >>> PHY respectively by the given configuration on the board and >>> then to perform the corresponding setup on TRGMII hardware >>> module. >> >> Based on my googling, it seems like Turbo RGMII is a Mediatek-specific >> thing for now, but this could become standard and used by other vendors >> at some point, so I would be inclined to just extend the phy-mode >> property to support trgmii as another interface type. >> >> If you do so, do you also mind proposing an update to the Device Tree >> specification: >> >> https://www.devicetree.org/specifications/ >> >> Thanks! > > I am willing to do the these thing > > 1) > in the next version, I will extend rgmii mode as > another interface type as PHY_INTERFACE_MODE_TRGMII > defined in linux/phy.h instead of extension only inside > the current driver. This change also helps to save some code. > > 2) > I send another separate patch for updating the Device Tree > specification about TRGMII adding description > > are these all okay for you? Absolutely, thanks a lot! -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH net-next 2/3] net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII 2016-09-20 7:59 ` sean.wang @ 2016-09-20 7:59 ` sean.wang -1 siblings, 0 replies; 19+ messages in thread From: sean.wang @ 2016-09-20 7:59 UTC (permalink / raw) To: john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf, Sean Wang From: Sean Wang <sean.wang@mediatek.com> Changing dynamically source clock, TX/RX delay and interface mode used by TRGMII hardware module inside PHY capability polling routine for adapting to the various speed of RGMII used by external PHY for GMAC0. Signed-off-by: Sean Wang <sean.wang@mediatek.com> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ++++++++++++++++++++++++++++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index a0e338b..609fd2b 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -52,7 +52,7 @@ static const struct mtk_ethtool_stats { }; static const char * const mtk_clks_source_name[] = { - "ethif", "esw", "gp1", "gp2" + "ethif", "esw", "gp1", "gp2", "trgpll" }; void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) @@ -135,6 +135,33 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) return _mtk_mdio_read(eth, phy_addr, phy_reg); } +static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) +{ + u32 val; + int ret; + + val = (speed == SPEED_1000) ? + INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; + mtk_w32(eth, val, INTF_MODE); + + regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, + ETHSYS_TRGMII_CLK_SEL362_5, + ETHSYS_TRGMII_CLK_SEL362_5); + + val = (speed == SPEED_1000) ? 250000000 : 500000000; + ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); + if (ret) + dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); + + val = (speed == SPEED_1000) ? + RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; + mtk_w32(eth, val, TRGMII_RCK_CTRL); + + val = (speed == SPEED_1000) ? + TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; + mtk_w32(eth, val, TRGMII_TCK_CTRL); +} + static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np) { int phy_mode, err; @@ -149,6 +176,7 @@ static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np) return err; if (!strcasecmp(pm, "trgmii")) { mac->trgmii = true; + /* TRGMII could be compatible with RGMII */ return PHY_INTERFACE_MODE_RGMII; } else @@ -177,6 +205,9 @@ static void mtk_phy_link_adjust(struct net_device *dev) break; }; + if (mac->id == 0 && !mac->trgmii) + mtk_gmac0_rgmii_adjust(mac->hw, mac->phy_dev->speed); + if (mac->phy_dev->link) mcr |= MAC_MCR_FORCE_LINK; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index e3b9525..f1f44de 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -313,6 +313,30 @@ MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) +/*TRGMII RXC control register*/ +#define TRGMII_RCK_CTRL 0x10300 +#define DQSI0(x) ((x << 0) & GENMASK(6, 0)) +#define DQSI1(x) ((x << 8) & GENMASK(14, 8)) +#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) +#define RXC_DQSISEL BIT(30) +#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) +#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) + +/*TRGMII RXC control register*/ +#define TRGMII_TCK_CTRL 0x10340 +#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) +#define TXC_INV BIT(30) +#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) +#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) + +/*TRGMII Interface mode register*/ +#define INTF_MODE 0x10390 +#define TRGMII_INTF_DIS BIT(0) +#define TRGMII_MODE BIT(1) +#define TRGMII_CENTRAL_ALIGNED BIT(2) +#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) +#define INTF_MODE_RGMII_10_100 0 + /* GPIO port control registers for GMAC 2*/ #define GPIO_OD33_CTRL8 0x4c0 #define GPIO_BIAS_CTRL 0xed0 @@ -323,6 +347,10 @@ #define SYSCFG0_GE_MASK 0x3 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) +/* ethernet subsystem clock register */ +#define ETHSYS_CLKCFG0 0x2c +#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) + /*ethernet reset control register*/ #define ETHSYS_RSTCTRL 0x34 #define RSTCTRL_FE BIT(6) @@ -389,6 +417,7 @@ enum mtk_clks_map { MTK_CLK_ESW, MTK_CLK_GP1, MTK_CLK_GP2, + MTK_CLK_TRGPLL, MTK_CLK_MAX }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH net-next 2/3] net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII @ 2016-09-20 7:59 ` sean.wang 0 siblings, 0 replies; 19+ messages in thread From: sean.wang @ 2016-09-20 7:59 UTC (permalink / raw) To: john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf, Sean Wang From: Sean Wang <sean.wang@mediatek.com> Changing dynamically source clock, TX/RX delay and interface mode used by TRGMII hardware module inside PHY capability polling routine for adapting to the various speed of RGMII used by external PHY for GMAC0. Signed-off-by: Sean Wang <sean.wang@mediatek.com> --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ++++++++++++++++++++++++++++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +++++++++++++++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index a0e338b..609fd2b 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -52,7 +52,7 @@ static const struct mtk_ethtool_stats { }; static const char * const mtk_clks_source_name[] = { - "ethif", "esw", "gp1", "gp2" + "ethif", "esw", "gp1", "gp2", "trgpll" }; void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) @@ -135,6 +135,33 @@ static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) return _mtk_mdio_read(eth, phy_addr, phy_reg); } +static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) +{ + u32 val; + int ret; + + val = (speed == SPEED_1000) ? + INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; + mtk_w32(eth, val, INTF_MODE); + + regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, + ETHSYS_TRGMII_CLK_SEL362_5, + ETHSYS_TRGMII_CLK_SEL362_5); + + val = (speed == SPEED_1000) ? 250000000 : 500000000; + ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); + if (ret) + dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); + + val = (speed == SPEED_1000) ? + RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; + mtk_w32(eth, val, TRGMII_RCK_CTRL); + + val = (speed == SPEED_1000) ? + TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; + mtk_w32(eth, val, TRGMII_TCK_CTRL); +} + static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np) { int phy_mode, err; @@ -149,6 +176,7 @@ static int mtk_of_get_phy_mode(struct mtk_mac *mac, struct device_node *np) return err; if (!strcasecmp(pm, "trgmii")) { mac->trgmii = true; + /* TRGMII could be compatible with RGMII */ return PHY_INTERFACE_MODE_RGMII; } else @@ -177,6 +205,9 @@ static void mtk_phy_link_adjust(struct net_device *dev) break; }; + if (mac->id == 0 && !mac->trgmii) + mtk_gmac0_rgmii_adjust(mac->hw, mac->phy_dev->speed); + if (mac->phy_dev->link) mcr |= MAC_MCR_FORCE_LINK; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index e3b9525..f1f44de 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -313,6 +313,30 @@ MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) +/*TRGMII RXC control register*/ +#define TRGMII_RCK_CTRL 0x10300 +#define DQSI0(x) ((x << 0) & GENMASK(6, 0)) +#define DQSI1(x) ((x << 8) & GENMASK(14, 8)) +#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) +#define RXC_DQSISEL BIT(30) +#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16)) +#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2) + +/*TRGMII RXC control register*/ +#define TRGMII_TCK_CTRL 0x10340 +#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16)) +#define TXC_INV BIT(30) +#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2) +#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2)) + +/*TRGMII Interface mode register*/ +#define INTF_MODE 0x10390 +#define TRGMII_INTF_DIS BIT(0) +#define TRGMII_MODE BIT(1) +#define TRGMII_CENTRAL_ALIGNED BIT(2) +#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) +#define INTF_MODE_RGMII_10_100 0 + /* GPIO port control registers for GMAC 2*/ #define GPIO_OD33_CTRL8 0x4c0 #define GPIO_BIAS_CTRL 0xed0 @@ -323,6 +347,10 @@ #define SYSCFG0_GE_MASK 0x3 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) +/* ethernet subsystem clock register */ +#define ETHSYS_CLKCFG0 0x2c +#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) + /*ethernet reset control register*/ #define ETHSYS_RSTCTRL 0x34 #define RSTCTRL_FE BIT(6) @@ -389,6 +417,7 @@ enum mtk_clks_map { MTK_CLK_ESW, MTK_CLK_GP1, MTK_CLK_GP2, + MTK_CLK_TRGPLL, MTK_CLK_MAX }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 2/3] net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII 2016-09-20 7:59 ` sean.wang (?) @ 2016-09-21 4:50 ` David Miller -1 siblings, 0 replies; 19+ messages in thread From: David Miller @ 2016-09-21 4:50 UTC (permalink / raw) To: sean.wang; +Cc: john, nbd, netdev, linux-mediatek, keyhaede, objelf From: <sean.wang@mediatek.com> Date: Tue, 20 Sep 2016 15:59:19 +0800 > +/*TRGMII RXC control register*/ ... > +/*TRGMII RXC control register*/ ... > +/*TRGMII Interface mode register*/ Please put a space at the beginning and end of comment lines like this. Thanks. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 2016-09-20 7:59 ` sean.wang @ 2016-09-20 7:59 ` sean.wang -1 siblings, 0 replies; 19+ messages in thread From: sean.wang @ 2016-09-20 7:59 UTC (permalink / raw) To: john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf, Sean Wang From: Sean Wang <sean.wang@mediatek.com> Add the dts property for the capability if TRGMII supported on GAMC0 Signed-off-by: Sean Wang <sean.wang@mediatek.com> --- Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt index 6103e55..32f79d8 100644 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt @@ -31,7 +31,10 @@ Optional properties: Required properties: - compatible: Should be "mediatek,eth-mac" - reg: The number of the MAC -- phy-handle: see ethernet.txt file in the same directory. +- phy-handle: see ethernet.txt file in the same directory and + the additional phy-mode "tgrmii" is provided in order to connect + with the internal switch MT7530 which is only applicable when reg + is equal to 0. Example: -- 1.9.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 @ 2016-09-20 7:59 ` sean.wang 0 siblings, 0 replies; 19+ messages in thread From: sean.wang @ 2016-09-20 7:59 UTC (permalink / raw) To: john, davem; +Cc: nbd, netdev, linux-mediatek, keyhaede, objelf, Sean Wang From: Sean Wang <sean.wang@mediatek.com> Add the dts property for the capability if TRGMII supported on GAMC0 Signed-off-by: Sean Wang <sean.wang@mediatek.com> --- Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt index 6103e55..32f79d8 100644 --- a/Documentation/devicetree/bindings/net/mediatek-net.txt +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt @@ -31,7 +31,10 @@ Optional properties: Required properties: - compatible: Should be "mediatek,eth-mac" - reg: The number of the MAC -- phy-handle: see ethernet.txt file in the same directory. +- phy-handle: see ethernet.txt file in the same directory and + the additional phy-mode "tgrmii" is provided in order to connect + with the internal switch MT7530 which is only applicable when reg + is equal to 0. Example: -- 1.9.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 2016-09-20 7:59 ` sean.wang (?) @ 2016-09-20 19:37 ` Andrew Lunn -1 siblings, 0 replies; 19+ messages in thread From: Andrew Lunn @ 2016-09-20 19:37 UTC (permalink / raw) To: sean.wang; +Cc: john, davem, nbd, netdev, linux-mediatek, keyhaede, objelf On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang <sean.wang@mediatek.com> > > Add the dts property for the capability if TRGMII supported on GAMC0 > > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > --- > Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt > index 6103e55..32f79d8 100644 > --- a/Documentation/devicetree/bindings/net/mediatek-net.txt > +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt > @@ -31,7 +31,10 @@ Optional properties: > Required properties: > - compatible: Should be "mediatek,eth-mac" > - reg: The number of the MAC > -- phy-handle: see ethernet.txt file in the same directory. > +- phy-handle: see ethernet.txt file in the same directory and > + the additional phy-mode "tgrmii" is provided in order to connect > + with the internal switch MT7530 which is only applicable when reg > + is equal to 0. Humm. How is the switch connected? Is it on the MDIO bus? If it is on the mdio bus, the binding is going to look something like: eth: ethernet@1b100000 { compatible = "mediatek,mt7623-eth"; reg = <0 0x1b100000 0 0x20000>; clocks = <&topckgen CLK_TOP_ETHIF_SEL>, <ðsys CLK_ETHSYS_ESW>, <ðsys CLK_ETHSYS_GP2>, <ðsys CLK_ETHSYS_GP1>; clock-names = "ethif", "esw", "gp2", "gp1"; interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW GIC_SPI 199 IRQ_TYPE_LEVEL_LOW GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; resets = <ðsys MT2701_ETHSYS_ETH_RST>; reset-names = "eth"; mediatek,ethsys = <ðsys>; mediatek,pctl = <&syscfg_pctl_a>; #address-cells = <1>; #size-cells = <0>; gmac1: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; }; gmac2: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; }; mdio-bus { reg = <1>; #address-cells = <1>; #size-cells = <0>; switch0: switch0@0 { compatible = "marvell,mv88e6085"; #address-cells = <1>; #size-cells = <0>; reg = <0>; dsa,member = <0 0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; label = "lan0"; ... ... In this case the switch is an MDIO device, not an PHY. It will not have an phy-mode. It cannot have a phy mode, it is not a PHY. Or am i missing something here? Thanks Andrew ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 2016-09-20 7:59 ` sean.wang @ 2016-09-21 6:16 ` Sean Wang -1 siblings, 0 replies; 19+ messages in thread From: Sean Wang @ 2016-09-21 6:16 UTC (permalink / raw) To: andrew; +Cc: john, davem, nbd, netdev, linux-mediatek, keyhaede Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: >> From: Sean Wang <sean.wang@mediatek.com> >> >> Add the dts property for the capability if TRGMII supported on GAMC0 >> >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> >> --- >> Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt >> index 6103e55..32f79d8 100644 >> --- a/Documentation/devicetree/bindings/net/mediatek-net.txt >> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt >> @@ -31,7 +31,10 @@ Optional properties: >> Required properties: >> - compatible: Should be "mediatek,eth-mac" >> - reg: The number of the MAC >> -- phy-handle: see ethernet.txt file in the same directory. >> +- phy-handle: see ethernet.txt file in the same directory and >> + the additional phy-mode "tgrmii" is provided in order to connect >> + with the internal switch MT7530 which is only applicable when reg >> + is equal to 0. > >Humm. How is the switch connected? Is it on the MDIO bus? the switch is connected to MDIO bus >If it is on the mdio bus, the binding is going to look something like: > >eth: ethernet@1b100000 { > compatible = "mediatek,mt7623-eth"; > reg = <0 0x1b100000 0 0x20000>; > clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > <ðsys CLK_ETHSYS_ESW>, > <ðsys CLK_ETHSYS_GP2>, > <ðsys CLK_ETHSYS_GP1>; > clock-names = "ethif", "esw", "gp2", "gp1"; > interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW > GIC_SPI 199 IRQ_TYPE_LEVEL_LOW > GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > resets = <ðsys MT2701_ETHSYS_ETH_RST>; > reset-names = "eth"; > mediatek,ethsys = <ðsys>; > mediatek,pctl = <&syscfg_pctl_a>; > #address-cells = <1>; > #size-cells = <0>; > > gmac1: mac@0 { > compatible = "mediatek,eth-mac"; > reg = <0>; > }; > > gmac2: mac@1 { > compatible = "mediatek,eth-mac"; > reg = <1>; > }; > > mdio-bus { > reg = <1>; > #address-cells = <1>; > #size-cells = <0>; > > switch0: switch0@0 { > compatible = "marvell,mv88e6085"; > #address-cells = <1>; > #size-cells = <0>; > reg = <0>; > dsa,member = <0 0>; > > ports { > #address-cells = <1>; > #size-cells = <0>; > port@0 { > reg = <0>; > label = "lan0"; >... >... >In this case the switch is an MDIO device, not an PHY. It will not >have an phy-mode. It cannot have a phy mode, it is not a PHY. > >Or am i missing something here? > >Thanks > 1) The switch driver is not supported for DSA so far yet but DSA is good thing and I will try make it happen in the near future. And another question about DSA, that is if I use DSA for switch, how to know the relationship between MAC and DSA ? such like I could know relationship between MAC and PHY by phy-handle. The cause I ask is becasue I think it's good if the topology about MAC/PHYs/Switch is known just by dts files. 2) The phy-mode I mention is for fixed-link. For current MAC driver, it just uses fixed phy to adapt into the part of switch, so the device tree looks something like the below. ð { status = "okay"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-handle = <&phy5>; }; ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 @ 2016-09-21 6:16 ` Sean Wang 0 siblings, 0 replies; 19+ messages in thread From: Sean Wang @ 2016-09-21 6:16 UTC (permalink / raw) To: andrew; +Cc: john, davem, nbd, netdev, linux-mediatek, keyhaede Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: >> From: Sean Wang <sean.wang@mediatek.com> >> >> Add the dts property for the capability if TRGMII supported on GAMC0 >> >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> >> --- >> Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt >> index 6103e55..32f79d8 100644 >> --- a/Documentation/devicetree/bindings/net/mediatek-net.txt >> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt >> @@ -31,7 +31,10 @@ Optional properties: >> Required properties: >> - compatible: Should be "mediatek,eth-mac" >> - reg: The number of the MAC >> -- phy-handle: see ethernet.txt file in the same directory. >> +- phy-handle: see ethernet.txt file in the same directory and >> + the additional phy-mode "tgrmii" is provided in order to connect >> + with the internal switch MT7530 which is only applicable when reg >> + is equal to 0. > >Humm. How is the switch connected? Is it on the MDIO bus? the switch is connected to MDIO bus >If it is on the mdio bus, the binding is going to look something like: > >eth: ethernet@1b100000 { > compatible = "mediatek,mt7623-eth"; > reg = <0 0x1b100000 0 0x20000>; > clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > <ðsys CLK_ETHSYS_ESW>, > <ðsys CLK_ETHSYS_GP2>, > <ðsys CLK_ETHSYS_GP1>; > clock-names = "ethif", "esw", "gp2", "gp1"; > interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW > GIC_SPI 199 IRQ_TYPE_LEVEL_LOW > GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > resets = <ðsys MT2701_ETHSYS_ETH_RST>; > reset-names = "eth"; > mediatek,ethsys = <ðsys>; > mediatek,pctl = <&syscfg_pctl_a>; > #address-cells = <1>; > #size-cells = <0>; > > gmac1: mac@0 { > compatible = "mediatek,eth-mac"; > reg = <0>; > }; > > gmac2: mac@1 { > compatible = "mediatek,eth-mac"; > reg = <1>; > }; > > mdio-bus { > reg = <1>; > #address-cells = <1>; > #size-cells = <0>; > > switch0: switch0@0 { > compatible = "marvell,mv88e6085"; > #address-cells = <1>; > #size-cells = <0>; > reg = <0>; > dsa,member = <0 0>; > > ports { > #address-cells = <1>; > #size-cells = <0>; > port@0 { > reg = <0>; > label = "lan0"; >... >... >In this case the switch is an MDIO device, not an PHY. It will not >have an phy-mode. It cannot have a phy mode, it is not a PHY. > >Or am i missing something here? > >Thanks > 1) The switch driver is not supported for DSA so far yet but DSA is good thing and I will try make it happen in the near future. And another question about DSA, that is if I use DSA for switch, how to know the relationship between MAC and DSA ? such like I could know relationship between MAC and PHY by phy-handle. The cause I ask is becasue I think it's good if the topology about MAC/PHYs/Switch is known just by dts files. 2) The phy-mode I mention is for fixed-link. For current MAC driver, it just uses fixed phy to adapt into the part of switch, so the device tree looks something like the below. ð { status = "okay"; gmac0: mac@0 { compatible = "mediatek,eth-mac"; reg = <0>; phy-mode = "trgmii"; fixed-link { speed = <1000>; full-duplex; pause; }; }; gmac1: mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; phy-handle = <&phy5>; }; ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 2016-09-21 6:16 ` Sean Wang (?) @ 2016-09-21 14:17 ` Andrew Lunn 2016-09-21 15:37 ` Sean Wang -1 siblings, 1 reply; 19+ messages in thread From: Andrew Lunn @ 2016-09-21 14:17 UTC (permalink / raw) To: Sean Wang; +Cc: john, davem, nbd, netdev, linux-mediatek, keyhaede On Wed, Sep 21, 2016 at 02:16:30PM +0800, Sean Wang wrote: > Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: > >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: > >> From: Sean Wang <sean.wang@mediatek.com> > >> > >> Add the dts property for the capability if TRGMII supported on GAMC0 > >> > >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> > >> --- > >> Documentation/devicetree/bindings/net/mediatek-net.txt | 5 ++++- > >> 1 file changed, 4 insertions(+), 1 deletion(-) > >> > >> diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt > >> index 6103e55..32f79d8 100644 > >> --- a/Documentation/devicetree/bindings/net/mediatek-net.txt > >> +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt > >> @@ -31,7 +31,10 @@ Optional properties: > >> Required properties: > >> - compatible: Should be "mediatek,eth-mac" > >> - reg: The number of the MAC > >> -- phy-handle: see ethernet.txt file in the same directory. > >> +- phy-handle: see ethernet.txt file in the same directory and > >> + the additional phy-mode "tgrmii" is provided in order to connect > >> + with the internal switch MT7530 which is only applicable when reg > >> + is equal to 0. > > > >Humm. How is the switch connected? Is it on the MDIO bus? > > the switch is connected to MDIO bus > > >If it is on the mdio bus, the binding is going to look something like: > > > >eth: ethernet@1b100000 { > > compatible = "mediatek,mt7623-eth"; > > reg = <0 0x1b100000 0 0x20000>; > > clocks = <&topckgen CLK_TOP_ETHIF_SEL>, > > <ðsys CLK_ETHSYS_ESW>, > > <ðsys CLK_ETHSYS_GP2>, > > <ðsys CLK_ETHSYS_GP1>; > > clock-names = "ethif", "esw", "gp2", "gp1"; > > interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW > > GIC_SPI 199 IRQ_TYPE_LEVEL_LOW > > GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; > > power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; > > resets = <ðsys MT2701_ETHSYS_ETH_RST>; > > reset-names = "eth"; > > mediatek,ethsys = <ðsys>; > > mediatek,pctl = <&syscfg_pctl_a>; > > #address-cells = <1>; > > #size-cells = <0>; > > > > gmac1: mac@0 { > > compatible = "mediatek,eth-mac"; > > reg = <0>; > > }; > > > > gmac2: mac@1 { > > compatible = "mediatek,eth-mac"; > > reg = <1>; > > }; > > > > mdio-bus { > > reg = <1>; > > #address-cells = <1>; > > #size-cells = <0>; > > > > switch0: switch0@0 { > > compatible = "marvell,mv88e6085"; > > #address-cells = <1>; > > #size-cells = <0>; > > reg = <0>; > > dsa,member = <0 0>; > > > > ports { > > #address-cells = <1>; > > #size-cells = <0>; > > port@0 { > > reg = <0>; > > label = "lan0"; > >... > >... > >In this case the switch is an MDIO device, not an PHY. It will not > >have an phy-mode. It cannot have a phy mode, it is not a PHY. > > > >Or am i missing something here? > > > >Thanks > > > > 1) > > The switch driver is not supported for DSA so far yet > but DSA is good thing and I will try make it happen > in the near future. O.K. But if i understand correctly, the TRGMII is so you can use the switch. So it needs to work when you have DSA. > And another question about DSA, that is > if I use DSA for switch, how to know the relationship > between MAC and DSA ? such like I could know relationship > between MAC and PHY by phy-handle. It will look like what i stated above. But i missed the cpu node in the ports, which is what you are asking about. There will also be a node like: port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac1>; }; And this is how you couple the MAC to DSA. > The cause I ask is becasue I think it's good if the topology > about MAC/PHYs/Switch is known just by dts files. > > 2) > > The phy-mode I mention is for fixed-link. For current MAC driver, > it just uses fixed phy to adapt into the part of switch, so the > device tree looks something like the below. > > ð { > status = "okay"; > gmac0: mac@0 { > compatible = "mediatek,eth-mac"; > reg = <0>; > phy-mode = "trgmii"; > fixed-link { > speed = <1000>; > full-duplex; > pause; > }; > }; > > gmac1: mac@1 { > compatible = "mediatek,eth-mac"; > reg = <1>; > phy-handle = <&phy5>; > }; static int mtk_phy_connect(struct mtk_mac *mac) { struct mtk_eth *eth = mac->hw; struct device_node *np; u32 val; np = of_parse_phandle(mac->of_node, "phy-handle", 0); if (!np && of_phy_is_fixed_link(mac->of_node)) if (!of_phy_register_fixed_link(mac->of_node)) np = of_node_get(mac->of_node); ... ... mtk_phy_connect_node(eth, mac, np); So in the case of a fixed-phy, you do look in the MAC node, and when there is a phy-handle, you look in the PHY node. So this does work.... Andrew ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 2016-09-21 14:17 ` Andrew Lunn @ 2016-09-21 15:37 ` Sean Wang 0 siblings, 0 replies; 19+ messages in thread From: Sean Wang @ 2016-09-21 15:37 UTC (permalink / raw) To: andrew; +Cc: john, davem, nbd, netdev, linux-kernel, linux-mediatek, keyhaede Date: Wed, 21 Sep 2016 16:17:20 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >On Wed, Sep 21, 2016 at 02:16:30PM +0800, Sean Wang wrote: >> Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >> >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: >> >> From: Sean Wang <sean.wang@mediatek.com> >> >> >> >> Add the dts property for the capability if TRGMII supported on GAMC0 >> >> >> >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> .... deleted >> >In this case the switch is an MDIO device, not an PHY. It will not >> >have an phy-mode. It cannot have a phy mode, it is not a PHY. >> > >> >Or am i missing something here? >> > >> >Thanks >> > >> >> 1) >> >> The switch driver is not supported for DSA so far yet >> but DSA is good thing and I will try make it happen >> in the near future. > >O.K. But if i understand correctly, the TRGMII is so you can use the >switch. So it needs to work when you have DSA. > yes, you are right. TRGMII for now is dedicated for switch and furthermore it needs doing calibration between the host and the switch before it works, that I expect to put the logic of calibration into setup callback of DSA driver. >> And another question about DSA, that is >> if I use DSA for switch, how to know the relationship >> between MAC and DSA ? such like I could know relationship >> between MAC and PHY by phy-handle. > >It will look like what i stated above. But i missed the cpu node in >the ports, which is what you are asking about. There will also be a >node like: > > port@6 { > reg = <6>; > label = "cpu"; > ethernet = <&gmac1>; > }; > >And this is how you couple the MAC to DSA. thanks, it is answerig my question : i can get the relationship from the node of cpu port pointing to what MAC it runs for. >> The cause I ask is becasue I think it's good if the topology >> about MAC/PHYs/Switch is known just by dts files. >> >> 2) >> >> The phy-mode I mention is for fixed-link. For current MAC driver, >> it just uses fixed phy to adapt into the part of switch, so the >> device tree looks something like the below. >> >> ð { >> status = "okay"; >> gmac0: mac@0 { >> compatible = "mediatek,eth-mac"; >> reg = <0>; >> phy-mode = "trgmii"; >> fixed-link { >> speed = <1000>; >> full-duplex; >> pause; >> }; >> }; >> >> gmac1: mac@1 { >> compatible = "mediatek,eth-mac"; >> reg = <1>; >> phy-handle = <&phy5>; >> }; > > >static int mtk_phy_connect(struct mtk_mac *mac) >{ > struct mtk_eth *eth = mac->hw; > struct device_node *np; > u32 val; > > np = of_parse_phandle(mac->of_node, "phy-handle", 0); > if (!np && of_phy_is_fixed_link(mac->of_node)) > if (!of_phy_register_fixed_link(mac->of_node)) > np = of_node_get(mac->of_node); > ... > ... > mtk_phy_connect_node(eth, mac, np); > > >So in the case of a fixed-phy, you do look in the MAC node, and when >there is a phy-handle, you look in the PHY node. > >So this does work.... yes , it is all > > Andrew ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 @ 2016-09-21 15:37 ` Sean Wang 0 siblings, 0 replies; 19+ messages in thread From: Sean Wang @ 2016-09-21 15:37 UTC (permalink / raw) To: andrew; +Cc: john, davem, nbd, netdev, linux-kernel, linux-mediatek, keyhaede Date: Wed, 21 Sep 2016 16:17:20 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >On Wed, Sep 21, 2016 at 02:16:30PM +0800, Sean Wang wrote: >> Date: Tue, 20 Sep 2016 21:37:58 +0200, Andrew Lunn <andrew@lunn.ch> wrote: >> >On Tue, Sep 20, 2016 at 03:59:20PM +0800, sean.wang@mediatek.com wrote: >> >> From: Sean Wang <sean.wang@mediatek.com> >> >> >> >> Add the dts property for the capability if TRGMII supported on GAMC0 >> >> >> >> Signed-off-by: Sean Wang <sean.wang@mediatek.com> .... deleted >> >In this case the switch is an MDIO device, not an PHY. It will not >> >have an phy-mode. It cannot have a phy mode, it is not a PHY. >> > >> >Or am i missing something here? >> > >> >Thanks >> > >> >> 1) >> >> The switch driver is not supported for DSA so far yet >> but DSA is good thing and I will try make it happen >> in the near future. > >O.K. But if i understand correctly, the TRGMII is so you can use the >switch. So it needs to work when you have DSA. > yes, you are right. TRGMII for now is dedicated for switch and furthermore it needs doing calibration between the host and the switch before it works, that I expect to put the logic of calibration into setup callback of DSA driver. >> And another question about DSA, that is >> if I use DSA for switch, how to know the relationship >> between MAC and DSA ? such like I could know relationship >> between MAC and PHY by phy-handle. > >It will look like what i stated above. But i missed the cpu node in >the ports, which is what you are asking about. There will also be a >node like: > > port@6 { > reg = <6>; > label = "cpu"; > ethernet = <&gmac1>; > }; > >And this is how you couple the MAC to DSA. thanks, it is answerig my question : i can get the relationship from the node of cpu port pointing to what MAC it runs for. >> The cause I ask is becasue I think it's good if the topology >> about MAC/PHYs/Switch is known just by dts files. >> >> 2) >> >> The phy-mode I mention is for fixed-link. For current MAC driver, >> it just uses fixed phy to adapt into the part of switch, so the >> device tree looks something like the below. >> >> ð { >> status = "okay"; >> gmac0: mac@0 { >> compatible = "mediatek,eth-mac"; >> reg = <0>; >> phy-mode = "trgmii"; >> fixed-link { >> speed = <1000>; >> full-duplex; >> pause; >> }; >> }; >> >> gmac1: mac@1 { >> compatible = "mediatek,eth-mac"; >> reg = <1>; >> phy-handle = <&phy5>; >> }; > > >static int mtk_phy_connect(struct mtk_mac *mac) >{ > struct mtk_eth *eth = mac->hw; > struct device_node *np; > u32 val; > > np = of_parse_phandle(mac->of_node, "phy-handle", 0); > if (!np && of_phy_is_fixed_link(mac->of_node)) > if (!of_phy_register_fixed_link(mac->of_node)) > np = of_node_get(mac->of_node); > ... > ... > mtk_phy_connect_node(eth, mac, np); > > >So in the case of a fixed-phy, you do look in the MAC node, and when >there is a phy-handle, you look in the PHY node. > >So this does work.... yes , it is all > > Andrew ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2016-09-21 16:59 UTC | newest] Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-09-20 7:59 [PATCH net-next 0/3] add support for RGMII on GMAC0 through TRGMII hardware module sean.wang 2016-09-20 7:59 ` sean.wang [not found] ` <1474358360-29901-1-git-send-email-sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> 2016-09-20 7:59 ` [PATCH net-next 1/3] net: ethernet: mediatek: add extension of phy-mode for TRGMII sean.wang-NuS5LvNUpcJWk0Htik3J/w 2016-09-20 7:59 ` sean.wang-NuS5LvNUpcJWk0Htik3J/w 2016-09-20 21:23 ` Florian Fainelli [not found] ` <064d43fb-2942-efd2-6dc7-09f47a256691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-09-21 7:33 ` Sean Wang 2016-09-21 7:33 ` Sean Wang 2016-09-21 16:59 ` Florian Fainelli 2016-09-20 7:59 ` [PATCH net-next 2/3] net: ethernet: mediatek: add support for GMAC0 connecting with external PHY through TRGMII sean.wang 2016-09-20 7:59 ` sean.wang 2016-09-21 4:50 ` David Miller 2016-09-20 7:59 ` [PATCH net-next 3/3] net: ethernet: mediatek: add the dts property to set if TRGMII supported on GMAC0 sean.wang 2016-09-20 7:59 ` sean.wang 2016-09-20 19:37 ` Andrew Lunn 2016-09-21 6:16 ` Sean Wang 2016-09-21 6:16 ` Sean Wang 2016-09-21 14:17 ` Andrew Lunn 2016-09-21 15:37 ` Sean Wang 2016-09-21 15:37 ` Sean Wang
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