[Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I

[Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I

[Jose Ricardo Ziviani]

v2:
 - implements all fixes and suggestions

This serie contains 4 new instructions for POWER9 ISA3.0

 bcdcfn.: Decimal Convert From National
 bcdctn.: Decimal Convert To National
 bcdcfz.: Decimal Convert From Zoned
 bcdctz.: Decimal Convert to Zoned

Jose Ricardo Ziviani (4):
  target-ppc: Implement bcdcfn. instruction
  target-ppc: Implement bcdctn. instruction
  target-ppc: Implement bcdcfz. instruction
  target-ppc: Implement bcdctz. instruction

 target-ppc/helper.h                 |   4 +
 target-ppc/int_helper.c             | 200 ++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c | 103 +++++++++++++++++++
 target-ppc/translate/vmx-ops.inc.c  |   4 +-
 4 files changed, 309 insertions(+), 2 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH v2 1/4] target-ppc: Implement bcdcfn. instruction

[Jose Ricardo Ziviani]

bcdcfn. converts from National numeric format to BCD. National format
uses a byte to represent a digit where the most significant nibble is
always 0x3 and the least sign. nibbles is the digit itself.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  1 +
 target-ppc/int_helper.c             | 54 ++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c | 75 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-ops.inc.c  |  4 +-
 4 files changed, 132 insertions(+), 2 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3916b2e..3b23eed 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -371,6 +371,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
 
 DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
+DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index dca4798..9d620a6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2429,6 +2429,8 @@ void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
 #define BCD_NEG_PREF    0xD
 #define BCD_NEG_ALT     0xB
 #define BCD_PLUS_ALT_2  0xE
+#define NATIONAL_PLUS   0x2B
+#define NATIONAL_NEG    0x2D
 
 #if defined(HOST_WORDS_BIGENDIAN)
 #define BCD_DIG_BYTE(n) (15 - (n/2))
@@ -2495,6 +2497,15 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n)
     }
 }
 
+static uint8_t get_national_digit(ppc_avr_t *reg, int n)
+{
+#if defined(HOST_WORDS_BIGENDIAN)
+    return reg->u16[8 - n];
+#else
+    return reg->u16[n];
+#endif
+}
+
 static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
 {
     int i;
@@ -2625,6 +2636,49 @@ uint32_t helper_bcdsub(ppc_avr_t *r,  ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
     return helper_bcdadd(r, a, &bcopy, ps);
 }
 
+uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+    int i;
+    int neq_flag = 0;
+    int cr = 0;
+    int national = 0;
+    ppc_avr_t ret = { .u64 = { 0, 0 } };
+    uint16_t sgnb = get_national_digit(b, 0);
+    int invalid = (sgnb != NATIONAL_PLUS && sgnb != NATIONAL_NEG);
+
+    for (i = 1; i < 8; i++) {
+        national = get_national_digit(b, i);
+
+        neq_flag += (national != 0x30);
+        if (unlikely(national < 0x30 || national > 0x39)) {
+            invalid = 1;
+            break;
+        }
+
+        bcd_put_digit(&ret, national & 0xf, i);
+    }
+
+    if (sgnb == NATIONAL_PLUS) {
+        bcd_put_digit(&ret, (ps == 0) ? BCD_PLUS_PREF_1 : BCD_PLUS_PREF_2, 0);
+    } else {
+        bcd_put_digit(&ret, BCD_NEG_PREF, 0);
+    }
+
+    if (neq_flag) {
+        cr = (sgnb == NATIONAL_PLUS) ? 1 << CRF_GT : 1 << CRF_LT;
+    } else {
+        cr = 1 << CRF_EQ;
+    }
+
+    if (unlikely(invalid)) {
+        cr = 1 << CRF_SO;
+    }
+
+    *r = ret;
+
+    return cr;
+}
+
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index fc612d9..06d28f2 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -945,8 +945,81 @@ static void gen_##op(DisasContext *ctx)             \
     tcg_temp_free_i32(ps);                          \
 }
 
+#define GEN_BCD2(op)                                \
+static void gen_##op(DisasContext *ctx)             \
+{                                                   \
+    TCGv_ptr rd, rb;                                \
+    TCGv_i32 ps;                                    \
+                                                    \
+    if (unlikely(!ctx->altivec_enabled)) {          \
+        gen_exception(ctx, POWERPC_EXCP_VPU);       \
+        return;                                     \
+    }                                               \
+                                                    \
+    rb = gen_avr_ptr(rB(ctx->opcode));              \
+    rd = gen_avr_ptr(rD(ctx->opcode));              \
+                                                    \
+    ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+                                                    \
+    gen_helper_##op(cpu_crf[6], rd, rb, ps);        \
+                                                    \
+    tcg_temp_free_ptr(rb);                          \
+    tcg_temp_free_ptr(rd);                          \
+    tcg_temp_free_i32(ps);                          \
+}
+
 GEN_BCD(bcdadd)
 GEN_BCD(bcdsub)
+GEN_BCD2(bcdcfn)
+
+static void gen_xpnd04_1(DisasContext *ctx)
+{
+    switch (opc4(ctx->opcode)) {
+    case 0:
+        break; /* bcdctsq. */
+    case 2:
+        break; /* bcdcfsq. */
+    case 4:
+        break; /* bcdctz. */
+    case 5:
+        break; /* bcdctn. */
+    case 6:
+        break; /* bcdcfz. */
+    case 7:
+        gen_bcdcfn(ctx);
+        break;
+    case 31:
+        break; /* bcdsetsgn. */
+    default:
+        break;
+    }
+}
+
+static void gen_xpnd04_2(DisasContext *ctx)
+{
+    switch (opc4(ctx->opcode)) {
+    case 0:
+        break; /* bcdctsq. */
+    case 2:
+        break; /* bcdcfsq. */
+    case 4:
+        break; /* bcdctz. */
+    case 6:
+        break; /* bcdcfz. */
+    case 7:
+        gen_bcdcfn(ctx);
+        break;
+    case 31:
+        break; /* bcdsetsgn. */
+    default:
+        break;
+    }
+}
+
+GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
+                xpnd04_1, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
+                xpnd04_2, PPC_NONE, PPC2_ISA300)
 
 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
                 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
@@ -1023,3 +1096,5 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
 #undef GEN_VXFORM_NOA
 #undef GEN_VXFORM_UIMM
 #undef GEN_VAFORM_PAIRED
+
+#undef GEN_BCD2
diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
index cc7ed7e..637b43c 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -122,7 +122,7 @@ GEN_VXFORM_300(vslv, 2, 29),
 GEN_VXFORM(vslo, 6, 16),
 GEN_VXFORM(vsro, 6, 17),
 GEN_VXFORM(vaddcuw, 0, 6),
-GEN_VXFORM(vsubcuw, 0, 22),
+GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM(vadduws, 0, 10),
@@ -134,7 +134,7 @@ GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM(vsubuws, 0, 26),
 GEN_VXFORM(vsubsbs, 0, 28),
 GEN_VXFORM(vsubshs, 0, 29),
-GEN_VXFORM(vsubsws, 0, 30),
+GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
 GEN_VXFORM_207(vadduqm, 0, 4),
 GEN_VXFORM_207(vaddcuq, 0, 5),
 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-- 
2.7.4

[Qemu-devel] [PATCH v2 2/4] target-ppc: Implement bcdctn. instruction

[Jose Ricardo Ziviani]

bcdctn. converts from BCD to National numeric format. National format
uses a byte to represent a digit where the most significant nibble is
always 0x3 and the least sign. nibbles is the digit itself.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  1 +
 target-ppc/int_helper.c             | 48 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c | 24 ++++++++++++++++++-
 3 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 3b23eed..53d1e7a 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -372,6 +372,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
 DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
 DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
+DEF_HELPER_2(bcdctn, i32, avr, avr)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 9d620a6..a58ed30 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2506,6 +2506,15 @@ static uint8_t get_national_digit(ppc_avr_t *reg, int n)
 #endif
 }
 
+static void set_national_digit(ppc_avr_t *reg, uint8_t val, int n)
+{
+#if defined(HOST_WORDS_BIGENDIAN)
+    reg->u16[8 - n] = val;
+#else
+    reg->u16[n] = val;
+#endif
+}
+
 static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
 {
     int i;
@@ -2679,6 +2688,45 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
     return cr;
 }
 
+uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b)
+{
+    int i;
+    int cr = 0;
+    int sgnb = bcd_get_sgn(b);
+    int invalid = (sgnb == 0);
+    ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+    int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0);
+    int ox_flag = (b->u64[HI_IDX] != 0) || ((b->u64[LO_IDX] >> 32) != 0);
+
+    for (i = 1; i < 8; i++) {
+        set_national_digit(&ret, 0x30 + bcd_get_digit(b, i, &invalid), i);
+
+        if (unlikely(invalid)) {
+            break;
+        }
+    }
+    set_national_digit(&ret, (sgnb == -1) ? NATIONAL_NEG : NATIONAL_PLUS, 0);
+
+    if (!eq_flag) {
+        cr = (sgnb == -1) ? 1 << CRF_LT : 1 << CRF_GT;
+    } else {
+        cr = 1 << CRF_EQ;
+    }
+
+    if (ox_flag) {
+        cr |= 1 << CRF_SO;
+    }
+
+    if (unlikely(invalid)) {
+        cr = 1 << CRF_SO;
+    }
+
+    *r = ret;
+
+    return cr;
+}
+
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 06d28f2..e37fc11 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -968,9 +968,29 @@ static void gen_##op(DisasContext *ctx)             \
     tcg_temp_free_i32(ps);                          \
 }
 
+#define GEN_BCD3(op)                                \
+static void gen_##op(DisasContext *ctx)             \
+{                                                   \
+    TCGv_ptr rb, rd;                                \
+                                                    \
+    if (unlikely(!ctx->altivec_enabled)) {          \
+        gen_exception(ctx, POWERPC_EXCP_VPU);       \
+        return;                                     \
+    }                                               \
+                                                    \
+    rb = gen_avr_ptr(rB(ctx->opcode));              \
+    rd = gen_avr_ptr(rD(ctx->opcode));              \
+                                                    \
+    gen_helper_##op(cpu_crf[6], rd, rb);            \
+                                                    \
+    tcg_temp_free_ptr(rb);                          \
+    tcg_temp_free_ptr(rd);                          \
+}
+
 GEN_BCD(bcdadd)
 GEN_BCD(bcdsub)
 GEN_BCD2(bcdcfn)
+GEN_BCD3(bcdctn)
 
 static void gen_xpnd04_1(DisasContext *ctx)
 {
@@ -982,7 +1002,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
     case 4:
         break; /* bcdctz. */
     case 5:
-        break; /* bcdctn. */
+        gen_bcdctn(ctx);
+        break;
     case 6:
         break; /* bcdcfz. */
     case 7:
@@ -1098,3 +1119,4 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
 #undef GEN_VAFORM_PAIRED
 
 #undef GEN_BCD2
+#undef GEN_BCD3
-- 
2.7.4

[Qemu-devel] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction

[Jose Ricardo Ziviani]

bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses
a byte to represent a digit where the most significant nibble is 0x3
or 0xf, depending on the preferred signal.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  1 +
 target-ppc/int_helper.c             | 47 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  7 ++++--
 3 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 53d1e7a..a9ac28b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -373,6 +373,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
 DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
 DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
 DEF_HELPER_2(bcdctn, i32, avr, avr)
+DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index a58ed30..19e6a3a 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2727,6 +2727,53 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b)
     return cr;
 }
 
+uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+    int i;
+    int j;
+    int cr = 0;
+    int invalid = 0;
+    int neq_flag = 0;
+    int zone_digit = 0;
+    int zone_lead = (ps) ? 0xF : 0x3;
+    int digit = 0;
+    ppc_avr_t ret = { .u64 = { 0, 0 } };
+    int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4;
+
+    if (unlikely((sgnb < 0xA) && ps)) {
+        invalid = 1;
+    }
+
+    for (i = 0, j = 1; i < 31; i += 2, j++) {
+        zone_digit = (i) ? b->u8[BCD_DIG_BYTE(i)] >> 4 : zone_lead;
+        digit = b->u8[BCD_DIG_BYTE(i)] & 0xF;
+
+        if (unlikely(zone_digit != zone_lead || digit > 0x9)) {
+            invalid = 1;
+            break;
+        }
+
+        neq_flag += (digit != 0);
+        bcd_put_digit(&ret, digit, j);
+    }
+
+    if ((ps && (sgnb == 0xB || sgnb == 0xD)) ||
+            (!ps && (sgnb & 0x4))) {
+        bcd_put_digit(&ret, BCD_NEG_PREF, 0);
+        cr = (neq_flag) ? 1 << CRF_LT : 1 << CRF_EQ;
+    } else {
+        bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0);
+        cr = (neq_flag) ? 1 << CRF_GT : 1 << CRF_EQ;
+    }
+
+    if (unlikely(invalid)) {
+        cr = 1 << CRF_SO;
+    }
+
+    *r = ret;
+
+    return cr;
+}
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index e37fc11..6e54437 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -991,6 +991,7 @@ GEN_BCD(bcdadd)
 GEN_BCD(bcdsub)
 GEN_BCD2(bcdcfn)
 GEN_BCD3(bcdctn)
+GEN_BCD2(bcdcfz)
 
 static void gen_xpnd04_1(DisasContext *ctx)
 {
@@ -1005,7 +1006,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
         gen_bcdctn(ctx);
         break;
     case 6:
-        break; /* bcdcfz. */
+        gen_bcdcfz(ctx);
+        break;
     case 7:
         gen_bcdcfn(ctx);
         break;
@@ -1026,7 +1028,8 @@ static void gen_xpnd04_2(DisasContext *ctx)
     case 4:
         break; /* bcdctz. */
     case 6:
-        break; /* bcdcfz. */
+        gen_bcdcfz(ctx);
+        break;
     case 7:
         gen_bcdcfn(ctx);
         break;
-- 
2.7.4

[Qemu-devel] [PATCH v2 4/4] target-ppc: Implement bcdctz. instruction

[Jose Ricardo Ziviani]

bcdctz. converts from BCD to Zoned numeric format. Zoned format uses
a byte to represent a digit where the most significant nibble is 0x3
or 0xf, depending on the preferred signal.

Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
 target-ppc/helper.h                 |  1 +
 target-ppc/int_helper.c             | 51 +++++++++++++++++++++++++++++++++++++
 target-ppc/translate/vmx-impl.inc.c |  7 +++--
 3 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a9ac28b..489a405 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -374,6 +374,7 @@ DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
 DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
 DEF_HELPER_2(bcdctn, i32, avr, avr)
 DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
+DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
 
 DEF_HELPER_2(xsadddp, void, env, i32)
 DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 19e6a3a..518824e 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2774,6 +2774,57 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
 
     return cr;
 }
+
+uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+    int i;
+    int j;
+    int cr = 0;
+    uint8_t digit = 0;
+    int sgnb = bcd_get_sgn(b);
+    int zone_lead = (ps) ? 0xF0 : 0x30;
+    int invalid = (sgnb == 0);
+    ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+    int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0);
+    int ox_flag = ((b->u64[HI_IDX] >> 4) != 0);
+
+    for (i = 0, j = 1; i < 32; i += 2, j++) {
+        digit = bcd_get_digit(b, j, &invalid);
+
+        if (unlikely(invalid)) {
+            break;
+        }
+
+        ret.u8[BCD_DIG_BYTE(i)] = zone_lead + digit;
+    }
+
+    if (ps) {
+        bcd_put_digit(&ret, (sgnb == 1) ? 0xC : 0xD, 1);
+    } else {
+        bcd_put_digit(&ret, (sgnb == 1) ? 0x3 : 0x7, 1);
+    }
+    bcd_put_digit(&ret, b->u8[BCD_DIG_BYTE(0)] >> 4, 0);
+
+    if (!eq_flag) {
+        cr = (sgnb == 1) ? 1 << CRF_GT : 1 << CRF_LT;
+    } else {
+        cr = 1 << CRF_EQ;
+    }
+
+    if (ox_flag) {
+        cr |= 1 << CRF_SO;
+    }
+
+    if (unlikely(invalid)) {
+        cr = 1 << CRF_SO;
+    }
+
+    *r = ret;
+
+    return cr;
+}
+
 void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
 {
     int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
index 6e54437..a868740 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -992,6 +992,7 @@ GEN_BCD(bcdsub)
 GEN_BCD2(bcdcfn)
 GEN_BCD3(bcdctn)
 GEN_BCD2(bcdcfz)
+GEN_BCD2(bcdctz)
 
 static void gen_xpnd04_1(DisasContext *ctx)
 {
@@ -1001,7 +1002,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
     case 2:
         break; /* bcdcfsq. */
     case 4:
-        break; /* bcdctz. */
+        gen_bcdctz(ctx);
+        break;
     case 5:
         gen_bcdctn(ctx);
         break;
@@ -1026,7 +1028,8 @@ static void gen_xpnd04_2(DisasContext *ctx)
     case 2:
         break; /* bcdcfsq. */
     case 4:
-        break; /* bcdctz. */
+        gen_bcdctz(ctx);
+        break;
     case 6:
         gen_bcdcfz(ctx);
         break;
-- 
2.7.4

Re: [Qemu-devel] [PATCH v2 1/4] target-ppc: Implement bcdcfn. instruction

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 8555 bytes --]

On Fri, Oct 28, 2016 at 03:18:01PM -0200, Jose Ricardo Ziviani wrote:
> bcdcfn. converts from National numeric format to BCD. National format
> uses a byte to represent a digit where the most significant nibble is
> always 0x3 and the least sign. nibbles is the digit itself.
> 
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h                 |  1 +
>  target-ppc/int_helper.c             | 54 ++++++++++++++++++++++++++
>  target-ppc/translate/vmx-impl.inc.c | 75 +++++++++++++++++++++++++++++++++++++
>  target-ppc/translate/vmx-ops.inc.c  |  4 +-
>  4 files changed, 132 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 3916b2e..3b23eed 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -371,6 +371,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
>  
>  DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
>  DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
> +DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
>  
>  DEF_HELPER_2(xsadddp, void, env, i32)
>  DEF_HELPER_2(xssubdp, void, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index dca4798..9d620a6 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2429,6 +2429,8 @@ void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>  #define BCD_NEG_PREF    0xD
>  #define BCD_NEG_ALT     0xB
>  #define BCD_PLUS_ALT_2  0xE
> +#define NATIONAL_PLUS   0x2B
> +#define NATIONAL_NEG    0x2D
>  
>  #if defined(HOST_WORDS_BIGENDIAN)
>  #define BCD_DIG_BYTE(n) (15 - (n/2))
> @@ -2495,6 +2497,15 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n)
>      }
>  }
>  
> +static uint8_t get_national_digit(ppc_avr_t *reg, int n)
> +{
> +#if defined(HOST_WORDS_BIGENDIAN)
> +    return reg->u16[8 - n];
> +#else
> +    return reg->u16[n];
> +#endif
> +}

You're still truncating each digit, and hence not detecting bad
encodings in the upper byte of each digit.  Better to just return a
uint16_t and check the whole thing against the range 0x30..0x39 in the
caller.

> +
>  static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
>  {
>      int i;
> @@ -2625,6 +2636,49 @@ uint32_t helper_bcdsub(ppc_avr_t *r,  ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
>      return helper_bcdadd(r, a, &bcopy, ps);
>  }
>  
> +uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
> +{
> +    int i;
> +    int neq_flag = 0;
> +    int cr = 0;
> +    int national = 0;
> +    ppc_avr_t ret = { .u64 = { 0, 0 } };
> +    uint16_t sgnb = get_national_digit(b, 0);
> +    int invalid = (sgnb != NATIONAL_PLUS && sgnb != NATIONAL_NEG);
> +
> +    for (i = 1; i < 8; i++) {
> +        national = get_national_digit(b, i);
> +
> +        neq_flag += (national != 0x30);
> +        if (unlikely(national < 0x30 || national > 0x39)) {
> +            invalid = 1;
> +            break;
> +        }
> +
> +        bcd_put_digit(&ret, national & 0xf, i);
> +    }
> +
> +    if (sgnb == NATIONAL_PLUS) {
> +        bcd_put_digit(&ret, (ps == 0) ? BCD_PLUS_PREF_1 : BCD_PLUS_PREF_2, 0);
> +    } else {
> +        bcd_put_digit(&ret, BCD_NEG_PREF, 0);
> +    }
> +
> +    if (neq_flag) {
> +        cr = (sgnb == NATIONAL_PLUS) ? 1 << CRF_GT : 1 << CRF_LT;
> +    } else {
> +        cr = 1 << CRF_EQ;
> +    }
> +
> +    if (unlikely(invalid)) {
> +        cr = 1 << CRF_SO;
> +    }
> +
> +    *r = ret;
> +
> +    return cr;
> +}
> +
>  void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
>  {
>      int i;
> diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
> index fc612d9..06d28f2 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -945,8 +945,81 @@ static void gen_##op(DisasContext *ctx)             \
>      tcg_temp_free_i32(ps);                          \
>  }
>  
> +#define GEN_BCD2(op)                                \
> +static void gen_##op(DisasContext *ctx)             \
> +{                                                   \
> +    TCGv_ptr rd, rb;                                \
> +    TCGv_i32 ps;                                    \
> +                                                    \
> +    if (unlikely(!ctx->altivec_enabled)) {          \
> +        gen_exception(ctx, POWERPC_EXCP_VPU);       \
> +        return;                                     \
> +    }                                               \
> +                                                    \
> +    rb = gen_avr_ptr(rB(ctx->opcode));              \
> +    rd = gen_avr_ptr(rD(ctx->opcode));              \
> +                                                    \
> +    ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
> +                                                    \
> +    gen_helper_##op(cpu_crf[6], rd, rb, ps);        \
> +                                                    \
> +    tcg_temp_free_ptr(rb);                          \
> +    tcg_temp_free_ptr(rd);                          \
> +    tcg_temp_free_i32(ps);                          \
> +}
> +
>  GEN_BCD(bcdadd)
>  GEN_BCD(bcdsub)
> +GEN_BCD2(bcdcfn)
> +
> +static void gen_xpnd04_1(DisasContext *ctx)
> +{
> +    switch (opc4(ctx->opcode)) {
> +    case 0:
> +        break; /* bcdctsq. */
> +    case 2:
> +        break; /* bcdcfsq. */
> +    case 4:
> +        break; /* bcdctz. */
> +    case 5:
> +        break; /* bcdctn. */
> +    case 6:
> +        break; /* bcdcfz. */
> +    case 7:
> +        gen_bcdcfn(ctx);
> +        break;
> +    case 31:
> +        break; /* bcdsetsgn. */
> +    default:
> +        break;
> +    }
> +}
> +
> +static void gen_xpnd04_2(DisasContext *ctx)
> +{
> +    switch (opc4(ctx->opcode)) {
> +    case 0:
> +        break; /* bcdctsq. */
> +    case 2:
> +        break; /* bcdcfsq. */
> +    case 4:
> +        break; /* bcdctz. */
> +    case 6:
> +        break; /* bcdcfz. */
> +    case 7:
> +        gen_bcdcfn(ctx);
> +        break;
> +    case 31:
> +        break; /* bcdsetsgn. */
> +    default:
> +        break;

So, I read your explanation in the other thread, and I agree that
there isn't an obvious simpler way of handling this.  Basically you
need to do the split based on Rc (GEN_VCFORM_DUAL) at the opc3 level,
because that's what vsubsws and vsubcuw need, but then you need to
multiplex based on opc4.

However, I think your default case doesn't really work here.  IIUC
this will treat one of the opc4 values you haven't explicitly handled
as a no-op.  Surely it should generate an invalid instruction
exception instead.


> +    }
> +}
> +
> +GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
> +                xpnd04_1, PPC_NONE, PPC2_ISA300)
> +GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
> +                xpnd04_2, PPC_NONE, PPC2_ISA300)
>  
>  GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
>                  bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
> @@ -1023,3 +1096,5 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
>  #undef GEN_VXFORM_NOA
>  #undef GEN_VXFORM_UIMM
>  #undef GEN_VAFORM_PAIRED
> +
> +#undef GEN_BCD2
> diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c
> index cc7ed7e..637b43c 100644
> --- a/target-ppc/translate/vmx-ops.inc.c
> +++ b/target-ppc/translate/vmx-ops.inc.c
> @@ -122,7 +122,7 @@ GEN_VXFORM_300(vslv, 2, 29),
>  GEN_VXFORM(vslo, 6, 16),
>  GEN_VXFORM(vsro, 6, 17),
>  GEN_VXFORM(vaddcuw, 0, 6),
> -GEN_VXFORM(vsubcuw, 0, 22),
> +GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
>  GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
>  GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
>  GEN_VXFORM(vadduws, 0, 10),
> @@ -134,7 +134,7 @@ GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
>  GEN_VXFORM(vsubuws, 0, 26),
>  GEN_VXFORM(vsubsbs, 0, 28),
>  GEN_VXFORM(vsubshs, 0, 29),
> -GEN_VXFORM(vsubsws, 0, 30),
> +GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
>  GEN_VXFORM_207(vadduqm, 0, 4),
>  GEN_VXFORM_207(vaddcuq, 0, 5),
>  GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 2/4] target-ppc: Implement bcdctn. instruction

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 5117 bytes --]

On Fri, Oct 28, 2016 at 03:18:02PM -0200, Jose Ricardo Ziviani wrote:
> bcdctn. converts from BCD to National numeric format. National format
> uses a byte to represent a digit where the most significant nibble is
> always 0x3 and the least sign. nibbles is the digit itself.
> 
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h                 |  1 +
>  target-ppc/int_helper.c             | 48 +++++++++++++++++++++++++++++++++++++
>  target-ppc/translate/vmx-impl.inc.c | 24 ++++++++++++++++++-
>  3 files changed, 72 insertions(+), 1 deletion(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 3b23eed..53d1e7a 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -372,6 +372,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
>  DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
>  DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
>  DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
> +DEF_HELPER_2(bcdctn, i32, avr, avr)
>  
>  DEF_HELPER_2(xsadddp, void, env, i32)
>  DEF_HELPER_2(xssubdp, void, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 9d620a6..a58ed30 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2506,6 +2506,15 @@ static uint8_t get_national_digit(ppc_avr_t *reg, int n)
>  #endif
>  }
>  
> +static void set_national_digit(ppc_avr_t *reg, uint8_t val, int n)
> +{
> +#if defined(HOST_WORDS_BIGENDIAN)
> +    reg->u16[8 - n] = val;
> +#else
> +    reg->u16[n] = val;
> +#endif
> +}
> +
>  static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
>  {
>      int i;
> @@ -2679,6 +2688,45 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
>      return cr;
>  }
>  
> +uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b)
> +{
> +    int i;
> +    int cr = 0;
> +    int sgnb = bcd_get_sgn(b);
> +    int invalid = (sgnb == 0);
> +    ppc_avr_t ret = { .u64 = { 0, 0 } };
> +
> +    int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0);
> +    int ox_flag = (b->u64[HI_IDX] != 0) || ((b->u64[LO_IDX] >> 32) != 0);
> +
> +    for (i = 1; i < 8; i++) {
> +        set_national_digit(&ret, 0x30 + bcd_get_digit(b, i, &invalid), i);
> +
> +        if (unlikely(invalid)) {
> +            break;
> +        }
> +    }
> +    set_national_digit(&ret, (sgnb == -1) ? NATIONAL_NEG : NATIONAL_PLUS, 0);
> +
> +    if (!eq_flag) {
> +        cr = (sgnb == -1) ? 1 << CRF_LT : 1 << CRF_GT;
> +    } else {
> +        cr = 1 << CRF_EQ;
> +    }
> +
> +    if (ox_flag) {
> +        cr |= 1 << CRF_SO;
> +    }
> +
> +    if (unlikely(invalid)) {
> +        cr = 1 << CRF_SO;
> +    }
> +
> +    *r = ret;
> +
> +    return cr;
> +}
> +
>  void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
>  {
>      int i;
> diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
> index 06d28f2..e37fc11 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -968,9 +968,29 @@ static void gen_##op(DisasContext *ctx)             \
>      tcg_temp_free_i32(ps);                          \
>  }
>  
> +#define GEN_BCD3(op)                                \
> +static void gen_##op(DisasContext *ctx)             \
> +{                                                   \
> +    TCGv_ptr rb, rd;                                \
> +                                                    \
> +    if (unlikely(!ctx->altivec_enabled)) {          \
> +        gen_exception(ctx, POWERPC_EXCP_VPU);       \
> +        return;                                     \
> +    }                                               \
> +                                                    \
> +    rb = gen_avr_ptr(rB(ctx->opcode));              \
> +    rd = gen_avr_ptr(rD(ctx->opcode));              \
> +                                                    \
> +    gen_helper_##op(cpu_crf[6], rd, rb);            \
> +                                                    \
> +    tcg_temp_free_ptr(rb);                          \
> +    tcg_temp_free_ptr(rd);                          \
> +}

I don't think it's worth bothering with another GEN macro here.  Just
use GEN_BCD2 and ignore the ps parameter in the helper function.

> +
>  GEN_BCD(bcdadd)
>  GEN_BCD(bcdsub)
>  GEN_BCD2(bcdcfn)
> +GEN_BCD3(bcdctn)
>  
>  static void gen_xpnd04_1(DisasContext *ctx)
>  {
> @@ -982,7 +1002,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
>      case 4:
>          break; /* bcdctz. */
>      case 5:
> -        break; /* bcdctn. */
> +        gen_bcdctn(ctx);
> +        break;
>      case 6:
>          break; /* bcdcfz. */
>      case 7:
> @@ -1098,3 +1119,4 @@ GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
>  #undef GEN_VAFORM_PAIRED
>  
>  #undef GEN_BCD2
> +#undef GEN_BCD3

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 3/4] target-ppc: Implement bcdcfz. instruction

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 4094 bytes --]

On Fri, Oct 28, 2016 at 03:18:03PM -0200, Jose Ricardo Ziviani wrote:
> bcdcfz. converts from Zoned numeric format to BCD. Zoned format uses
> a byte to represent a digit where the most significant nibble is 0x3
> or 0xf, depending on the preferred signal.
> 
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>

Only a trivial fix, otherwise looks ok now  (I wouldn't mention
something this small, except that the series will need a respin
anyway, so it might as well get fixed).

> ---
>  target-ppc/helper.h                 |  1 +
>  target-ppc/int_helper.c             | 47 +++++++++++++++++++++++++++++++++++++
>  target-ppc/translate/vmx-impl.inc.c |  7 ++++--
>  3 files changed, 53 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 53d1e7a..a9ac28b 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -373,6 +373,7 @@ DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
>  DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
>  DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
>  DEF_HELPER_2(bcdctn, i32, avr, avr)
> +DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
>  
>  DEF_HELPER_2(xsadddp, void, env, i32)
>  DEF_HELPER_2(xssubdp, void, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index a58ed30..19e6a3a 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2727,6 +2727,53 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b)
>      return cr;
>  }
>  
> +uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
> +{
> +    int i;
> +    int j;
> +    int cr = 0;
> +    int invalid = 0;
> +    int neq_flag = 0;
> +    int zone_digit = 0;
> +    int zone_lead = (ps) ? 0xF : 0x3;

No need to bracket ps here.

> +    int digit = 0;
> +    ppc_avr_t ret = { .u64 = { 0, 0 } };
> +    int sgnb = b->u8[BCD_DIG_BYTE(0)] >> 4;
> +
> +    if (unlikely((sgnb < 0xA) && ps)) {
> +        invalid = 1;
> +    }
> +
> +    for (i = 0, j = 1; i < 31; i += 2, j++) {
> +        zone_digit = (i) ? b->u8[BCD_DIG_BYTE(i)] >> 4 : zone_lead;
> +        digit = b->u8[BCD_DIG_BYTE(i)] & 0xF;
> +
> +        if (unlikely(zone_digit != zone_lead || digit > 0x9)) {
> +            invalid = 1;
> +            break;
> +        }
> +
> +        neq_flag += (digit != 0);
> +        bcd_put_digit(&ret, digit, j);
> +    }
> +
> +    if ((ps && (sgnb == 0xB || sgnb == 0xD)) ||
> +            (!ps && (sgnb & 0x4))) {
> +        bcd_put_digit(&ret, BCD_NEG_PREF, 0);
> +        cr = (neq_flag) ? 1 << CRF_LT : 1 << CRF_EQ;
> +    } else {
> +        bcd_put_digit(&ret, BCD_PLUS_PREF_1, 0);
> +        cr = (neq_flag) ? 1 << CRF_GT : 1 << CRF_EQ;
> +    }
> +
> +    if (unlikely(invalid)) {
> +        cr = 1 << CRF_SO;
> +    }
> +
> +    *r = ret;
> +
> +    return cr;
> +}
>  void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
>  {
>      int i;
> diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
> index e37fc11..6e54437 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -991,6 +991,7 @@ GEN_BCD(bcdadd)
>  GEN_BCD(bcdsub)
>  GEN_BCD2(bcdcfn)
>  GEN_BCD3(bcdctn)
> +GEN_BCD2(bcdcfz)
>  
>  static void gen_xpnd04_1(DisasContext *ctx)
>  {
> @@ -1005,7 +1006,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
>          gen_bcdctn(ctx);
>          break;
>      case 6:
> -        break; /* bcdcfz. */
> +        gen_bcdcfz(ctx);
> +        break;
>      case 7:
>          gen_bcdcfn(ctx);
>          break;
> @@ -1026,7 +1028,8 @@ static void gen_xpnd04_2(DisasContext *ctx)
>      case 4:
>          break; /* bcdctz. */
>      case 6:
> -        break; /* bcdcfz. */
> +        gen_bcdcfz(ctx);
> +        break;
>      case 7:
>          gen_bcdcfn(ctx);
>          break;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 4/4] target-ppc: Implement bcdctz. instruction

[David Gibson]

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On Fri, Oct 28, 2016 at 03:18:04PM -0200, Jose Ricardo Ziviani wrote:
> bcdctz. converts from BCD to Zoned numeric format. Zoned format uses
> a byte to represent a digit where the most significant nibble is 0x3
> or 0xf, depending on the preferred signal.
> 
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h                 |  1 +
>  target-ppc/int_helper.c             | 51 +++++++++++++++++++++++++++++++++++++
>  target-ppc/translate/vmx-impl.inc.c |  7 +++--
>  3 files changed, 57 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index a9ac28b..489a405 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -374,6 +374,7 @@ DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
>  DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
>  DEF_HELPER_2(bcdctn, i32, avr, avr)
>  DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
> +DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
>  
>  DEF_HELPER_2(xsadddp, void, env, i32)
>  DEF_HELPER_2(xssubdp, void, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 19e6a3a..518824e 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2774,6 +2774,57 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
>  
>      return cr;
>  }
> +
> +uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
> +{
> +    int i;
> +    int j;
> +    int cr = 0;
> +    uint8_t digit = 0;
> +    int sgnb = bcd_get_sgn(b);
> +    int zone_lead = (ps) ? 0xF0 : 0x30;
> +    int invalid = (sgnb == 0);
> +    ppc_avr_t ret = { .u64 = { 0, 0 } };
> +
> +    int eq_flag = (b->u64[HI_IDX] == 0) && ((b->u64[LO_IDX] >> 4) == 0);
> +    int ox_flag = ((b->u64[HI_IDX] >> 4) != 0);
> +
> +    for (i = 0, j = 1; i < 32; i += 2, j++) {
> +        digit = bcd_get_digit(b, j, &invalid);
> +
> +        if (unlikely(invalid)) {
> +            break;
> +        }
> +
> +        ret.u8[BCD_DIG_BYTE(i)] = zone_lead + digit;
> +    }
> +
> +    if (ps) {
> +        bcd_put_digit(&ret, (sgnb == 1) ? 0xC : 0xD, 1);
> +    } else {
> +        bcd_put_digit(&ret, (sgnb == 1) ? 0x3 : 0x7, 1);
> +    }
> +    bcd_put_digit(&ret, b->u8[BCD_DIG_BYTE(0)] >> 4, 0);

This last bcd_put_digit looks unneccessary - your loop above has
already put all the actual digits into the output, and writing the
sign nibble won't have overwritten that.

> +
> +    if (!eq_flag) {
> +        cr = (sgnb == 1) ? 1 << CRF_GT : 1 << CRF_LT;
> +    } else {
> +        cr = 1 << CRF_EQ;
> +    }
> +
> +    if (ox_flag) {
> +        cr |= 1 << CRF_SO;
> +    }
> +
> +    if (unlikely(invalid)) {
> +        cr = 1 << CRF_SO;
> +    }
> +
> +    *r = ret;
> +
> +    return cr;
> +}
> +
>  void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
>  {
>      int i;
> diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
> index 6e54437..a868740 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -992,6 +992,7 @@ GEN_BCD(bcdsub)
>  GEN_BCD2(bcdcfn)
>  GEN_BCD3(bcdctn)
>  GEN_BCD2(bcdcfz)
> +GEN_BCD2(bcdctz)
>  
>  static void gen_xpnd04_1(DisasContext *ctx)
>  {
> @@ -1001,7 +1002,8 @@ static void gen_xpnd04_1(DisasContext *ctx)
>      case 2:
>          break; /* bcdcfsq. */
>      case 4:
> -        break; /* bcdctz. */
> +        gen_bcdctz(ctx);
> +        break;
>      case 5:
>          gen_bcdctn(ctx);
>          break;
> @@ -1026,7 +1028,8 @@ static void gen_xpnd04_2(DisasContext *ctx)
>      case 2:
>          break; /* bcdcfsq. */
>      case 4:
> -        break; /* bcdctz. */
> +        gen_bcdctz(ctx);
> +        break;
>      case 6:
>          gen_bcdcfz(ctx);
>          break;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I

[David Gibson]

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On Fri, Oct 28, 2016 at 03:18:00PM -0200, Jose Ricardo Ziviani wrote:
> v2:
>  - implements all fixes and suggestions

Ok, I think the implementations are correct now, but there is still
some polish necessary - comments on the individual patches.

I have to wonder what the chip designers were smoking to put into a
2016 CPU special instructions for handling obscure decimal formats
that appear to be from the EBCDIC era.  Still, if they're in the
silicon, I guess we need to put them in qemu as well.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part I

[joserz]

On Mon, Oct 31, 2016 at 01:37:35PM +1100, David Gibson wrote:
> On Fri, Oct 28, 2016 at 03:18:00PM -0200, Jose Ricardo Ziviani wrote:
> > v2:
> >  - implements all fixes and suggestions
> 
> Ok, I think the implementations are correct now, but there is still
> some polish necessary - comments on the individual patches.

Thanks again for reviewing it, learned a lot in this process. Really
appreciated.
> 
> I have to wonder what the chip designers were smoking to put into a
> 2016 CPU special instructions for handling obscure decimal formats
> that appear to be from the EBCDIC era.  Still, if they're in the
> silicon, I guess we need to put them in qemu as well.

my guess is to have improvements to run/convert cobol (db2?) programs,
just a guess :D

> 
> -- 
> David Gibson			| I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
> 				| _way_ _around_!
> http://www.ozlabs.org/~dgibson