From: mengdong.lin@intel.com
To: alsa-devel@alsa-project.org, broonie@kernel.org, bardliao@realtek.com
Cc: Mengdong Lin <mengdong.lin@intel.com>
Subject: [PATCH 1/3] ASoC: rt5670: fix bit definition for ASRC control
Date: Mon, 5 Jan 2015 17:48:15 +0800 [thread overview]
Message-ID: <1481c597e90b5daacce80a021fa0c513a7a2ec6d.1420451186.git.mengdong.lin@intel.com> (raw)
From: Bard Liao <bardliao@realtek.com>
This patch fixes bit definitions for two ASRC control registers 0x84 and 0x85.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
diff --git a/sound/soc/codecs/rt5670.h b/sound/soc/codecs/rt5670.h
index 54933f3..7c37b00 100644
--- a/sound/soc/codecs/rt5670.h
+++ b/sound/soc/codecs/rt5670.h
@@ -1023,50 +1023,33 @@
#define RT5670_DMIC_2_M_NOR (0x0 << 8)
#define RT5670_DMIC_2_M_ASYN (0x1 << 8)
+/* ASRC clock source selection (0x84, 0x85) */
+#define RT5670_CLK_SEL_SYS (0x0)
+#define RT5670_CLK_SEL_I2S1_ASRC (0x1)
+#define RT5670_CLK_SEL_I2S2_ASRC (0x2)
+#define RT5670_CLK_SEL_I2S3_ASRC (0x3)
+#define RT5670_CLK_SEL_SYS2 (0x5)
+#define RT5670_CLK_SEL_SYS3 (0x6)
+
/* ASRC Control 2 (0x84) */
-#define RT5670_MDA_L_M_MASK (0x1 << 15)
-#define RT5670_MDA_L_M_SFT 15
-#define RT5670_MDA_L_M_NOR (0x0 << 15)
-#define RT5670_MDA_L_M_ASYN (0x1 << 15)
-#define RT5670_MDA_R_M_MASK (0x1 << 14)
-#define RT5670_MDA_R_M_SFT 14
-#define RT5670_MDA_R_M_NOR (0x0 << 14)
-#define RT5670_MDA_R_M_ASYN (0x1 << 14)
-#define RT5670_MAD_L_M_MASK (0x1 << 13)
-#define RT5670_MAD_L_M_SFT 13
-#define RT5670_MAD_L_M_NOR (0x0 << 13)
-#define RT5670_MAD_L_M_ASYN (0x1 << 13)
-#define RT5670_MAD_R_M_MASK (0x1 << 12)
-#define RT5670_MAD_R_M_SFT 12
-#define RT5670_MAD_R_M_NOR (0x0 << 12)
-#define RT5670_MAD_R_M_ASYN (0x1 << 12)
-#define RT5670_ADC_M_MASK (0x1 << 11)
-#define RT5670_ADC_M_SFT 11
-#define RT5670_ADC_M_NOR (0x0 << 11)
-#define RT5670_ADC_M_ASYN (0x1 << 11)
-#define RT5670_STO_DAC_M_MASK (0x1 << 5)
-#define RT5670_STO_DAC_M_SFT 5
-#define RT5670_STO_DAC_M_NOR (0x0 << 5)
-#define RT5670_STO_DAC_M_ASYN (0x1 << 5)
-#define RT5670_I2S1_R_D_MASK (0x1 << 4)
-#define RT5670_I2S1_R_D_SFT 4
-#define RT5670_I2S1_R_D_DIS (0x0 << 4)
-#define RT5670_I2S1_R_D_EN (0x1 << 4)
-#define RT5670_I2S2_R_D_MASK (0x1 << 3)
-#define RT5670_I2S2_R_D_SFT 3
-#define RT5670_I2S2_R_D_DIS (0x0 << 3)
-#define RT5670_I2S2_R_D_EN (0x1 << 3)
-#define RT5670_PRE_SCLK_MASK (0x3)
-#define RT5670_PRE_SCLK_SFT 0
-#define RT5670_PRE_SCLK_512 (0x0)
-#define RT5670_PRE_SCLK_1024 (0x1)
-#define RT5670_PRE_SCLK_2048 (0x2)
+#define RT5670_DA_STO_CLK_SEL_MASK (0xf << 12)
+#define RT5670_DA_STO_CLK_SEL_SFT 12
+#define RT5670_DA_MONOL_CLK_SEL_MASK (0xf << 8)
+#define RT5670_DA_MONOL_CLK_SEL_SFT 8
+#define RT5670_DA_MONOR_CLK_SEL_MASK (0xf << 4)
+#define RT5670_DA_MONOR_CLK_SEL_SFT 4
+#define RT5670_AD_STO1_CLK_SEL_MASK (0xf << 0)
+#define RT5670_AD_STO1_CLK_SEL_SFT 0
/* ASRC Control 3 (0x85) */
-#define RT5670_I2S1_RATE_MASK (0xf << 12)
-#define RT5670_I2S1_RATE_SFT 12
-#define RT5670_I2S2_RATE_MASK (0xf << 8)
-#define RT5670_I2S2_RATE_SFT 8
+#define RT5670_UP_CLK_SEL_MASK (0xf << 12)
+#define RT5670_UP_CLK_SEL_SFT 12
+#define RT5670_DOWN_CLK_SEL_MASK (0xf << 8)
+#define RT5670_DOWN_CLK_SEL_SFT 8
+#define RT5670_AD_MONOL_CLK_SEL_MASK (0xf << 4)
+#define RT5670_AD_MONOL_CLK_SEL_SFT 4
+#define RT5670_AD_MONOR_CLK_SEL_MASK (0xf << 0)
+#define RT5670_AD_MONOR_CLK_SEL_SFT 0
/* ASRC Control 4 (0x89) */
#define RT5670_I2S1_PD_MASK (0x7 << 12)
--
1.9.1
next reply other threads:[~2015-01-05 9:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-05 9:48 mengdong.lin [this message]
2015-01-05 9:48 ` [PATCH 2/3] ASoC: rt5670: add API to select ASRC clock source mengdong.lin
2015-01-05 9:48 ` [PATCH 3/3] ASoC: Intel: Select RT5672 ASRC clock source on Cherrytrail and Braswell mengdong.lin
2015-01-05 18:17 ` [PATCH 1/3] ASoC: rt5670: fix bit definition for ASRC control Mark Brown
2015-01-06 2:08 ` Bard Liao
2015-01-06 11:03 ` Mark Brown
2015-01-07 2:16 ` Lin, Mengdong
2015-01-07 2:19 ` [PATCH v2 1/3] ASoC: rt5670: redefine ASRC control registers 0x84 and 0x85 mengdong.lin
2015-01-07 17:42 ` Mark Brown
2015-01-07 2:19 ` [PATCH v2 2/3] ASoC: rt5670: add API to select ASRC clock source mengdong.lin
2015-01-07 2:19 ` [PATCH v2 3/3] ASoC: Intel: Select RT5672 ASRC clock source on Cherrytrail and Braswell mengdong.lin
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