All of lore.kernel.org
 help / color / mirror / Atom feed
From: Bard Liao <bardliao@realtek.com>
To: Mark Brown <broonie@kernel.org>,
	"mengdong.lin@intel.com" <mengdong.lin@intel.com>
Cc: "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>
Subject: Re: [PATCH 1/3] ASoC: rt5670: fix bit definition for ASRC control
Date: Tue, 6 Jan 2015 02:08:45 +0000	[thread overview]
Message-ID: <ABFD875FF5FB574BA706497D987D48D70103ABE3@RTITMBSV03.realtek.com.tw> (raw)
In-Reply-To: <20150105181714.GA2634@sirena.org.uk>

> -----Original Message-----
> From: Mark Brown [mailto:broonie@kernel.org]
> Sent: Tuesday, January 06, 2015 2:17 AM
> To: mengdong.lin@intel.com
> Cc: alsa-devel@alsa-project.org; Bard Liao
> Subject: Re: [PATCH 1/3] ASoC: rt5670: fix bit definition for ASRC control
> 
> On Mon, Jan 05, 2015 at 05:48:15PM +0800, mengdong.lin@intel.com
> wrote:
> > From: Bard Liao <bardliao@realtek.com>
> >
> > This patch fixes bit definitions for two ASRC control registers 0x84 and
> 0x85.
> 
> This appears to do something more or different to fixing definitions - if it
> was fixing I'd expect to see equal numbers of lines added and removed in
> blocks identical apart from some numbers but this appears to be adding
> some new definitions like these...

Maybe we should call redefine rather than fix. The previous definition of
registers 0x84 and 0x85 doesn't match the register's description. To make
the code more readable, we would like to rewrite the definition of registers
0x84 and 0x85.

> 
> > +/* ASRC clock source selection (0x84, 0x85) */
> > +#define RT5670_CLK_SEL_SYS			(0x0)
> > +#define RT5670_CLK_SEL_I2S1_ASRC		(0x1)
> > +#define RT5670_CLK_SEL_I2S2_ASRC		(0x2)
> > +#define RT5670_CLK_SEL_I2S3_ASRC		(0x3)
> > +#define RT5670_CLK_SEL_SYS2			(0x5)
> > +#define RT5670_CLK_SEL_SYS3			(0x6)
> 
> ...among other things, and this block here:

The description above is the same for all ASRC blocks. To save code size,
we define it in a separate part.
If we define it in each ASRC block, it would be something like
+#define RT5670_DA_STO_CLK_SEL_MASK		(0xf << 12)
+#define RT5670_DA_STO_CLK_SEL_SFT		12
+#define RT5670_DA_STO_CLK_SEL_SYS		(0 << 12)
+#define RT5670_DA_STO_CLK_SEL_I2S1_ASRC	(1 << 12)
+#define RT5670_DA_STO_CLK_SEL_I2S2_ASRC	(2 << 12)
+#define RT5670_DA_STO_CLK_SEL_I2S3_ASRC	(3 << 12)
+#define RT5670_DA_STO_CLK_SEL_ SYS2		(5 << 12)
+#define RT5670_DA_STO_CLK_SEL_ SYS3		(6 << 12)
And same thing for other ASRC blocks.

> 
> >  /* ASRC Control 2 (0x84) */
> > -#define RT5670_MDA_L_M_MASK			(0x1 << 15)
> > -#define RT5670_MDA_L_M_SFT			15
> > -#define RT5670_MDA_L_M_NOR			(0x0 << 15)
> > -#define RT5670_MDA_L_M_ASYN			(0x1 << 15)
> > -#define RT5670_MDA_R_M_MASK			(0x1 << 14)
> > -#define RT5670_MDA_R_M_SFT			14
> > -#define RT5670_MDA_R_M_NOR			(0x0 << 14)
> > -#define RT5670_MDA_R_M_ASYN			(0x1 << 14)
> > -#define RT5670_MAD_L_M_MASK			(0x1 << 13)
> > -#define RT5670_MAD_L_M_SFT			13
> > -#define RT5670_MAD_L_M_NOR			(0x0 << 13)
> > -#define RT5670_MAD_L_M_ASYN			(0x1 << 13)
> > -#define RT5670_MAD_R_M_MASK			(0x1 << 12)
> > -#define RT5670_MAD_R_M_SFT			12
> > -#define RT5670_MAD_R_M_NOR			(0x0 << 12)
> > -#define RT5670_MAD_R_M_ASYN			(0x1 << 12)
> > -#define RT5670_ADC_M_MASK			(0x1 << 11)
> > -#define RT5670_ADC_M_SFT			11
> > -#define RT5670_ADC_M_NOR			(0x0 << 11)
> > -#define RT5670_ADC_M_ASYN			(0x1 << 11)
> > -#define RT5670_STO_DAC_M_MASK			(0x1 << 5)
> > -#define RT5670_STO_DAC_M_SFT			5
> > -#define RT5670_STO_DAC_M_NOR			(0x0 << 5)
> > -#define RT5670_STO_DAC_M_ASYN			(0x1 << 5)
> > -#define RT5670_I2S1_R_D_MASK			(0x1 << 4)
> > -#define RT5670_I2S1_R_D_SFT			4
> > -#define RT5670_I2S1_R_D_DIS			(0x0 << 4)
> > -#define RT5670_I2S1_R_D_EN			(0x1 << 4)
> > -#define RT5670_I2S2_R_D_MASK			(0x1 << 3)
> > -#define RT5670_I2S2_R_D_SFT			3
> > -#define RT5670_I2S2_R_D_DIS			(0x0 << 3)
> > -#define RT5670_I2S2_R_D_EN			(0x1 << 3)
> > -#define RT5670_PRE_SCLK_MASK			(0x3)
> > -#define RT5670_PRE_SCLK_SFT			0
> > -#define RT5670_PRE_SCLK_512			(0x0)
> > -#define RT5670_PRE_SCLK_1024			(0x1)
> > -#define RT5670_PRE_SCLK_2048			(0x2)
> > +#define RT5670_DA_STO_CLK_SEL_MASK		(0xf << 12)
> > +#define RT5670_DA_STO_CLK_SEL_SFT		12
> > +#define RT5670_DA_MONOL_CLK_SEL_MASK		(0xf << 8)
> > +#define RT5670_DA_MONOL_CLK_SEL_SFT		8
> > +#define RT5670_DA_MONOR_CLK_SEL_MASK		(0xf << 4)
> > +#define RT5670_DA_MONOR_CLK_SEL_SFT		4
> > +#define RT5670_AD_STO1_CLK_SEL_MASK		(0xf << 0)
> > +#define RT5670_AD_STO1_CLK_SEL_SFT		0
> 
> removes a lot more things than it adds, with different names too.

The previous definition is totally wrong, so we just remove it and
write a new definition for it.

> 
> ------Please consider the environment before printing this e-mail.

  reply	other threads:[~2015-01-06  2:08 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-05  9:48 [PATCH 1/3] ASoC: rt5670: fix bit definition for ASRC control mengdong.lin
2015-01-05  9:48 ` [PATCH 2/3] ASoC: rt5670: add API to select ASRC clock source mengdong.lin
2015-01-05  9:48 ` [PATCH 3/3] ASoC: Intel: Select RT5672 ASRC clock source on Cherrytrail and Braswell mengdong.lin
2015-01-05 18:17 ` [PATCH 1/3] ASoC: rt5670: fix bit definition for ASRC control Mark Brown
2015-01-06  2:08   ` Bard Liao [this message]
2015-01-06 11:03     ` Mark Brown
2015-01-07  2:16       ` Lin, Mengdong
2015-01-07  2:19 ` [PATCH v2 1/3] ASoC: rt5670: redefine ASRC control registers 0x84 and 0x85 mengdong.lin
2015-01-07 17:42   ` Mark Brown
2015-01-07  2:19 ` [PATCH v2 2/3] ASoC: rt5670: add API to select ASRC clock source mengdong.lin
2015-01-07  2:19 ` [PATCH v2 3/3] ASoC: Intel: Select RT5672 ASRC clock source on Cherrytrail and Braswell mengdong.lin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ABFD875FF5FB574BA706497D987D48D70103ABE3@RTITMBSV03.realtek.com.tw \
    --to=bardliao@realtek.com \
    --cc=alsa-devel@alsa-project.org \
    --cc=broonie@kernel.org \
    --cc=mengdong.lin@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.