All of lore.kernel.org
 help / color / mirror / Atom feed
From: Will Deacon <will.deacon@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: marc.zyngier@arm.com, mark.rutland@arm.com, kim.phillips@arm.com,
	alex.bennee@linaro.org, christoffer.dall@linaro.org,
	tglx@linutronix.de, peterz@infradead.org,
	alexander.shishkin@linux.intel.com, robh@kernel.org,
	suzuki.poulose@arm.com, pawel.moll@arm.com,
	mathieu.poirier@linaro.org, mingo@redhat.com,
	linux-kernel@vger.kernel.org, Will Deacon <will.deacon@arm.com>
Subject: [RFC PATCH v2 01/10] arm64: cpufeature: allow for version discrepancy in PMU implementations
Date: Fri, 13 Jan 2017 16:03:40 +0000	[thread overview]
Message-ID: <1484323429-15231-2-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1484323429-15231-1-git-send-email-will.deacon@arm.com>

Perf already supports multiple PMU instances for heterogeneous systems,
so there's no need to be strict in the cpufeature checking, particularly
as the PMU extension is optional in the architecture.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index fdf8f045929f..47d0226620e8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -184,7 +184,11 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
-	S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
+	/*
+	 * We can instantiate multiple PMU instances with different levels
+	 * of support.
+	 * */
+	S_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 	ARM64_FTR_END,
-- 
2.1.4

WARNING: multiple messages have this Message-ID (diff)
From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v2 01/10] arm64: cpufeature: allow for version discrepancy in PMU implementations
Date: Fri, 13 Jan 2017 16:03:40 +0000	[thread overview]
Message-ID: <1484323429-15231-2-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1484323429-15231-1-git-send-email-will.deacon@arm.com>

Perf already supports multiple PMU instances for heterogeneous systems,
so there's no need to be strict in the cpufeature checking, particularly
as the PMU extension is optional in the architecture.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index fdf8f045929f..47d0226620e8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -184,7 +184,11 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
-	S_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
+	/*
+	 * We can instantiate multiple PMU instances with different levels
+	 * of support.
+	 * */
+	S_ARM64_FTR_BITS(FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 	ARM64_FTR_END,
-- 
2.1.4

  reply	other threads:[~2017-01-13 16:04 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-13 16:03 [RFC PATCH v2 00/10] Add support for the ARMv8.2 Statistical Profiling Extension Will Deacon
2017-01-13 16:03 ` Will Deacon
2017-01-13 16:03 ` Will Deacon [this message]
2017-01-13 16:03   ` [RFC PATCH v2 01/10] arm64: cpufeature: allow for version discrepancy in PMU implementations Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 02/10] arm64: cpufeature: Don't enforce system-wide SPE capability Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 03/10] arm64: KVM: Save/restore the host SPE state when entering/leaving a VM Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-16 11:25   ` Marc Zyngier
2017-01-16 11:25     ` Marc Zyngier
2017-01-18 15:24     ` Will Deacon
2017-01-18 15:24       ` Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 04/10] arm64: head.S: Enable EL1 (host) access to SPE when entered at EL2 Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 19:21   ` Marc Zyngier
2017-01-13 19:21     ` Marc Zyngier
2017-01-13 16:03 ` [RFC PATCH v2 05/10] genirq: export irq_get_percpu_devid_partition to modules Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 19:04   ` Marc Zyngier
2017-01-13 19:04     ` Marc Zyngier
2017-01-16  9:06   ` Thomas Gleixner
2017-01-16  9:06     ` Thomas Gleixner
2017-01-13 16:03 ` [RFC PATCH v2 06/10] perf/core: Export AUX buffer helpers " Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 07/10] perf: Directly pass PERF_AUX_* flags to perf_aux_output_end Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 08/10] perf/core: Add PERF_AUX_FLAG_COLLISION to report colliding samples Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 16:03 ` [RFC PATCH v2 09/10] drivers/perf: Add support for ARMv8.2 Statistical Profiling Extension Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 16:40   ` Kim Phillips
2017-01-13 16:40     ` Kim Phillips
2017-01-13 17:03     ` Will Deacon
2017-01-13 17:03       ` Will Deacon
2017-01-13 18:17       ` Kim Phillips
2017-01-13 18:17         ` Kim Phillips
2017-01-13 16:03 ` [RFC PATCH v2 10/10] dt-bindings: Document devicetree binding for ARM SPE Will Deacon
2017-01-13 16:03   ` Will Deacon
2017-01-13 18:43   ` Mark Rutland
2017-01-13 18:43     ` Mark Rutland
2017-01-16 10:59     ` Will Deacon
2017-01-16 10:59       ` Will Deacon
2017-01-17 16:31       ` Kim Phillips
2017-01-17 16:31         ` Kim Phillips
2017-01-17 16:50         ` Mark Rutland
2017-01-17 16:50           ` Mark Rutland
2017-01-17 16:45       ` Mark Rutland
2017-01-17 16:45         ` Mark Rutland

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1484323429-15231-2-git-send-email-will.deacon@arm.com \
    --to=will.deacon@arm.com \
    --cc=alex.bennee@linaro.org \
    --cc=alexander.shishkin@linux.intel.com \
    --cc=christoffer.dall@linaro.org \
    --cc=kim.phillips@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=mark.rutland@arm.com \
    --cc=mathieu.poirier@linaro.org \
    --cc=mingo@redhat.com \
    --cc=pawel.moll@arm.com \
    --cc=peterz@infradead.org \
    --cc=robh@kernel.org \
    --cc=suzuki.poulose@arm.com \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.