From: linucherian@gmail.com To: catalin.marinas@arm.com, will.deacon@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com Cc: rjw@rjwysocki.net, lenb@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robert.moore@intel.com, lv.zheng@intel.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, devel@acpica.org, Sunil.Goutham@cavium.com, Geethasowjanya.Akula@cavium.com, robert.richter@cavium.com, linu.cherian@cavium.com Subject: [RFC PATCH 1/7] iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for Silicon errata. Date: Tue, 11 Apr 2017 20:12:39 +0530 [thread overview] Message-ID: <1491921765-29475-2-git-send-email-linucherian@gmail.com> (raw) In-Reply-To: <1491921765-29475-1-git-send-email-linucherian@gmail.com> From: Linu Cherian <linu.cherian@cavium.com> Cavium 99xx SMMU implementation doesn't support page 1 register space and PAGE0_REGS_ONLY option will be enabled as an errata workaround. This option when turned on, replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. Signed-off-by: Linu Cherian <linu.cherian@cavium.com> --- drivers/iommu/arm-smmu-v3.c | 44 ++++++++++++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 05b4592..df9f27b 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -176,15 +176,15 @@ #define ARM_SMMU_CMDQ_CONS 0x9c #define ARM_SMMU_EVTQ_BASE 0xa0 -#define ARM_SMMU_EVTQ_PROD 0x100a8 -#define ARM_SMMU_EVTQ_CONS 0x100ac +#define ARM_SMMU_EVTQ_PROD(s) (page1_offset_adjust(0x100a8, s)) +#define ARM_SMMU_EVTQ_CONS(s) (page1_offset_adjust(0x100ac, s)) #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc #define ARM_SMMU_PRIQ_BASE 0xc0 -#define ARM_SMMU_PRIQ_PROD 0x100c8 -#define ARM_SMMU_PRIQ_CONS 0x100cc +#define ARM_SMMU_PRIQ_PROD(s) (page1_offset_adjust(0x100c8, s)) +#define ARM_SMMU_PRIQ_CONS(s) (page1_offset_adjust(0x100cc, s)) #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc @@ -412,6 +412,9 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +#define ARM_SMMU_PAGE0_REGS_ONLY(s) \ + ((s)->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) + static bool disable_bypass; module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, @@ -597,6 +600,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -663,9 +667,19 @@ struct arm_smmu_option_prop { static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, + { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium-cn99xx,broken-page1-regspace"}, { 0, NULL}, }; +static inline unsigned long page1_offset_adjust( + unsigned long off, struct arm_smmu_device *smmu) +{ + if (!ARM_SMMU_PAGE0_REGS_ONLY(smmu)) + return off; + else + return (off - SZ_64K); +} + static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) { return container_of(dom, struct arm_smmu_domain, domain); @@ -1983,8 +1997,10 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) return ret; /* evtq */ - ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, - ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS); + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, + ARM_SMMU_EVTQ_PROD(smmu), + ARM_SMMU_EVTQ_CONS(smmu), + EVTQ_ENT_DWORDS); if (ret) return ret; @@ -1992,8 +2008,10 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (!(smmu->features & ARM_SMMU_FEAT_PRI)) return 0; - return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, - ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS); + return arm_smmu_init_one_queue(smmu, &smmu->priq.q, + ARM_SMMU_PRIQ_PROD(smmu), + ARM_SMMU_PRIQ_CONS(smmu), + PRIQ_ENT_DWORDS); } static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) @@ -2360,8 +2378,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) /* Event queue */ writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); - writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); + writel_relaxed(smmu->evtq.q.prod, smmu->base + + ARM_SMMU_EVTQ_PROD(smmu)); + writel_relaxed(smmu->evtq.q.cons, smmu->base + + ARM_SMMU_EVTQ_CONS(smmu)); enables |= CR0_EVTQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, @@ -2376,9 +2396,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) writeq_relaxed(smmu->priq.q.q_base, smmu->base + ARM_SMMU_PRIQ_BASE); writel_relaxed(smmu->priq.q.prod, - smmu->base + ARM_SMMU_PRIQ_PROD); + smmu->base + ARM_SMMU_PRIQ_PROD(smmu)); writel_relaxed(smmu->priq.q.cons, - smmu->base + ARM_SMMU_PRIQ_CONS); + smmu->base + ARM_SMMU_PRIQ_CONS(smmu)); enables |= CR0_PRIQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: linucherian@gmail.com (linucherian at gmail.com) To: linux-arm-kernel@lists.infradead.org Subject: [RFC PATCH 1/7] iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for Silicon errata. Date: Tue, 11 Apr 2017 20:12:39 +0530 [thread overview] Message-ID: <1491921765-29475-2-git-send-email-linucherian@gmail.com> (raw) In-Reply-To: <1491921765-29475-1-git-send-email-linucherian@gmail.com> From: Linu Cherian <linu.cherian@cavium.com> Cavium 99xx SMMU implementation doesn't support page 1 register space and PAGE0_REGS_ONLY option will be enabled as an errata workaround. This option when turned on, replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets. Signed-off-by: Linu Cherian <linu.cherian@cavium.com> --- drivers/iommu/arm-smmu-v3.c | 44 ++++++++++++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 05b4592..df9f27b 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -176,15 +176,15 @@ #define ARM_SMMU_CMDQ_CONS 0x9c #define ARM_SMMU_EVTQ_BASE 0xa0 -#define ARM_SMMU_EVTQ_PROD 0x100a8 -#define ARM_SMMU_EVTQ_CONS 0x100ac +#define ARM_SMMU_EVTQ_PROD(s) (page1_offset_adjust(0x100a8, s)) +#define ARM_SMMU_EVTQ_CONS(s) (page1_offset_adjust(0x100ac, s)) #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc #define ARM_SMMU_PRIQ_BASE 0xc0 -#define ARM_SMMU_PRIQ_PROD 0x100c8 -#define ARM_SMMU_PRIQ_CONS 0x100cc +#define ARM_SMMU_PRIQ_PROD(s) (page1_offset_adjust(0x100c8, s)) +#define ARM_SMMU_PRIQ_CONS(s) (page1_offset_adjust(0x100cc, s)) #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc @@ -412,6 +412,9 @@ #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 +#define ARM_SMMU_PAGE0_REGS_ONLY(s) \ + ((s)->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) + static bool disable_bypass; module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO); MODULE_PARM_DESC(disable_bypass, @@ -597,6 +600,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -663,9 +667,19 @@ struct arm_smmu_option_prop { static struct arm_smmu_option_prop arm_smmu_options[] = { { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, + { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium-cn99xx,broken-page1-regspace"}, { 0, NULL}, }; +static inline unsigned long page1_offset_adjust( + unsigned long off, struct arm_smmu_device *smmu) +{ + if (!ARM_SMMU_PAGE0_REGS_ONLY(smmu)) + return off; + else + return (off - SZ_64K); +} + static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) { return container_of(dom, struct arm_smmu_domain, domain); @@ -1983,8 +1997,10 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) return ret; /* evtq */ - ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, - ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS); + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, + ARM_SMMU_EVTQ_PROD(smmu), + ARM_SMMU_EVTQ_CONS(smmu), + EVTQ_ENT_DWORDS); if (ret) return ret; @@ -1992,8 +2008,10 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (!(smmu->features & ARM_SMMU_FEAT_PRI)) return 0; - return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, - ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS); + return arm_smmu_init_one_queue(smmu, &smmu->priq.q, + ARM_SMMU_PRIQ_PROD(smmu), + ARM_SMMU_PRIQ_CONS(smmu), + PRIQ_ENT_DWORDS); } static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) @@ -2360,8 +2378,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) /* Event queue */ writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.prod, smmu->base + ARM_SMMU_EVTQ_PROD); - writel_relaxed(smmu->evtq.q.cons, smmu->base + ARM_SMMU_EVTQ_CONS); + writel_relaxed(smmu->evtq.q.prod, smmu->base + + ARM_SMMU_EVTQ_PROD(smmu)); + writel_relaxed(smmu->evtq.q.cons, smmu->base + + ARM_SMMU_EVTQ_CONS(smmu)); enables |= CR0_EVTQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, @@ -2376,9 +2396,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) writeq_relaxed(smmu->priq.q.q_base, smmu->base + ARM_SMMU_PRIQ_BASE); writel_relaxed(smmu->priq.q.prod, - smmu->base + ARM_SMMU_PRIQ_PROD); + smmu->base + ARM_SMMU_PRIQ_PROD(smmu)); writel_relaxed(smmu->priq.q.cons, - smmu->base + ARM_SMMU_PRIQ_CONS); + smmu->base + ARM_SMMU_PRIQ_CONS(smmu)); enables |= CR0_PRIQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, -- 1.9.1
next prev parent reply other threads:[~2017-04-11 14:43 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-04-11 14:42 [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds linucherian-Re5JQEeQqe8AvxtiuMwx3w 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-11 14:42 ` linucherian [this message] 2017-04-11 14:42 ` [RFC PATCH 1/7] iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for Silicon errata linucherian at gmail.com 2017-04-11 15:42 ` Robin Murphy 2017-04-11 15:42 ` Robin Murphy 2017-04-12 5:05 ` Linu Cherian 2017-04-12 5:05 ` Linu Cherian 2017-04-11 14:42 ` [RFC PATCH 2/7] iommu/arm-smmu-v3: Do resource size checks based on smmu option PAGE0_REGS_ONLY linucherian 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-11 15:43 ` Robin Murphy 2017-04-11 15:43 ` Robin Murphy 2017-04-11 16:39 ` Sunil Kovvuri 2017-04-11 16:39 ` Sunil Kovvuri 2017-04-11 14:42 ` [RFC PATCH 3/7] iommu/arm-smmu-v3: Introduce smmu option USE_SHARED_IRQS for Silicon errata linucherian 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-11 15:54 ` Robin Murphy 2017-04-11 15:54 ` Robin Murphy 2017-04-11 16:21 ` Will Deacon 2017-04-11 16:21 ` Will Deacon [not found] ` <20170411162123.GF17109-5wv7dgnIgG8@public.gmane.org> 2017-04-11 16:34 ` Sunil Kovvuri 2017-04-11 16:34 ` Sunil Kovvuri 2017-04-11 16:38 ` Robin Murphy 2017-04-11 16:38 ` Robin Murphy [not found] ` <a971af83-10f1-5696-f0c6-0600c04705c3-5wv7dgnIgG8@public.gmane.org> 2017-04-11 16:41 ` Will Deacon 2017-04-11 16:41 ` Will Deacon 2017-04-11 14:42 ` [RFC PATCH 4/7] ACPICA: IORT: Add SMMuV3 model definitions linucherian 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-11 15:59 ` Robin Murphy 2017-04-11 15:59 ` Robin Murphy 2017-04-11 16:57 ` Sunil Kovvuri 2017-04-11 16:57 ` Sunil Kovvuri 2017-04-12 2:33 ` Hanjun Guo 2017-04-12 2:33 ` [Devel] " Hanjun Guo 2017-04-12 2:33 ` Hanjun Guo 2017-04-12 15:21 ` Lorenzo Pieralisi 2017-04-12 15:21 ` Lorenzo Pieralisi 2017-04-11 14:42 ` [RFC PATCH 5/7] iommu/arm-smmu-v3: For ACPI based device probing, set relevant options for different SMMUv3 implementations linucherian 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-12 8:43 ` Robert Richter 2017-04-12 8:43 ` Robert Richter 2017-04-12 10:32 ` Linu Cherian 2017-04-12 10:32 ` Linu Cherian 2017-04-11 14:42 ` [RFC PATCH 6/7] ACPI/IORT: Fixup SMMUv3 resource size for Cavium 99xx SMMUv3 model linucherian 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-11 14:42 ` [RFC PATCH 7/7] arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas linucherian 2017-04-11 14:42 ` linucherian at gmail.com 2017-04-11 16:30 ` [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds Will Deacon 2017-04-11 16:30 ` Will Deacon
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1491921765-29475-2-git-send-email-linucherian@gmail.com \ --to=linucherian@gmail.com \ --cc=Geethasowjanya.Akula@cavium.com \ --cc=Sunil.Goutham@cavium.com \ --cc=catalin.marinas@arm.com \ --cc=devel@acpica.org \ --cc=hanjun.guo@linaro.org \ --cc=iommu@lists.linux-foundation.org \ --cc=joro@8bytes.org \ --cc=lenb@kernel.org \ --cc=linu.cherian@cavium.com \ --cc=linux-acpi@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=lorenzo.pieralisi@arm.com \ --cc=lv.zheng@intel.com \ --cc=rjw@rjwysocki.net \ --cc=robert.moore@intel.com \ --cc=robert.richter@cavium.com \ --cc=robin.murphy@arm.com \ --cc=sudeep.holla@arm.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.