From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
Date: Tue, 6 Jun 2017 08:19:53 +0000 [thread overview]
Message-ID: <1496737192.2428.52.camel@intel.com> (raw)
In-Reply-To: <e6406a78-4e6f-dab6-be28-f547d40a1907@denx.de>
On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote:
> On 06/06/2017 08:35 AM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > This patch is for enabling FPGA driver support on SPL
> Why would we want that on Gen5 ? I believe this is only needed on
> Gen10.
>
I already moved the fpga_manager driver into drivers/fpga/ on patch 6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > configs/socfpga_arria5_defconfig | 1 +
> > configs/socfpga_cyclone5_defconfig | 1 +
> > configs/socfpga_de0_nano_soc_defconfig | 1 +
> > configs/socfpga_de10_nano_defconfig | 1 +
> > configs/socfpga_de1_soc_defconfig | 1 +
> > configs/socfpga_is1_defconfig | 1 +
> > configs/socfpga_mcvevk_defconfig | 1 +
> > configs/socfpga_sockit_defconfig | 1 +
> > configs/socfpga_socrates_defconfig | 1 +
> > configs/socfpga_sr1500_defconfig | 1 +
> > configs/socfpga_vining_fpga_defconfig | 1 +
> > 11 files changed, 11 insertions(+)
> >
> > diff --git a/configs/socfpga_arria5_defconfig
> > b/configs/socfpga_arria5_defconfig
> > index 6f2a06f..4b1e252 100644
> > --- a/configs/socfpga_arria5_defconfig
> > +++ b/configs/socfpga_arria5_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_cyclone5_defconfig
> > b/configs/socfpga_cyclone5_defconfig
> > index 1047657..fe7ac08 100644
> > --- a/configs/socfpga_cyclone5_defconfig
> > +++ b/configs/socfpga_cyclone5_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_de0_nano_soc_defconfig
> > b/configs/socfpga_de0_nano_soc_defconfig
> > index 72a9e5d..d86a9d6 100644
> > --- a/configs/socfpga_de0_nano_soc_defconfig
> > +++ b/configs/socfpga_de0_nano_soc_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_de10_nano_defconfig
> > b/configs/socfpga_de10_nano_defconfig
> > index 67864cf..ac8ca70 100644
> > --- a/configs/socfpga_de10_nano_defconfig
> > +++ b/configs/socfpga_de10_nano_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_de1_soc_defconfig
> > b/configs/socfpga_de1_soc_defconfig
> > index 35c4484..cc0a35d 100644
> > --- a/configs/socfpga_de1_soc_defconfig
> > +++ b/configs/socfpga_de1_soc_defconfig
> > @@ -16,6 +16,7 @@ CONFIG_SPL=y
> > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_SPL_YMODEM_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > diff --git a/configs/socfpga_is1_defconfig
> > b/configs/socfpga_is1_defconfig
> > index ae688f8..ccfed7a 100644
> > --- a/configs/socfpga_is1_defconfig
> > +++ b/configs/socfpga_is1_defconfig
> > @@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
> > # CONFIG_DISPLAY_BOARDINFO is not set
> > CONFIG_SPL=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_mcvevk_defconfig
> > b/configs/socfpga_mcvevk_defconfig
> > index c5e3b7b..9bcb47d 100644
> > --- a/configs/socfpga_mcvevk_defconfig
> > +++ b/configs/socfpga_mcvevk_defconfig
> > @@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_sockit_defconfig
> > b/configs/socfpga_sockit_defconfig
> > index 3ff7bb7..ef54e1f 100644
> > --- a/configs/socfpga_sockit_defconfig
> > +++ b/configs/socfpga_sockit_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_socrates_defconfig
> > b/configs/socfpga_socrates_defconfig
> > index fb9c13f..78daf26 100644
> > --- a/configs/socfpga_socrates_defconfig
> > +++ b/configs/socfpga_socrates_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_sr1500_defconfig
> > b/configs/socfpga_sr1500_defconfig
> > index d90d6a1..4a12379 100644
> > --- a/configs/socfpga_sr1500_defconfig
> > +++ b/configs/socfpga_sr1500_defconfig
> > @@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> > diff --git a/configs/socfpga_vining_fpga_defconfig
> > b/configs/socfpga_vining_fpga_defconfig
> > index c3fbe40..3fc37dc 100644
> > --- a/configs/socfpga_vining_fpga_defconfig
> > +++ b/configs/socfpga_vining_fpga_defconfig
> > @@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
> > CONFIG_SPL=y
> > CONFIG_SPL_SYS_MALLOC_SIMPLE=y
> > CONFIG_SPL_STACK_R=y
> > +CONFIG_SPL_FPGA_SUPPORT=y
> > CONFIG_HUSH_PARSER=y
> > CONFIG_CMD_BOOTZ=y
> > # CONFIG_CMD_IMLS is not set
> >
>
next prev parent reply other threads:[~2017-06-06 8:19 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-06 6:35 [U-Boot] [PATCH v8 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 2/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 3/7] arm: socfpga: Convert all Intel related FPGA configuration to Kconfig tien.fong.chee at intel.com
2017-06-06 7:57 ` Marek Vasut
2017-06-06 8:16 ` Chee, Tien Fong
2017-06-06 8:32 ` Marek Vasut
2017-06-06 8:48 ` Chee, Tien Fong
2017-06-06 8:53 ` Marek Vasut
2017-06-06 9:40 ` Chee, Tien Fong
2017-06-06 6:35 ` [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL tien.fong.chee at intel.com
2017-06-06 8:03 ` Marek Vasut
2017-06-06 8:19 ` Chee, Tien Fong [this message]
2017-06-06 8:35 ` Marek Vasut
2017-06-06 9:36 ` Chee, Tien Fong
2017-06-06 9:41 ` Marek Vasut
2017-06-06 9:46 ` Chee, Tien Fong
2017-06-06 9:50 ` Marek Vasut
2017-06-07 3:06 ` Chee, Tien Fong
2017-06-07 6:36 ` Marek Vasut
2017-06-07 8:04 ` Chee, Tien Fong
2017-06-07 11:26 ` Chee, Tien Fong
2017-06-07 12:31 ` Marek Vasut
2017-06-08 3:40 ` Chee, Tien Fong
2017-06-08 12:14 ` Marek Vasut
2017-06-09 3:39 ` Chee, Tien Fong
2017-06-09 8:25 ` Marek Vasut
2017-06-09 13:52 ` Dinh Nguyen
2017-06-12 8:38 ` Chee, Tien Fong
2017-06-13 3:26 ` Chee, Tien Fong
2017-06-13 9:05 ` Marek Vasut
2017-06-14 5:35 ` Chee, Tien Fong
2017-06-19 10:32 ` Chee, Tien Fong
2017-06-19 13:18 ` Dinh Nguyen
2017-06-07 12:30 ` Marek Vasut
2017-06-06 6:35 ` [U-Boot] [PATCH v8 5/7] drivers: Enable FPGA driver build " tien.fong.chee at intel.com
2017-06-06 8:03 ` Marek Vasut
2017-06-06 8:26 ` Chee, Tien Fong
2017-06-06 8:35 ` Marek Vasut
2017-06-06 9:38 ` Chee, Tien Fong
2017-06-06 6:35 ` [U-Boot] [PATCH v8 6/7] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 7/7] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
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