From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 3/7] arm: socfpga: Convert all Intel related FPGA configuration to Kconfig
Date: Tue, 6 Jun 2017 09:57:44 +0200 [thread overview]
Message-ID: <9e4f38e3-e8d3-c34d-a541-33f0b28f8c4f@denx.de> (raw)
In-Reply-To: <1496730959-13353-4-git-send-email-tien.fong.chee@intel.com>
On 06/06/2017 08:35 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This converts the following to Kconfig:
> CONFIG_FPGA
> CONFIG_FPGA_ALTERA
> CONFIG_FPGA_SOCFPGA
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> configs/astro_mcf5373l_defconfig | 1 +
> configs/socfpga_arria5_defconfig | 1 +
> configs/socfpga_cyclone5_defconfig | 1 +
> configs/socfpga_de0_nano_soc_defconfig | 1 +
> configs/socfpga_de10_nano_defconfig | 1 +
> configs/socfpga_de1_soc_defconfig | 1 +
> configs/socfpga_is1_defconfig | 1 +
> configs/socfpga_mcvevk_defconfig | 1 +
> configs/socfpga_sockit_defconfig | 1 +
> configs/socfpga_socrates_defconfig | 1 +
> configs/socfpga_sr1500_defconfig | 1 +
> configs/socfpga_vining_fpga_defconfig | 1 +
> configs/theadorable_debug_defconfig | 1 +
> configs/theadorable_defconfig | 1 +
> drivers/fpga/Kconfig | 8 ++++++++
> include/configs/astro_mcf5373l.h | 2 --
> include/configs/socfpga_common.h | 3 ---
> include/configs/theadorable.h | 2 --
> 18 files changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig
> index d5e8430..80fb1fa 100644
> --- a/configs/astro_mcf5373l_defconfig
> +++ b/configs/astro_mcf5373l_defconfig
> @@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
> # CONFIG_CMD_NFS is not set
> CONFIG_CMD_CACHE=y
> CONFIG_CMD_DATE=y
> +CONFIG_FPGA_ALTERA=y
This MCF should be in separate patch, otherwise looks OK.
> CONFIG_MTD_NOR_FLASH=y
> diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
> index a565384..6f2a06f 100644
> --- a/configs/socfpga_arria5_defconfig
> +++ b/configs/socfpga_arria5_defconfig
> @@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
> index 06fc82c..1047657 100644
> --- a/configs/socfpga_cyclone5_defconfig
> +++ b/configs/socfpga_cyclone5_defconfig
> @@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
> index 0697e2e..72a9e5d 100644
> --- a/configs/socfpga_de0_nano_soc_defconfig
> +++ b/configs/socfpga_de0_nano_soc_defconfig
> @@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y
> CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
> index cd64fb9..67864cf 100644
> --- a/configs/socfpga_de10_nano_defconfig
> +++ b/configs/socfpga_de10_nano_defconfig
> @@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
> CONFIG_CMD_FS_GENERIC=y
> CONFIG_SPL_DM=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
> index bba90be..35c4484 100644
> --- a/configs/socfpga_de1_soc_defconfig
> +++ b/configs/socfpga_de1_soc_defconfig
> @@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
> CONFIG_CMD_FAT=y
> CONFIG_CMD_FS_GENERIC=y
> CONFIG_SPL_DM=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
> index 058791e..ae688f8 100644
> --- a/configs/socfpga_is1_defconfig
> +++ b/configs/socfpga_is1_defconfig
> @@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y
> CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
> index 627b90f..c5e3b7b 100644
> --- a/configs/socfpga_mcvevk_defconfig
> +++ b/configs/socfpga_mcvevk_defconfig
> @@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
> CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
> index bf5d63d..3ff7bb7 100644
> --- a/configs/socfpga_sockit_defconfig
> +++ b/configs/socfpga_sockit_defconfig
> @@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
> index 5915faf..fb9c13f 100644
> --- a/configs/socfpga_socrates_defconfig
> +++ b/configs/socfpga_socrates_defconfig
> @@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
> index 4468d3b..d90d6a1 100644
> --- a/configs/socfpga_sr1500_defconfig
> +++ b/configs/socfpga_sr1500_defconfig
> @@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
> CONFIG_CMD_UBI=y
> CONFIG_SPL_DM=y
> CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_SYS_I2C_DW=y
> diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
> index fb9bae4..c3fbe40 100644
> --- a/configs/socfpga_vining_fpga_defconfig
> +++ b/configs/socfpga_vining_fpga_defconfig
> @@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
> CONFIG_DFU_MMC=y
> CONFIG_DFU_RAM=y
> CONFIG_DFU_SF=y
> +CONFIG_FPGA_SOCFPGA=y
> CONFIG_DM_GPIO=y
> CONFIG_DWAPB_GPIO=y
> CONFIG_LED_STATUS=y
> diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
> index 2164237..e07b7b6 100644
> --- a/configs/theadorable_debug_defconfig
> +++ b/configs/theadorable_debug_defconfig
> @@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
> # CONFIG_SPL_PARTITION_UUIDS is not set
> CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_SPL_OF_TRANSLATE=y
> +CONFIG_FPGA_ALTERA=y
> CONFIG_DM_GPIO=y
> # CONFIG_MMC is not set
> CONFIG_SPI_FLASH=y
> diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
> index d5eef70..3d2977c 100644
> --- a/configs/theadorable_defconfig
> +++ b/configs/theadorable_defconfig
> @@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
> # CONFIG_PARTITION_UUIDS is not set
> # CONFIG_SPL_PARTITION_UUIDS is not set
> CONFIG_SPL_OF_TRANSLATE=y
> +CONFIG_FPGA_ALTERA=y
> CONFIG_DM_GPIO=y
> # CONFIG_MMC is not set
> CONFIG_SPI_FLASH=y
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index a760944..6b2c866 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -13,6 +13,14 @@ config FPGA_ALTERA
> Enable Altera FPGA specific functions which includes bitstream
> (in BIT format), fpga and device validation.
>
> +config FPGA_SOCFPGA
> + bool "Enable Gen5 and Arria10 common FPGA drivers"
> + select FPGA_ALTERA
> + help
> + Say Y here to enable the Gen5 and Arria10 common FPGA driver
> +
> + This provides common functionality for Gen5 and Arria10 devices.
> +
> config FPGA_CYCLON2
> bool "Enable Altera FPGA driver for Cyclone II"
> depends on FPGA_ALTERA
> diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
> index 8899579..f4acea1 100644
> --- a/include/configs/astro_mcf5373l.h
> +++ b/include/configs/astro_mcf5373l.h
> @@ -201,10 +201,8 @@
> #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>
> #define CONFIG_FPGA_COUNT 1
> -#define CONFIG_FPGA
> #define CONFIG_FPGA_XILINX
> #define CONFIG_FPGA_SPARTAN3
> -#define CONFIG_FPGA_ALTERA
> #define CONFIG_FPGA_CYCLON2
> #define CONFIG_SYS_FPGA_PROG_FEEDBACK
> #define CONFIG_SYS_FPGA_WAIT 1000
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index da7e4ad..1b79c03 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -107,9 +107,6 @@
> */
> #ifdef CONFIG_TARGET_SOCFPGA_GEN5
> #ifdef CONFIG_CMD_FPGA
> -#define CONFIG_FPGA
> -#define CONFIG_FPGA_ALTERA
> -#define CONFIG_FPGA_SOCFPGA
> #define CONFIG_FPGA_COUNT 1
> #endif
> #endif
> diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
> index 2a671e8..5459f4f 100644
> --- a/include/configs/theadorable.h
> +++ b/include/configs/theadorable.h
> @@ -89,8 +89,6 @@
> #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
>
> /* FPGA programming support */
> -#define CONFIG_FPGA
> -#define CONFIG_FPGA_ALTERA
> #define CONFIG_FPGA_STRATIX_V
>
> /*
>
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2017-06-06 7:57 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-06 6:35 [U-Boot] [PATCH v8 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 2/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 3/7] arm: socfpga: Convert all Intel related FPGA configuration to Kconfig tien.fong.chee at intel.com
2017-06-06 7:57 ` Marek Vasut [this message]
2017-06-06 8:16 ` Chee, Tien Fong
2017-06-06 8:32 ` Marek Vasut
2017-06-06 8:48 ` Chee, Tien Fong
2017-06-06 8:53 ` Marek Vasut
2017-06-06 9:40 ` Chee, Tien Fong
2017-06-06 6:35 ` [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL tien.fong.chee at intel.com
2017-06-06 8:03 ` Marek Vasut
2017-06-06 8:19 ` Chee, Tien Fong
2017-06-06 8:35 ` Marek Vasut
2017-06-06 9:36 ` Chee, Tien Fong
2017-06-06 9:41 ` Marek Vasut
2017-06-06 9:46 ` Chee, Tien Fong
2017-06-06 9:50 ` Marek Vasut
2017-06-07 3:06 ` Chee, Tien Fong
2017-06-07 6:36 ` Marek Vasut
2017-06-07 8:04 ` Chee, Tien Fong
2017-06-07 11:26 ` Chee, Tien Fong
2017-06-07 12:31 ` Marek Vasut
2017-06-08 3:40 ` Chee, Tien Fong
2017-06-08 12:14 ` Marek Vasut
2017-06-09 3:39 ` Chee, Tien Fong
2017-06-09 8:25 ` Marek Vasut
2017-06-09 13:52 ` Dinh Nguyen
2017-06-12 8:38 ` Chee, Tien Fong
2017-06-13 3:26 ` Chee, Tien Fong
2017-06-13 9:05 ` Marek Vasut
2017-06-14 5:35 ` Chee, Tien Fong
2017-06-19 10:32 ` Chee, Tien Fong
2017-06-19 13:18 ` Dinh Nguyen
2017-06-07 12:30 ` Marek Vasut
2017-06-06 6:35 ` [U-Boot] [PATCH v8 5/7] drivers: Enable FPGA driver build " tien.fong.chee at intel.com
2017-06-06 8:03 ` Marek Vasut
2017-06-06 8:26 ` Chee, Tien Fong
2017-06-06 8:35 ` Marek Vasut
2017-06-06 9:38 ` Chee, Tien Fong
2017-06-06 6:35 ` [U-Boot] [PATCH v8 6/7] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 7/7] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
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