* [PATCH 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 02/14] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
` (14 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
skl_wm_values struct contains values os pipe/plane DDB only.
so rename it for better readability of code.
s/skl_wm_values/skl_ddb_values
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 770305b..1b5cf18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1851,7 +1851,7 @@ struct skl_ddb_allocation {
struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
-struct skl_wm_values {
+struct skl_ddb_values {
unsigned dirty_pipes;
struct skl_ddb_allocation ddb;
};
@@ -2511,7 +2511,7 @@ struct drm_i915_private {
/* current hardware state */
union {
struct ilk_wm_values hw;
- struct skl_wm_values skl_hw;
+ struct skl_ddb_values skl_hw;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667..160fded 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -396,7 +396,7 @@ struct intel_atomic_state {
bool skip_intermediate_wm;
/* Gen9+ only */
- struct skl_wm_values wm_results;
+ struct skl_ddb_values wm_results;
struct i915_sw_fence commit_ready;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9d0ca26..029487d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4981,8 +4981,8 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
}
static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
- struct skl_wm_values *src,
+skl_copy_wm_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
enum pipe pipe)
{
memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5034,7 +5034,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
struct drm_crtc *crtc;
struct drm_crtc_state *cstate;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- struct skl_wm_values *results = &intel_state->wm_results;
+ struct skl_ddb_values *results = &intel_state->wm_results;
struct drm_device *dev = state->dev;
struct skl_pipe_wm *pipe_wm;
bool changed = false;
@@ -5136,8 +5136,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *results = &state->wm_results;
- struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *results = &state->wm_results;
+ struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
enum pipe pipe = intel_crtc->pipe;
if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5280,7 +5280,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
void skl_wm_get_hw_state(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+ struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct drm_crtc *crtc;
struct intel_crtc *intel_crtc;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 02/14] drm/i915/skl+: refactore WM calculation for NV12
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
2017-10-10 12:17 ` [PATCH 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
` (13 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 120 +++++++++++++++++++--------------------
3 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1b5cf18..090832c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1848,7 +1848,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
struct skl_ddb_allocation {
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
- struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+ struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 160fded..f897580 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -510,6 +510,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level trans_wm;
+ bool is_nv12;
};
struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 029487d..b09d81b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3990,9 +3990,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
static unsigned int
skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
const struct drm_plane_state *pstate,
- int y)
+ const int plane)
{
- struct intel_plane *plane = to_intel_plane(pstate->plane);
+ struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
uint32_t data_rate;
uint32_t width = 0, height = 0;
@@ -4006,9 +4006,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
fb = pstate->fb;
format = fb->format->format;
- if (plane->id == PLANE_CURSOR)
+ if (intel_plane->id == PLANE_CURSOR)
return 0;
- if (y && format != DRM_FORMAT_NV12)
+ if (plane == 1 && format != DRM_FORMAT_NV12)
return 0;
/*
@@ -4019,19 +4019,14 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
width = drm_rect_width(&intel_pstate->base.src) >> 16;
height = drm_rect_height(&intel_pstate->base.src) >> 16;
- /* for planar format */
- if (format == DRM_FORMAT_NV12) {
- if (y) /* y-plane data rate */
- data_rate = width * height *
- fb->format->cpp[0];
- else /* uv-plane data rate */
- data_rate = (width / 2) * (height / 2) *
- fb->format->cpp[1];
- } else {
- /* for packed formats */
- data_rate = width * height * fb->format->cpp[0];
+ /* UV plane does 1/2 pixel sub-sampling */
+ if (plane == 1 && format == DRM_FORMAT_NV12) {
+ width /= 2;
+ height /= 2;
}
+ data_rate = width * height * fb->format->cpp[plane];
+
down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4044,8 +4039,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
*/
static unsigned int
skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
- unsigned *plane_data_rate,
- unsigned *plane_y_data_rate)
+ unsigned int *plane_data_rate,
+ unsigned int *uv_plane_data_rate)
{
struct drm_crtc_state *cstate = &intel_cstate->base;
struct drm_atomic_state *state = cstate->state;
@@ -4061,17 +4056,16 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
enum plane_id plane_id = to_intel_plane(plane)->id;
unsigned int rate;
- /* packed/uv */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 0);
plane_data_rate[plane_id] = rate;
total_data_rate += rate;
- /* y-plane */
+ /* uv-plane */
rate = skl_plane_relative_data_rate(intel_cstate,
pstate, 1);
- plane_y_data_rate[plane_id] = rate;
+ uv_plane_data_rate[plane_id] = rate;
total_data_rate += rate;
}
@@ -4080,8 +4074,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
}
static uint16_t
-skl_ddb_min_alloc(const struct drm_plane_state *pstate,
- const int y)
+skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
{
struct drm_framebuffer *fb = pstate->fb;
struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
@@ -4092,8 +4085,8 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
if (WARN_ON(!fb))
return 0;
- /* For packed formats, no y-plane, return 0 */
- if (y && fb->format->format != DRM_FORMAT_NV12)
+ /* For packed formats, and uv-plane, return 0 */
+ if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
return 0;
/* For Non Y-tile return 8-blocks */
@@ -4112,15 +4105,12 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
/* Halve UV plane width and height for NV12 */
- if (fb->format->format == DRM_FORMAT_NV12 && !y) {
+ if (plane == 1) {
src_w /= 2;
src_h /= 2;
}
- if (fb->format->format == DRM_FORMAT_NV12 && !y)
- plane_bpp = fb->format->cpp[1];
- else
- plane_bpp = fb->format->cpp[0];
+ plane_bpp = fb->format->cpp[plane];
if (drm_rotation_90_or_270(pstate->rotation)) {
switch (plane_bpp) {
@@ -4148,7 +4138,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
static void
skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
- uint16_t *minimum, uint16_t *y_minimum)
+ uint16_t *minimum, uint16_t *uv_minimum)
{
const struct drm_plane_state *pstate;
struct drm_plane *plane;
@@ -4163,7 +4153,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
continue;
minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
- y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
+ uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
}
minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -4181,17 +4171,17 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
uint16_t alloc_size, start;
uint16_t minimum[I915_MAX_PLANES] = {};
- uint16_t y_minimum[I915_MAX_PLANES] = {};
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
unsigned int total_data_rate;
enum plane_id plane_id;
int num_active;
- unsigned plane_data_rate[I915_MAX_PLANES] = {};
- unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
+ unsigned int plane_data_rate[I915_MAX_PLANES] = {};
+ unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
uint16_t total_min_blocks = 0;
/* Clear the partitioning for disabled planes. */
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
- memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
+ memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
if (WARN_ON(!state))
return 0;
@@ -4206,7 +4196,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
if (alloc_size == 0)
return 0;
- skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
+ skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
/*
* 1. Allocate the mininum required blocks for each active plane
@@ -4216,7 +4206,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
total_min_blocks += minimum[plane_id];
- total_min_blocks += y_minimum[plane_id];
+ total_min_blocks += uv_minimum[plane_id];
}
if (total_min_blocks > alloc_size) {
@@ -4238,14 +4228,14 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
*/
total_data_rate = skl_get_total_relative_data_rate(cstate,
plane_data_rate,
- plane_y_data_rate);
+ uv_plane_data_rate);
if (total_data_rate == 0)
return 0;
start = alloc->start;
for_each_plane_id_on_crtc(intel_crtc, plane_id) {
- unsigned int data_rate, y_data_rate;
- uint16_t plane_blocks, y_plane_blocks = 0;
+ unsigned int data_rate, uv_data_rate;
+ uint16_t plane_blocks, uv_plane_blocks;
if (plane_id == PLANE_CURSOR)
continue;
@@ -4269,21 +4259,20 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
start += plane_blocks;
- /*
- * allocation for y_plane part of planar format:
- */
- y_data_rate = plane_y_data_rate[plane_id];
+ /* Allocate DDB for UV plane for planar format/NV12 */
+ uv_data_rate = uv_plane_data_rate[plane_id];
- y_plane_blocks = y_minimum[plane_id];
- y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
+ uv_plane_blocks = uv_minimum[plane_id];
+ uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
total_data_rate);
- if (y_data_rate) {
- ddb->y_plane[pipe][plane_id].start = start;
- ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
+ if (uv_data_rate) {
+ ddb->uv_plane[pipe][plane_id].start = start;
+ ddb->uv_plane[pipe][plane_id].end = start +
+ uv_plane_blocks;
}
- start += y_plane_blocks;
+ start += uv_plane_blocks;
}
return 0;
@@ -4411,8 +4400,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
- fb->format->cpp[0];
+ wp->cpp = fb->format->cpp[0];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4604,6 +4592,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
return ret;
}
+ if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
+ wm->is_nv12 = true;
+
return 0;
}
@@ -4774,10 +4765,19 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
- skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
- &ddb->plane[pipe][plane_id]);
- skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
- &ddb->y_plane[pipe][plane_id]);
+ if (wm->is_nv12) {
+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->uv_plane[pipe][plane_id]);
+ skl_ddb_entry_write(dev_priv,
+ PLANE_NV12_BUF_CFG(pipe, plane_id),
+ &ddb->plane[pipe][plane_id]);
+ } else {
+ skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+ &ddb->plane[pipe][plane_id]);
+ skl_ddb_entry_write(dev_priv,
+ PLANE_NV12_BUF_CFG(pipe, plane_id),
+ &ddb->uv_plane[pipe][plane_id]);
+ }
}
static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -4890,8 +4890,8 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
&new_ddb->plane[pipe][plane_id]) &&
- skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
- &new_ddb->y_plane[pipe][plane_id]))
+ skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
+ &new_ddb->uv_plane[pipe][plane_id]))
continue;
plane_state = drm_atomic_get_plane_state(state, plane);
@@ -4985,8 +4985,8 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
struct skl_ddb_values *src,
enum pipe pipe)
{
- memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
- sizeof(dst->ddb.y_plane[pipe]));
+ memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
+ sizeof(dst->ddb.uv_plane[pipe]));
memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
sizeof(dst->ddb.plane[pipe]));
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
2017-10-10 12:17 ` [PATCH 01/14] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2017-10-10 12:17 ` [PATCH 02/14] drm/i915/skl+: refactore WM calculation for NV12 Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 04/14] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
` (12 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 45d6e57..36c2640 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2708,6 +2708,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
return DRM_FORMAT_RGB565;
+ case PLANE_CTL_FORMAT_NV12:
+ return DRM_FORMAT_NV12;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 04/14] drm/i915/skl+: support varification of DDB HW state for NV12
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (2 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 03/14] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 05/14] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
` (11 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
NV12 formats have two registers for DDB. verify both the registers for
NV12 during verify_wm_state.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 50 ++++++++++++++++++++++++++++--------
3 files changed, 42 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 36c2640..a10bbe8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2703,7 +2703,7 @@ static int i9xx_format_to_fourcc(int format)
}
}
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f897580..4f98684 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1502,6 +1502,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
unsigned int rotation);
int skl_check_plane_surface(struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
/* intel_csr.c */
void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b09d81b..ac4bba1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3807,6 +3807,43 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
entry->end += 1;
}
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+ const enum pipe pipe,
+ const enum plane_id plane_id,
+ struct skl_ddb_allocation *ddb /* out */)
+{
+ u32 val, val2 = 0;
+ int fourcc, pixel_format;
+
+ /* Cursor doesn't support NV12, so no extra calculation needed */
+ if (plane_id == PLANE_CURSOR) {
+ val = I915_READ(CUR_BUF_CFG(pipe));
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+ return;
+ }
+
+ val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+ /* No DDB allocated for disabled planes */
+ if (!(val & PLANE_CTL_ENABLE))
+ return;
+
+ pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ fourcc = skl_format_to_fourcc(pixel_format,
+ val & PLANE_CTL_ORDER_RGBX,
+ val & PLANE_CTL_ALPHA_MASK);
+
+ val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+ val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+ if (fourcc == DRM_FORMAT_NV12) {
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+ skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+ } else
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+}
+
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */)
{
@@ -3823,16 +3860,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
- for_each_plane_id_on_crtc(crtc, plane_id) {
- u32 val;
-
- if (plane_id != PLANE_CURSOR)
- val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
- else
- val = I915_READ(CUR_BUF_CFG(pipe));
-
- skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
- }
+ for_each_plane_id_on_crtc(crtc, plane_id)
+ skl_ddb_get_hw_plane_state(dev_priv, pipe,
+ plane_id, ddb);
intel_display_power_put(dev_priv, power_domain);
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 05/14] drm/i915/skl+: NV12 related changes for WM
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (3 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 04/14] drm/i915/skl+: support varification of DDB HW state for NV12 Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
` (10 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
NV12 require WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 54 ++++++++++++++++++++++++++++++++--------
3 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 090832c..e697ead 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1866,6 +1866,7 @@ struct skl_wm_level {
struct skl_wm_params {
bool x_tiled, y_tiled;
bool rc_surface;
+ bool is_nv12;
uint32_t width;
uint8_t cpp;
uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4f98684..51ae058 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -509,6 +509,7 @@ struct intel_pipe_wm {
struct skl_plane_wm {
struct skl_wm_level wm[8];
+ struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
bool is_nv12;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac4bba1..7b3160c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4398,7 +4398,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
- struct skl_wm_params *wp)
+ struct skl_wm_params *wp, int plane_num)
{
struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4411,6 +4411,12 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
if (!intel_wm_plane_visible(cstate, intel_pstate))
return 0;
+ /* only NV12 format has two planes */
+ if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+ DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+ return -EINVAL;
+ }
+
wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4418,6 +4424,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+ wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4430,7 +4437,10 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
}
- wp->cpp = fb->format->cpp[0];
+ if (plane_num == 1 && wp->is_nv12)
+ wp->width /= 2;
+
+ wp->cpp = fb->format->cpp[plane_num];
wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
intel_pstate);
@@ -4591,7 +4601,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
const struct intel_plane_state *intel_pstate,
const struct skl_wm_params *wm_params,
- struct skl_plane_wm *wm)
+ struct skl_plane_wm *wm,
+ int plane_num)
{
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
struct drm_plane *plane = intel_pstate->base.plane;
@@ -4599,15 +4610,20 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_blocks;
enum pipe pipe = intel_crtc->pipe;
int level, max_level = ilk_wm_max_level(dev_priv);
+ enum plane_id plane_id = intel_plane->id;
int ret;
if (WARN_ON(!intel_pstate->base.fb))
return -EINVAL;
- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
+ if (plane_num == 0)
+ ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+ else
+ ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
for (level = 0; level <= max_level; level++) {
- struct skl_wm_level *result = &wm->wm[level];
+ struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
+ &wm->wm[level];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4622,9 +4638,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
return ret;
}
- if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
- wm->is_nv12 = true;
-
return 0;
}
@@ -4733,20 +4746,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
wm = &pipe_wm->planes[plane_id];
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
- memset(&wm_params, 0, sizeof(struct skl_wm_params));
ret = skl_compute_plane_wm_params(dev_priv, cstate,
- intel_pstate, &wm_params);
+ intel_pstate, &wm_params, 0);
if (ret)
return ret;
ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
- intel_pstate, &wm_params, wm);
+ intel_pstate, &wm_params, wm, 0);
if (ret)
return ret;
+
skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
ddb_blocks, &wm->trans_wm);
+
+ /* uv plane watermarks must also be validated for NV12 */
+ if (wm_params.is_nv12) {
+ memset(&wm_params, 0, sizeof(struct skl_wm_params));
+ wm->is_nv12 = true;
+
+ ret = skl_compute_plane_wm_params(dev_priv, cstate,
+ intel_pstate,
+ &wm_params, 1);
+ if (ret)
+ return ret;
+
+ ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
+ intel_pstate, &wm_params,
+ wm, 1);
+ if (ret)
+ return ret;
+ }
}
+
pipe_wm->linetime = skl_compute_linetime_wm(cstate);
return 0;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (4 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 05/14] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
` (9 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
This will reduce number of arguments required to be pass in
skl_compute_plane_wm function.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7b3160c..e931e4a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4499,9 +4499,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
- uint16_t *out_blocks, /* out */
- uint8_t *out_lines, /* out */
- bool *enabled /* out */)
+ struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4514,7 +4512,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
if (latency == 0 ||
!intel_wm_plane_visible(cstate, intel_pstate)) {
- *enabled = false;
+ result->plane_en = false;
return 0;
}
@@ -4569,7 +4567,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
if (res_blocks >= ddb_allocation || res_lines > 31) {
- *enabled = false;
+ result->plane_en = false;
/*
* If there are no valid level 0 watermarks, then we can't
@@ -4588,9 +4586,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
- *out_blocks = res_blocks;
- *out_lines = res_lines;
- *enabled = true;
+ result->plane_res_b = res_blocks;
+ result->plane_res_l = res_lines;
+ result->plane_en = true;
return 0;
}
@@ -4631,9 +4629,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
- &result->plane_res_b,
- &result->plane_res_l,
- &result->plane_en);
+ result);
if (ret)
return ret;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (5 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 06/14] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
` (8 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
DDB allocation optimization algorithm require/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression require level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e931e4a..c99639b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4499,6 +4499,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+ const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4564,6 +4565,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+ /*
+ * Make sure result blocks for higher latency levels are atleast
+ * as high as level below.
+ * Assumption in DDB algorithm optimization for special cases.
+ * Also covers Display WA #1125 for RC.
+ */
+ if (result_prev->plane_res_b > res_blocks)
+ res_blocks = result_prev->plane_res_b;
}
if (res_blocks >= ddb_allocation || res_lines > 31) {
@@ -4622,6 +4632,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
&wm->wm[level];
+ struct skl_wm_level *result_prev;
+
+ if (level)
+ result_prev = plane_num ? &wm->uv_wm[level - 1] :
+ &wm->wm[level - 1];
+ else
+ result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4629,6 +4646,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
+ result_prev,
result);
if (ret)
return ret;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (6 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 09/14] drm/i915: Set scaler mode for NV12 Vidya Srinivas
` (7 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx
From: Mahesh Kumar <mahesh1.kumar@intel.com>
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c99639b..7117011 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4596,6 +4596,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
}
}
+ /*
+ * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+ * disable wm level 1-7 on NV12 planes
+ */
+ if (wp->is_nv12 && level && (IS_SKYLAKE(dev_priv) ||
+ IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+ result->plane_en = false;
+ return 0;
+ }
+
result->plane_res_b = res_blocks;
result->plane_res_l = res_lines;
result->plane_en = true;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 09/14] drm/i915: Set scaler mode for NV12
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (7 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 13:53 ` Mahesh Kumar
2017-10-10 12:17 ` [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
` (6 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler
v3: Rebased (me)
v4: Rebased (me)
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50e65c9..976b501 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6607,6 +6607,7 @@ enum {
#define PS_SCALER_MODE_MASK (3 << 28)
#define PS_SCALER_MODE_DYN (0 << 28)
#define PS_SCALER_MODE_HQ (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
#define PS_PLANE_SEL_MASK (7 << 25)
#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 36d4e63..606b5e3 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
}
/* set scaler mode */
- if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ plane_state && plane_state->base.fb &&
+ plane_state->base.fb->format->format ==
+ DRM_FORMAT_NV12) {
+ scaler_state->scalers[*scaler_id].mode =
+ PS_SCALER_MODE_NV12;
+ } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
scaler_state->scalers[*scaler_id].mode = 0;
} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
/*
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 09/14] drm/i915: Set scaler mode for NV12
2017-10-10 12:17 ` [PATCH 09/14] drm/i915: Set scaler mode for NV12 Vidya Srinivas
@ 2017-10-10 13:53 ` Mahesh Kumar
2017-10-10 20:24 ` Srinivas, Vidya
0 siblings, 1 reply; 27+ messages in thread
From: Mahesh Kumar @ 2017-10-10 13:53 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Hi,
On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch sets appropriate scaler mode for NV12 format.
> In this mode, skylake scaler does either chroma-upsampling or
> chroma-upsampling and resolution scaling
>
> v2: Review comments from Ville addressed
> NV12 case to be checked first for setting
> the scaler
>
> v3: Rebased (me)
>
> v4: Rebased (me)
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v6: Rebased (me)
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> Restricting the NV12 change for scaler to BXT and KBL
> in this series.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 50e65c9..976b501 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6607,6 +6607,7 @@ enum {
> #define PS_SCALER_MODE_MASK (3 << 28)
> #define PS_SCALER_MODE_DYN (0 << 28)
> #define PS_SCALER_MODE_HQ (1 << 28)
> +#define PS_SCALER_MODE_NV12 (2 << 28)
> #define PS_PLANE_SEL_MASK (7 << 25)
> #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> #define PS_FILTER_MASK (3 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 36d4e63..606b5e3 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> }
>
> /* set scaler mode */
> - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + plane_state && plane_state->base.fb &&
> + plane_state->base.fb->format->format ==
> + DRM_FORMAT_NV12) {
> + scaler_state->scalers[*scaler_id].mode =
> + PS_SCALER_MODE_NV12;
> + } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> scaler_state->scalers[*scaler_id].mode = 0;
IN CNL for NV12 (planar formats) bit 29 of PS_CTRL register should be
set to 1b. This require respective change in
skylake_update_primary_plane & skl_update_plane as well.
please take care of that.
better like plane_ctl calculate ps_ctl in advance only & write during
plane_update.
-Mahesh
> } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
> /*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 09/14] drm/i915: Set scaler mode for NV12
2017-10-10 13:53 ` Mahesh Kumar
@ 2017-10-10 20:24 ` Srinivas, Vidya
0 siblings, 0 replies; 27+ messages in thread
From: Srinivas, Vidya @ 2017-10-10 20:24 UTC (permalink / raw)
To: Kumar, Mahesh1, intel-gfx
> -----Original Message-----
> From: Kumar, Mahesh1
> Sent: Tuesday, October 10, 2017 7:24 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Maiti, Nabendu Bikash <nabendu.bikash.maiti@intel.com>
> Subject: Re: [PATCH 09/14] drm/i915: Set scaler mode for NV12
>
> Hi,
>
>
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch sets appropriate scaler mode for NV12 format.
> > In this mode, skylake scaler does either chroma-upsampling or
> > chroma-upsampling and resolution scaling
> >
> > v2: Review comments from Ville addressed
> > NV12 case to be checked first for setting
> > the scaler
> >
> > v3: Rebased (me)
> >
> > v4: Rebased (me)
> >
> > v5: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v6: Rebased (me)
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> > Restricting the NV12 change for scaler to BXT and KBL
> > in this series.
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++-
> > 2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 50e65c9..976b501 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6607,6 +6607,7 @@ enum {
> > #define PS_SCALER_MODE_MASK (3 << 28)
> > #define PS_SCALER_MODE_DYN (0 << 28)
> > #define PS_SCALER_MODE_HQ (1 << 28)
> > +#define PS_SCALER_MODE_NV12 (2 << 28)
> > #define PS_PLANE_SEL_MASK (7 << 25)
> > #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
> > #define PS_FILTER_MASK (3 << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_atomic.c
> > b/drivers/gpu/drm/i915/intel_atomic.c
> > index 36d4e63..606b5e3 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic.c
> > @@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct
> drm_i915_private *dev_priv,
> > }
> >
> > /* set scaler mode */
> > - if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
> {
> > + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> > + plane_state && plane_state->base.fb &&
> > + plane_state->base.fb->format->format ==
> > + DRM_FORMAT_NV12) {
> > + scaler_state->scalers[*scaler_id].mode =
> > + PS_SCALER_MODE_NV12;
> > + } else if (IS_GEMINILAKE(dev_priv) ||
> IS_CANNONLAKE(dev_priv)) {
> > scaler_state->scalers[*scaler_id].mode = 0;
> IN CNL for NV12 (planar formats) bit 29 of PS_CTRL register should be set to
> 1b. This require respective change in skylake_update_primary_plane &
> skl_update_plane as well.
> please take care of that.
> better like plane_ctl calculate ps_ctl in advance only & write during
> plane_update.
Thank you. I tested the series currently only on BXT APL and the patches were also tested by other teams on KBL.
That’s why did not add changes for other platforms yet. Was planning to add them as enhancement.
>
> -Mahesh
> > } else if (num_scalers_need == 1 && intel_crtc->pipe !=
> PIPE_C) {
> > /*
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (8 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 09/14] drm/i915: Set scaler mode for NV12 Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:17 ` [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
` (5 subsequent siblings)
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to format_is_yuv() function
for sprite planes.
v2:
-Use intel_ prefix for format_is_yuv (Ville)
v3: Rebased (me)
v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v6: Rebased (me)
v7: Rebased (me)
v8: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_sprite.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index b0d6e3e..091bb42 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -42,13 +42,14 @@
#include "i915_drv.h"
static bool
-format_is_yuv(uint32_t format)
+intel_format_is_yuv(uint32_t format)
{
switch (format) {
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_NV12:
return true;
default:
return false;
@@ -330,7 +331,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
enum plane_id plane_id = plane->id;
/* Seems RGB data bypasses the CSC always */
- if (!format_is_yuv(format))
+ if (!intel_format_is_yuv(format))
return;
/*
@@ -894,7 +895,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
src_y = src->y1 >> 16;
src_h = drm_rect_height(src) >> 16;
- if (format_is_yuv(fb->format->format)) {
+ if (intel_format_is_yuv(fb->format->format)) {
src_x &= ~1;
src_w &= ~1;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (9 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 14:05 ` Mahesh Kumar
2017-10-10 12:17 ` [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
` (4 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch updates scaler max limit support for NV12
v2: Rebased (me)
v3: Rebased (me)
v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series
v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.
v7: Rebased (me)
v8: Rebased (me)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++----------
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
3 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a10bbe8..f71a704 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3472,6 +3472,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
case DRM_FORMAT_VYUY:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ case DRM_FORMAT_NV12:
+ return PLANE_CTL_FORMAT_NV12;
default:
MISSING_CASE(pixel_format);
}
@@ -4727,7 +4729,8 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
static int
skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
unsigned int scaler_user, int *scaler_id,
- int src_w, int src_h, int dst_w, int dst_h)
+ int src_w, int src_h, int dst_w, int dst_h,
+ uint32_t pixel_format)
{
struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
@@ -4743,7 +4746,8 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
* the 90/270 degree plane rotation cases (to match the
* GTT mapping), hence no need to account for rotation here.
*/
- need_scaling = src_w != dst_w || src_h != dst_h;
+ need_scaling = src_w != dst_w || src_h != dst_h ||
+ (pixel_format == DRM_FORMAT_NV12);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4822,7 +4826,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
&state->scaler_state.scaler_id,
state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+ adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
}
/**
@@ -4852,7 +4856,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
drm_rect_width(&plane_state->base.src) >> 16,
drm_rect_height(&plane_state->base.src) >> 16,
drm_rect_width(&plane_state->base.dst),
- drm_rect_height(&plane_state->base.dst));
+ drm_rect_height(&plane_state->base.dst),
+ fb ? fb->format->format : 0);
if (ret || plane_state->scaler_id < 0)
return ret;
@@ -4878,6 +4883,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV12:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -12799,11 +12805,12 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, uint32_t pixel_format)
{
struct drm_i915_private *dev_priv;
- int max_scale;
- int crtc_clock, max_dotclk;
+ int max_scale, mult;
+ int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
@@ -12825,8 +12832,10 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
* or
* cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1,
- (1 << 8) * ((max_dotclk << 8) / crtc_clock));
+ mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ tmpclk1 = (1 << 16) * mult - 1;
+ tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
+ max_scale = min(tmpclk1, tmpclk2);
return max_scale;
}
@@ -12847,7 +12856,11 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
/* use scaler when colorkey is not required */
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
min_scale = 1;
- max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+ max_scale = skl_max_scale(to_intel_crtc(crtc),
+ crtc_state,
+ state->base.fb ?
+ state->base.fb->format->format :
+ 0);
}
can_position = true;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 51ae058..fd60635 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1490,7 +1490,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
struct intel_crtc_state *pipe_config);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+ uint32_t pixel_format);
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
{
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 091bb42..6f98bc5 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -817,7 +817,8 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
can_scale = 1;
min_scale = 1;
- max_scale = skl_max_scale(crtc, crtc_state);
+ max_scale = skl_max_scale(crtc, crtc_state,
+ fb->format->format);
} else {
can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12
2017-10-10 12:17 ` [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
@ 2017-10-10 14:05 ` Mahesh Kumar
2017-10-10 20:26 ` Srinivas, Vidya
0 siblings, 1 reply; 27+ messages in thread
From: Mahesh Kumar @ 2017-10-10 14:05 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch updates scaler max limit support for NV12
>
> v2: Rebased (me)
>
> v3: Rebased (me)
>
> v4: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v5: Addressed review comments from Ville and rebased
> - calculation of max_scale to be made
> less convoluted by splitting it up a bit
> - Indentation errors to be fixed in the series
>
> v6: Rebased (me)
> Fixed review comments from Paauwe, Bob J
> Previous version, where a split of calculation
> was done, was wrong. Fixed that issue here.
>
> v7: Rebased (me)
>
> v8: Rebased (me)
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++----------
> drivers/gpu/drm/i915/intel_drv.h | 3 ++-
> drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
> 3 files changed, 27 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a10bbe8..f71a704 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3472,6 +3472,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> case DRM_FORMAT_VYUY:
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> + case DRM_FORMAT_NV12:
> + return PLANE_CTL_FORMAT_NV12;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4727,7 +4729,8 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
> static int
> skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> unsigned int scaler_user, int *scaler_id,
> - int src_w, int src_h, int dst_w, int dst_h)
> + int src_w, int src_h, int dst_w, int dst_h,
> + uint32_t pixel_format)
> {
> struct intel_crtc_scaler_state *scaler_state =
> &crtc_state->scaler_state;
> @@ -4743,7 +4746,8 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
> * the 90/270 degree plane rotation cases (to match the
> * GTT mapping), hence no need to account for rotation here.
> */
> - need_scaling = src_w != dst_w || src_h != dst_h;
> + need_scaling = src_w != dst_w || src_h != dst_h ||
> + (pixel_format == DRM_FORMAT_NV12);
IMHO keep nv12 check separate from rest of src/dst_w/h checks.
>
> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
> @@ -4822,7 +4826,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
> return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
> &state->scaler_state.scaler_id,
> state->pipe_src_w, state->pipe_src_h,
> - adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
> + adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
> }
>
> /**
> @@ -4852,7 +4856,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> drm_rect_width(&plane_state->base.src) >> 16,
> drm_rect_height(&plane_state->base.src) >> 16,
> drm_rect_width(&plane_state->base.dst),
> - drm_rect_height(&plane_state->base.dst));
> + drm_rect_height(&plane_state->base.dst),
> + fb ? fb->format->format : 0);
>
> if (ret || plane_state->scaler_id < 0)
> return ret;
> @@ -4878,6 +4883,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> + case DRM_FORMAT_NV12:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -12799,11 +12805,12 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
> }
>
> int
> -skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
> +skl_max_scale(struct intel_crtc *intel_crtc,
> + struct intel_crtc_state *crtc_state, uint32_t pixel_format)
> {
> struct drm_i915_private *dev_priv;
> - int max_scale;
> - int crtc_clock, max_dotclk;
> + int max_scale, mult;
> + int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
>
> if (!intel_crtc || !crtc_state->base.enable)
> return DRM_PLANE_HELPER_NO_SCALING;
> @@ -12825,8 +12832,10 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
> * or
> * cdclk/crtc_clock
> */
> - max_scale = min((1 << 16) * 3 - 1,
> - (1 << 8) * ((max_dotclk << 8) / crtc_clock));
> + mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> + tmpclk1 = (1 << 16) * mult - 1;
> + tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> + max_scale = min(tmpclk1, tmpclk2);
you can optimize use of max_scale by directly returning min(tmpclk1,
tmpclk2) :)
-Mahesh
>
> return max_scale;
> }
> @@ -12847,7 +12856,11 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
> /* use scaler when colorkey is not required */
> if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> min_scale = 1;
> - max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
> + max_scale = skl_max_scale(to_intel_crtc(crtc),
> + crtc_state,
> + state->base.fb ?
> + state->base.fb->format->format :
> + 0);
> }
> can_position = true;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 51ae058..fd60635 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1490,7 +1490,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
> struct intel_crtc_state *pipe_config);
>
> int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
> -int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
> +int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
> + uint32_t pixel_format);
>
> static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 091bb42..6f98bc5 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -817,7 +817,8 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> can_scale = 1;
> min_scale = 1;
> - max_scale = skl_max_scale(crtc, crtc_state);
> + max_scale = skl_max_scale(crtc, crtc_state,
> + fb->format->format);
> } else {
> can_scale = 0;
> min_scale = DRM_PLANE_HELPER_NO_SCALING;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12
2017-10-10 14:05 ` Mahesh Kumar
@ 2017-10-10 20:26 ` Srinivas, Vidya
0 siblings, 0 replies; 27+ messages in thread
From: Srinivas, Vidya @ 2017-10-10 20:26 UTC (permalink / raw)
To: Kumar, Mahesh1, intel-gfx
> -----Original Message-----
> From: Kumar, Mahesh1
> Sent: Tuesday, October 10, 2017 7:35 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Maiti, Nabendu Bikash <nabendu.bikash.maiti@intel.com>
> Subject: Re: [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12
>
>
>
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch updates scaler max limit support for NV12
> >
> > v2: Rebased (me)
> >
> > v3: Rebased (me)
> >
> > v4: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v5: Addressed review comments from Ville and rebased
> > - calculation of max_scale to be made
> > less convoluted by splitting it up a bit
> > - Indentation errors to be fixed in the series
> >
> > v6: Rebased (me)
> > Fixed review comments from Paauwe, Bob J
> > Previous version, where a split of calculation
> > was done, was wrong. Fixed that issue here.
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++---
> -------
> > drivers/gpu/drm/i915/intel_drv.h | 3 ++-
> > drivers/gpu/drm/i915/intel_sprite.c | 3 ++-
> > 3 files changed, 27 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index a10bbe8..f71a704 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3472,6 +3472,8 @@ static u32 skl_plane_ctl_format(uint32_t
> pixel_format)
> > return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_UYVY;
> > case DRM_FORMAT_VYUY:
> > return PLANE_CTL_FORMAT_YUV422 |
> PLANE_CTL_YUV422_VYUY;
> > + case DRM_FORMAT_NV12:
> > + return PLANE_CTL_FORMAT_NV12;
> > default:
> > MISSING_CASE(pixel_format);
> > }
> > @@ -4727,7 +4729,8 @@ static void cpt_verify_modeset(struct
> drm_device *dev, int pipe)
> > static int
> > skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> > unsigned int scaler_user, int *scaler_id,
> > - int src_w, int src_h, int dst_w, int dst_h)
> > + int src_w, int src_h, int dst_w, int dst_h,
> > + uint32_t pixel_format)
> > {
> > struct intel_crtc_scaler_state *scaler_state =
> > &crtc_state->scaler_state;
> > @@ -4743,7 +4746,8 @@ static void cpt_verify_modeset(struct
> drm_device *dev, int pipe)
> > * the 90/270 degree plane rotation cases (to match the
> > * GTT mapping), hence no need to account for rotation here.
> > */
> > - need_scaling = src_w != dst_w || src_h != dst_h;
> > + need_scaling = src_w != dst_w || src_h != dst_h ||
> > + (pixel_format == DRM_FORMAT_NV12);
> IMHO keep nv12 check separate from rest of src/dst_w/h checks.
> >
> > if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> > need_scaling = true;
> > @@ -4822,7 +4826,7 @@ int skl_update_scaler_crtc(struct
> intel_crtc_state *state)
> > return skl_update_scaler(state, !state->base.active,
> SKL_CRTC_INDEX,
> > &state->scaler_state.scaler_id,
> > state->pipe_src_w, state->pipe_src_h,
> > - adjusted_mode->crtc_hdisplay, adjusted_mode-
> >crtc_vdisplay);
> > + adjusted_mode->crtc_hdisplay, adjusted_mode-
> >crtc_vdisplay, 0);
> > }
> >
> > /**
> > @@ -4852,7 +4856,8 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> > drm_rect_width(&plane_state->base.src) >>
> 16,
> > drm_rect_height(&plane_state->base.src) >>
> 16,
> > drm_rect_width(&plane_state->base.dst),
> > - drm_rect_height(&plane_state->base.dst));
> > + drm_rect_height(&plane_state->base.dst),
> > + fb ? fb->format->format : 0);
> >
> > if (ret || plane_state->scaler_id < 0)
> > return ret;
> > @@ -4878,6 +4883,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> > case DRM_FORMAT_YVYU:
> > case DRM_FORMAT_UYVY:
> > case DRM_FORMAT_VYUY:
> > + case DRM_FORMAT_NV12:
> > break;
> > default:
> > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported
> scaling format
> > 0x%x\n", @@ -12799,11 +12805,12 @@ static void
> add_rps_boost_after_vblank(struct drm_crtc *crtc,
> > }
> >
> > int
> > -skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state
> > *crtc_state)
> > +skl_max_scale(struct intel_crtc *intel_crtc,
> > + struct intel_crtc_state *crtc_state, uint32_t pixel_format)
> > {
> > struct drm_i915_private *dev_priv;
> > - int max_scale;
> > - int crtc_clock, max_dotclk;
> > + int max_scale, mult;
> > + int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
> >
> > if (!intel_crtc || !crtc_state->base.enable)
> > return DRM_PLANE_HELPER_NO_SCALING; @@ -12825,8
> +12832,10 @@
> > static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
> > * or
> > * cdclk/crtc_clock
> > */
> > - max_scale = min((1 << 16) * 3 - 1,
> > - (1 << 8) * ((max_dotclk << 8) / crtc_clock));
> > + mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> > + tmpclk1 = (1 << 16) * mult - 1;
> > + tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> > + max_scale = min(tmpclk1, tmpclk2);
> you can optimize use of max_scale by directly returning min(tmpclk1,
> tmpclk2) :)
Thank you. Will add the change for next version.
>
> -Mahesh
> >
> > return max_scale;
> > }
> > @@ -12847,7 +12856,11 @@ static void
> add_rps_boost_after_vblank(struct drm_crtc *crtc,
> > /* use scaler when colorkey is not required */
> > if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> > min_scale = 1;
> > - max_scale = skl_max_scale(to_intel_crtc(crtc),
> crtc_state);
> > + max_scale = skl_max_scale(to_intel_crtc(crtc),
> > + crtc_state,
> > + state->base.fb ?
> > + state->base.fb->format-
> >format :
> > + 0);
> > }
> > can_position = true;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 51ae058..fd60635 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1490,7 +1490,8 @@ void intel_mode_from_pipe_config(struct
> drm_display_mode *mode,
> > struct intel_crtc_state *pipe_config);
> >
> > int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
> > -int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
> > *crtc_state);
> > +int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
> *crtc_state,
> > + uint32_t pixel_format);
> >
> > static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state
> *state)
> > {
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 091bb42..6f98bc5 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -817,7 +817,8 @@ static u32 g4x_sprite_ctl(const struct
> intel_crtc_state *crtc_state,
> > if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
> > can_scale = 1;
> > min_scale = 1;
> > - max_scale = skl_max_scale(crtc, crtc_state);
> > + max_scale = skl_max_scale(crtc, crtc_state,
> > + fb->format->format);
> > } else {
> > can_scale = 0;
> > min_scale = DRM_PLANE_HELPER_NO_SCALING;
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (10 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 14:09 ` Mahesh Kumar
2017-10-16 22:33 ` Kristian Kristensen
2017-10-10 12:17 ` [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
` (3 subsequent siblings)
15 siblings, 2 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats
v5: Rebased (me)
v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
v7: Review comments by Ville addressed
Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)
v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f71a704..e551f59 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -106,6 +106,22 @@
DRM_FORMAT_MOD_INVALID
};
+static const uint32_t nv12_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB8888,
@@ -13256,8 +13272,14 @@ static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
primary->update_plane = skylake_update_primary_plane;
primary->disable_plane = skylake_disable_primary_plane;
} else if (INTEL_GEN(dev_priv) >= 9) {
- intel_primary_formats = skl_primary_formats;
- num_formats = ARRAY_SIZE(skl_primary_formats);
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ ((pipe == PIPE_A || pipe == PIPE_B))) {
+ intel_primary_formats = nv12_primary_formats;
+ num_formats = ARRAY_SIZE(nv12_primary_formats);
+ } else {
+ intel_primary_formats = skl_primary_formats;
+ num_formats = ARRAY_SIZE(skl_primary_formats);
+ }
if (pipe < PIPE_C)
modifiers = skl_format_modifiers_ccs;
else
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane
2017-10-10 12:17 ` [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
@ 2017-10-10 14:09 ` Mahesh Kumar
2017-10-10 14:29 ` Mahesh Kumar
2017-10-10 20:25 ` Srinivas, Vidya
2017-10-16 22:33 ` Kristian Kristensen
1 sibling, 2 replies; 27+ messages in thread
From: Mahesh Kumar @ 2017-10-10 14:09 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
Hi,
On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to list of supported formats for
> primary plane
>
> v2: Rebased (Chandra Konduru)
>
> v3: Rebased (me)
>
> v4: Review comments by Ville addressed
> Removed the skl_primary_formats_with_nv12 and
> added NV12 case in existing skl_primary_formats
>
> v5: Rebased (me)
>
> v6: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v7: Review comments by Ville addressed
> Restricting the NV12 for BXT and on PIPE A and B
> Rebased (me)
>
> v8: Rebased (me)
> Modified restricting the NV12 support for both BXT and KBL.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f71a704..e551f59 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -106,6 +106,22 @@
> DRM_FORMAT_MOD_INVALID
> };
>
> +static const uint32_t nv12_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> +};
> +
> /* Cursor formats */
> static const uint32_t intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> @@ -13256,8 +13272,14 @@ static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
> primary->update_plane = skylake_update_primary_plane;
> primary->disable_plane = skylake_disable_primary_plane;
> } else if (INTEL_GEN(dev_priv) >= 9) {
> - intel_primary_formats = skl_primary_formats;
> - num_formats = ARRAY_SIZE(skl_primary_formats);
> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + ((pipe == PIPE_A || pipe == PIPE_B))) {
This will add support only for BXT & KBL, what about other platforms?
Please mention that as comment or update the check.
-Mahesh
> + intel_primary_formats = nv12_primary_formats;
> + num_formats = ARRAY_SIZE(nv12_primary_formats);
> + } else {
> + intel_primary_formats = skl_primary_formats;
> + num_formats = ARRAY_SIZE(skl_primary_formats);
> + }
> if (pipe < PIPE_C)
> modifiers = skl_format_modifiers_ccs;
> else
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane
2017-10-10 14:09 ` Mahesh Kumar
@ 2017-10-10 14:29 ` Mahesh Kumar
2017-10-10 20:25 ` Srinivas, Vidya
1 sibling, 0 replies; 27+ messages in thread
From: Mahesh Kumar @ 2017-10-10 14:29 UTC (permalink / raw)
To: Vidya Srinivas, intel-gfx
On Tuesday 10 October 2017 07:39 PM, Mahesh Kumar wrote:
> Hi,
>
>
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
>> From: Chandra Konduru <chandra.konduru@intel.com>
>>
>> This patch adds NV12 to list of supported formats for
>> primary plane
>>
>> v2: Rebased (Chandra Konduru)
>>
>> v3: Rebased (me)
>>
>> v4: Review comments by Ville addressed
>> Removed the skl_primary_formats_with_nv12 and
>> added NV12 case in existing skl_primary_formats
>>
>> v5: Rebased (me)
>>
>> v6: Missed the Tested-by/Reviewed-by in the previous series
>> Adding the same to commit message in this version.
>>
>> v7: Review comments by Ville addressed
>> Restricting the NV12 for BXT and on PIPE A and B
>> Rebased (me)
>>
>> v8: Rebased (me)
>> Modified restricting the NV12 support for both BXT and KBL.
>>
>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
>> 1 file changed, 24 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index f71a704..e551f59 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -106,6 +106,22 @@
>> DRM_FORMAT_MOD_INVALID
>> };
>> +static const uint32_t nv12_primary_formats[] = {
>> + DRM_FORMAT_C8,
>> + DRM_FORMAT_RGB565,
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_XBGR8888,
>> + DRM_FORMAT_ARGB8888,
>> + DRM_FORMAT_ABGR8888,
>> + DRM_FORMAT_XRGB2101010,
>> + DRM_FORMAT_XBGR2101010,
>> + DRM_FORMAT_YUYV,
>> + DRM_FORMAT_YVYU,
>> + DRM_FORMAT_UYVY,
>> + DRM_FORMAT_VYUY,
>> + DRM_FORMAT_NV12,
>> +};
>> +
>> /* Cursor formats */
>> static const uint32_t intel_cursor_formats[] = {
>> DRM_FORMAT_ARGB8888,
>> @@ -13256,8 +13272,14 @@ static bool
>> intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
>> primary->update_plane = skylake_update_primary_plane;
>> primary->disable_plane = skylake_disable_primary_plane;
>> } else if (INTEL_GEN(dev_priv) >= 9) {
>> - intel_primary_formats = skl_primary_formats;
>> - num_formats = ARRAY_SIZE(skl_primary_formats);
>> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
>> + ((pipe == PIPE_A || pipe == PIPE_B))) {
> This will add support only for BXT & KBL, what about other platforms?
> Please mention that as comment or update the check.
after digging more in comments, it seems matt is suggesting there could
be customer with BXT stepping < E0, which doesn't support NV12 fully.
so IMO and as other suggested make is something like
(!(IS_SKYLAKE(dev_priv) || IS_BXT_REVID(dev_priv, BXT_REVIC_A0,
BXT_REVID_D0))
or others can comments if it should not be enabled for CFL/CNL yet?
>
> -Mahesh
>> + intel_primary_formats = nv12_primary_formats;
>> + num_formats = ARRAY_SIZE(nv12_primary_formats);
>> + } else {
>> + intel_primary_formats = skl_primary_formats;
>> + num_formats = ARRAY_SIZE(skl_primary_formats);
>> + }
>> if (pipe < PIPE_C)
>> modifiers = skl_format_modifiers_ccs;
>> else
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane
2017-10-10 14:09 ` Mahesh Kumar
2017-10-10 14:29 ` Mahesh Kumar
@ 2017-10-10 20:25 ` Srinivas, Vidya
1 sibling, 0 replies; 27+ messages in thread
From: Srinivas, Vidya @ 2017-10-10 20:25 UTC (permalink / raw)
To: Kumar, Mahesh1, intel-gfx
> -----Original Message-----
> From: Kumar, Mahesh1
> Sent: Tuesday, October 10, 2017 7:40 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Konduru, Chandra
> <chandra.konduru@intel.com>; Kamath, Sunil <sunil.kamath@intel.com>;
> Maiti, Nabendu Bikash <nabendu.bikash.maiti@intel.com>
> Subject: Re: [PATCH 12/14] drm/i915: Add NV12 as supported format for
> primary plane
>
> Hi,
>
>
> On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 to list of supported formats for primary plane
> >
> > v2: Rebased (Chandra Konduru)
> >
> > v3: Rebased (me)
> >
> > v4: Review comments by Ville addressed
> > Removed the skl_primary_formats_with_nv12 and
> > added NV12 case in existing skl_primary_formats
> >
> > v5: Rebased (me)
> >
> > v6: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> >
> > v7: Review comments by Ville addressed
> > Restricting the NV12 for BXT and on PIPE A and B
> > Rebased (me)
> >
> > v8: Rebased (me)
> > Modified restricting the NV12 support for both BXT and KBL.
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
> > 1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index f71a704..e551f59 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -106,6 +106,22 @@
> > DRM_FORMAT_MOD_INVALID
> > };
> >
> > +static const uint32_t nv12_primary_formats[] = {
> > + DRM_FORMAT_C8,
> > + DRM_FORMAT_RGB565,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_ARGB8888,
> > + DRM_FORMAT_ABGR8888,
> > + DRM_FORMAT_XRGB2101010,
> > + DRM_FORMAT_XBGR2101010,
> > + DRM_FORMAT_YUYV,
> > + DRM_FORMAT_YVYU,
> > + DRM_FORMAT_UYVY,
> > + DRM_FORMAT_VYUY,
> > + DRM_FORMAT_NV12,
> > +};
> > +
> > /* Cursor formats */
> > static const uint32_t intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB8888,
> > @@ -13256,8 +13272,14 @@ static bool
> intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
> > primary->update_plane = skylake_update_primary_plane;
> > primary->disable_plane = skylake_disable_primary_plane;
> > } else if (INTEL_GEN(dev_priv) >= 9) {
> > - intel_primary_formats = skl_primary_formats;
> > - num_formats = ARRAY_SIZE(skl_primary_formats);
> > + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> > + ((pipe == PIPE_A || pipe == PIPE_B))) {
> This will add support only for BXT & KBL, what about other platforms?
> Please mention that as comment or update the check.
Thank you. I tested the series currently only on BXT APL and the patches were also tested by other teams on KBL.
That’s why did not add changes for other platforms yet. Was planning to add them as enhancement.
>
> -Mahesh
> > + intel_primary_formats = nv12_primary_formats;
> > + num_formats =
> ARRAY_SIZE(nv12_primary_formats);
> > + } else {
> > + intel_primary_formats = skl_primary_formats;
> > + num_formats = ARRAY_SIZE(skl_primary_formats);
> > + }
> > if (pipe < PIPE_C)
> > modifiers = skl_format_modifiers_ccs;
> > else
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane
2017-10-10 12:17 ` [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2017-10-10 14:09 ` Mahesh Kumar
@ 2017-10-16 22:33 ` Kristian Kristensen
1 sibling, 0 replies; 27+ messages in thread
From: Kristian Kristensen @ 2017-10-16 22:33 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
Vidya Srinivas <vidya.srinivas@intel.com> writes:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to list of supported formats for
> primary plane
>
> v2: Rebased (Chandra Konduru)
>
> v3: Rebased (me)
>
> v4: Review comments by Ville addressed
> Removed the skl_primary_formats_with_nv12 and
> added NV12 case in existing skl_primary_formats
>
> v5: Rebased (me)
>
> v6: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v7: Review comments by Ville addressed
> Restricting the NV12 for BXT and on PIPE A and B
> Rebased (me)
>
> v8: Rebased (me)
> Modified restricting the NV12 support for both BXT and KBL.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
> 1 file changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f71a704..e551f59 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -106,6 +106,22 @@
> DRM_FORMAT_MOD_INVALID
> };
>
> +static const uint32_t nv12_primary_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> +};
> +
You need to extend skl_mod_supported() with a case for DRM_FORMAT_NV12
so that KMS can advertise the supported modifiers for NV12.
Kristian
> /* Cursor formats */
> static const uint32_t intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> @@ -13256,8 +13272,14 @@ static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane,
> primary->update_plane = skylake_update_primary_plane;
> primary->disable_plane = skylake_disable_primary_plane;
> } else if (INTEL_GEN(dev_priv) >= 9) {
> - intel_primary_formats = skl_primary_formats;
> - num_formats = ARRAY_SIZE(skl_primary_formats);
> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + ((pipe == PIPE_A || pipe == PIPE_B))) {
> + intel_primary_formats = nv12_primary_formats;
> + num_formats = ARRAY_SIZE(nv12_primary_formats);
> + } else {
> + intel_primary_formats = skl_primary_formats;
> + num_formats = ARRAY_SIZE(skl_primary_formats);
> + }
> if (pipe < PIPE_C)
> modifiers = skl_format_modifiers_ccs;
> else
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (11 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-16 22:35 ` Kristian Kristensen
2017-10-10 12:17 ` [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
` (2 subsequent siblings)
15 siblings, 1 reply; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats
v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series
v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.
v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B
v7: Rebased (me)
v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 6f98bc5..7e9cfe1 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1196,6 +1196,19 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
.format_mod_supported = intel_sprite_plane_format_mod_supported,
};
+static uint32_t nv12_plane_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+};
+
struct intel_plane *
intel_sprite_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, int plane)
@@ -1238,9 +1251,14 @@ struct intel_plane *
intel_plane->update_plane = skl_update_plane;
intel_plane->disable_plane = skl_disable_plane;
-
- plane_formats = skl_plane_formats;
- num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+ (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
+ plane_formats = nv12_plane_formats;
+ num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
modifiers = skl_plane_format_modifiers;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
intel_plane->can_scale = false;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane
2017-10-10 12:17 ` [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2017-10-16 22:35 ` Kristian Kristensen
2017-10-17 3:58 ` Srinivas, Vidya
0 siblings, 1 reply; 27+ messages in thread
From: Kristian Kristensen @ 2017-10-16 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
Vidya Srinivas <vidya.srinivas@intel.com> writes:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to list of supported formats for sprite plane.
>
> v2: Rebased (me)
>
> v3: Review comments by Ville addressed
> - Removed skl_plane_formats_with_nv12 and added
> NV12 case in existing skl_plane_formats
> - Added the 10bpc RGB formats
>
> v4: Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Removed 10bit RGB formats added previously with NV12 series
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
> Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Previous version has 10bit RGB format removed from VLV formats
> by mistake. Fixing that in this version.
> Removed 10bit RGB formats added previously with NV12 series
> for SKL.
>
> v6: Addressed review comments by Ville
> Restricting the NV12 to BXT and PIPE A and B
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> Restricting NV12 changes to BXT and KBL
> Restricting NV12 changes for plane 0 (overlay)
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
> 1 file changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 6f98bc5..7e9cfe1 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1196,6 +1196,19 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
> .format_mod_supported = intel_sprite_plane_format_mod_supported,
> };
>
> +static uint32_t nv12_plane_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR8888,
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_XBGR8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> +};
As for intel_display.c you need to extend
skl_sprite_plane_format_mod_supported() with a case for DRM_FORMAT_NV12
so that KMS can advertise the supported modifiers for NV12.
Kristian
> +
> struct intel_plane *
> intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> enum pipe pipe, int plane)
> @@ -1238,9 +1251,14 @@ struct intel_plane *
>
> intel_plane->update_plane = skl_update_plane;
> intel_plane->disable_plane = skl_disable_plane;
> -
> - plane_formats = skl_plane_formats;
> - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
> + plane_formats = nv12_plane_formats;
> + num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
> + } else {
> + plane_formats = skl_plane_formats;
> + num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> + }
> modifiers = skl_plane_format_modifiers;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_plane->can_scale = false;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane
2017-10-16 22:35 ` Kristian Kristensen
@ 2017-10-17 3:58 ` Srinivas, Vidya
0 siblings, 0 replies; 27+ messages in thread
From: Srinivas, Vidya @ 2017-10-17 3:58 UTC (permalink / raw)
To: Kristian Kristensen, intel-gfx
> -----Original Message-----
> From: Kristian Kristensen [mailto:hoegsberg@gmail.com]
> Sent: Tuesday, October 17, 2017 4:05 AM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Srinivas, Vidya <vidya.srinivas@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 13/14] drm/i915: Add NV12 as supported
> format for sprite plane
>
> Vidya Srinivas <vidya.srinivas@intel.com> writes:
>
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 to list of supported formats for sprite plane.
> >
> > v2: Rebased (me)
> >
> > v3: Review comments by Ville addressed
> > - Removed skl_plane_formats_with_nv12 and added
> > NV12 case in existing skl_plane_formats
> > - Added the 10bpc RGB formats
> >
> > v4: Addressed review comments from Clinton A Taylor
> > "Why are we adding 10 bit RGB formats with the NV12 series
> patches?
> > Trying to set XR30 or AB30 results in error returned even though
> > the modes are advertised for the planes"
> > - Removed 10bit RGB formats added previously with NV12 series
> >
> > v5: Missed the Tested-by/Reviewed-by in the previous series
> > Adding the same to commit message in this version.
> > Addressed review comments from Clinton A Taylor
> > "Why are we adding 10 bit RGB formats with the NV12 series
> patches?
> > Trying to set XR30 or AB30 results in error returned even though
> > the modes are advertised for the planes"
> > - Previous version has 10bit RGB format removed from VLV formats
> > by mistake. Fixing that in this version.
> > Removed 10bit RGB formats added previously with NV12 series
> > for SKL.
> >
> > v6: Addressed review comments by Ville
> > Restricting the NV12 to BXT and PIPE A and B
> >
> > v7: Rebased (me)
> >
> > v8: Rebased (me)
> > Restricting NV12 changes to BXT and KBL
> > Restricting NV12 changes for plane 0 (overlay)
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
> > 1 file changed, 21 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 6f98bc5..7e9cfe1 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1196,6 +1196,19 @@ static bool
> intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
> > .format_mod_supported =
> > intel_sprite_plane_format_mod_supported,
> > };
> >
> > +static uint32_t nv12_plane_formats[] = {
> > + DRM_FORMAT_RGB565,
> > + DRM_FORMAT_ABGR8888,
> > + DRM_FORMAT_ARGB8888,
> > + DRM_FORMAT_XBGR8888,
> > + DRM_FORMAT_XRGB8888,
> > + DRM_FORMAT_YUYV,
> > + DRM_FORMAT_YVYU,
> > + DRM_FORMAT_UYVY,
> > + DRM_FORMAT_VYUY,
> > + DRM_FORMAT_NV12,
> > +};
>
> As for intel_display.c you need to extend
> skl_sprite_plane_format_mod_supported() with a case for
> DRM_FORMAT_NV12 so that KMS can advertise the supported modifiers for
> NV12.
>
> Kristian
>
Thank you. I will add this in the next version before re-floating.
Regards
Vidya
>
> > +
> > struct intel_plane *
> > intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> > enum pipe pipe, int plane)
> > @@ -1238,9 +1251,14 @@ struct intel_plane *
> >
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > -
> > - plane_formats = skl_plane_formats;
> > - num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> > + if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> > + (pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
> > + plane_formats = nv12_plane_formats;
> > + num_plane_formats =
> ARRAY_SIZE(nv12_plane_formats);
> > + } else {
> > + plane_formats = skl_plane_formats;
> > + num_plane_formats =
> ARRAY_SIZE(skl_plane_formats);
> > + }
> > modifiers = skl_plane_format_modifiers;
> > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > intel_plane->can_scale = false;
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (12 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2017-10-10 12:17 ` Vidya Srinivas
2017-10-10 12:47 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev3) Patchwork
2017-10-10 16:48 ` ✓ Fi.CI.IGT: " Patchwork
15 siblings, 0 replies; 27+ messages in thread
From: Vidya Srinivas @ 2017-10-10 12:17 UTC (permalink / raw)
To: intel-gfx; +Cc: Vidya Srinivas
From: Chandra Konduru <chandra.konduru@intel.com>
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case
v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.
v6: Rebased (me)
v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.
v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.
Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e551f59..f66a73e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14071,6 +14071,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_NV12:
+ if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, &format_name));
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* ✓ Fi.CI.BAT: success for Adding NV12 support (rev3)
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (13 preceding siblings ...)
2017-10-10 12:17 ` [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
@ 2017-10-10 12:47 ` Patchwork
2017-10-10 16:48 ` ✓ Fi.CI.IGT: " Patchwork
15 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2017-10-10 12:47 UTC (permalink / raw)
To: Vidya Srinivas; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev3)
URL : https://patchwork.freedesktop.org/series/28103/
State : success
== Summary ==
Series 28103v3 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/3/mbox/
Test chamelium:
Subgroup dp-crc-fast:
pass -> FAIL (fi-kbl-7500u) fdo#102514
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-n2820) fdo#101705
pass -> DMESG-WARN (fi-skl-6700k) fdo#100367
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fdo#100367 https://bugs.freedesktop.org/show_bug.cgi?id=100367
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:470s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:394s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:581s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:285s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:523s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:521s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:533s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:523s
fi-cfl-s total:289 pass:256 dwarn:1 dfail:0 fail:0 skip:32 time:562s
fi-cnl-y total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:614s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:602s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:440s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:416s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:457s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:475s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:495s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:580s
fi-kbl-7567u total:289 pass:265 dwarn:4 dfail:0 fail:0 skip:20 time:486s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:589s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:662s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:475s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:656s
fi-skl-6700k total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:534s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:513s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:467s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:576s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:428s
6bcaf2275e52e258c737bc355e73072640be5ac3 drm-tip: 2017y-10m-10d-10h-57m-51s UTC integration manifest
004745daefae drm/i915: Add NV12 support to intel_framebuffer_init
ae6d144a9703 drm/i915: Add NV12 as supported format for sprite plane
303ea3604085 drm/i915: Add NV12 as supported format for primary plane
df988cd8065f drm/i915: Upscale scaler max scale for NV12
f884b0667862 drm/i915: Update format_is_yuv() to include NV12
5efd04f2a779 drm/i915: Set scaler mode for NV12
3d2d6ca030cb drm/i915/skl+: nv12 workaround disable WM level 1-7
0efd0ff59025 drm/i915/skl+: make sure higher latency level has higher wm value
34929470fcbf drm/i915/skl+: pass skl_wm_level struct to wm compute func
140217bcc810 drm/i915/skl+: NV12 related changes for WM
50cfca0614bb drm/i915/skl+: support varification of DDB HW state for NV12
0de16b2f24ed drm/i915/skl+: add NV12 in skl_format_to_fourcc
72bc128ecba2 drm/i915/skl+: refactore WM calculation for NV12
205ac002dabf drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5971/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ Fi.CI.IGT: success for Adding NV12 support (rev3)
2017-10-10 12:17 [PATCH 00/14] Adding NV12 support Vidya Srinivas
` (14 preceding siblings ...)
2017-10-10 12:47 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev3) Patchwork
@ 2017-10-10 16:48 ` Patchwork
15 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2017-10-10 16:48 UTC (permalink / raw)
To: Vidya Srinivas; +Cc: intel-gfx
== Series Details ==
Series: Adding NV12 support (rev3)
URL : https://patchwork.freedesktop.org/series/28103/
State : success
== Summary ==
shard-hsw total:2552 pass:1431 dwarn:5 dfail:0 fail:13 skip:1103 time:9650s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5971/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread