From: Julien Thierry <julien.thierry@arm.com> To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org, joel@joelfernandes.org, marc.zyngier@arm.com, mark.rutland@arm.com, christoffer.dall@arm.com, james.morse@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, Julien Thierry <julien.thierry@arm.com>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net> Subject: [PATCH v4 26/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Date: Fri, 25 May 2018 10:49:32 +0100 [thread overview] Message-ID: <1527241772-48007-27-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> Provide a way to set a GICv3 interrupt as pseudo-NMI. The interrupt must not be enabled when setting/clearing the NMI status of the interrupt. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> --- drivers/irqchip/irq-gic-v3.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/interrupt.h | 1 + 2 files changed, 55 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index fa23d12..cea1000 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -305,6 +305,43 @@ static void handle_percpu_devid_nmi(struct irq_desc *desc) chip->irq_eoi(&desc->irq_data); } +static int gic_irq_set_irqchip_prio(struct irq_data *d, bool val) +{ + u8 prio; + irq_flow_handler_t handler; + + if (gic_peek_irq(d, GICD_ISENABLER)) { + pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); + return -EPERM; + } + + if (val) { + prio = GICD_INT_NMI_PRI; + + if (gic_irq(d) < 32) + handler = handle_percpu_devid_nmi; + else + handler = handle_fasteoi_nmi; + } else { + prio = GICD_INT_DEF_PRI; + + if (gic_irq(d) < 32) + handler = handle_percpu_devid_irq; + else + handler = handle_fasteoi_irq; + } + + /* + * Already in a locked context for the desc from calling + * irq_set_irq_chip_state. + * It should be safe to simply modify the handler. + */ + irq_to_desc(d->irq)->handle_irq = handler; + gic_set_irq_prio(gic_irq(d), gic_dist_base(d), prio); + + return 0; +} + static int gic_irq_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool val) { @@ -326,6 +363,16 @@ static int gic_irq_set_irqchip_state(struct irq_data *d, reg = val ? GICD_ICENABLER : GICD_ISENABLER; break; + case IRQCHIP_STATE_NMI: + if (gic_supports_nmi()) { + return gic_irq_set_irqchip_prio(d, val); + } else if (val) { + pr_warn("Failed to set IRQ %u as NMI, NMIs are unsupported\n", + gic_irq(d)); + return -EINVAL; + } + return 0; + default: return -EINVAL; } @@ -353,6 +400,13 @@ static int gic_irq_get_irqchip_state(struct irq_data *d, *val = !gic_peek_irq(d, GICD_ISENABLER); break; + case IRQCHIP_STATE_NMI: + if (!gic_supports_nmi()) + return -EINVAL; + *val = (gic_get_irq_prio(gic_irq(d), gic_dist_base(d)) == + GICD_INT_NMI_PRI); + break; + default: return -EINVAL; } diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 5426627..02c794f 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -419,6 +419,7 @@ enum irqchip_irq_state { IRQCHIP_STATE_ACTIVE, /* Is interrupt in progress? */ IRQCHIP_STATE_MASKED, /* Is interrupt masked? */ IRQCHIP_STATE_LINE_LEVEL, /* Is IRQ line high? */ + IRQCHIP_STATE_NMI, /* Is IRQ an NMI? */ }; extern int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: julien.thierry@arm.com (Julien Thierry) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 26/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Date: Fri, 25 May 2018 10:49:32 +0100 [thread overview] Message-ID: <1527241772-48007-27-git-send-email-julien.thierry@arm.com> (raw) In-Reply-To: <1527241772-48007-1-git-send-email-julien.thierry@arm.com> Provide a way to set a GICv3 interrupt as pseudo-NMI. The interrupt must not be enabled when setting/clearing the NMI status of the interrupt. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> --- drivers/irqchip/irq-gic-v3.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/interrupt.h | 1 + 2 files changed, 55 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index fa23d12..cea1000 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -305,6 +305,43 @@ static void handle_percpu_devid_nmi(struct irq_desc *desc) chip->irq_eoi(&desc->irq_data); } +static int gic_irq_set_irqchip_prio(struct irq_data *d, bool val) +{ + u8 prio; + irq_flow_handler_t handler; + + if (gic_peek_irq(d, GICD_ISENABLER)) { + pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); + return -EPERM; + } + + if (val) { + prio = GICD_INT_NMI_PRI; + + if (gic_irq(d) < 32) + handler = handle_percpu_devid_nmi; + else + handler = handle_fasteoi_nmi; + } else { + prio = GICD_INT_DEF_PRI; + + if (gic_irq(d) < 32) + handler = handle_percpu_devid_irq; + else + handler = handle_fasteoi_irq; + } + + /* + * Already in a locked context for the desc from calling + * irq_set_irq_chip_state. + * It should be safe to simply modify the handler. + */ + irq_to_desc(d->irq)->handle_irq = handler; + gic_set_irq_prio(gic_irq(d), gic_dist_base(d), prio); + + return 0; +} + static int gic_irq_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which, bool val) { @@ -326,6 +363,16 @@ static int gic_irq_set_irqchip_state(struct irq_data *d, reg = val ? GICD_ICENABLER : GICD_ISENABLER; break; + case IRQCHIP_STATE_NMI: + if (gic_supports_nmi()) { + return gic_irq_set_irqchip_prio(d, val); + } else if (val) { + pr_warn("Failed to set IRQ %u as NMI, NMIs are unsupported\n", + gic_irq(d)); + return -EINVAL; + } + return 0; + default: return -EINVAL; } @@ -353,6 +400,13 @@ static int gic_irq_get_irqchip_state(struct irq_data *d, *val = !gic_peek_irq(d, GICD_ISENABLER); break; + case IRQCHIP_STATE_NMI: + if (!gic_supports_nmi()) + return -EINVAL; + *val = (gic_get_irq_prio(gic_irq(d), gic_dist_base(d)) == + GICD_INT_NMI_PRI); + break; + default: return -EINVAL; } diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h index 5426627..02c794f 100644 --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h @@ -419,6 +419,7 @@ enum irqchip_irq_state { IRQCHIP_STATE_ACTIVE, /* Is interrupt in progress? */ IRQCHIP_STATE_MASKED, /* Is interrupt masked? */ IRQCHIP_STATE_LINE_LEVEL, /* Is IRQ line high? */ + IRQCHIP_STATE_NMI, /* Is IRQ an NMI? */ }; extern int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, -- 1.9.1
next prev parent reply other threads:[~2018-05-25 9:52 UTC|newest] Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-05-25 9:49 [PATCH v4 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 01/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 10:04 ` Suzuki K Poulose 2018-05-25 10:04 ` Suzuki K Poulose 2018-05-25 10:17 ` Julien Thierry 2018-05-25 10:17 ` Julien Thierry 2018-05-25 10:36 ` Suzuki K Poulose 2018-05-25 10:36 ` Suzuki K Poulose 2018-05-25 10:39 ` Julien Thierry 2018-05-25 10:39 ` Julien Thierry 2018-05-25 10:41 ` Suzuki K Poulose 2018-05-25 10:41 ` Suzuki K Poulose 2018-05-25 10:48 ` Julien Thierry 2018-05-25 10:48 ` Julien Thierry 2018-06-12 13:46 ` Julien Thierry 2018-06-12 13:46 ` Julien Thierry 2018-06-15 10:16 ` Suzuki K Poulose 2018-06-15 10:16 ` Suzuki K Poulose 2018-05-25 9:49 ` [PATCH v4 03/26] arm64: cpufeature: Use alternatives for VHE cpu_enable Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 04/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 10:00 ` Suzuki K Poulose 2018-05-25 10:00 ` Suzuki K Poulose 2018-05-25 10:25 ` Julien Thierry 2018-05-25 10:25 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 05/26] irqchip/gic: Unify GIC priority definitions Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 06/26] irqchip/gic: Lower priority of GIC interrupts Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 07/26] irqchip/gic-v3: Remove acknowledge loop Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 08/26] arm64: daifflags: Use irqflags functions for daifflags Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 09/26] arm64: Use daifflag_restore after bp_hardening Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 10/26] arm64: Delay daif masking for user return Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 11/26] arm64: Make PMR part of task context Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 12/26] arm64: Unmask PMR before going idle Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 13/26] arm/arm64: gic-v3: Add helper functions to manage IRQ priorities Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 14/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 15/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 16/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 17/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 18/26] irqchip/gic-v3: Do not overwrite PMR value Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 19/26] irqchip/gic-v3: Switch to PMR masking after IRQ acknowledge Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 20/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 21/26] arm64: Add build option for IRQ masking via priority Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 22/26] arm64: Detect current view of GIC priorities Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 23/26] irqchip/gic: Add functions to access irq priorities Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 24/26] irqchip/gic-v3: Add base support for pseudo-NMI Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-06-13 11:14 ` Julien Thierry 2018-06-13 11:14 ` Julien Thierry 2018-05-25 9:49 ` [PATCH v4 25/26] irqchip/gic-v3: Provide NMI handlers Julien Thierry 2018-05-25 9:49 ` Julien Thierry 2018-05-25 9:49 ` Julien Thierry [this message] 2018-05-25 9:49 ` [PATCH v4 26/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2018-06-13 11:07 ` Julien Thierry 2018-06-13 11:07 ` Julien Thierry 2018-05-25 10:16 ` [PATCH v4 00/26] arm64: provide pseudo NMI with GICv3 Daniel Thompson 2018-05-25 10:16 ` Daniel Thompson 2018-05-25 10:40 ` Julien Thierry 2018-05-25 10:40 ` Julien Thierry 2018-05-25 13:42 ` Julien Thierry 2018-05-25 13:42 ` Julien Thierry 2018-07-20 15:09 ` Daniel Thompson 2018-07-20 15:09 ` Daniel Thompson 2018-07-23 12:39 ` Julien Thierry 2018-07-23 12:39 ` Julien Thierry
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