From: Julien Thierry <julien.thierry@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org,
joel@joelfernandes.org, marc.zyngier@arm.com,
mark.rutland@arm.com, christoffer.dall@arm.com,
james.morse@arm.com, catalin.marinas@arm.com,
will.deacon@arm.com, Julien Thierry <julien.thierry@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Subject: [PATCH v4 05/26] irqchip/gic: Unify GIC priority definitions
Date: Fri, 25 May 2018 10:49:11 +0100 [thread overview]
Message-ID: <1527241772-48007-6-git-send-email-julien.thierry@arm.com> (raw)
In-Reply-To: <1527241772-48007-1-git-send-email-julien.thierry@arm.com>
LPIs use the same priority value as other GIC interrupts.
Make the GIC default priority definition visible to ITS implementation
and use this same definition for LPI priorities.
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-common.h | 6 ++++++
include/linux/irqchip/arm-gic.h | 5 -----
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 5416f2b..9ac146c 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -62,7 +62,7 @@
#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
-#define LPI_PROP_DEFAULT_PRIO 0xa0
+#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
/*
* Collection structure - just an ID, and a redistributor address to
diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h
index 0a83b43..9a1a479 100644
--- a/include/linux/irqchip/arm-gic-common.h
+++ b/include/linux/irqchip/arm-gic-common.h
@@ -13,6 +13,12 @@
#include <linux/types.h>
#include <linux/ioport.h>
+#define GICD_INT_DEF_PRI 0xa0
+#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
+ (GICD_INT_DEF_PRI << 16) |\
+ (GICD_INT_DEF_PRI << 8) |\
+ GICD_INT_DEF_PRI)
+
enum gic_type {
GIC_V2,
GIC_V3,
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 68d8b1f..5f2129b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -65,11 +65,6 @@
#define GICD_INT_EN_CLR_X32 0xffffffff
#define GICD_INT_EN_SET_SGI 0x0000ffff
#define GICD_INT_EN_CLR_PPI 0xffff0000
-#define GICD_INT_DEF_PRI 0xa0
-#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
- (GICD_INT_DEF_PRI << 16) |\
- (GICD_INT_DEF_PRI << 8) |\
- GICD_INT_DEF_PRI)
#define GICH_HCR 0x0
#define GICH_VTR 0x4
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: julien.thierry@arm.com (Julien Thierry)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 05/26] irqchip/gic: Unify GIC priority definitions
Date: Fri, 25 May 2018 10:49:11 +0100 [thread overview]
Message-ID: <1527241772-48007-6-git-send-email-julien.thierry@arm.com> (raw)
In-Reply-To: <1527241772-48007-1-git-send-email-julien.thierry@arm.com>
LPIs use the same priority value as other GIC interrupts.
Make the GIC default priority definition visible to ITS implementation
and use this same definition for LPI priorities.
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-common.h | 6 ++++++
include/linux/irqchip/arm-gic.h | 5 -----
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 5416f2b..9ac146c 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -62,7 +62,7 @@
#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
-#define LPI_PROP_DEFAULT_PRIO 0xa0
+#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
/*
* Collection structure - just an ID, and a redistributor address to
diff --git a/include/linux/irqchip/arm-gic-common.h b/include/linux/irqchip/arm-gic-common.h
index 0a83b43..9a1a479 100644
--- a/include/linux/irqchip/arm-gic-common.h
+++ b/include/linux/irqchip/arm-gic-common.h
@@ -13,6 +13,12 @@
#include <linux/types.h>
#include <linux/ioport.h>
+#define GICD_INT_DEF_PRI 0xa0
+#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
+ (GICD_INT_DEF_PRI << 16) |\
+ (GICD_INT_DEF_PRI << 8) |\
+ GICD_INT_DEF_PRI)
+
enum gic_type {
GIC_V2,
GIC_V3,
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 68d8b1f..5f2129b 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -65,11 +65,6 @@
#define GICD_INT_EN_CLR_X32 0xffffffff
#define GICD_INT_EN_SET_SGI 0x0000ffff
#define GICD_INT_EN_CLR_PPI 0xffff0000
-#define GICD_INT_DEF_PRI 0xa0
-#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\
- (GICD_INT_DEF_PRI << 16) |\
- (GICD_INT_DEF_PRI << 8) |\
- GICD_INT_DEF_PRI)
#define GICH_HCR 0x0
#define GICH_VTR 0x4
--
1.9.1
next prev parent reply other threads:[~2018-05-25 9:50 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-25 9:49 [PATCH v4 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 01/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 02/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 10:04 ` Suzuki K Poulose
2018-05-25 10:04 ` Suzuki K Poulose
2018-05-25 10:17 ` Julien Thierry
2018-05-25 10:17 ` Julien Thierry
2018-05-25 10:36 ` Suzuki K Poulose
2018-05-25 10:36 ` Suzuki K Poulose
2018-05-25 10:39 ` Julien Thierry
2018-05-25 10:39 ` Julien Thierry
2018-05-25 10:41 ` Suzuki K Poulose
2018-05-25 10:41 ` Suzuki K Poulose
2018-05-25 10:48 ` Julien Thierry
2018-05-25 10:48 ` Julien Thierry
2018-06-12 13:46 ` Julien Thierry
2018-06-12 13:46 ` Julien Thierry
2018-06-15 10:16 ` Suzuki K Poulose
2018-06-15 10:16 ` Suzuki K Poulose
2018-05-25 9:49 ` [PATCH v4 03/26] arm64: cpufeature: Use alternatives for VHE cpu_enable Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 04/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 10:00 ` Suzuki K Poulose
2018-05-25 10:00 ` Suzuki K Poulose
2018-05-25 10:25 ` Julien Thierry
2018-05-25 10:25 ` Julien Thierry
2018-05-25 9:49 ` Julien Thierry [this message]
2018-05-25 9:49 ` [PATCH v4 05/26] irqchip/gic: Unify GIC priority definitions Julien Thierry
2018-05-25 9:49 ` [PATCH v4 06/26] irqchip/gic: Lower priority of GIC interrupts Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 07/26] irqchip/gic-v3: Remove acknowledge loop Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 08/26] arm64: daifflags: Use irqflags functions for daifflags Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 09/26] arm64: Use daifflag_restore after bp_hardening Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 10/26] arm64: Delay daif masking for user return Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 11/26] arm64: Make PMR part of task context Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 12/26] arm64: Unmask PMR before going idle Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 13/26] arm/arm64: gic-v3: Add helper functions to manage IRQ priorities Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 14/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 15/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 16/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 17/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 18/26] irqchip/gic-v3: Do not overwrite PMR value Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 19/26] irqchip/gic-v3: Switch to PMR masking after IRQ acknowledge Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 20/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 21/26] arm64: Add build option for IRQ masking via priority Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 22/26] arm64: Detect current view of GIC priorities Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 23/26] irqchip/gic: Add functions to access irq priorities Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 24/26] irqchip/gic-v3: Add base support for pseudo-NMI Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-06-13 11:14 ` Julien Thierry
2018-06-13 11:14 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 25/26] irqchip/gic-v3: Provide NMI handlers Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-05-25 9:49 ` [PATCH v4 26/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry
2018-05-25 9:49 ` Julien Thierry
2018-06-13 11:07 ` Julien Thierry
2018-06-13 11:07 ` Julien Thierry
2018-05-25 10:16 ` [PATCH v4 00/26] arm64: provide pseudo NMI with GICv3 Daniel Thompson
2018-05-25 10:16 ` Daniel Thompson
2018-05-25 10:40 ` Julien Thierry
2018-05-25 10:40 ` Julien Thierry
2018-05-25 13:42 ` Julien Thierry
2018-05-25 13:42 ` Julien Thierry
2018-07-20 15:09 ` Daniel Thompson
2018-07-20 15:09 ` Daniel Thompson
2018-07-23 12:39 ` Julien Thierry
2018-07-23 12:39 ` Julien Thierry
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