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From: lzenz at dh-electronics.de <lzenz@dh-electronics.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"
Date: Thu, 5 Jul 2018 09:23:46 +0200	[thread overview]
Message-ID: <1530775428-19269-1-git-send-email-lzenz@dh-electronics.de> (raw)

From: Ludwig Zenz <lzenz@dh-electronics.de>

This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac.

The DDR DRAM calibration was enhanced by write leveling correction code.
It can be used with T-topology now.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
---
 board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index dffe4eb..beda389 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -384,6 +384,10 @@ void board_init_f(ulong dummy)
 				  &dhcom6sdl_grp_ioregs);
 	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
 
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_dqs_calibration(&dhcom_ddr_info);
+
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
-- 
2.7.4

             reply	other threads:[~2018-07-05  7:23 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-05  7:23 lzenz at dh-electronics.de [this message]
2018-07-05  7:23 ` [U-Boot] [PATCH 2/3] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK lzenz at dh-electronics.de
2018-07-23  9:31   ` Stefano Babic
2018-07-05  7:23 ` [U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips lzenz at dh-electronics.de
2018-07-23  9:31   ` Stefano Babic
2018-09-30 16:39   ` Marek Vasut
2018-10-11  7:09     ` Ludwig Zenz
2018-10-11  8:48       ` Marek Vasut
2018-07-23  9:31 ` [U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK" Stefano Babic

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