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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips
Date: Sun, 30 Sep 2018 18:39:13 +0200	[thread overview]
Message-ID: <440e7c41-42b1-4766-493b-cbb7517604b9@denx.de> (raw)
In-Reply-To: <1530775428-19269-3-git-send-email-lzenz@dh-electronics.de>

On 07/05/2018 09:23 AM, lzenz at dh-electronics.de wrote:
> From: Ludwig Zenz <lzenz@dh-electronics.de>
> 
> Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width
> 
> Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
> ---
>  board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++---
>  1 file changed, 173 insertions(+), 18 deletions(-)
> 
> diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
[...]

This patch causes memory instability on 1GiB MX6Q part.

Can you check that and fix it ? Thanks.

-- 
Best regards,
Marek Vasut

  parent reply	other threads:[~2018-09-30 16:39 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-05  7:23 [U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK" lzenz at dh-electronics.de
2018-07-05  7:23 ` [U-Boot] [PATCH 2/3] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK lzenz at dh-electronics.de
2018-07-23  9:31   ` Stefano Babic
2018-07-05  7:23 ` [U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips lzenz at dh-electronics.de
2018-07-23  9:31   ` Stefano Babic
2018-09-30 16:39   ` Marek Vasut [this message]
2018-10-11  7:09     ` Ludwig Zenz
2018-10-11  8:48       ` Marek Vasut
2018-07-23  9:31 ` [U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK" Stefano Babic

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