From: lzenz at dh-electronics.de <lzenz@dh-electronics.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/3] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK
Date: Thu, 5 Jul 2018 09:23:47 +0200 [thread overview]
Message-ID: <1530775428-19269-2-git-send-email-lzenz@dh-electronics.de> (raw)
In-Reply-To: <1530775428-19269-1-git-send-email-lzenz@dh-electronics.de>
From: Ludwig Zenz <lzenz@dh-electronics.de>
Preperation for conditional DDR3 initialization based on GPIO codes.
Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.de>
---
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 40 +++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index beda389..eafb86d 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -208,6 +208,45 @@ static void setup_iomux_boardid(void)
SETUP_IOMUX_PADS(hwcode_pads);
}
+/* DDR Code */
+static iomux_v3_cfg_t const ddrcode_pads[] = {
+ IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_ddrcode(void)
+{
+ /* ddr code pins */
+ SETUP_IOMUX_PADS(ddrcode_pads);
+}
+
+enum dhcom_ddr3_code {
+ DH_DDR3_SIZE_256MIB = 0x00,
+ DH_DDR3_SIZE_512MIB = 0x01,
+ DH_DDR3_SIZE_1GIB = 0x02,
+ DH_DDR3_SIZE_2GIB = 0x03
+};
+
+#define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22)
+#define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21)
+
+enum dhcom_ddr3_code dhcom_get_ddr3_code(void)
+{
+ enum dhcom_ddr3_code ddr3_code;
+
+ gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0");
+ gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1");
+
+ gpio_direction_input(DDR3_CODE_BIT_0);
+ gpio_direction_input(DDR3_CODE_BIT_1);
+
+ /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */
+ ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1)
+ | (!!gpio_get_value(DDR3_CODE_BIT_0));
+
+ return ddr3_code;
+}
+
/* GPIO */
static iomux_v3_cfg_t const gpio_pads[] = {
IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
@@ -365,6 +404,7 @@ void board_init_f(ulong dummy)
timer_init();
setup_iomux_boardid();
+ setup_iomux_ddrcode();
setup_iomux_gpio();
setup_iomux_enet();
setup_iomux_sd();
--
2.7.4
next prev parent reply other threads:[~2018-07-05 7:23 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-05 7:23 [U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK" lzenz at dh-electronics.de
2018-07-05 7:23 ` lzenz at dh-electronics.de [this message]
2018-07-23 9:31 ` [U-Boot] [PATCH 2/3] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK Stefano Babic
2018-07-05 7:23 ` [U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips lzenz at dh-electronics.de
2018-07-23 9:31 ` Stefano Babic
2018-09-30 16:39 ` Marek Vasut
2018-10-11 7:09 ` Ludwig Zenz
2018-10-11 8:48 ` Marek Vasut
2018-07-23 9:31 ` [U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK" Stefano Babic
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