[PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

This patch series include an attempt to avoid the use of custom
read and writes in driver code and use PCI subsystem common ones.

In order to do this 'map_bus' callback is implemented and also
data structures for driver are included. The regs base address
is being readed from device tree and the driver gets clean a lot
of code.

Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.

Changes in v6:
    - Reorder patches to be each patch correct in itself.
    - PATCH 1 adds also Kconfig to do the step from legacy to generic code
    - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
      a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
    - Other patches rebased and adapted with this changes.

Changes in v5:
    - Include driver Kconfig file to add compilation depends of PCI_DRIVERS_GENERIC.
      The new added configuration option is CONFIG_PCI_MT7621.
    - Add list_splice_init(&res, &bridge->windows); in PATCH 1 to set windows
      from resources obtanined from devm_request_pci_bus_resources.
    - Move devm_of_pci_get_host_bridge_resources and devm_request_pci_bus_resources
      after the ports initialization legacy code.
    - Add pcie ports 1 and 2 RC registers to device tree. There was only being included
      port RC register for port 0.
    - Review includes and order them alphabetically.

Changes in v4:
    - Rebased onto staging-next.

Changes in v3:
    - Include new patches to delete all RALINK_BASE definition
      dependant code and be able to avoid use of pci_legacy code.
    - use devm_of_pci_get_host_bridge_resources,
      devm_request_pci_bus_resources and pci_scan_root_bus_bridge
      and pci_bus_add_devices

Changes in v2:
    - squash PATCH 1 and PATCH 2 of previous series in only PATCH 1
    - Change name for host structure.
    - Create a new port structure (platform has 3 pcie controllers)
    - Replace the use of pci_generic_config_[read|write]32 in favour
      of pci_generic_config_[read|write] and change map_bus implemen-
      tation for hopefully the right one.

Best regards,
    Sergio Paracuellos


Sergio Paracuellos (15):
  staging: mt7621-pci: use generic kernel pci subsystem read and write
  staging: mt7621-pci: remove dead code derived to not use custom reads
    and writes
  staging: mt7621-pci: add pcie_write and pcie_read helpers
  staging: mt7621-pci: use pcie_[read|write] in [write|read]_config
  staging: mt7621-pci: simplify read_config function
  staging: mt7621-pci: simplify write_config function
  staging: mt7621-pci: remove unused macros
  staging: mt7621-pci: avoid register duplication per controller using
    pcie_[read|write]
  staging: mt7621-pci: review includes putting them in alphabethic order
  staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR
    and RALINK_PCI_PCIMSK_ADDR
  staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions
  staging: mt7621-pci: use BIT macro in preprocessor definitions
  staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
    definition
  staging: mt7621-pci: remove remaining pci_legacy dependant code
  staging: mt7621-dts: add pcie controller port registers

 drivers/staging/Kconfig                 |   2 +
 drivers/staging/mt7621-dts/mt7621.dtsi  |   6 +-
 drivers/staging/mt7621-pci/Kconfig      |   7 +
 drivers/staging/mt7621-pci/pci-mt7621.c | 716 +++++++++++++++-----------------
 4 files changed, 347 insertions(+), 384 deletions(-)
 create mode 100644 drivers/staging/mt7621-pci/Kconfig

-- 
2.7.4

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[PATCH v6 01/15] staging: mt7621-pci: use generic kernel pci subsystem read and write

[Sergio Paracuellos]

map_bus callback is called before every .read/.write operation.
Implement it and change custom read write operations for the
pci subsystem generics. Make the probe function to don't use
legacy stuff and request bus resources directly. Get pci register
base and ranges from device tree.
The driver is not using PCI_LEGACY code anymore and shall use the
PCI_DRIVERS_GENERIC option to correct compile it. Add also new
Kconfig file for this controller setting there its correct dependencies.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/Kconfig                 |   2 +
 drivers/staging/mt7621-pci/Kconfig      |   7 ++
 drivers/staging/mt7621-pci/pci-mt7621.c | 174 +++++++++++++++++++++++++++++---
 3 files changed, 169 insertions(+), 14 deletions(-)
 create mode 100644 drivers/staging/mt7621-pci/Kconfig

diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2bce647..732b631 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -110,6 +110,8 @@ source "drivers/staging/vboxvideo/Kconfig"
 
 source "drivers/staging/pi433/Kconfig"
 
+source "drivers/staging/mt7621-pci/Kconfig"
+
 source "drivers/staging/mt7621-pinctrl/Kconfig"
 
 source "drivers/staging/mt7621-spi/Kconfig"
diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
new file mode 100644
index 0000000..d335338
--- /dev/null
+++ b/drivers/staging/mt7621-pci/Kconfig
@@ -0,0 +1,7 @@
+config PCI_MT7621
+	tristate "MediaTek MT7621 PCI Controller"
+	depends on RALINK
+	select PCI_DRIVERS_GENERIC
+	help
+	  This selects a driver for the MediaTek MT7621 PCI Controller.
+
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 650e49b..45c02f7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -53,11 +53,16 @@
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/platform_device.h>
 
 #include <ralink_regs.h>
 #include <mt7621.h>
 
+#include "../../pci/pci.h"
+
 /*
  * These functions and structures provide the BIOS scan and mapping of the PCI
  * devices.
@@ -178,6 +183,32 @@ static int pcie_link_status = 0;
 #define PCI_ACCESS_WRITE_2 4
 #define PCI_ACCESS_WRITE_4 5
 
+/**
+ * struct mt7621_pcie_port - PCIe port information
+ * @base: IO mapped register base
+ * @list: port list
+ * @pcie: pointer to PCIe host info
+ * @reset: pointer to port reset control
+ */
+struct mt7621_pcie_port {
+	void __iomem *base;
+	struct list_head list;
+	struct mt7621_pcie *pcie;
+	struct reset_control *reset;
+};
+
+/**
+ * struct mt7621_pcie - PCIe host information
+ * @base: IO Mapped Register Base
+ * @dev: Pointer to PCIe device
+ * @ports: pointer to PCIe port information
+ */
+struct mt7621_pcie {
+	void __iomem *base;
+	struct device *dev;
+	struct list_head ports;
+};
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
@@ -297,17 +328,22 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
 	}
 }
 
-struct pci_ops mt7621_pci_ops = {
-	.read		= pci_config_read,
-	.write		= pci_config_write,
-};
+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
+					 unsigned int devfn, int where)
+{
+	struct mt7621_pcie *pcie = bus->sysdata;
+	u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					     PCI_FUNC(devfn), where);
+
+	writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
 
-static struct resource mt7621_res_pci_mem1;
-static struct resource mt7621_res_pci_io1;
-static struct pci_controller mt7621_controller = {
-	.pci_ops	= &mt7621_pci_ops,
-	.mem_resource	= &mt7621_res_pci_mem1,
-	.io_resource	= &mt7621_res_pci_io1,
+	return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+}
+
+struct pci_ops mt7621_pci_ops = {
+	.map_bus	= mt7621_pcie_map_bus,
+	.read		= pci_generic_config_read,
+	.write		= pci_generic_config_write,
 };
 
 static void
@@ -480,14 +516,108 @@ void setup_cm_memory_region(struct resource *mem_resource)
 	}
 }
 
+
+static int mt7621_pci_parse_request_of_pci_ranges(struct device *dev,
+						  struct list_head *res)
+{
+	int err;
+	resource_size_t iobase;
+	struct resource_entry *win, *tmp;
+
+	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, res, &iobase);
+	if (err) {
+		dev_err(dev, "Getting bridge resources failed\n");
+		return err;
+	}
+
+	err = devm_request_pci_bus_resources(dev, res);
+	if (err)
+		return err;
+
+	resource_list_for_each_entry_safe(win, tmp, res) {
+		struct resource *res = win->res;
+
+		switch (resource_type(res)) {
+		case IORESOURCE_IO:
+			err = devm_pci_remap_iospace(dev, res, iobase);
+			if (err) {
+				dev_warn(dev, "error %d: failed to map resource %pR\n",
+					 err, res);
+				resource_list_destroy_entry(win);
+			}
+			break;
+		case IORESOURCE_MEM:
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie, struct list_head *res)
+{
+	struct device *dev = pcie->dev;
+	struct device_node *node = dev->of_node;
+	struct resource regs;
+	const char *type;
+	int err;
+
+	type = of_get_property(node, "device_type", NULL);
+	if (!type || strcmp(type, "pci") != 0) {
+		dev_err(dev, "invalid \"device_type\" %s\n", type);
+		return -EINVAL;
+	}
+
+	err = of_address_to_resource(node, 0, &regs);
+	if (err) {
+		dev_err(dev, "missing \"reg\" property\n");
+		return err;
+	}
+
+	pcie->base = devm_ioremap_resource(dev, &regs);
+	if (IS_ERR(pcie->base))
+		return PTR_ERR(pcie->base);
+
+	err = mt7621_pci_parse_request_of_pci_ranges(dev, res);
+	if (err)
+		return err;
+
+	return 0;
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
+	struct mt7621_pcie *pcie;
+	struct pci_host_bridge *bridge;
+	struct pci_bus *bus, *child;
+	int err;
 	unsigned long val = 0;
+	LIST_HEAD(res);
 
+	if (!dev->of_node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
+	if (!bridge)
+		return -ENODEV;
+
+	pcie = pci_host_bridge_priv(bridge);
+	pcie->dev = dev;
+	INIT_LIST_HEAD(&pcie->ports);
+
+	err = mt7621_pcie_parse_dt(pcie, &res);
+	if (err) {
+		dev_err(dev, "Parsing DT failed\n");
+		return err;
+	}
+
+	/*
 	iomem_resource.start = 0;
 	iomem_resource.end = ~0;
 	ioport_resource.start = 0;
 	ioport_resource.end = ~0;
+	*/
 
 	val = RALINK_PCIE0_RST;
 	val |= RALINK_PCIE1_RST;
@@ -665,11 +795,27 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 		write_config(0, 0, 0, 0x70c, val);
 	}
 
-	pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-	setup_cm_memory_region(mt7621_controller.mem_resource);
-	register_pci_controller(&mt7621_controller);
-	return 0;
+	list_splice_init(&res, &bridge->windows);
+	bridge->busnr = 0;
+	bridge->dev.parent = dev;
+	bridge->sysdata = pcie;
+	bridge->ops = &mt7621_pci_ops;
+	bridge->map_irq = pcibios_map_irq;
+	bridge->swizzle_irq = pci_common_swizzle;
 
+	err = pci_scan_root_bus_bridge(bridge);
+	if (err < 0)
+		return err;
+
+	bus = bridge->bus;
+
+	pci_assign_unassigned_bus_resources(bus);
+	list_for_each_entry(child, &bus->children, node)
+		pcie_bus_configure_settings(child);
+
+	pci_bus_add_devices(bus);
+
+	return 0;
 }
 
 int pcibios_plat_dev_init(struct pci_dev *dev)
-- 
2.7.4

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[PATCH v6 02/15] staging: mt7621-pci: remove dead code derived to not use custom reads and writes

[Sergio Paracuellos]

Driver is using now pci subsystem generics reads and writes and requesting
bus resources without using legacy code functions. Because of this there is
a lot of dead code that can be removed.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 153 --------------------------------
 1 file changed, 153 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 45c02f7..14b9107 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -123,15 +123,6 @@
 	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 #define MV_READ(ofs, data)	\
 	*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_WRITE_16(ofs, data)	\
-	*(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data)	\
-	*(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data)	\
-	*(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data)	\
-	*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
@@ -176,13 +167,6 @@
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
 
-#define PCI_ACCESS_READ_1  0
-#define PCI_ACCESS_READ_2  1
-#define PCI_ACCESS_READ_4  2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
-
 /**
  * struct mt7621_pcie_port - PCIe port information
  * @base: IO mapped register base
@@ -216,118 +200,6 @@ static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 		(func << 8) | (where & 0xfc) | 0x80000000;
 }
 
-static int config_access(unsigned char access_type, struct pci_bus *bus,
-			unsigned int devfn, unsigned int where, u32 *data)
-{
-	unsigned int slot = PCI_SLOT(devfn);
-	u8 func = PCI_FUNC(devfn);
-	u32 address_reg, data_reg;
-	unsigned int address;
-
-	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-
-	address = mt7621_pci_get_cfgaddr(bus->number, slot, func, where);
-
-	MV_WRITE(address_reg, address);
-
-	switch (access_type) {
-	case PCI_ACCESS_WRITE_1:
-		MV_WRITE_8(data_reg+(where&0x3), *data);
-		break;
-	case PCI_ACCESS_WRITE_2:
-		MV_WRITE_16(data_reg+(where&0x3), *data);
-		break;
-	case PCI_ACCESS_WRITE_4:
-		MV_WRITE(data_reg, *data);
-		break;
-	case PCI_ACCESS_READ_1:
-		MV_READ_8(data_reg+(where&0x3), data);
-		break;
-	case PCI_ACCESS_READ_2:
-		MV_READ_16(data_reg+(where&0x3), data);
-		break;
-	case PCI_ACCESS_READ_4:
-		MV_READ(data_reg, data);
-		break;
-	default:
-		printk("no specify access type\n");
-		break;
-	}
-	return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
-	return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
-	return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
-	return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
-		return -1;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
-		return -1;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
-		return -1;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
-{
-	switch (size) {
-	case 1:
-		return read_config_byte(bus, devfn, where, (u8 *) val);
-	case 2:
-		return read_config_word(bus, devfn, where, (u16 *) val);
-	default:
-		return read_config_dword(bus, devfn, where, val);
-	}
-}
-
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-{
-	switch (size) {
-	case 1:
-		return write_config_byte(bus, devfn, where, (u8) val);
-	case 2:
-		return write_config_word(bus, devfn, where, (u16) val);
-	default:
-		return write_config_dword(bus, devfn, where, val);
-	}
-}
-
 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
 					 unsigned int devfn, int where)
 {
@@ -499,24 +371,6 @@ set_phy_for_ssc(void)
 	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
 }
 
-void setup_cm_memory_region(struct resource *mem_resource)
-{
-	resource_size_t mask;
-	if (mips_cps_numiocu(0)) {
-		/* FIXME: hardware doesn't accept mask values with 1s after
-		 * 0s (e.g. 0xffef), so it would be great to warn if that's
-		 * about to happen */
-		mask = ~(mem_resource->end - mem_resource->start);
-
-		write_gcr_reg1_base(mem_resource->start);
-		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-			(unsigned long long)read_gcr_reg1_base(),
-			(unsigned long long)read_gcr_reg1_mask());
-	}
-}
-
-
 static int mt7621_pci_parse_request_of_pci_ranges(struct device *dev,
 						  struct list_head *res)
 {
@@ -612,13 +466,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		return err;
 	}
 
-	/*
-	iomem_resource.start = 0;
-	iomem_resource.end = ~0;
-	ioport_resource.start = 0;
-	ioport_resource.end = ~0;
-	*/
-
 	val = RALINK_PCIE0_RST;
 	val |= RALINK_PCIE1_RST;
 	val |= RALINK_PCIE2_RST;
-- 
2.7.4

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[PATCH v6 03/15] staging: mt7621-pci: add pcie_write and pcie_read helpers

[Sergio Paracuellos]

Introdice this functions to make easier to write/read to/from
an offset relative to base address

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 14b9107..a20e903 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -193,6 +193,16 @@ struct mt7621_pcie {
 	struct list_head ports;
 };
 
+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
+{
+	return readl(pcie->base + reg);
+}
+
+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
+{
+	writel(val, pcie->base + reg);
+}
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
-- 
2.7.4

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[PATCH v6 04/15] staging: mt7621-pci: use pcie_[read|write] in [write|read]_config

[Sergio Paracuellos]

Instead of custom macros use pcie_read and pcie_write functions.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 67 ++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 35 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index a20e903..84e6f41 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -229,41 +229,38 @@ struct pci_ops mt7621_pci_ops = {
 };
 
 static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
+read_config(struct mt7621_pcie *pcie,
+	    unsigned long bus, unsigned long dev,
+	    unsigned long func, unsigned long reg, unsigned long *val)
 {
-	u32 address_reg, data_reg, address;
-
-	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-	address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
-	MV_WRITE(address_reg, address);
-	MV_READ(data_reg, val);
-	return;
+	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+	*val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 }
 
 static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie,
+	     unsigned long bus, unsigned long dev,
+	     unsigned long func, unsigned long reg, unsigned long val)
 {
-	u32 address_reg, data_reg, address;
-
-	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-	address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
-	MV_WRITE(address_reg, address);
-	MV_WRITE(data_reg, val);
-	return;
+	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 }
 
 int
 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
+	struct mt7621_pcie *pcie = dev->bus->sysdata;
 	u16 cmd;
 	u32 val;
 	int irq;
 
 	if (dev->bus->number == 0) {
-		write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
+		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+		read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
 
@@ -501,13 +498,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst();
 	set_phy_for_ssc();
 
-	read_config(0, 0, 0, 0x70c, &val);
+	read_config(pcie, 0, 0, 0, 0x70c, &val);
 	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(0, 1, 0, 0x70c, &val);
+	read_config(pcie, 0, 1, 0, 0x70c, &val);
 	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(0, 2, 0, 0x70c, &val);
+	read_config(pcie, 0, 2, 0, 0x70c, &val);
 	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -628,28 +625,28 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	switch (pcie_link_status) {
 	case 7:
-		read_config(0, 2, 0, 0x4, &val);
-		write_config(0, 2, 0, 0x4, val|0x4);
-		read_config(0, 2, 0, 0x70c, &val);
+		read_config(pcie, 0, 2, 0, 0x4, &val);
+		write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+		read_config(pcie, 0, 2, 0, 0x70c, &val);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 2, 0, 0x70c, val);
+		write_config(pcie, 0, 2, 0, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
-		read_config(0, 1, 0, 0x4, &val);
-		write_config(0, 1, 0, 0x4, val|0x4);
-		read_config(0, 1, 0, 0x70c, &val);
+		read_config(pcie, 0, 1, 0, 0x4, &val);
+		write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+		read_config(pcie, 0, 1, 0, 0x70c, &val);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 1, 0, 0x70c, val);
+		write_config(pcie, 0, 1, 0, 0x70c, val);
 	default:
-		read_config(0, 0, 0, 0x4, &val);
-		write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
-		read_config(0, 0, 0, 0x70c, &val);
+		read_config(pcie, 0, 0, 0, 0x4, &val);
+		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+		read_config(pcie, 0, 0, 0, 0x70c, &val);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 0, 0, 0x70c, val);
+		write_config(pcie, 0, 0, 0, 0x70c, val);
 	}
 
 	list_splice_init(&res, &bridge->windows);
-- 
2.7.4

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[PATCH v6 05/15] staging: mt7621-pci: simplify read_config function

[Sergio Paracuellos]

read_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Return readed value instead pass a reference
parameter.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 32 +++++++++++++++-----------------
 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 84e6f41..4a729de 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -228,15 +228,13 @@ struct pci_ops mt7621_pci_ops = {
 	.write		= pci_generic_config_write,
 };
 
-static void
-read_config(struct mt7621_pcie *pcie,
-	    unsigned long bus, unsigned long dev,
-	    unsigned long func, unsigned long reg, unsigned long *val)
+static u32
+read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 {
-	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-	*val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 }
 
 static void
@@ -260,7 +258,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 
 	if (dev->bus->number == 0) {
 		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
+		val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
 
@@ -453,7 +451,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	struct pci_host_bridge *bridge;
 	struct pci_bus *bus, *child;
 	int err;
-	unsigned long val = 0;
+	u32 val = 0;
 	LIST_HEAD(res);
 
 	if (!dev->of_node)
@@ -498,13 +496,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst();
 	set_phy_for_ssc();
 
-	read_config(pcie, 0, 0, 0, 0x70c, &val);
+	val = read_config(pcie, 0, 0x70c);
 	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(pcie, 0, 1, 0, 0x70c, &val);
+	val = read_config(pcie, 1, 0x70c);
 	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(pcie, 0, 2, 0, 0x70c, &val);
+	val = read_config(pcie, 2, 0x70c);
 	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -625,25 +623,25 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	switch (pcie_link_status) {
 	case 7:
-		read_config(pcie, 0, 2, 0, 0x4, &val);
+		val = read_config(pcie, 2, 0x4);
 		write_config(pcie, 0, 2, 0, 0x4, val|0x4);
-		read_config(pcie, 0, 2, 0, 0x70c, &val);
+		val = read_config(pcie, 2, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
 		write_config(pcie, 0, 2, 0, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
-		read_config(pcie, 0, 1, 0, 0x4, &val);
+		val = read_config(pcie, 1, 0x4);
 		write_config(pcie, 0, 1, 0, 0x4, val|0x4);
-		read_config(pcie, 0, 1, 0, 0x70c, &val);
+		val = read_config(pcie, 1, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
 		write_config(pcie, 0, 1, 0, 0x70c, val);
 	default:
-		read_config(pcie, 0, 0, 0, 0x4, &val);
+		val = read_config(pcie, 0, 0x4);
 		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
-		read_config(pcie, 0, 0, 0, 0x70c, &val);
+		val = read_config(pcie, 0, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
 		write_config(pcie, 0, 0, 0, 0x70c, val);
-- 
2.7.4

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[PATCH v6 06/15] staging: mt7621-pci: simplify write_config function

[Sergio Paracuellos]

write_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Review parameter types changing for more proper
ones.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 4a729de..dfc83ed 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -238,11 +238,9 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 }
 
 static void
-write_config(struct mt7621_pcie *pcie,
-	     unsigned long bus, unsigned long dev,
-	     unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 {
-	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
@@ -257,7 +255,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 	int irq;
 
 	if (dev->bus->number == 0) {
-		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+		write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 		val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
@@ -624,27 +622,27 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	switch (pcie_link_status) {
 	case 7:
 		val = read_config(pcie, 2, 0x4);
-		write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+		write_config(pcie, 2, 0x4, val|0x4);
 		val = read_config(pcie, 2, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(pcie, 0, 2, 0, 0x70c, val);
+		write_config(pcie, 2, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
 		val = read_config(pcie, 1, 0x4);
-		write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+		write_config(pcie, 1, 0x4, val|0x4);
 		val = read_config(pcie, 1, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(pcie, 0, 1, 0, 0x70c, val);
+		write_config(pcie, 1, 0x70c, val);
 	default:
 		val = read_config(pcie, 0, 0x4);
-		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+		write_config(pcie, 0, 0x4, val|0x4); //bus master enable
 		val = read_config(pcie, 0, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(pcie, 0, 0, 0, 0x70c, val);
+		write_config(pcie, 0, 0x70c, val);
 	}
 
 	list_splice_init(&res, &bridge->windows);
-- 
2.7.4

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[PATCH v6 07/15] staging: mt7621-pci: remove unused macros

[Sergio Paracuellos]

There some macros that are not being used. Remove them.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 24 +-----------------------
 1 file changed, 1 insertion(+), 23 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index dfc83ed..adac455 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -84,7 +84,6 @@
 #define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
 #define RALINK_PCI_BASE	0xBE140000
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RT6855_PCIE0_OFFSET		0x2000
 #define RT6855_PCIE1_OFFSET		0x3000
 #define RT6855_PCIE2_OFFSET		0x4000
@@ -95,8 +94,6 @@
 #define RALINK_PCI0_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
 #define RALINK_PCI0_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
 #define RALINK_PCI0_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-#define RALINK_PCI0_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
-#define RALINK_PCI0_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
 
 #define RALINK_PCI1_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
 #define RALINK_PCI1_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
@@ -104,8 +101,6 @@
 #define RALINK_PCI1_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
 #define RALINK_PCI1_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 #define RALINK_PCI1_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-#define RALINK_PCI1_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
-#define RALINK_PCI1_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 
 #define RALINK_PCI2_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 #define RALINK_PCI2_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
@@ -113,17 +108,10 @@
 #define RALINK_PCI2_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 #define RALINK_PCI2_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 #define RALINK_PCI2_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
-#define RALINK_PCI2_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
-#define RALINK_PCI2_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
 
-#define MV_WRITE(ofs, data)	\
-	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define MV_READ(ofs, data)	\
-	*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
@@ -141,28 +129,18 @@
 		else							\
 			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
 	} while (0)
+
 #define RALINK_CLKCFG1			0x30
 #define RALINK_RSTCTRL			0x34
 #define RALINK_GPIOMODE			0x60
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
-#define PPLL_CFG1			0x9c
-#define PPLL_DRV			0xa0
-/* SYSC_REG_SYSTEM_CONFIG1 bits */
-#define RALINK_PCI_HOST_MODE_EN		(1<<7)
-#define RALINK_PCIE_RC_MODE_EN		(1<<8)
 //RALINK_RSTCTRL bit
 #define RALINK_PCIE_RST			(1<<23)
 #define RALINK_PCI_RST			(1<<24)
 //RALINK_CLKCFG1 bit
 #define RALINK_PCI_CLK_EN		(1<<19)
 #define RALINK_PCIE_CLK_EN		(1<<21)
-//RALINK_GPIOMODE bit
-#define PCI_SLOTx2			(1<<11)
-#define PCI_SLOTx1			(2<<11)
-//MTK PCIE PLL bit
-#define PDRV_SW_SET			(1<<31)
-#define LC_CKDRVPD_			(1<<19)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
-- 
2.7.4

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[PATCH v6 08/15] staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write]

[Sergio Paracuellos]

Use pcie_[read|write] fucntions to read and write controller registers.
Define those only by offset and pass controller offset + register offset
relative to base address to functions.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 70 ++++++++++++++++-----------------
 1 file changed, 34 insertions(+), 36 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index adac455..05816e3 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
-#define RALINK_PCI_MEMBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
-#define RALINK_PCI_IOBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
+#define RALINK_PCI_MEMBASE		0x28
+#define RALINK_PCI_IOBASE		0x2C
 #define RALINK_PCIE0_RST		(1<<24)
 #define RALINK_PCIE1_RST		(1<<25)
 #define RALINK_PCIE2_RST		(1<<26)
@@ -88,26 +88,12 @@
 #define RT6855_PCIE1_OFFSET		0x3000
 #define RT6855_PCIE2_OFFSET		0x4000
 
-#define RALINK_PCI0_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
+#define RALINK_PCI_BAR0SETUP_ADDR	0x0010
+#define RALINK_PCI_IMBASEBAR0_ADDR	0x0018
+#define RALINK_PCI_ID			0x0030
+#define RALINK_PCI_CLASS		0x0034
+#define RALINK_PCI_SUBID		0x0038
+#define RALINK_PCI_STATUS		0x0050
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
@@ -495,7 +481,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
 	mdelay(1000);
 
-	if ((RALINK_PCI0_STATUS & 0x1) == 0) {
+	if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 		printk("PCIE0 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
@@ -505,7 +491,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 	}
 
-	if ((RALINK_PCI1_STATUS & 0x1) == 0) {
+	if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 		printk("PCIE1 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
@@ -515,7 +501,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 	}
 
-	if ((RALINK_PCI2_STATUS & 0x1) == 0) {
+	if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 		printk("PCIE2 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
@@ -570,30 +556,42 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	ioport_resource.end = mt7621_res_pci_io1.end;
 */
 
-	RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
-	RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
+	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
+	pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
 	//PCIe0
 	if ((pcie_link_status & 0x1) != 0) {
-		RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI0_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		pcie_write(pcie, 0x7FFF0001,
+			   RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
+		pcie_write(pcie, MEMORY_BASE,
+			   RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
+		pcie_write(pcie, 0x06040001,
+			   RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
 		printk("PCIE0 enabled\n");
 	}
 
 	//PCIe1
 	if ((pcie_link_status & 0x2) != 0) {
-		RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI1_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		pcie_write(pcie, 0x7FFF0001,
+			   RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
+		pcie_write(pcie, MEMORY_BASE,
+			   RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
+		pcie_write(pcie, 0x06040001,
+			   RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
 		printk("PCIE1 enabled\n");
 	}
 
 	//PCIe2
 	if ((pcie_link_status & 0x4) != 0) {
-		RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI2_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		pcie_write(pcie, 0x7FFF0001,
+			   RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
+		pcie_write(pcie, MEMORY_BASE,
+			   RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
+		pcie_write(pcie, 0x06040001,
+			   RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
 		printk("PCIE2 enabled\n");
 	}
 
-- 
2.7.4

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[PATCH v6 09/15] staging: mt7621-pci: review includes putting them in alphabethic order

[Sergio Paracuellos]

There are some includes that are being used that are not really
needed to correct driver compilation. Remove them and reorder the
rest alphabetically.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 05816e3..85e8dc8 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -40,26 +40,20 @@
  **************************************************************************
  */
 
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/version.h>
-#include <linux/pci.h>
-#include <linux/io.h>
-#include <asm/mips-cm.h>
-#include <linux/init.h>
-#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/module.h>
 #include <linux/of.h>
-#include <linux/of_pci.h>
-#include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
 #include <linux/platform_device.h>
-
-#include <ralink_regs.h>
+#include <linux/reset.h>
 #include <mt7621.h>
+#include <ralink_regs.h>
 
 #include "../../pci/pci.h"
 
-- 
2.7.4

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[PATCH v6 10/15] staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR

[Sergio Paracuellos]

RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR are defined to be directly
referenced for read and write. Use pcie_read and pcie_write instead changing
its definition to a simple relative offset to pcie base address.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 54 +++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 85e8dc8..034c6c5 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
 #define RALINK_PCIE1_RST		(1<<25)
 #define RALINK_PCIE2_RST		(1<<26)
 
-#define RALINK_PCI_PCICFG_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
-#define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
+#define RALINK_PCI_PCICFG_ADDR		0x0000
+#define RALINK_PCI_PCIMSK_ADDR		0x000C
 #define RALINK_PCI_BASE	0xBE140000
 
 #define RT6855_PCIE0_OFFSET		0x2000
@@ -482,7 +482,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<0);
 	} else {
 		pcie_link_status |= 1<<0;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= (1<<20); // enable pcie1 interrupt
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
@@ -492,7 +494,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<1);
 	} else {
 		pcie_link_status |= 1<<1;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= (1<<21); // enable pcie1 interrupt
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
@@ -502,7 +506,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<2);
 	} else {
 		pcie_link_status |= 1<<2;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= (1<<22); // enable pcie2 interrupt
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if (pcie_link_status == 0)
@@ -521,27 +527,35 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 */
 	switch (pcie_link_status) {
 	case 2:
-		RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x00ff0000;
+		val |= 0x1 << 16;	// port 0
+		val |= 0x0 << 20;	// port 1
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	case 4:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;	//port2
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x0fff0000;
+		val |= 0x1 << 16;	//port0
+		val |= 0x2 << 20;	//port1
+		val |= 0x0 << 24;	//port2
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	case 5:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x0fff0000;
+		val |= 0x0 << 16;	//port0
+		val |= 0x2 << 20;	//port1
+		val |= 0x1 << 24;	//port2
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	case 6:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x0fff0000;
+		val |= 0x2 << 16;	//port0
+		val |= 0x0 << 20;	//port1
+		val |= 0x1 << 24;	//port2
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	}
 
-- 
2.7.4

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[PATCH v6 11/15] staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions

[Sergio Paracuellos]

RALINK_PCI_BASE has no sense and this driver has base address readed
and mapped from device tree. Remove remaining uses of it and
change code to use pcie_read and pcie_write functions in places
where this was being used.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 131 ++++++++++++++++----------------
 1 file changed, 67 insertions(+), 64 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 034c6c5..93821aa 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -76,7 +76,6 @@
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
-#define RALINK_PCI_BASE	0xBE140000
 
 #define RT6855_PCIE0_OFFSET		0x2000
 #define RT6855_PCIE1_OFFSET		0x3000
@@ -89,8 +88,8 @@
 #define RALINK_PCI_SUBID		0x0038
 #define RALINK_PCI_STATUS		0x0050
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
 
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
@@ -231,105 +230,109 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
+	     int start_b, int bits, int val)
 {
-	*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
-	*(unsigned int *)(addr) |= val << start_b;
+	u32 reg = pcie_read(pcie, offset);
+
+	reg &= ~(((1 << bits) - 1) << start_b);
+	reg |= val << start_b;
+	pcie_write(pcie, reg, offset);
 }
 
 void
-bypass_pipe_rst(void)
+bypass_pipe_rst(struct mt7621_pcie *pcie)
 {
 	/* PCIe Port 0 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 	/* PCIe Port 1 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 	/* PCIe Port 2 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 }
 
 void
-set_phy_for_ssc(void)
+set_phy_for_ssc(struct mt7621_pcie *pcie)
 {
 	unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 
 	reg = (reg >> 6) & 0x7;
 	/* Set PCIe Port0 & Port1 PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		printk("***** Xtal 40MHz *****\n");
 	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		if (reg >= 6) {
 			printk("***** Xtal 25MHz *****\n");
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
 		} else {
 			printk("***** Xtal 20MHz *****\n");
 		}
 	}
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
 	}
 	/* Enable PHY and disable force mode */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
 
 	/* Set PCIe Port2 PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		if (reg >= 6) {		// 25MHz Xtal
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
 		}
 	}
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
 	}
 	/* Enable PHY and disable force mode */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
 }
 
 static int mt7621_pci_parse_request_of_pci_ranges(struct device *dev,
@@ -449,8 +452,8 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	DEASSERT_SYSRST_PCIE(val);
 
 	if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
-		bypass_pipe_rst();
-	set_phy_for_ssc();
+		bypass_pipe_rst(pcie);
+	set_phy_for_ssc(pcie);
 
 	val = read_config(pcie, 0, 0x70c);
 	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
-- 
2.7.4

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[PATCH v6 12/15] staging: mt7621-pci: use BIT macro in preprocessor definitions

[Sergio Paracuellos]

Some preprocessor definitions are using a custom implementation of
BIT macro. Just use linux kernel BIT macro instead.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 93821aa..0217ee7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -62,17 +62,17 @@
  * devices.
  */
 
-#define RALINK_PCIE0_CLK_EN		(1<<24)
-#define RALINK_PCIE1_CLK_EN		(1<<25)
-#define RALINK_PCIE2_CLK_EN		(1<<26)
+#define RALINK_PCIE0_CLK_EN		BIT(24)
+#define RALINK_PCIE1_CLK_EN		BIT(25)
+#define RALINK_PCIE2_CLK_EN		BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
 #define RALINK_PCI_MEMBASE		0x28
 #define RALINK_PCI_IOBASE		0x2C
-#define RALINK_PCIE0_RST		(1<<24)
-#define RALINK_PCIE1_RST		(1<<25)
-#define RALINK_PCIE2_RST		(1<<26)
+#define RALINK_PCIE0_RST		BIT(24)
+#define RALINK_PCIE1_RST		BIT(25)
+#define RALINK_PCIE2_RST		BIT(26)
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
@@ -115,11 +115,11 @@
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
 //RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST			(1<<23)
-#define RALINK_PCI_RST			(1<<24)
+#define RALINK_PCIE_RST			BIT(23)
+#define RALINK_PCI_RST			BIT(24)
 //RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN		(1<<19)
-#define RALINK_PCIE_CLK_EN		(1<<21)
+#define RALINK_PCI_CLK_EN		BIT(19)
+#define RALINK_PCIE_CLK_EN		BIT(21)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
-- 
2.7.4

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[PATCH v6 13/15] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition

[Sergio Paracuellos]

RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 0217ee7..9feca70 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -67,7 +67,7 @@
 #define RALINK_PCIE2_CLK_EN		BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
+#define RALINK_PCI_CONFIG_DATA		0x24
 #define RALINK_PCI_MEMBASE		0x28
 #define RALINK_PCI_IOBASE		0x2C
 #define RALINK_PCIE0_RST		BIT(24)
@@ -176,7 +176,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
 
 	writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
 
-	return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+	return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
 }
 
 struct pci_ops mt7621_pci_ops = {
@@ -191,7 +191,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
 }
 
 static void
@@ -200,7 +200,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 }
 
 int
-- 
2.7.4

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[PATCH v6 14/15] staging: mt7621-pci: remove remaining pci_legacy dependant code

[Sergio Paracuellos]

pcibios_* remaining code is not neccessary at all. We can use
map_irq set to of_irq_parse_and_map_pci driver 'probe' function.
Remove this code.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 33 +--------------------------------
 1 file changed, 1 insertion(+), 32 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 9feca70..0bf450f 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -203,32 +203,6 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 }
 
-int
-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	struct mt7621_pcie *pcie = dev->bus->sysdata;
-	u16 cmd;
-	u32 val;
-	int irq;
-
-	if (dev->bus->number == 0) {
-		write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
-		printk("BAR0 at slot %d = %x\n", slot, val);
-	}
-
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
-	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
-	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-	pci_write_config_word(dev, PCI_COMMAND, cmd);
-
-	irq = of_irq_parse_and_map_pci(dev, slot, pin);
-
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-	return irq;
-}
-
 void
 set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
 	     int start_b, int bits, int val)
@@ -637,7 +611,7 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	bridge->dev.parent = dev;
 	bridge->sysdata = pcie;
 	bridge->ops = &mt7621_pci_ops;
-	bridge->map_irq = pcibios_map_irq;
+	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
 
 	err = pci_scan_root_bus_bridge(bridge);
@@ -655,11 +629,6 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	return 0;
 }
 
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
-
 static const struct of_device_id mt7621_pci_ids[] = {
 	{ .compatible = "mediatek,mt7621-pci" },
 	{},
-- 
2.7.4

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[PATCH v6 15/15] staging: mt7621-dts: add pcie controller port registers

[Sergio Paracuellos]

The pcie node of the device tree only contains registers
for the host-bridge and pcie port 0. Add the pcie port 1
and pcie port 2 also.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-dts/mt7621.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 4610403..2e837e6 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -394,8 +394,10 @@
 
 	pcie: pcie@1e140000 {
 		compatible = "mediatek,mt7621-pci";
-		reg = <0x1e140000 0x100
-			0x1e142000 0x100>;
+		reg = <0x1e140000 0x100     /* host-pci bridge registers */
+			0x1e142000 0x100    /* pcie port 0 RC control registers */
+			0x1e143000 0x100    /* pcie port 1 RC control registers */
+			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 
 		#address-cells = <3>;
 		#size-cells = <2>;
-- 
2.7.4

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Re: [PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[NeilBrown]

[-- Attachment #1.1: Type: text/plain, Size: 25108 bytes --]

On Mon, Jul 30 2018, Sergio Paracuellos wrote:

> This patch series include an attempt to avoid the use of custom
> read and writes in driver code and use PCI subsystem common ones.
>
> In order to do this 'map_bus' callback is implemented and also
> data structures for driver are included. The regs base address
> is being readed from device tree and the driver gets clean a lot
> of code.
>
> Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.
>
> Changes in v6:
>     - Reorder patches to be each patch correct in itself.
>     - PATCH 1 adds also Kconfig to do the step from legacy to generic code
>     - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
>       a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
>     - Other patches rebased and adapted with this changes.

No noticeable difference.
Still hangs after
[    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)

the readl() at the start of ahci_enable_ahci() hangs, reading c4017004.

I built on a merge of
 Merge: 527838d470e3 b9f13084580c

linus' master + staging/staging-testing

dmesg below.

Thanks,
NeilBrown

[    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #254 SMP Tue Jul 31 08:49:52 AEST 2018
[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
[    0.000000] MIPS: machine is GB-PC1
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 1c000000 @ 00000000 (usable)
[    0.000000]  memory: 04000000 @ 20000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] VPE topology {2,2} total 4
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
[    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
[    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
[    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
[    0.000000] Kernel command line: console=ttyS0,57600
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Writing ErrCtl register=00010882
[    0.000000] Readback ErrCtl register=00010882
[    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS: 256
[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
[    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
[    0.070000] pid_max: default: 32768 minimum: 301
[    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.100000] Hierarchical SRCU implementation.
[    0.110000] smp: Bringing up secondary CPUs ...
[    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
[    0.180000] Synchronize counters for CPU 1: done.
[    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
[    0.280000] Synchronize counters for CPU 2: done.
[    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
[    0.380000] Synchronize counters for CPU 3: done.
[    0.420000] smp: Brought up 1 node, 4 CPUs
[    0.430000] devtmpfs: initialized
[    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
[    0.500000] pinctrl core: initialized pinctrl subsystem
[    0.510000] NET: Registered protocol family 16
[    0.570000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
[    0.580000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
[    0.600000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
[    0.910000] ***** Xtal 40MHz *****
[    0.920000] Port 0 N_FTS = 1b102800
[    0.930000] Port 1 N_FTS = 1b102800
[    0.930000] Port 2 N_FTS = 1b102800
[    1.990000] PCIE0 enabled
[    2.000000] PCIE1 enabled
[    2.000000] PCIE2 enabled
[    2.010000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
[    2.020000] pci_bus 0000:00: root bus resource [bus 00-ff]
[    2.030000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
[    2.060000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.070000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.090000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.110000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    2.120000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[    2.130000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[    2.140000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[    2.160000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.170000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[    2.180000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.200000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
[    2.210000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.220000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[    2.240000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
[    2.250000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
[    2.260000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
[    2.280000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
[    2.290000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
[    2.300000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
[    2.320000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
[    2.330000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
[    2.340000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
[    2.360000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
[    2.370000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
[    2.380000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
[    2.390000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
[    2.410000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
[    2.420000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
[    2.430000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
[    2.450000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.460000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
[    2.470000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.480000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
[    2.500000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.510000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
[    2.520000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.530000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
[    2.550000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.560000] pci 0000:00:00.0: PCI bridge to [bus 01]
[    2.570000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
[    2.580000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
[    2.600000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
[    2.610000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
[    2.620000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.640000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
[    2.650000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.660000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
[    2.670000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.690000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
[    2.700000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.710000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
[    2.720000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.740000] pci 0000:00:01.0: PCI bridge to [bus 02]
[    2.750000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
[    2.760000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
[    2.770000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
[    2.790000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
[    2.800000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.810000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
[    2.820000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.840000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
[    2.850000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.860000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
[    2.870000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.890000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
[    2.900000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.910000] pci 0000:00:02.0: PCI bridge to [bus 03]
[    2.920000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
[    2.940000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
[    3.020000] SCSI subsystem initialized
[    3.030000] random: fast init done
[    3.040000] clocksource: Switched to clocksource GIC
[    3.060000] NET: Registered protocol family 2
[    3.070000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[    3.080000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[    3.100000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[    3.110000] TCP: Hash tables configured (established 4096 bind 4096)
[    3.120000] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    3.140000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    3.150000] NET: Registered protocol family 1
[    8.130000] Initialise system trusted keyrings
[    8.140000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
[    8.270000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    8.280000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    8.310000] SGI XFS with security attributes, no debug enabled
[    8.360000] Key type asymmetric registered
[    8.370000] Asymmetric key parser 'x509' registered
[    8.380000] bounce: pool size: 64 pages
[    8.390000] io scheduler noop registered
[    8.400000] io scheduler deadline registered (default)
[    8.410000] io scheduler mq-deadline registered (default)
[    8.420000] io scheduler kyber registered
[    8.430000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
[    8.460000] console [ttyS0] disabled
[    8.460000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
[    8.480000] console [ttyS0] enabled
[    8.480000] console [ttyS0] enabled
[    8.500000] bootconsole [early0] disabled
[    8.500000] bootconsole [early0] disabled
[    8.510000] cacheinfo: Failed to find cpu0 device node
[    8.520000] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    8.610000] loop: module loaded
[    8.620000] pci 0000:00:00.0: enabling device (0004 -> 0006)
[    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)


Though messages were a little different first time:

[    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #253 SMP Tue Jul 31 08:41:34 AEST 2018
[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
[    0.000000] MIPS: machine is GB-PC1
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 1c000000 @ 00000000 (usable)
[    0.000000]  memory: 04000000 @ 20000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] VPE topology {2,2} total 4
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
[    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
[    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
[    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
[    0.000000] Kernel command line: console=ttyS0,57600
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Writing ErrCtl register=000108a2
[    0.000000] Readback ErrCtl register=000108a2
[    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS: 256
[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
[    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
[    0.070000] pid_max: default: 32768 minimum: 301
[    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.100000] Hierarchical SRCU implementation.
[    0.110000] smp: Bringing up secondary CPUs ...
[    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
[    0.180000] Synchronize counters for CPU 1: done.
[    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
[    0.280000] Synchronize counters for CPU 2: done.
[    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
[    0.380000] Synchronize counters for CPU 3: done.
[    0.420000] smp: Brought up 1 node, 4 CPUs
[    0.430000] devtmpfs: initialized
[    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
[    0.500000] pinctrl core: initialized pinctrl subsystem
[    0.510000] NET: Registered protocol family 16
[    0.570000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
[    0.580000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
[    0.600000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
[    0.910000] ***** Xtal 40MHz *****
[    0.920000] Port 0 N_FTS = 1b105000
[    0.930000] Port 1 N_FTS = 1b105000
[    0.930000] Port 2 N_FTS = 1b105000
[    1.990000] PCIE0 enabled
[    2.000000] PCIE1 enabled
[    2.000000] PCIE2 enabled
[    2.010000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
[    2.020000] pci_bus 0000:00: root bus resource [bus 00-ff]
[    2.030000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
[    2.050000] pci 0000:00:00.0: reg 0x14: initial BAR value 0x60300000 invalid
[    2.070000] pci 0000:00:01.0: reg 0x14: initial BAR value 0x60310000 invalid
[    2.080000] pci 0000:00:02.0: reg 0x14: initial BAR value 0x60320000 invalid
[    2.100000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    2.110000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[    2.130000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[    2.140000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[    2.150000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.160000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[    2.180000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.190000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
[    2.200000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.220000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[    2.230000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff]
[    2.240000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
[    2.260000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60300000-0x6030ffff]
[    2.270000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60310000-0x6031ffff]
[    2.280000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60320000-0x6032ffff]
[    2.300000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
[    2.310000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
[    2.320000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
[    2.330000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
[    2.350000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
[    2.360000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
[    2.370000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
[    2.390000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
[    2.400000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.410000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
[    2.420000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.440000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
[    2.450000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.460000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
[    2.470000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.490000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
[    2.500000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.510000] pci 0000:00:00.0: PCI bridge to [bus 01]
[    2.520000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
[    2.530000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60100000-0x601001ff]
[    2.550000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
[    2.560000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.570000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
[    2.590000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.600000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
[    2.610000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.620000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
[    2.640000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.650000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
[    2.660000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.670000] pci 0000:00:01.0: PCI bridge to [bus 02]
[    2.680000] pci 0000:00:01.0:   bridge window [mem 0x60100000-0x601fffff]
[    2.700000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
[    2.710000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
[    2.720000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.740000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
[    2.750000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.760000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
[    2.770000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.790000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
[    2.800000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.810000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
[    2.820000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.840000] pci 0000:00:02.0: PCI bridge to [bus 03]
[    2.850000] pci 0000:00:02.0:   bridge window [mem 0x60200000-0x602fffff]
[    2.930000] SCSI subsystem initialized
[    2.940000] random: fast init done
[    2.960000] clocksource: Switched to clocksource GIC
[    2.990000] NET: Registered protocol family 2
[    3.000000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[    3.020000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[    3.030000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[    3.040000] TCP: Hash tables configured (established 4096 bind 4096)
[    3.060000] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    3.070000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    3.080000] NET: Registered protocol family 1
[    8.070000] Initialise system trusted keyrings
[    8.080000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
[    8.210000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    8.220000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    8.250000] SGI XFS with security attributes, no debug enabled
[    8.300000] Key type asymmetric registered
[    8.310000] Asymmetric key parser 'x509' registered
[    8.320000] bounce: pool size: 64 pages
[    8.330000] io scheduler noop registered
[    8.330000] io scheduler deadline registered (default)
[    8.340000] io scheduler mq-deadline registered (default)
[    8.350000] io scheduler kyber registered
[    8.370000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
[    8.390000] console [ttyS0] disabled
[    8.400000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
[    8.420000] console [ttyS0] enabled
[    8.420000] console [ttyS0] enabled
[    8.430000] bootconsole [early0] disabled
[    8.430000] bootconsole [early0] disabled
[    8.450000] cacheinfo: Failed to find cpu0 device node
[    8.460000] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    8.550000] loop: module loaded
[    8.560000] ahci 0000:01:00.0: enabling device (0000 -> 0002)



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Re: [PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

On Tue, Jul 31, 2018 at 08:55:52AM +1000, NeilBrown wrote:
> On Mon, Jul 30 2018, Sergio Paracuellos wrote:
> 
> > This patch series include an attempt to avoid the use of custom
> > read and writes in driver code and use PCI subsystem common ones.
> >
> > In order to do this 'map_bus' callback is implemented and also
> > data structures for driver are included. The regs base address
> > is being readed from device tree and the driver gets clean a lot
> > of code.
> >
> > Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.
> >
> > Changes in v6:
> >     - Reorder patches to be each patch correct in itself.
> >     - PATCH 1 adds also Kconfig to do the step from legacy to generic code
> >     - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
> >       a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
> >     - Other patches rebased and adapted with this changes.
> 
> No noticeable difference.
> Still hangs after
> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> 
> the readl() at the start of ahci_enable_ahci() hangs, reading c4017004.
> 
> I built on a merge of
>  Merge: 527838d470e3 b9f13084580c
> 
> linus' master + staging/staging-testing
> 
> dmesg below.

Thanks for this.

> 
> Thanks,
> NeilBrown
> 
> [    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #254 SMP Tue Jul 31 08:49:52 AEST 2018
> [    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
> [    0.000000] bootconsole [early0] enabled
> [    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [    0.000000] MIPS: machine is GB-PC1
> [    0.000000] Determined physical RAM map:
> [    0.000000]  memory: 1c000000 @ 00000000 (usable)
> [    0.000000]  memory: 04000000 @ 20000000 (usable)
> [    0.000000] Initrd not found or empty - disabling initrd
> [    0.000000] VPE topology {2,2} total 4
> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.000000] Zone ranges:
> [    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
> [    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
> [    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
> [    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
> [    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
> [    0.000000] Kernel command line: console=ttyS0,57600
> [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [    0.000000] Writing ErrCtl register=00010882
> [    0.000000] Readback ErrCtl register=00010882
> [    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000] NR_IRQS: 256
> [    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
> [    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
> [    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
> [    0.070000] pid_max: default: 32768 minimum: 301
> [    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.100000] Hierarchical SRCU implementation.
> [    0.110000] smp: Bringing up secondary CPUs ...
> [    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
> [    0.180000] Synchronize counters for CPU 1: done.
> [    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
> [    0.280000] Synchronize counters for CPU 2: done.
> [    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
> [    0.380000] Synchronize counters for CPU 3: done.
> [    0.420000] smp: Brought up 1 node, 4 CPUs
> [    0.430000] devtmpfs: initialized
> [    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
> [    0.500000] pinctrl core: initialized pinctrl subsystem
> [    0.510000] NET: Registered protocol family 16
> [    0.570000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
> [    0.580000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
> [    0.600000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
> [    0.910000] ***** Xtal 40MHz *****
> [    0.920000] Port 0 N_FTS = 1b102800
> [    0.930000] Port 1 N_FTS = 1b102800
> [    0.930000] Port 2 N_FTS = 1b102800
> [    1.990000] PCIE0 enabled
> [    2.000000] PCIE1 enabled
> [    2.000000] PCIE2 enabled
> [    2.010000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [    2.020000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    2.030000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
> [    2.060000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.070000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.090000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.110000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    2.120000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [    2.130000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [    2.140000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [    2.160000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.170000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [    2.180000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.200000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [    2.210000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.220000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [    2.240000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
> [    2.250000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [    2.260000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
> [    2.280000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
> [    2.290000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
> [    2.300000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
> [    2.320000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
> [    2.330000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
> [    2.340000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [    2.360000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.370000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [    2.380000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.390000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [    2.410000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.420000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [    2.430000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.450000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.460000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.470000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.480000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.500000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.510000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.520000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.530000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.550000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.560000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    2.570000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [    2.580000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
> [    2.600000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [    2.610000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.620000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.640000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.650000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.660000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.670000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.690000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.700000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.710000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.720000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.740000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [    2.750000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
> [    2.760000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
> [    2.770000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
> [    2.790000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.800000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.810000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.820000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.840000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.850000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.860000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.870000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.890000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.900000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.910000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [    2.920000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
> [    2.940000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
> [    3.020000] SCSI subsystem initialized
> [    3.030000] random: fast init done
> [    3.040000] clocksource: Switched to clocksource GIC
> [    3.060000] NET: Registered protocol family 2
> [    3.070000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
> [    3.080000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
> [    3.100000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
> [    3.110000] TCP: Hash tables configured (established 4096 bind 4096)
> [    3.120000] UDP hash table entries: 256 (order: 1, 8192 bytes)
> [    3.140000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
> [    3.150000] NET: Registered protocol family 1
> [    8.130000] Initialise system trusted keyrings
> [    8.140000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
> [    8.270000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
> [    8.280000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
> [    8.310000] SGI XFS with security attributes, no debug enabled
> [    8.360000] Key type asymmetric registered
> [    8.370000] Asymmetric key parser 'x509' registered
> [    8.380000] bounce: pool size: 64 pages
> [    8.390000] io scheduler noop registered
> [    8.400000] io scheduler deadline registered (default)
> [    8.410000] io scheduler mq-deadline registered (default)
> [    8.420000] io scheduler kyber registered
> [    8.430000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
> [    8.460000] console [ttyS0] disabled
> [    8.460000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
> [    8.480000] console [ttyS0] enabled
> [    8.480000] console [ttyS0] enabled
> [    8.500000] bootconsole [early0] disabled
> [    8.500000] bootconsole [early0] disabled
> [    8.510000] cacheinfo: Failed to find cpu0 device node
> [    8.520000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    8.610000] loop: module loaded
> [    8.620000] pci 0000:00:00.0: enabling device (0004 -> 0006)
> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> 
> 
> Though messages were a little different first time:
> 
> [    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #253 SMP Tue Jul 31 08:41:34 AEST 2018
> [    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
> [    0.000000] bootconsole [early0] enabled
> [    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [    0.000000] MIPS: machine is GB-PC1
> [    0.000000] Determined physical RAM map:
> [    0.000000]  memory: 1c000000 @ 00000000 (usable)
> [    0.000000]  memory: 04000000 @ 20000000 (usable)
> [    0.000000] Initrd not found or empty - disabling initrd
> [    0.000000] VPE topology {2,2} total 4
> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.000000] Zone ranges:
> [    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
> [    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
> [    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
> [    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
> [    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
> [    0.000000] Kernel command line: console=ttyS0,57600
> [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [    0.000000] Writing ErrCtl register=000108a2
> [    0.000000] Readback ErrCtl register=000108a2
> [    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000] NR_IRQS: 256
> [    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
> [    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
> [    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
> [    0.070000] pid_max: default: 32768 minimum: 301
> [    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.100000] Hierarchical SRCU implementation.
> [    0.110000] smp: Bringing up secondary CPUs ...
> [    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
> [    0.180000] Synchronize counters for CPU 1: done.
> [    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
> [    0.280000] Synchronize counters for CPU 2: done.
> [    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
> [    0.380000] Synchronize counters for CPU 3: done.
> [    0.420000] smp: Brought up 1 node, 4 CPUs
> [    0.430000] devtmpfs: initialized
> [    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
> [    0.500000] pinctrl core: initialized pinctrl subsystem
> [    0.510000] NET: Registered protocol family 16
> [    0.570000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
> [    0.580000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
> [    0.600000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
> [    0.910000] ***** Xtal 40MHz *****
> [    0.920000] Port 0 N_FTS = 1b105000
> [    0.930000] Port 1 N_FTS = 1b105000
> [    0.930000] Port 2 N_FTS = 1b105000
> [    1.990000] PCIE0 enabled
> [    2.000000] PCIE1 enabled
> [    2.000000] PCIE2 enabled
> [    2.010000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [    2.020000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    2.030000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
> [    2.050000] pci 0000:00:00.0: reg 0x14: initial BAR value 0x60300000 invalid
> [    2.070000] pci 0000:00:01.0: reg 0x14: initial BAR value 0x60310000 invalid
> [    2.080000] pci 0000:00:02.0: reg 0x14: initial BAR value 0x60320000 invalid
> [    2.100000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    2.110000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [    2.130000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [    2.140000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [    2.150000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.160000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [    2.180000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.190000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [    2.200000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.220000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [    2.230000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff]
> [    2.240000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [    2.260000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60300000-0x6030ffff]
> [    2.270000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60310000-0x6031ffff]
> [    2.280000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60320000-0x6032ffff]
> [    2.300000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [    2.310000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.320000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [    2.330000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.350000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [    2.360000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.370000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [    2.390000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.400000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.410000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.420000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.440000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.450000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.460000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.470000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.490000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.500000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.510000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    2.520000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [    2.530000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60100000-0x601001ff]
> [    2.550000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.560000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.570000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.590000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.600000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.610000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.620000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.640000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.650000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.660000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.670000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [    2.680000] pci 0000:00:01.0:   bridge window [mem 0x60100000-0x601fffff]
> [    2.700000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [    2.710000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.720000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.740000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.750000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.760000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.770000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.790000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.800000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.810000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.820000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.840000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [    2.850000] pci 0000:00:02.0:   bridge window [mem 0x60200000-0x602fffff]
> [    2.930000] SCSI subsystem initialized
> [    2.940000] random: fast init done
> [    2.960000] clocksource: Switched to clocksource GIC
> [    2.990000] NET: Registered protocol family 2
> [    3.000000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
> [    3.020000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
> [    3.030000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
> [    3.040000] TCP: Hash tables configured (established 4096 bind 4096)
> [    3.060000] UDP hash table entries: 256 (order: 1, 8192 bytes)
> [    3.070000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
> [    3.080000] NET: Registered protocol family 1
> [    8.070000] Initialise system trusted keyrings
> [    8.080000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
> [    8.210000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
> [    8.220000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
> [    8.250000] SGI XFS with security attributes, no debug enabled
> [    8.300000] Key type asymmetric registered
> [    8.310000] Asymmetric key parser 'x509' registered
> [    8.320000] bounce: pool size: 64 pages
> [    8.330000] io scheduler noop registered
> [    8.330000] io scheduler deadline registered (default)
> [    8.340000] io scheduler mq-deadline registered (default)
> [    8.350000] io scheduler kyber registered
> [    8.370000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
> [    8.390000] console [ttyS0] disabled
> [    8.400000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
> [    8.420000] console [ttyS0] enabled
> [    8.420000] console [ttyS0] enabled
> [    8.430000] bootconsole [early0] disabled
> [    8.430000] bootconsole [early0] disabled
> [    8.450000] cacheinfo: Failed to find cpu0 device node
> [    8.460000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    8.550000] loop: module loaded
> [    8.560000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> 
> 

So this last dmesg is the new one with last v6, right? Because I can see 
that at least now the assigned resources are pretty much the same of the ones in the dmesg of the
original code talking in terms of assigned BAR's and bridge windows. No weird BAR 9 anymore, which I think is 
good. We can try to get back the hack which I removed at first and see what happend. The hack is
this function removed in PATCH 2:

-void setup_cm_memory_region(struct resource *mem_resource)
-{
-	resource_size_t mask;
-	if (mips_cps_numiocu(0)) {
-		/* FIXME: hardware doesn't accept mask values with 1s after
-		 * 0s (e.g. 0xffef), so it would be great to warn if that's
-		 * about to happen */
-		mask = ~(mem_resource->end - mem_resource->start);
-
-		write_gcr_reg1_base(mem_resource->start);
-		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-			(unsigned long long)read_gcr_reg1_base(),
-			(unsigned long long)read_gcr_reg1_mask());
-	}
-}

We can try to add it again and and call it from 'mt7621_pci_parse_request_of_pci_ranges'
in the label of the case of the case 'IORESOURCE_MEM' (as you can see this was intentionally
without code just to test this if this v6 fails):

		break;
		case IORESOURCE_MEM:
+           setup_cm_memory_region(res);
			break;

If this also fails we can try to move the call to 'mt7621_pcie_parse_dt(pcie, &res);' after the
HW initialization code just before the list_splice_init(&res, &bridge->windows); line:

-   err = mt7621_pcie_parse_dt(pcie, &res);
-	if (err) {
-		dev_err(dev, "Parsing DT failed\n");
-		return err;
-	}
-
-	/*
 	iomem_resource.start = 0;
 	iomem_resource.end = ~0;
...

        write_config(0, 0, 0, 0x70c, val);
 	}

+   err = mt7621_pcie_parse_dt(pcie, &res);
+	if (err) {
+		dev_err(dev, "Parsing DT failed\n");
+		return err;
+	}
+
    list_splice_init(&res, &bridge->windows);

(I don't have access now to the laptop with the code and cannot diff properly, sorry).

Hopefully it boots now?

Thanks in advance.

Best regards,
    Sergio Paracuellos
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Re: [PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[NeilBrown]

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On Tue, Jul 31 2018, Sergio Paracuellos wrote:

> On Tue, Jul 31, 2018 at 08:55:52AM +1000, NeilBrown wrote:
>> On Mon, Jul 30 2018, Sergio Paracuellos wrote:
>> 
>> > This patch series include an attempt to avoid the use of custom
>> > read and writes in driver code and use PCI subsystem common ones.
>> >
>> > In order to do this 'map_bus' callback is implemented and also
>> > data structures for driver are included. The regs base address
>> > is being readed from device tree and the driver gets clean a lot
>> > of code.
>> >
>> > Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.
>> >
>> > Changes in v6:
>> >     - Reorder patches to be each patch correct in itself.
>> >     - PATCH 1 adds also Kconfig to do the step from legacy to generic code
>> >     - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
>> >       a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
>> >     - Other patches rebased and adapted with this changes.
>> 
>> No noticeable difference.
>> Still hangs after
>> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
>> 
>> the readl() at the start of ahci_enable_ahci() hangs, reading c4017004.
>> 
>> I built on a merge of
>>  Merge: 527838d470e3 b9f13084580c
>> 
>> linus' master + staging/staging-testing
>> 
>> dmesg below.
>
> Thanks for this.
>
....
>> [    8.430000] bootconsole [early0] disabled
>> [    8.430000] bootconsole [early0] disabled
>> [    8.450000] cacheinfo: Failed to find cpu0 device node
>> [    8.460000] cacheinfo: Unable to detect cache hierarchy for CPU 0
>> [    8.550000] loop: module loaded
>> [    8.560000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
>> 
>> 
>
> So this last dmesg is the new one with last v6, right? Because I can see 

Right.


> that at least now the assigned resources are pretty much the same of the ones in the dmesg of the
> original code talking in terms of assigned BAR's and bridge windows. No weird BAR 9 anymore, which I think is 
> good. We can try to get back the hack which I removed at first and see what happend. The hack is
> this function removed in PATCH 2:
>
> -void setup_cm_memory_region(struct resource *mem_resource)
> -{
> -	resource_size_t mask;
> -	if (mips_cps_numiocu(0)) {
> -		/* FIXME: hardware doesn't accept mask values with 1s after
> -		 * 0s (e.g. 0xffef), so it would be great to warn if that's
> -		 * about to happen */
> -		mask = ~(mem_resource->end - mem_resource->start);
> -
> -		write_gcr_reg1_base(mem_resource->start);
> -		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
> -		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
> -			(unsigned long long)read_gcr_reg1_base(),
> -			(unsigned long long)read_gcr_reg1_mask());
> -	}
> -}
>
> We can try to add it again and and call it from 'mt7621_pci_parse_request_of_pci_ranges'
> in the label of the case of the case 'IORESOURCE_MEM' (as you can see this was intentionally
> without code just to test this if this v6 fails):
>
> 		break;
> 		case IORESOURCE_MEM:
> +           setup_cm_memory_region(res);
> 			break;

I added setup_cm_memory_region() back in and called it from
mt7621_pci_parse_request_of_pci_ranges()
as suggested.
Now we don't hang at the same place, but crash shortly after.

[    8.750000] WARNING: CPU: 2 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0

This is at the end of ahci_enable_ahci(). the HOST_AHCI_EN bit never was
set.


>
> If this also fails we can try to move the call to 'mt7621_pcie_parse_dt(pcie, &res);' after the
> HW initialization code just before the list_splice_init(&res, &bridge->windows); line:
>
> -   err = mt7621_pcie_parse_dt(pcie, &res);
> -	if (err) {
> -		dev_err(dev, "Parsing DT failed\n");
> -		return err;
> -	}
> -
> -	/*
>  	iomem_resource.start = 0;
>  	iomem_resource.end = ~0;
> ...
>
>         write_config(0, 0, 0, 0x70c, val);
>  	}
>
> +   err = mt7621_pcie_parse_dt(pcie, &res);
> +	if (err) {
> +		dev_err(dev, "Parsing DT failed\n");
> +		return err;
> +	}
> +
>     list_splice_init(&res, &bridge->windows);

If I move the call to mt7621_pcie_parse_dt() anywhere after
the call to set_phy_for_ssc() I get a crash at the start of
set_pcie_phy() called from set_phy_for_ssc(), presumably because
pcie->base isn't set.

Keep trying, I'm sure we'll get there.

NeilBrown

>
> (I don't have access now to the laptop with the code and cannot diff properly, sorry).
>
> Hopefully it boots now?
>
> Thanks in advance.
>
> Best regards,
>     Sergio Paracuellos

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Re: [PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

On Tue, Jul 31, 2018 at 03:25:43PM +1000, NeilBrown wrote:
> On Tue, Jul 31 2018, Sergio Paracuellos wrote:
> 
> > On Tue, Jul 31, 2018 at 08:55:52AM +1000, NeilBrown wrote:
> >> On Mon, Jul 30 2018, Sergio Paracuellos wrote:
> >> 
> >> > This patch series include an attempt to avoid the use of custom
> >> > read and writes in driver code and use PCI subsystem common ones.
> >> >
> >> > In order to do this 'map_bus' callback is implemented and also
> >> > data structures for driver are included. The regs base address
> >> > is being readed from device tree and the driver gets clean a lot
> >> > of code.
> >> >
> >> > Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.
> >> >
> >> > Changes in v6:
> >> >     - Reorder patches to be each patch correct in itself.
> >> >     - PATCH 1 adds also Kconfig to do the step from legacy to generic code
> >> >     - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
> >> >       a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
> >> >     - Other patches rebased and adapted with this changes.
> >> 
> >> No noticeable difference.
> >> Still hangs after
> >> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> >> 
> >> the readl() at the start of ahci_enable_ahci() hangs, reading c4017004.
> >> 
> >> I built on a merge of
> >>  Merge: 527838d470e3 b9f13084580c
> >> 
> >> linus' master + staging/staging-testing
> >> 
> >> dmesg below.
> >
> > Thanks for this.
> >
> ....
> >> [    8.430000] bootconsole [early0] disabled
> >> [    8.430000] bootconsole [early0] disabled
> >> [    8.450000] cacheinfo: Failed to find cpu0 device node
> >> [    8.460000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> >> [    8.550000] loop: module loaded
> >> [    8.560000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> >> 
> >> 
> >
> > So this last dmesg is the new one with last v6, right? Because I can see 
> 
> Right.
> 
> 
> > that at least now the assigned resources are pretty much the same of the ones in the dmesg of the
> > original code talking in terms of assigned BAR's and bridge windows. No weird BAR 9 anymore, which I think is 
> > good. We can try to get back the hack which I removed at first and see what happend. The hack is
> > this function removed in PATCH 2:
> >
> > -void setup_cm_memory_region(struct resource *mem_resource)
> > -{
> > -	resource_size_t mask;
> > -	if (mips_cps_numiocu(0)) {
> > -		/* FIXME: hardware doesn't accept mask values with 1s after
> > -		 * 0s (e.g. 0xffef), so it would be great to warn if that's
> > -		 * about to happen */
> > -		mask = ~(mem_resource->end - mem_resource->start);
> > -
> > -		write_gcr_reg1_base(mem_resource->start);
> > -		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
> > -		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
> > -			(unsigned long long)read_gcr_reg1_base(),
> > -			(unsigned long long)read_gcr_reg1_mask());
> > -	}
> > -}
> >
> > We can try to add it again and and call it from 'mt7621_pci_parse_request_of_pci_ranges'
> > in the label of the case of the case 'IORESOURCE_MEM' (as you can see this was intentionally
> > without code just to test this if this v6 fails):
> >
> > 		break;
> > 		case IORESOURCE_MEM:
> > +           setup_cm_memory_region(res);
> > 			break;
> 
> I added setup_cm_memory_region() back in and called it from
> mt7621_pci_parse_request_of_pci_ranges()
> as suggested.
> Now we don't hang at the same place, but crash shortly after.
> 
> [    8.750000] WARNING: CPU: 2 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
> 
> This is at the end of ahci_enable_ahci(). the HOST_AHCI_EN bit never was
> set.

So it seems this hack is really needed. Does something changed in dmesg with this?

> 
> 
> >
> > If this also fails we can try to move the call to 'mt7621_pcie_parse_dt(pcie, &res);' after the
> > HW initialization code just before the list_splice_init(&res, &bridge->windows); line:
> >
> > -   err = mt7621_pcie_parse_dt(pcie, &res);
> > -	if (err) {
> > -		dev_err(dev, "Parsing DT failed\n");
> > -		return err;
> > -	}
> > -
> > -	/*
> >  	iomem_resource.start = 0;
> >  	iomem_resource.end = ~0;
> > ...
> >
> >         write_config(0, 0, 0, 0x70c, val);
> >  	}
> >
> > +   err = mt7621_pcie_parse_dt(pcie, &res);
> > +	if (err) {
> > +		dev_err(dev, "Parsing DT failed\n");
> > +		return err;
> > +	}
> > +
> >     list_splice_init(&res, &bridge->windows);
> 
> If I move the call to mt7621_pcie_parse_dt() anywhere after
> the call to set_phy_for_ssc() I get a crash at the start of
> set_pcie_phy() called from set_phy_for_ssc(), presumably because
> pcie->base isn't set.
> 
> Keep trying, I'm sure we'll get there.

True, sorry. Maybe we can get out the mt7621_pci_parse_request_of_pci_ranges
call from mt7621_pcie_parse_dt and put it after the initialization code
just before the list_splice_init to try to reproduce the original code trace.

I never give up :). I only concern if I am not doing you to waste your time
with this tests. I really like to be able to test this by myself but this
board gets its price really increase buying it from Spain :-(.

> 
> NeilBrown

Best regards,
    Sergio Paracuellos

> 
> >
> > (I don't have access now to the laptop with the code and cannot diff properly, sorry).
> >
> > Hopefully it boots now?
> >
> > Thanks in advance.
> >
> > Best regards,
> >     Sergio Paracuellos


_______________________________________________
devel mailing list
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Re: [PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

On Tue, Jul 31, 2018 at 03:25:43PM +1000, NeilBrown wrote:
> On Tue, Jul 31 2018, Sergio Paracuellos wrote:
> 
> > On Tue, Jul 31, 2018 at 08:55:52AM +1000, NeilBrown wrote:
> >> On Mon, Jul 30 2018, Sergio Paracuellos wrote:
> >> 
> >> > This patch series include an attempt to avoid the use of custom
> >> > read and writes in driver code and use PCI subsystem common ones.
> >> >
> >> > In order to do this 'map_bus' callback is implemented and also
> >> > data structures for driver are included. The regs base address
> >> > is being readed from device tree and the driver gets clean a lot
> >> > of code.
> >> >
> >> > Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.
> >> >
> >> > Changes in v6:
> >> >     - Reorder patches to be each patch correct in itself.
> >> >     - PATCH 1 adds also Kconfig to do the step from legacy to generic code
> >> >     - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
> >> >       a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
> >> >     - Other patches rebased and adapted with this changes.
> >> 
> >> No noticeable difference.
> >> Still hangs after
> >> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> >> 
> >> the readl() at the start of ahci_enable_ahci() hangs, reading c4017004.
> >> 
> >> I built on a merge of
> >>  Merge: 527838d470e3 b9f13084580c
> >> 
> >> linus' master + staging/staging-testing
> >> 
> >> dmesg below.
> >
> > Thanks for this.
> >
> ....
> >> [    8.430000] bootconsole [early0] disabled
> >> [    8.430000] bootconsole [early0] disabled
> >> [    8.450000] cacheinfo: Failed to find cpu0 device node
> >> [    8.460000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> >> [    8.550000] loop: module loaded
> >> [    8.560000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> >> 
> >> 
> >
> > So this last dmesg is the new one with last v6, right? Because I can see 
> 
> Right.
> 
> 
> > that at least now the assigned resources are pretty much the same of the ones in the dmesg of the
> > original code talking in terms of assigned BAR's and bridge windows. No weird BAR 9 anymore, which I think is 
> > good. We can try to get back the hack which I removed at first and see what happend. The hack is
> > this function removed in PATCH 2:
> >
> > -void setup_cm_memory_region(struct resource *mem_resource)
> > -{
> > -	resource_size_t mask;
> > -	if (mips_cps_numiocu(0)) {
> > -		/* FIXME: hardware doesn't accept mask values with 1s after
> > -		 * 0s (e.g. 0xffef), so it would be great to warn if that's
> > -		 * about to happen */
> > -		mask = ~(mem_resource->end - mem_resource->start);
> > -
> > -		write_gcr_reg1_base(mem_resource->start);
> > -		write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
> > -		printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
> > -			(unsigned long long)read_gcr_reg1_base(),
> > -			(unsigned long long)read_gcr_reg1_mask());
> > -	}
> > -}
> >
> > We can try to add it again and and call it from 'mt7621_pci_parse_request_of_pci_ranges'
> > in the label of the case of the case 'IORESOURCE_MEM' (as you can see this was intentionally
> > without code just to test this if this v6 fails):
> >
> > 		break;
> > 		case IORESOURCE_MEM:
> > +           setup_cm_memory_region(res);
> > 			break;
> 
> I added setup_cm_memory_region() back in and called it from
> mt7621_pci_parse_request_of_pci_ranges()
> as suggested.
> Now we don't hang at the same place, but crash shortly after.
> 
> [    8.750000] WARNING: CPU: 2 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
> 
> This is at the end of ahci_enable_ahci(). the HOST_AHCI_EN bit never was
> set.
> 
> 
> >
> > If this also fails we can try to move the call to 'mt7621_pcie_parse_dt(pcie, &res);' after the
> > HW initialization code just before the list_splice_init(&res, &bridge->windows); line:
> >
> > -   err = mt7621_pcie_parse_dt(pcie, &res);
> > -	if (err) {
> > -		dev_err(dev, "Parsing DT failed\n");
> > -		return err;
> > -	}
> > -
> > -	/*
> >  	iomem_resource.start = 0;
> >  	iomem_resource.end = ~0;
> > ...
> >
> >         write_config(0, 0, 0, 0x70c, val);
> >  	}
> >
> > +   err = mt7621_pcie_parse_dt(pcie, &res);
> > +	if (err) {
> > +		dev_err(dev, "Parsing DT failed\n");
> > +		return err;
> > +	}
> > +
> >     list_splice_init(&res, &bridge->windows);
> 
> If I move the call to mt7621_pcie_parse_dt() anywhere after
> the call to set_phy_for_ssc() I get a crash at the start of
> set_pcie_phy() called from set_phy_for_ssc(), presumably because
> pcie->base isn't set.
> 
> Keep trying, I'm sure we'll get there.

Neil, I think you notice it actually, but just in case I think it is better
to confirm it. This series should be applicable patch by patch in order
to better debugging the errors. So just applying the first patch
and configuring properly with CONFIG_PCI_MT7621 option should run also...
I suspect this also get the system to hang, right?

Thanks in advance.

Also, hopefully this afternoon/tonigh I give this a new chance and this time
I am going to get resources by myself using pci_add_resource_offset for each
entry in the ranges property of the pcie node (like the mips pci-legacy code does) 
instead of using the devm_of_pci_get_host_bridge_resources. It should be the same
but it seems it is something different according the dmesg traces... So just to try 
and discard this... v7 is comming soon.

> 
> NeilBrown

Best regards,
    Sergio Paracuellos
> 
> >
> > (I don't have access now to the laptop with the code and cannot diff properly, sorry).
> >
> > Hopefully it boots now?
> >
> > Thanks in advance.
> >
> > Best regards,
> >     Sergio Paracuellos


_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

Re: [PATCH v6 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

On Tue, Jul 31, 2018 at 08:55:52AM +1000, NeilBrown wrote:
> On Mon, Jul 30 2018, Sergio Paracuellos wrote:
> 
> > This patch series include an attempt to avoid the use of custom
> > read and writes in driver code and use PCI subsystem common ones.
> >
> > In order to do this 'map_bus' callback is implemented and also
> > data structures for driver are included. The regs base address
> > is being readed from device tree and the driver gets clean a lot
> > of code.
> >
> > Also the driver get removes all legacy PCI code using now PCI_DRIVERS_GENERIC.
> >
> > Changes in v6:
> >     - Reorder patches to be each patch correct in itself.
> >     - PATCH 1 adds also Kconfig to do the step from legacy to generic code
> >     - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in 
> >       a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
> >     - Other patches rebased and adapted with this changes.
> 
> No noticeable difference.
> Still hangs after
> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> 
> the readl() at the start of ahci_enable_ahci() hangs, reading c4017004.
> 
> I built on a merge of
>  Merge: 527838d470e3 b9f13084580c
> 
> linus' master + staging/staging-testing
> 
> dmesg below.
> 
> Thanks,
> NeilBrown
> 
> [    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #254 SMP Tue Jul 31 08:49:52 AEST 2018
> [    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
> [    0.000000] bootconsole [early0] enabled
> [    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [    0.000000] MIPS: machine is GB-PC1
> [    0.000000] Determined physical RAM map:
> [    0.000000]  memory: 1c000000 @ 00000000 (usable)
> [    0.000000]  memory: 04000000 @ 20000000 (usable)
> [    0.000000] Initrd not found or empty - disabling initrd
> [    0.000000] VPE topology {2,2} total 4
> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.000000] Zone ranges:
> [    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
> [    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
> [    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
> [    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
> [    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
> [    0.000000] Kernel command line: console=ttyS0,57600
> [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [    0.000000] Writing ErrCtl register=00010882
> [    0.000000] Readback ErrCtl register=00010882
> [    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000] NR_IRQS: 256
> [    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
> [    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
> [    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
> [    0.070000] pid_max: default: 32768 minimum: 301
> [    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.100000] Hierarchical SRCU implementation.
> [    0.110000] smp: Bringing up secondary CPUs ...
> [    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
> [    0.180000] Synchronize counters for CPU 1: done.
> [    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
> [    0.280000] Synchronize counters for CPU 2: done.
> [    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
> [    0.380000] Synchronize counters for CPU 3: done.
> [    0.420000] smp: Brought up 1 node, 4 CPUs
> [    0.430000] devtmpfs: initialized
> [    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
> [    0.500000] pinctrl core: initialized pinctrl subsystem
> [    0.510000] NET: Registered protocol family 16
> [    0.570000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
> [    0.580000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
> [    0.600000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
> [    0.910000] ***** Xtal 40MHz *****
> [    0.920000] Port 0 N_FTS = 1b102800
> [    0.930000] Port 1 N_FTS = 1b102800
> [    0.930000] Port 2 N_FTS = 1b102800
> [    1.990000] PCIE0 enabled
> [    2.000000] PCIE1 enabled
> [    2.000000] PCIE2 enabled
> [    2.010000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [    2.020000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    2.030000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
> [    2.060000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.070000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.090000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.110000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    2.120000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [    2.130000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [    2.140000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [    2.160000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.170000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [    2.180000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.200000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [    2.210000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.220000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [    2.240000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
> [    2.250000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [    2.260000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
> [    2.280000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
> [    2.290000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
> [    2.300000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
> [    2.320000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
> [    2.330000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
> [    2.340000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [    2.360000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.370000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [    2.380000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.390000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [    2.410000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.420000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [    2.430000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.450000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.460000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.470000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.480000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.500000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.510000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.520000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.530000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.550000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.560000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    2.570000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [    2.580000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
> [    2.600000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [    2.610000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.620000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.640000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.650000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.660000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.670000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.690000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.700000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.710000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.720000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.740000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [    2.750000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
> [    2.760000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
> [    2.770000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
> [    2.790000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.800000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.810000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.820000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.840000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.850000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.860000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.870000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.890000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.900000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.910000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [    2.920000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
> [    2.940000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
> [    3.020000] SCSI subsystem initialized
> [    3.030000] random: fast init done
> [    3.040000] clocksource: Switched to clocksource GIC
> [    3.060000] NET: Registered protocol family 2
> [    3.070000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
> [    3.080000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
> [    3.100000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
> [    3.110000] TCP: Hash tables configured (established 4096 bind 4096)
> [    3.120000] UDP hash table entries: 256 (order: 1, 8192 bytes)
> [    3.140000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
> [    3.150000] NET: Registered protocol family 1
> [    8.130000] Initialise system trusted keyrings
> [    8.140000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
> [    8.270000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
> [    8.280000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
> [    8.310000] SGI XFS with security attributes, no debug enabled
> [    8.360000] Key type asymmetric registered
> [    8.370000] Asymmetric key parser 'x509' registered
> [    8.380000] bounce: pool size: 64 pages
> [    8.390000] io scheduler noop registered
> [    8.400000] io scheduler deadline registered (default)
> [    8.410000] io scheduler mq-deadline registered (default)
> [    8.420000] io scheduler kyber registered
> [    8.430000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
> [    8.460000] console [ttyS0] disabled
> [    8.460000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
> [    8.480000] console [ttyS0] enabled
> [    8.480000] console [ttyS0] enabled
> [    8.500000] bootconsole [early0] disabled
> [    8.500000] bootconsole [early0] disabled
> [    8.510000] cacheinfo: Failed to find cpu0 device node
> [    8.520000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    8.610000] loop: module loaded
> [    8.620000] pci 0000:00:00.0: enabling device (0004 -> 0006)
> [    8.630000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> 
> 
> Though messages were a little different first time:
> 
> [    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #253 SMP Tue Jul 31 08:41:34 AEST 2018
> [    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
> [    0.000000] bootconsole [early0] enabled
> [    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [    0.000000] MIPS: machine is GB-PC1
> [    0.000000] Determined physical RAM map:
> [    0.000000]  memory: 1c000000 @ 00000000 (usable)
> [    0.000000]  memory: 04000000 @ 20000000 (usable)
> [    0.000000] Initrd not found or empty - disabling initrd
> [    0.000000] VPE topology {2,2} total 4
> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.000000] Zone ranges:
> [    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
> [    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
> [    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
> [    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
> [    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
> [    0.000000] Kernel command line: console=ttyS0,57600
> [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [    0.000000] Writing ErrCtl register=000108a2
> [    0.000000] Readback ErrCtl register=000108a2
> [    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000] NR_IRQS: 256
> [    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
> [    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
> [    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
> [    0.070000] pid_max: default: 32768 minimum: 301
> [    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.100000] Hierarchical SRCU implementation.
> [    0.110000] smp: Bringing up secondary CPUs ...
> [    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
> [    0.180000] Synchronize counters for CPU 1: done.
> [    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
> [    0.280000] Synchronize counters for CPU 2: done.
> [    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
> [    0.380000] Synchronize counters for CPU 3: done.
> [    0.420000] smp: Brought up 1 node, 4 CPUs
> [    0.430000] devtmpfs: initialized
> [    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
> [    0.500000] pinctrl core: initialized pinctrl subsystem
> [    0.510000] NET: Registered protocol family 16
> [    0.570000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
> [    0.580000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
> [    0.600000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
> [    0.910000] ***** Xtal 40MHz *****
> [    0.920000] Port 0 N_FTS = 1b105000
> [    0.930000] Port 1 N_FTS = 1b105000
> [    0.930000] Port 2 N_FTS = 1b105000
> [    1.990000] PCIE0 enabled
> [    2.000000] PCIE1 enabled
> [    2.000000] PCIE2 enabled
> [    2.010000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [    2.020000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    2.030000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
> [    2.050000] pci 0000:00:00.0: reg 0x14: initial BAR value 0x60300000 invalid
> [    2.070000] pci 0000:00:01.0: reg 0x14: initial BAR value 0x60310000 invalid
> [    2.080000] pci 0000:00:02.0: reg 0x14: initial BAR value 0x60320000 invalid
> [    2.100000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    2.110000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [    2.130000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [    2.140000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [    2.150000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.160000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [    2.180000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.190000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [    2.200000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.220000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [    2.230000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff]
> [    2.240000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [    2.260000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60300000-0x6030ffff]
> [    2.270000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60310000-0x6031ffff]
> [    2.280000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60320000-0x6032ffff]
> [    2.300000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [    2.310000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.320000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [    2.330000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.350000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [    2.360000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.370000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [    2.390000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.400000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.410000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.420000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.440000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.450000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.460000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.470000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.490000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.500000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.510000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    2.520000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [    2.530000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60100000-0x601001ff]
> [    2.550000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.560000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.570000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.590000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.600000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.610000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.620000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.640000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.650000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.660000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.670000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [    2.680000] pci 0000:00:01.0:   bridge window [mem 0x60100000-0x601fffff]
> [    2.700000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [    2.710000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.720000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.740000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.750000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.760000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.770000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.790000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.800000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.810000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.820000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.840000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [    2.850000] pci 0000:00:02.0:   bridge window [mem 0x60200000-0x602fffff]
> [    2.930000] SCSI subsystem initialized
> [    2.940000] random: fast init done
> [    2.960000] clocksource: Switched to clocksource GIC
> [    2.990000] NET: Registered protocol family 2
> [    3.000000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
> [    3.020000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
> [    3.030000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
> [    3.040000] TCP: Hash tables configured (established 4096 bind 4096)
> [    3.060000] UDP hash table entries: 256 (order: 1, 8192 bytes)
> [    3.070000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
> [    3.080000] NET: Registered protocol family 1
> [    8.070000] Initialise system trusted keyrings
> [    8.080000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
> [    8.210000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
> [    8.220000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
> [    8.250000] SGI XFS with security attributes, no debug enabled
> [    8.300000] Key type asymmetric registered
> [    8.310000] Asymmetric key parser 'x509' registered
> [    8.320000] bounce: pool size: 64 pages
> [    8.330000] io scheduler noop registered
> [    8.330000] io scheduler deadline registered (default)
> [    8.340000] io scheduler mq-deadline registered (default)
> [    8.350000] io scheduler kyber registered
> [    8.370000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
> [    8.390000] console [ttyS0] disabled
> [    8.400000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
> [    8.420000] console [ttyS0] enabled
> [    8.420000] console [ttyS0] enabled
> [    8.430000] bootconsole [early0] disabled
> [    8.430000] bootconsole [early0] disabled
> [    8.450000] cacheinfo: Failed to find cpu0 device node
> [    8.460000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    8.550000] loop: module loaded
> [    8.560000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> 

Second though...

I think we should try together the two tests I have just described in my last email:
    - Get back the function to fix something about the memory resources
    - Call it from IO_MEMRESOURCE.
    - Move the dt parse function call after the initialization code.

Because the N_FTS values are also different getting the ranges parse stuff before
doing the init code. If we call it after that the trace should be pretty much the same as the one
in the original code.

Hope this helps.

Best regards,
    Sergio Paracuellos


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