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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 21/23] drm/i915/icl: Add Display Stream Splitter control registers
Date: Mon, 30 Jul 2018 19:13:01 -0700	[thread overview]
Message-ID: <1533003183-22793-22-git-send-email-manasi.d.navare@intel.com> (raw)
In-Reply-To: <1533003183-22793-1-git-send-email-manasi.d.navare@intel.com>

From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>

Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding display stream
compression enabled on left or right branch.

v2:
- Add define to conditionally check the buffer target depth (James Ausmus)

Suggested-by: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8e41db..0ae38b6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7792,6 +7792,39 @@ enum {
 #define RC_MAX_QP_SHIFT				5
 #define RC_MIN_QP_SHIFT				0
 
+/* Display Stream Splitter Control */
+#define DSS_CTL1				_MMIO(0x67400)
+#define  SPLITTER_ENABLE			(1 << 31)
+#define  JOINER_ENABLE				(1 << 30)
+#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
+#define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
+#define  OVERLAP_PIXELS_MASK			(0xf << 16)
+#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
+#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
+#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5A0
+
+#define DSS_CTL2				_MMIO(0x67404)
+#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
+#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
+#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
+#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
+
+#define _ICL_PIPE_DSS_CTL1_PB			0x78200
+#define _ICL_PIPE_DSS_CTL1_PC			0x78400
+#define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
+							   _ICL_PIPE_DSS_CTL1_PB, \
+							   _ICL_PIPE_DSS_CTL1_PC)
+#define  BIG_JOINER_ENABLE			(1 << 29)
+#define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
+#define  VGA_CENTERING_ENABLE			(1 << 27)
+
+#define _ICL_PIPE_DSS_CTL2_PB			0x78204
+#define _ICL_PIPE_DSS_CTL2_PC			0x78404
+#define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
+							   _ICL_PIPE_DSS_CTL2_PB, \
+							   _ICL_PIPE_DSS_CTL2_PC)
+
 #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
 #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
 #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)
-- 
2.7.4

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  parent reply	other threads:[~2018-07-31  2:10 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-31  2:12 [PATCH 00/23] Enable Display Stream Compression on eDP/DP Manasi Navare
2018-07-31  2:12 ` [PATCH 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-07-31 20:53   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-07-31  2:12 ` [PATCH 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-07-31  2:12 ` [PATCH 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-07-31  2:12 ` [PATCH 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-07-31  2:12 ` [PATCH 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-07-31  2:12 ` [PATCH 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-07-31  2:12 ` [PATCH 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-07-31  2:12 ` [PATCH 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-07-31  2:12 ` [PATCH 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-07-31  2:12 ` [PATCH 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-07-31  2:12 ` [PATCH 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-07-31 17:33   ` [PATCH v2] " Manasi Navare
2018-07-31  2:12 ` [PATCH 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-08-17 20:06   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-08-28 22:04   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-07-31  2:12 ` [PATCH 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-07-31  2:12 ` [PATCH 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-08-28 22:26   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-07-31  2:12 ` [PATCH 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-07-31  2:13 ` [PATCH 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-07-31  2:13 ` Manasi Navare [this message]
2018-08-02 10:26   ` [PATCH 21/23] drm/i915/icl: Add Display Stream Splitter control registers Madhav Chauhan
2018-07-31  2:13 ` [PATCH 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-07-31  2:13 ` [PATCH 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-07-31  2:27 ` ✗ Fi.CI.BAT: failure for Enable Display Stream Compression on eDP/DP Patchwork
2018-07-31 17:45 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Display Stream Compression on eDP/DP (rev2) Patchwork
2018-07-31 17:55 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-31 18:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-31 18:54 ` ✓ Fi.CI.IGT: " Patchwork

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