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From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
To: "Navare, Manasi D" <manasi.d.navare@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink
Date: Tue, 28 Aug 2018 22:26:24 +0000	[thread overview]
Message-ID: <83F5C7385F545743AD4FB2A62F75B07347F481A9@ORSMSX108.amr.corp.intel.com> (raw)
In-Reply-To: <1533003183-22793-18-git-send-email-manasi.d.navare@intel.com>



>-----Original Message-----
>From: Navare, Manasi D
>Sent: Monday, July 30, 2018 7:13 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; Srivatsa, Anusha
><anusha.srivatsa@intel.com>; Singh, Gaurav K <gaurav.k.singh@intel.com>;
>Navare, Manasi D <manasi.d.navare@intel.com>
>Subject: [PATCH 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink
>
>From: Gaurav K Singh <gaurav.k.singh@intel.com>
>
>This patch enables decompression support in sink device before link training and
>disables the same during the DDI disabling.
>
>v2:(From Manasi)
>* Change the enable/disable function to take crtc_state instead of intel_dp as an
>argument (Manasi)
>* Use the compression_enable flag as part of crtc_state (Manasi)
>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
>Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Looks good.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/intel_ddi.c |  5 +++++  drivers/gpu/drm/i915/intel_dp.c  |
>15 +++++++++++++++  drivers/gpu/drm/i915/intel_drv.h |  3 +++
> 3 files changed, 23 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 0adc043..5e8c891 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -2825,6 +2825,8 @@ static void intel_ddi_pre_enable_dp(struct
>intel_encoder *encoder,
> 	intel_ddi_init_dp_buf_reg(encoder);
> 	if (!is_mst)
> 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>+	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
>+					      DP_DECOMPRESSION_EN);
> 	intel_dp_start_link_train(intel_dp);
> 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> 		intel_dp_stop_link_train(intel_dp);
>@@ -3154,6 +3156,9 @@ static void intel_disable_ddi_dp(struct intel_encoder
>*encoder,
> 	intel_edp_drrs_disable(intel_dp, old_crtc_state);
> 	intel_psr_disable(intel_dp, old_crtc_state);
> 	intel_edp_backlight_off(old_conn_state);
>+	/* Disable the decompression in DP Sink */
>+	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
>+					      ~DP_DECOMPRESSION_EN);
> }
>
> static void intel_disable_ddi_hdmi(struct intel_encoder *encoder, diff --git
>a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index
>d7fc50f..436cbfb 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -2925,6 +2925,21 @@ static bool downstream_hpd_needs_d0(struct
>intel_dp *intel_dp)
> 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;  }
>
>+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
>+					   const struct intel_crtc_state
>*crtc_state,
>+					   int state)
>+{
>+	int ret;
>+
>+	if (!crtc_state->dsc_params.compression_enable)
>+		return;
>+
>+	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, state);
>+	if (ret < 0)
>+		DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
>+			      state == DP_DECOMPRESSION_EN ? "enable" :
>"disable"); }
>+
> /* If the sink supports it, try to set the power state appropriately */  void
>intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)  { diff --git
>a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index 01ab23d..85b6a37 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -1691,6 +1691,9 @@ void intel_dp_stop_link_train(struct intel_dp
>*intel_dp);  int intel_dp_retrain_link(struct intel_encoder *encoder,
> 			  struct drm_modeset_acquire_ctx *ctx);  void
>intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
>+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
>+					   const struct intel_crtc_state
>*crtc_state,
>+					   int state);
> void intel_dp_encoder_reset(struct drm_encoder *encoder);  void
>intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);  void
>intel_dp_encoder_destroy(struct drm_encoder *encoder);
>--
>2.7.4

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  reply	other threads:[~2018-08-28 22:26 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-31  2:12 [PATCH 00/23] Enable Display Stream Compression on eDP/DP Manasi Navare
2018-07-31  2:12 ` [PATCH 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-07-31 20:53   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-07-31  2:12 ` [PATCH 03/23] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-07-31  2:12 ` [PATCH 04/23] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-07-31  2:12 ` [PATCH 05/23] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-07-31  2:12 ` [PATCH 06/23] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-07-31  2:12 ` [PATCH 07/23] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-07-31  2:12 ` [PATCH 08/23] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-07-31  2:12 ` [PATCH 09/23] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-07-31  2:12 ` [PATCH 10/23] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-07-31  2:12 ` [PATCH 11/23] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-07-31  2:12 ` [PATCH 12/23] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-07-31 17:33   ` [PATCH v2] " Manasi Navare
2018-07-31  2:12 ` [PATCH 13/23] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-08-17 20:06   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 14/23] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-08-28 22:04   ` Srivatsa, Anusha
2018-07-31  2:12 ` [PATCH 15/23] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-07-31  2:12 ` [PATCH 16/23] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-07-31  2:12 ` [PATCH 17/23] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-08-28 22:26   ` Srivatsa, Anusha [this message]
2018-07-31  2:12 ` [PATCH 18/23] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-07-31  2:12 ` [PATCH 19/23] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-07-31  2:13 ` [PATCH 20/23] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-07-31  2:13 ` [PATCH 21/23] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-08-02 10:26   ` Madhav Chauhan
2018-07-31  2:13 ` [PATCH 22/23] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-07-31  2:13 ` [PATCH 23/23] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-07-31  2:27 ` ✗ Fi.CI.BAT: failure for Enable Display Stream Compression on eDP/DP Patchwork
2018-07-31 17:45 ` ✗ Fi.CI.CHECKPATCH: warning for Enable Display Stream Compression on eDP/DP (rev2) Patchwork
2018-07-31 17:55 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-31 18:07 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-31 18:54 ` ✓ Fi.CI.IGT: " Patchwork

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