* [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288
@ 2018-08-28 6:24 Janine Hagemann
2018-08-28 6:24 ` [U-Boot] [PATCH v4 1/7] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init Janine Hagemann
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:24 UTC (permalink / raw)
To: u-boot
- Change a used function
Janine Hagemann (7):
arch: arm: mach-rockchip: rk3288: Enable regulators in board_init
config: phycore-rk3288_defconfig: add PHY_TI
drivers: net: designware: Add reading of DT phy-handle node
ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing
rockchip: rk3288-phycore: set flash1 iodomain to 1.8V
net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii
net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID
arch/arm/dts/rk3288-phycore-som.dtsi | 1 +
arch/arm/mach-rockchip/rk3288-board.c | 12 ++---
board/phytec/phycore_rk3288/phycore-rk3288.c | 16 ++++++
configs/phycore-rk3288_defconfig | 1 +
drivers/net/designware.c | 11 +++-
drivers/net/designware.h | 1 +
drivers/net/gmac_rockchip.c | 80 ++++++++++++++++++++++------
7 files changed, 98 insertions(+), 24 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 1/7] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
@ 2018-08-28 6:24 ` Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 2/7] config: phycore-rk3288_defconfig: add PHY_TI Janine Hagemann
` (5 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:24 UTC (permalink / raw)
To: u-boot
Use regulators_enable_boot_on() to init all the regulators with
regulator-boot-on property. This is relevant for all rk3288-boards.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
---
v4: No changes
---
arch/arm/mach-rockchip/rk3288-board.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 9c4f7f2..067b988 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -132,12 +132,6 @@ static int veyron_init(void)
if (ret)
return ret;
- ret = regulators_enable_boot_on(false);
- if (ret) {
- debug("%s: Cannot enable boot on regulators\n", __func__);
- return ret;
- }
-
return 0;
}
#endif
@@ -175,6 +169,12 @@ err:
#else
int ret;
+ ret = regulators_enable_boot_on(false);
+ if (ret) {
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+ return ret;
+ }
+
/* We do some SoC one time setting here */
if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
ret = veyron_init();
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 2/7] config: phycore-rk3288_defconfig: add PHY_TI
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
2018-08-28 6:24 ` [U-Boot] [PATCH v4 1/7] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init Janine Hagemann
@ 2018-08-28 6:25 ` Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node Janine Hagemann
` (4 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:25 UTC (permalink / raw)
To: u-boot
add PHY_TI to support dp83867
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
---
v4: No changes
---
configs/phycore-rk3288_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index b81b5e6..340ba5d 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -54,6 +54,7 @@ CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_TI=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
2018-08-28 6:24 ` [U-Boot] [PATCH v4 1/7] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 2/7] config: phycore-rk3288_defconfig: add PHY_TI Janine Hagemann
@ 2018-08-28 6:25 ` Janine Hagemann
2018-08-28 23:53 ` Grygorii Strashko
2018-08-28 6:25 ` [U-Boot] [PATCH v4 4/7] ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing Janine Hagemann
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:25 UTC (permalink / raw)
To: u-boot
Add the ability to read the phy-handle node of the
gmac. Upon reading this handle the phy-id
can be stored based on the reg node in the DT.
The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
v4: Change used function from dev_set_of_offset( ) to
offset_to_ofnode( )
---
drivers/net/designware.c | 11 ++++++++++-
drivers/net/designware.h | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 19db0a8..bba12f2 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -477,7 +477,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
int mask = 0xffffffff, ret;
-
+ struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
#ifdef CONFIG_PHY_ADDR
mask = 1 << CONFIG_PHY_ADDR;
#endif
@@ -496,6 +496,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
}
phydev->advertising = phydev->supported;
+#ifdef CONFIG_DM_ETH
+ if (dw_pdata->phy_of_handle)
+ phydev->node = offset_to_ofnode(dw_pdata->phy_of_handle);
+#endif
+
priv->phydev = phydev;
phy_config(phydev);
@@ -803,6 +808,7 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
int reset_flags = GPIOD_IS_OUT;
#endif
int ret = 0;
+ int node = dev_of_offset(dev);
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
@@ -814,6 +820,9 @@ int designware_eth_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
}
+ dw_pdata->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
+ "phy-handle");
+
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
#ifdef CONFIG_DM_GPIO
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index dea12b7..a6b0443 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops;
struct dw_eth_pdata {
struct eth_pdata eth_pdata;
u32 reset_delays[3];
+ int phy_of_handle;
};
int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 4/7] ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
` (2 preceding siblings ...)
2018-08-28 6:25 ` [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node Janine Hagemann
@ 2018-08-28 6:25 ` Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 5/7] rockchip: rk3288-phycore: set flash1 iodomain to 1.8V Janine Hagemann
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:25 UTC (permalink / raw)
To: u-boot
The CLK_O_SEL default is synchronus to XI input clock,
which is 25 MHz. Set CLK_O_SEL to channel A transmit
clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
---
v4: No changes
---
arch/arm/dts/rk3288-phycore-som.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi
index 02d1196..2dba0aa 100644
--- a/arch/arm/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/dts/rk3288-phycore-som.dtsi
@@ -191,6 +191,7 @@
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
+ ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
};
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 5/7] rockchip: rk3288-phycore: set flash1 iodomain to 1.8V
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
` (3 preceding siblings ...)
2018-08-28 6:25 ` [U-Boot] [PATCH v4 4/7] ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing Janine Hagemann
@ 2018-08-28 6:25 ` Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID Janine Hagemann
6 siblings, 0 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:25 UTC (permalink / raw)
To: u-boot
This pin is supplied by 1.8V, but the default iodomain
setting is 3.3V.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
---
v4: No changes
---
board/phytec/phycore_rk3288/phycore-rk3288.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
index ffe1833..8c1844a 100644
--- a/board/phytec/phycore_rk3288/phycore-rk3288.c
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -11,6 +11,11 @@
#include <i2c.h>
#include <i2c_eeprom.h>
#include <netdev.h>
+#include <syscon.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3288.h>
#include "som.h"
static int valid_rk3288_som(struct rk3288_som *som)
@@ -27,6 +32,15 @@ static int valid_rk3288_som(struct rk3288_som *som)
return hw == som->bs;
}
+static void setup_iodomain(void)
+{
+ const u32 GRF_IO_VSEL_FLASH1_SHIFT = 3;
+ struct rk3288_grf *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_FLASH1_SHIFT);
+}
+
int rk_board_late_init(void)
{
int ret;
@@ -34,6 +48,8 @@ int rk_board_late_init(void)
struct rk3288_som opt;
int off;
+ setup_iodomain();
+
/* Get the identificatioin page of M24C32-D EEPROM */
off = fdt_path_offset(gd->fdt_blob, "eeprom0");
if (off < 0) {
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
` (4 preceding siblings ...)
2018-08-28 6:25 ` [U-Boot] [PATCH v4 5/7] rockchip: rk3288-phycore: set flash1 iodomain to 1.8V Janine Hagemann
@ 2018-08-28 6:25 ` Janine Hagemann
2018-08-31 11:57 ` [U-Boot] [U-Boot, v4, " David.Wu
2018-10-04 20:08 ` Philipp Tomsich
2018-08-28 6:25 ` [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID Janine Hagemann
6 siblings, 2 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:25 UTC (permalink / raw)
To: u-boot
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
to enable the RX delay.
The MASK was used in a wrong way.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Reviewed-by: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
v4: No changes
---
drivers/net/gmac_rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 30a24d1..0f91731 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -350,7 +350,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
RK3328_RXCLK_DLY_ENA_GMAC_MASK |
RK3328_TXCLK_DLY_ENA_GMAC_MASK,
RK3328_GMAC_PHY_INTF_SEL_RGMII |
- RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+ RK3328_RXCLK_DLY_ENA_GMAC_ENABLE |
RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
rk_clrsetreg(&grf->mac_con[0],
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
` (5 preceding siblings ...)
2018-08-28 6:25 ` [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii Janine Hagemann
@ 2018-08-28 6:25 ` Janine Hagemann
2018-08-31 11:54 ` [U-Boot] [U-Boot, v4, " David.Wu
2018-10-04 20:08 ` [U-Boot] " Philipp Tomsich
6 siblings, 2 replies; 14+ messages in thread
From: Janine Hagemann @ 2018-08-28 6:25 UTC (permalink / raw)
To: u-boot
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.
Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.
Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
v4: No changes
---
drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++----------
1 file changed, 63 insertions(+), 17 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 0f91731..c01ae75 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -24,6 +24,11 @@
#include <dt-bindings/clock/rk3288-cru.h>
#include "designware.h"
+DECLARE_GLOBAL_DATA_PTR;
+#define DELAY_ENABLE(soc, tx, rx) \
+ (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
+ ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
+
/*
* Platform data for the gmac
*
@@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
RK3228_RXCLK_DLY_ENA_GMAC_MASK |
RK3228_TXCLK_DLY_ENA_GMAC_MASK,
RK3228_GMAC_PHY_INTF_SEL_RGMII |
- RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
+ DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
rk_clrsetreg(&grf->mac_con[0],
RK3228_CLK_RX_DL_CFG_GMAC_MASK |
@@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
RK3288_TXCLK_DLY_ENA_GMAC_MASK |
RK3288_CLK_RX_DL_CFG_GMAC_MASK |
RK3288_CLK_TX_DL_CFG_GMAC_MASK,
- RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
+ DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
}
@@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
RK3328_RXCLK_DLY_ENA_GMAC_MASK |
RK3328_TXCLK_DLY_ENA_GMAC_MASK,
RK3328_GMAC_PHY_INTF_SEL_RGMII |
- RK3328_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+ DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
rk_clrsetreg(&grf->mac_con[0],
RK3328_CLK_RX_DL_CFG_GMAC_MASK |
@@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
RK3368_TXCLK_DLY_ENA_GMAC_MASK |
RK3368_CLK_RX_DL_CFG_GMAC_MASK |
RK3368_CLK_TX_DL_CFG_GMAC_MASK,
- RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+ DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
}
@@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
RK3399_TXCLK_DLY_ENA_GMAC_MASK |
RK3399_CLK_RX_DL_CFG_GMAC_MASK |
RK3399_CLK_TX_DL_CFG_GMAC_MASK,
- RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
- RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
+ DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
}
@@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)
switch (eth_pdata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
+ /* Set to RGMII mode */
+ if (ops->set_to_rgmii)
+ ops->set_to_rgmii(pdata);
+ else
+ return -EPERM;
+
/*
* If the gmac clock is from internal pll, need to set and
* check the return value for gmac clock at RGMII mode. If
* the gmac clock is from external source, the clock rate
* is not set, because of it is bypassed.
*/
+
if (!pdata->clock_input) {
rate = clk_set_rate(&clk, 125000000);
if (rate != 125000000)
return -EINVAL;
}
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
/* Set to RGMII mode */
- if (ops->set_to_rgmii)
+ if (ops->set_to_rgmii) {
+ pdata->tx_delay = 0;
+ pdata->rx_delay = 0;
ops->set_to_rgmii(pdata);
- else
+ } else
return -EPERM;
- break;
- case PHY_INTERFACE_MODE_RMII:
- /* The commet is the same as RGMII mode */
if (!pdata->clock_input) {
- rate = clk_set_rate(&clk, 50000000);
- if (rate != 50000000)
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
return -EINVAL;
}
+ break;
+ case PHY_INTERFACE_MODE_RMII:
/* Set to RMII mode */
if (ops->set_to_rmii)
ops->set_to_rmii(pdata);
else
return -EPERM;
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 50000000);
+ if (rate != 50000000)
+ return -EINVAL;
+ }
+ break;
+
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ /* Set to RGMII_RXID mode */
+ if (ops->set_to_rgmii) {
+ pdata->tx_delay = 0;
+ ops->set_to_rgmii(pdata);
+ } else
+ return -EPERM;
+
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
break;
+
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* Set to RGMII_TXID mode */
+ if (ops->set_to_rgmii) {
+ pdata->rx_delay = 0;
+ ops->set_to_rgmii(pdata);
+ } else
+ return -EPERM;
+
+ if (!pdata->clock_input) {
+ rate = clk_set_rate(&clk, 125000000);
+ if (rate != 125000000)
+ return -EINVAL;
+ }
+ break;
+
default:
debug("NO interface defined!\n");
return -ENXIO;
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node
2018-08-28 6:25 ` [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node Janine Hagemann
@ 2018-08-28 23:53 ` Grygorii Strashko
0 siblings, 0 replies; 14+ messages in thread
From: Grygorii Strashko @ 2018-08-28 23:53 UTC (permalink / raw)
To: u-boot
On 08/28/2018 01:25 AM, Janine Hagemann wrote:
> Add the ability to read the phy-handle node of the
> gmac. Upon reading this handle the phy-id
> can be stored based on the reg node in the DT.
>
> The phy-handle also needs to be stored and passed
> to the phy to access any phy data that is available.
>
> Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
> v4: Change used function from dev_set_of_offset( ) to
> offset_to_ofnode( )
> ---
> drivers/net/designware.c | 11 ++++++++++-
> drivers/net/designware.h | 1 +
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index 19db0a8..bba12f2 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -477,7 +477,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
> {
> struct phy_device *phydev;
> int mask = 0xffffffff, ret;
> -
> + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
> #ifdef CONFIG_PHY_ADDR
> mask = 1 << CONFIG_PHY_ADDR;
> #endif
> @@ -496,6 +496,11 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
> }
> phydev->advertising = phydev->supported;
>
> +#ifdef CONFIG_DM_ETH
> + if (dw_pdata->phy_of_handle)
> + phydev->node = offset_to_ofnode(dw_pdata->phy_of_handle);
> +#endif
> +
Above part looks good now. thank you.
--
regards,
-grygorii
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [U-Boot, v4, 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID
2018-08-28 6:25 ` [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID Janine Hagemann
@ 2018-08-31 11:54 ` David.Wu
2018-08-31 12:24 ` [U-Boot] [Resend] " David.Wu
2018-10-04 20:08 ` [U-Boot] " Philipp Tomsich
1 sibling, 1 reply; 14+ messages in thread
From: David.Wu @ 2018-08-31 11:54 UTC (permalink / raw)
To: u-boot
Hi Janine,
This patch looks good. Thank you for adding rgmii-id/rxid/txid.
Reviewed-by: David Wu <david.wu@rock-chips.com>
在 2018/8/28 14:25, Janine Hagemann 写道:
> Using PHY internal delays in combination with the phy-mode
> rgmii-id/rxid/txid was not possible. Only rgmii was supported.
>
> Now we can disable rockchip's gmac delay lines and also use
> rgmii-id/rxid/txid.
>
> Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
> handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
>
> Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
> v4: No changes
> ---
> drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++----------
> 1 file changed, 63 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index 0f91731..c01ae75 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -24,6 +24,11 @@
> #include <dt-bindings/clock/rk3288-cru.h>
> #include "designware.h"
>
> +DECLARE_GLOBAL_DATA_PTR;
> +#define DELAY_ENABLE(soc, tx, rx) \
> + (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
> + ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
> +
> /*
> * Platform data for the gmac
> *
> @@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
> RK3228_RXCLK_DLY_ENA_GMAC_MASK |
> RK3228_TXCLK_DLY_ENA_GMAC_MASK,
> RK3228_GMAC_PHY_INTF_SEL_RGMII |
> - RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
> - RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
> + DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
>
> rk_clrsetreg(&grf->mac_con[0],
> RK3228_CLK_RX_DL_CFG_GMAC_MASK |
> @@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
> RK3288_TXCLK_DLY_ENA_GMAC_MASK |
> RK3288_CLK_RX_DL_CFG_GMAC_MASK |
> RK3288_CLK_TX_DL_CFG_GMAC_MASK,
> - RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
> - RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
> + DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
> pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
> pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
> }
> @@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
> RK3328_RXCLK_DLY_ENA_GMAC_MASK |
> RK3328_TXCLK_DLY_ENA_GMAC_MASK,
> RK3328_GMAC_PHY_INTF_SEL_RGMII |
> - RK3328_RXCLK_DLY_ENA_GMAC_ENABLE |
> - RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
> + DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
>
> rk_clrsetreg(&grf->mac_con[0],
> RK3328_CLK_RX_DL_CFG_GMAC_MASK |
> @@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
> RK3368_TXCLK_DLY_ENA_GMAC_MASK |
> RK3368_CLK_RX_DL_CFG_GMAC_MASK |
> RK3368_CLK_TX_DL_CFG_GMAC_MASK,
> - RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
> - RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
> + DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
> pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
> pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
> }
> @@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
> RK3399_TXCLK_DLY_ENA_GMAC_MASK |
> RK3399_CLK_RX_DL_CFG_GMAC_MASK |
> RK3399_CLK_TX_DL_CFG_GMAC_MASK,
> - RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
> - RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
> + DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
> pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
> pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
> }
> @@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)
>
> switch (eth_pdata->phy_interface) {
> case PHY_INTERFACE_MODE_RGMII:
> + /* Set to RGMII mode */
> + if (ops->set_to_rgmii)
> + ops->set_to_rgmii(pdata);
> + else
> + return -EPERM;
> +
> /*
> * If the gmac clock is from internal pll, need to set and
> * check the return value for gmac clock at RGMII mode. If
> * the gmac clock is from external source, the clock rate
> * is not set, because of it is bypassed.
> */
> +
> if (!pdata->clock_input) {
> rate = clk_set_rate(&clk, 125000000);
> if (rate != 125000000)
> return -EINVAL;
> }
> + break;
>
> + case PHY_INTERFACE_MODE_RGMII_ID:
> /* Set to RGMII mode */
> - if (ops->set_to_rgmii)
> + if (ops->set_to_rgmii) {
> + pdata->tx_delay = 0;
> + pdata->rx_delay = 0;
> ops->set_to_rgmii(pdata);
> - else
> + } else
> return -EPERM;
>
> - break;
> - case PHY_INTERFACE_MODE_RMII:
> - /* The commet is the same as RGMII mode */
> if (!pdata->clock_input) {
> - rate = clk_set_rate(&clk, 50000000);
> - if (rate != 50000000)
> + rate = clk_set_rate(&clk, 125000000);
> + if (rate != 125000000)
> return -EINVAL;
> }
> + break;
>
> + case PHY_INTERFACE_MODE_RMII:
> /* Set to RMII mode */
> if (ops->set_to_rmii)
> ops->set_to_rmii(pdata);
> else
> return -EPERM;
>
> + if (!pdata->clock_input) {
> + rate = clk_set_rate(&clk, 50000000);
> + if (rate != 50000000)
> + return -EINVAL;
> + }
> + break;
> +
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + /* Set to RGMII_RXID mode */
> + if (ops->set_to_rgmii) {
> + pdata->tx_delay = 0;
> + ops->set_to_rgmii(pdata);
> + } else
> + return -EPERM;
> +
> + if (!pdata->clock_input) {
> + rate = clk_set_rate(&clk, 125000000);
> + if (rate != 125000000)
> + return -EINVAL;
> + }
> break;
> +
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + /* Set to RGMII_TXID mode */
> + if (ops->set_to_rgmii) {
> + pdata->rx_delay = 0;
> + ops->set_to_rgmii(pdata);
> + } else
> + return -EPERM;
> +
> + if (!pdata->clock_input) {
> + rate = clk_set_rate(&clk, 125000000);
> + if (rate != 125000000)
> + return -EINVAL;
> + }
> + break;
> +
> default:
> debug("NO interface defined!\n");
> return -ENXIO;
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [U-Boot, v4, 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii
2018-08-28 6:25 ` [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii Janine Hagemann
@ 2018-08-31 11:57 ` David.Wu
2018-10-04 20:08 ` Philipp Tomsich
1 sibling, 0 replies; 14+ messages in thread
From: David.Wu @ 2018-08-31 11:57 UTC (permalink / raw)
To: u-boot
Hi Janine,
Thank you for the fix.
在 2018/8/28 14:25, Janine Hagemann 写道:
> We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
> RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
> to enable the RX delay.
> The MASK was used in a wrong way.
>
> Signed-off-by: Janine Hagemann<j.hagemann@phytec.de>
> Reviewed-by: Philipp Tomisch<philipp.tomisch@theobroma-systems.com>
> Acked-by: Joe Hershberger<joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [Resend] [U-Boot, v4, 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID
2018-08-31 11:54 ` [U-Boot] [U-Boot, v4, " David.Wu
@ 2018-08-31 12:24 ` David.Wu
0 siblings, 0 replies; 14+ messages in thread
From: David.Wu @ 2018-08-31 12:24 UTC (permalink / raw)
To: u-boot
Resend it for Undelivered Mail.
在 2018/8/31 19:54, David.Wu 写道:
> Hi Janine,
>
> This patch looks good. Thank you for adding rgmii-id/rxid/txid.
> Reviewed-by: David Wu <david.wu@rock-chips.com>
>
> 在 2018/8/28 14:25, Janine Hagemann 写道:
>> Using PHY internal delays in combination with the phy-mode
>> rgmii-id/rxid/txid was not possible. Only rgmii was supported.
>>
>> Now we can disable rockchip's gmac delay lines and also use
>> rgmii-id/rxid/txid.
>>
>> Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
>> handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
>>
>> Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
>> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>> ---
>> v4: No changes
>> ---
>> drivers/net/gmac_rockchip.c | 80
>> +++++++++++++++++++++++++++++++++++----------
>> 1 file changed, 63 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
>> index 0f91731..c01ae75 100644
>> --- a/drivers/net/gmac_rockchip.c
>> +++ b/drivers/net/gmac_rockchip.c
>> @@ -24,6 +24,11 @@
>> #include <dt-bindings/clock/rk3288-cru.h>
>> #include "designware.h"
>> +DECLARE_GLOBAL_DATA_PTR;
>> +#define DELAY_ENABLE(soc, tx, rx) \
>> + (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE :
>> soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
>> + ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE :
>> soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
>> +
>> /*
>> * Platform data for the gmac
>> *
>> @@ -286,8 +291,7 @@ static void rk3228_gmac_set_to_rgmii(struct
>> gmac_rockchip_platdata *pdata)
>> RK3228_RXCLK_DLY_ENA_GMAC_MASK |
>> RK3228_TXCLK_DLY_ENA_GMAC_MASK,
>> RK3228_GMAC_PHY_INTF_SEL_RGMII |
>> - RK3228_RXCLK_DLY_ENA_GMAC_ENABLE |
>> - RK3228_TXCLK_DLY_ENA_GMAC_ENABLE);
>> + DELAY_ENABLE(RK3228, pdata->tx_delay, pdata->rx_delay));
>> rk_clrsetreg(&grf->mac_con[0],
>> RK3228_CLK_RX_DL_CFG_GMAC_MASK |
>> @@ -310,8 +314,7 @@ static void rk3288_gmac_set_to_rgmii(struct
>> gmac_rockchip_platdata *pdata)
>> RK3288_TXCLK_DLY_ENA_GMAC_MASK |
>> RK3288_CLK_RX_DL_CFG_GMAC_MASK |
>> RK3288_CLK_TX_DL_CFG_GMAC_MASK,
>> - RK3288_RXCLK_DLY_ENA_GMAC_ENABLE |
>> - RK3288_TXCLK_DLY_ENA_GMAC_ENABLE |
>> + DELAY_ENABLE(RK3288, pdata->rx_delay, pdata->tx_delay) |
>> pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT |
>> pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
>> }
>> @@ -350,8 +353,7 @@ static void rk3328_gmac_set_to_rgmii(struct
>> gmac_rockchip_platdata *pdata)
>> RK3328_RXCLK_DLY_ENA_GMAC_MASK |
>> RK3328_TXCLK_DLY_ENA_GMAC_MASK,
>> RK3328_GMAC_PHY_INTF_SEL_RGMII |
>> - RK3328_RXCLK_DLY_ENA_GMAC_ENABLE |
>> - RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
>> + DELAY_ENABLE(RK3328, pdata->tx_delay, pdata->rx_delay));
>> rk_clrsetreg(&grf->mac_con[0],
>> RK3328_CLK_RX_DL_CFG_GMAC_MASK |
>> @@ -392,8 +394,7 @@ static void rk3368_gmac_set_to_rgmii(struct
>> gmac_rockchip_platdata *pdata)
>> RK3368_TXCLK_DLY_ENA_GMAC_MASK |
>> RK3368_CLK_RX_DL_CFG_GMAC_MASK |
>> RK3368_CLK_TX_DL_CFG_GMAC_MASK,
>> - RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
>> - RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
>> + DELAY_ENABLE(RK3368, pdata->tx_delay, pdata->rx_delay) |
>> pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
>> pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
>> }
>> @@ -413,8 +414,7 @@ static void rk3399_gmac_set_to_rgmii(struct
>> gmac_rockchip_platdata *pdata)
>> RK3399_TXCLK_DLY_ENA_GMAC_MASK |
>> RK3399_CLK_RX_DL_CFG_GMAC_MASK |
>> RK3399_CLK_TX_DL_CFG_GMAC_MASK,
>> - RK3399_RXCLK_DLY_ENA_GMAC_ENABLE |
>> - RK3399_TXCLK_DLY_ENA_GMAC_ENABLE |
>> + DELAY_ENABLE(RK3399, pdata->tx_delay, pdata->rx_delay) |
>> pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT |
>> pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT);
>> }
>> @@ -451,40 +451,86 @@ static int gmac_rockchip_probe(struct udevice *dev)
>> switch (eth_pdata->phy_interface) {
>> case PHY_INTERFACE_MODE_RGMII:
>> + /* Set to RGMII mode */
>> + if (ops->set_to_rgmii)
>> + ops->set_to_rgmii(pdata);
>> + else
>> + return -EPERM;
>> +
>> /*
>> * If the gmac clock is from internal pll, need to set and
>> * check the return value for gmac clock at RGMII mode. If
>> * the gmac clock is from external source, the clock rate
>> * is not set, because of it is bypassed.
>> */
>> +
>> if (!pdata->clock_input) {
>> rate = clk_set_rate(&clk, 125000000);
>> if (rate != 125000000)
>> return -EINVAL;
>> }
>> + break;
>> + case PHY_INTERFACE_MODE_RGMII_ID:
>> /* Set to RGMII mode */
>> - if (ops->set_to_rgmii)
>> + if (ops->set_to_rgmii) {
>> + pdata->tx_delay = 0;
>> + pdata->rx_delay = 0;
>> ops->set_to_rgmii(pdata);
>> - else
>> + } else
>> return -EPERM;
>> - break;
>> - case PHY_INTERFACE_MODE_RMII:
>> - /* The commet is the same as RGMII mode */
>> if (!pdata->clock_input) {
>> - rate = clk_set_rate(&clk, 50000000);
>> - if (rate != 50000000)
>> + rate = clk_set_rate(&clk, 125000000);
>> + if (rate != 125000000)
>> return -EINVAL;
>> }
>> + break;
>> + case PHY_INTERFACE_MODE_RMII:
>> /* Set to RMII mode */
>> if (ops->set_to_rmii)
>> ops->set_to_rmii(pdata);
>> else
>> return -EPERM;
>> + if (!pdata->clock_input) {
>> + rate = clk_set_rate(&clk, 50000000);
>> + if (rate != 50000000)
>> + return -EINVAL;
>> + }
>> + break;
>> +
>> + case PHY_INTERFACE_MODE_RGMII_RXID:
>> + /* Set to RGMII_RXID mode */
>> + if (ops->set_to_rgmii) {
>> + pdata->tx_delay = 0;
>> + ops->set_to_rgmii(pdata);
>> + } else
>> + return -EPERM;
>> +
>> + if (!pdata->clock_input) {
>> + rate = clk_set_rate(&clk, 125000000);
>> + if (rate != 125000000)
>> + return -EINVAL;
>> + }
>> break;
>> +
>> + case PHY_INTERFACE_MODE_RGMII_TXID:
>> + /* Set to RGMII_TXID mode */
>> + if (ops->set_to_rgmii) {
>> + pdata->rx_delay = 0;
>> + ops->set_to_rgmii(pdata);
>> + } else
>> + return -EPERM;
>> +
>> + if (!pdata->clock_input) {
>> + rate = clk_set_rate(&clk, 125000000);
>> + if (rate != 125000000)
>> + return -EINVAL;
>> + }
>> + break;
>> +
>> default:
>> debug("NO interface defined!\n");
>> return -ENXIO;
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [U-Boot, v4, 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID
2018-08-28 6:25 ` [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID Janine Hagemann
2018-08-31 11:54 ` [U-Boot] [U-Boot, v4, " David.Wu
@ 2018-10-04 20:08 ` Philipp Tomsich
1 sibling, 0 replies; 14+ messages in thread
From: Philipp Tomsich @ 2018-10-04 20:08 UTC (permalink / raw)
To: u-boot
> Using PHY internal delays in combination with the phy-mode
> rgmii-id/rxid/txid was not possible. Only rgmii was supported.
>
> Now we can disable rockchip's gmac delay lines and also use
> rgmii-id/rxid/txid.
>
> Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
> handling for RGMII_ID/RXID/TXID") for mainline linux kernel.
>
> Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> Reviewed-by: David Wu <david.wu@rock-chips.com>
> ---
> v4: No changes
> ---
> drivers/net/gmac_rockchip.c | 80 +++++++++++++++++++++++++++++++++++----------
> 1 file changed, 63 insertions(+), 17 deletions(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [U-Boot, v4, 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii
2018-08-28 6:25 ` [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii Janine Hagemann
2018-08-31 11:57 ` [U-Boot] [U-Boot, v4, " David.Wu
@ 2018-10-04 20:08 ` Philipp Tomsich
1 sibling, 0 replies; 14+ messages in thread
From: Philipp Tomsich @ 2018-10-04 20:08 UTC (permalink / raw)
To: u-boot
> We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
> RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
> to enable the RX delay.
> The MASK was used in a wrong way.
>
> Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
> Reviewed-by: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
> v4: No changes
> ---
> drivers/net/gmac_rockchip.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2018-10-04 20:08 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-28 6:24 [U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288 Janine Hagemann
2018-08-28 6:24 ` [U-Boot] [PATCH v4 1/7] arch: arm: mach-rockchip: rk3288: Enable regulators in board_init Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 2/7] config: phycore-rk3288_defconfig: add PHY_TI Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 3/7] drivers: net: designware: Add reading of DT phy-handle node Janine Hagemann
2018-08-28 23:53 ` Grygorii Strashko
2018-08-28 6:25 ` [U-Boot] [PATCH v4 4/7] ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 5/7] rockchip: rk3288-phycore: set flash1 iodomain to 1.8V Janine Hagemann
2018-08-28 6:25 ` [U-Boot] [PATCH v4 6/7] net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii Janine Hagemann
2018-08-31 11:57 ` [U-Boot] [U-Boot, v4, " David.Wu
2018-10-04 20:08 ` Philipp Tomsich
2018-08-28 6:25 ` [U-Boot] [PATCH v4 7/7] net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID Janine Hagemann
2018-08-31 11:54 ` [U-Boot] [U-Boot, v4, " David.Wu
2018-08-31 12:24 ` [U-Boot] [Resend] " David.Wu
2018-10-04 20:08 ` [U-Boot] " Philipp Tomsich
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.